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OvmfPkg: PciHostBridgeDxe: look for all root buses
[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c
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1/**@file\r
2 Platform PEI driver\r
3\r
4 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
6\r
7 This program and the accompanying materials\r
8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17//\r
18// The package level header files this module uses\r
19//\r
20#include <PiPei.h>\r
21\r
22//\r
23// The Library classes this module consumes\r
24//\r
25#include <Library/DebugLib.h>\r
26#include <Library/HobLib.h>\r
27#include <Library/IoLib.h>\r
28#include <Library/MemoryAllocationLib.h>\r
29#include <Library/PcdLib.h>\r
30#include <Library/PciLib.h>\r
31#include <Library/PeimEntryPoint.h>\r
32#include <Library/PeiServicesLib.h>\r
33#include <Library/QemuFwCfgLib.h>\r
34#include <Library/ResourcePublicationLib.h>\r
35#include <Library/BaseMemoryLib.h>\r
36#include <Guid/MemoryTypeInformation.h>\r
37#include <Ppi/MasterBootMode.h>\r
38#include <IndustryStandard/Pci22.h>\r
39#include <IndustryStandard/SmBios.h>\r
40#include <OvmfPlatforms.h>\r
41\r
42#include "Platform.h"\r
43#include "Cmos.h"\r
44\r
45EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
46 { EfiACPIMemoryNVS, 0x004 },\r
47 { EfiACPIReclaimMemory, 0x008 },\r
48 { EfiReservedMemoryType, 0x004 },\r
49 { EfiRuntimeServicesData, 0x024 },\r
50 { EfiRuntimeServicesCode, 0x030 },\r
51 { EfiBootServicesCode, 0x180 },\r
52 { EfiBootServicesData, 0xF00 },\r
53 { EfiMaxMemoryType, 0x000 }\r
54};\r
55\r
56\r
57EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
58 {\r
59 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
60 &gEfiPeiMasterBootModePpiGuid,\r
61 NULL\r
62 }\r
63};\r
64\r
65\r
66UINT16 mHostBridgeDevId;\r
67\r
68EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
69\r
70BOOLEAN mS3Supported = FALSE;\r
71\r
72\r
73VOID\r
74AddIoMemoryBaseSizeHob (\r
75 EFI_PHYSICAL_ADDRESS MemoryBase,\r
76 UINT64 MemorySize\r
77 )\r
78{\r
79 BuildResourceDescriptorHob (\r
80 EFI_RESOURCE_MEMORY_MAPPED_IO,\r
81 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
82 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
83 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
84 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
85 MemoryBase,\r
86 MemorySize\r
87 );\r
88}\r
89\r
90VOID\r
91AddReservedMemoryBaseSizeHob (\r
92 EFI_PHYSICAL_ADDRESS MemoryBase,\r
93 UINT64 MemorySize\r
94 )\r
95{\r
96 BuildResourceDescriptorHob (\r
97 EFI_RESOURCE_MEMORY_RESERVED,\r
98 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
99 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
100 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
101 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
102 MemoryBase,\r
103 MemorySize\r
104 );\r
105}\r
106\r
107VOID\r
108AddIoMemoryRangeHob (\r
109 EFI_PHYSICAL_ADDRESS MemoryBase,\r
110 EFI_PHYSICAL_ADDRESS MemoryLimit\r
111 )\r
112{\r
113 AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
114}\r
115\r
116\r
117VOID\r
118AddMemoryBaseSizeHob (\r
119 EFI_PHYSICAL_ADDRESS MemoryBase,\r
120 UINT64 MemorySize\r
121 )\r
122{\r
123 BuildResourceDescriptorHob (\r
124 EFI_RESOURCE_SYSTEM_MEMORY,\r
125 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
126 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
127 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
128 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
129 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
130 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
131 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
132 MemoryBase,\r
133 MemorySize\r
134 );\r
135}\r
136\r
137\r
138VOID\r
139AddMemoryRangeHob (\r
140 EFI_PHYSICAL_ADDRESS MemoryBase,\r
141 EFI_PHYSICAL_ADDRESS MemoryLimit\r
142 )\r
143{\r
144 AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
145}\r
146\r
147\r
148VOID\r
149AddUntestedMemoryBaseSizeHob (\r
150 EFI_PHYSICAL_ADDRESS MemoryBase,\r
151 UINT64 MemorySize\r
152 )\r
153{\r
154 BuildResourceDescriptorHob (\r
155 EFI_RESOURCE_SYSTEM_MEMORY,\r
156 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
157 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
158 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
159 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
160 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
161 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
162 MemoryBase,\r
163 MemorySize\r
164 );\r
165}\r
166\r
167\r
168VOID\r
169AddUntestedMemoryRangeHob (\r
170 EFI_PHYSICAL_ADDRESS MemoryBase,\r
171 EFI_PHYSICAL_ADDRESS MemoryLimit\r
172 )\r
173{\r
174 AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
175}\r
176\r
177VOID\r
178MemMapInitialization (\r
179 VOID\r
180 )\r
181{\r
182 //\r
183 // Create Memory Type Information HOB\r
184 //\r
185 BuildGuidDataHob (\r
186 &gEfiMemoryTypeInformationGuid,\r
187 mDefaultMemoryTypeInformation,\r
188 sizeof(mDefaultMemoryTypeInformation)\r
189 );\r
190\r
191 //\r
192 // Add PCI IO Port space available for PCI resource allocations.\r
193 //\r
194 BuildResourceDescriptorHob (\r
195 EFI_RESOURCE_IO,\r
196 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
197 EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
198 0xC000,\r
199 0x4000\r
200 );\r
201\r
202 //\r
203 // Video memory + Legacy BIOS region\r
204 //\r
205 AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
206\r
207 if (!mXen) {\r
208 UINT32 TopOfLowRam;\r
209 TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
210\r
211 //\r
212 // address purpose size\r
213 // ------------ -------- -------------------------\r
214 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
215 // 0xFC000000 gap 44 MB\r
216 // 0xFEC00000 IO-APIC 4 KB\r
217 // 0xFEC01000 gap 1020 KB\r
218 // 0xFED00000 HPET 1 KB\r
219 // 0xFED00400 gap 111 KB\r
220 // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r
221 // 0xFED20000 gap 896 KB\r
222 // 0xFEE00000 LAPIC 1 MB\r
223 //\r
224 AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
225 BASE_2GB : TopOfLowRam, 0xFC000000);\r
226 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
227 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
228 if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
229 AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
230 }\r
231 AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
232 }\r
233}\r
234\r
235\r
236VOID\r
237MiscInitialization (\r
238 VOID\r
239 )\r
240{\r
241 UINTN PmCmd;\r
242 UINTN Pmba;\r
243 UINTN AcpiCtlReg;\r
244 UINT8 AcpiEnBit;\r
245\r
246 //\r
247 // Disable A20 Mask\r
248 //\r
249 IoOr8 (0x92, BIT1);\r
250\r
251 //\r
252 // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
253 // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
254 // S3 resume as well, so we build it unconditionally.)\r
255 //\r
256 BuildCpuHob (mPhysMemAddressWidth, 16);\r
257\r
258 //\r
259 // Determine platform type and save Host Bridge DID to PCD\r
260 //\r
261 switch (mHostBridgeDevId) {\r
262 case INTEL_82441_DEVICE_ID:\r
263 PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
264 Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
265 AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
266 AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
267 break;\r
268 case INTEL_Q35_MCH_DEVICE_ID:\r
269 PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
270 Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
271 AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
272 AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
273 break;\r
274 default:\r
275 DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
276 __FUNCTION__, mHostBridgeDevId));\r
277 ASSERT (FALSE);\r
278 return;\r
279 }\r
280 PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
281\r
282 //\r
283 // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
284 // has been configured (e.g., by Xen) and skip the setup here.\r
285 // This matches the logic in AcpiTimerLibConstructor ().\r
286 //\r
287 if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
288 //\r
289 // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
290 // 1. set PMBA\r
291 //\r
292 PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
293\r
294 //\r
295 // 2. set PCICMD/IOSE\r
296 //\r
297 PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
298\r
299 //\r
300 // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
301 //\r
302 PciOr8 (AcpiCtlReg, AcpiEnBit);\r
303 }\r
304\r
305 if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
306 //\r
307 // Set Root Complex Register Block BAR\r
308 //\r
309 PciWrite32 (\r
310 POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
311 ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
312 );\r
313 }\r
314}\r
315\r
316\r
317VOID\r
318BootModeInitialization (\r
319 VOID\r
320 )\r
321{\r
322 EFI_STATUS Status;\r
323\r
324 if (CmosRead8 (0xF) == 0xFE) {\r
325 mBootMode = BOOT_ON_S3_RESUME;\r
326 }\r
327\r
328 Status = PeiServicesSetBootMode (mBootMode);\r
329 ASSERT_EFI_ERROR (Status);\r
330\r
331 Status = PeiServicesInstallPpi (mPpiBootMode);\r
332 ASSERT_EFI_ERROR (Status);\r
333}\r
334\r
335\r
336VOID\r
337ReserveEmuVariableNvStore (\r
338 )\r
339{\r
340 EFI_PHYSICAL_ADDRESS VariableStore;\r
341\r
342 //\r
343 // Allocate storage for NV variables early on so it will be\r
344 // at a consistent address. Since VM memory is preserved\r
345 // across reboots, this allows the NV variable storage to survive\r
346 // a VM reboot.\r
347 //\r
348 VariableStore =\r
349 (EFI_PHYSICAL_ADDRESS)(UINTN)\r
350 AllocateAlignedRuntimePages (\r
351 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
352 PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
353 );\r
354 DEBUG ((EFI_D_INFO,\r
355 "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
356 VariableStore,\r
357 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
358 ));\r
359 PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
360}\r
361\r
362\r
363VOID\r
364DebugDumpCmos (\r
365 VOID\r
366 )\r
367{\r
368 UINTN Loop;\r
369\r
370 DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
371\r
372 for (Loop = 0; Loop < 0x80; Loop++) {\r
373 if ((Loop % 0x10) == 0) {\r
374 DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
375 }\r
376 DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
377 if ((Loop % 0x10) == 0xf) {\r
378 DEBUG ((EFI_D_INFO, "\n"));\r
379 }\r
380 }\r
381}\r
382\r
383\r
384/**\r
385 Set the SMBIOS entry point version for the generic SmbiosDxe driver.\r
386**/\r
387STATIC\r
388VOID\r
389SmbiosVersionInitialization (\r
390 VOID\r
391 )\r
392{\r
393 FIRMWARE_CONFIG_ITEM Anchor;\r
394 UINTN AnchorSize;\r
395 SMBIOS_TABLE_ENTRY_POINT QemuAnchor;\r
396 UINT16 SmbiosVersion;\r
397\r
398 if (RETURN_ERROR (QemuFwCfgFindFile ("etc/smbios/smbios-anchor", &Anchor,\r
399 &AnchorSize)) ||\r
400 AnchorSize != sizeof QemuAnchor) {\r
401 return;\r
402 }\r
403\r
404 QemuFwCfgSelectItem (Anchor);\r
405 QemuFwCfgReadBytes (AnchorSize, &QemuAnchor);\r
406 if (CompareMem (QemuAnchor.AnchorString, "_SM_", 4) != 0 ||\r
407 CompareMem (QemuAnchor.IntermediateAnchorString, "_DMI_", 5) != 0) {\r
408 return;\r
409 }\r
410\r
411 SmbiosVersion = (UINT16)(QemuAnchor.MajorVersion << 8 |\r
412 QemuAnchor.MinorVersion);\r
413 DEBUG ((EFI_D_INFO, "%a: SMBIOS version from QEMU: 0x%04x\n", __FUNCTION__,\r
414 SmbiosVersion));\r
415 PcdSet16 (PcdSmbiosVersion, SmbiosVersion);\r
416}\r
417\r
418\r
419/**\r
420 Perform Platform PEI initialization.\r
421\r
422 @param FileHandle Handle of the file being invoked.\r
423 @param PeiServices Describes the list of possible PEI Services.\r
424\r
425 @return EFI_SUCCESS The PEIM initialized successfully.\r
426\r
427**/\r
428EFI_STATUS\r
429EFIAPI\r
430InitializePlatform (\r
431 IN EFI_PEI_FILE_HANDLE FileHandle,\r
432 IN CONST EFI_PEI_SERVICES **PeiServices\r
433 )\r
434{\r
435 DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
436\r
437 DebugDumpCmos ();\r
438\r
439 XenDetect ();\r
440\r
441 if (QemuFwCfgS3Enabled ()) {\r
442 DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
443 mS3Supported = TRUE;\r
444 }\r
445\r
446 BootModeInitialization ();\r
447 AddressWidthInitialization ();\r
448\r
449 PublishPeiMemory ();\r
450\r
451 InitializeRamRegions ();\r
452\r
453 if (mXen) {\r
454 DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
455 InitializeXen ();\r
456 }\r
457\r
458 //\r
459 // Query Host Bridge DID\r
460 //\r
461 mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
462\r
463 if (mBootMode != BOOT_ON_S3_RESUME) {\r
464 ReserveEmuVariableNvStore ();\r
465\r
466 PeiFvInitialization ();\r
467\r
468 MemMapInitialization ();\r
469\r
470 SmbiosVersionInitialization ();\r
471 }\r
472\r
473 MiscInitialization ();\r
474\r
475 return EFI_SUCCESS;\r
476}\r
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