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MdeModulePkg: Introduce new PCD PcdAcpiS3Enable
[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c
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1/**@file\r
2 Platform PEI driver\r
3\r
4 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
6\r
7 This program and the accompanying materials\r
8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17//\r
18// The package level header files this module uses\r
19//\r
20#include <PiPei.h>\r
21\r
22//\r
23// The Library classes this module consumes\r
24//\r
25#include <Library/BaseLib.h>\r
26#include <Library/DebugLib.h>\r
27#include <Library/HobLib.h>\r
28#include <Library/IoLib.h>\r
29#include <Library/MemoryAllocationLib.h>\r
30#include <Library/PcdLib.h>\r
31#include <Library/PciLib.h>\r
32#include <Library/PeimEntryPoint.h>\r
33#include <Library/PeiServicesLib.h>\r
34#include <Library/QemuFwCfgLib.h>\r
35#include <Library/ResourcePublicationLib.h>\r
36#include <Guid/MemoryTypeInformation.h>\r
37#include <Ppi/MasterBootMode.h>\r
38#include <IndustryStandard/Pci22.h>\r
39#include <OvmfPlatforms.h>\r
40\r
41#include "Platform.h"\r
42#include "Cmos.h"\r
43\r
44EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
45 { EfiACPIMemoryNVS, 0x004 },\r
46 { EfiACPIReclaimMemory, 0x008 },\r
47 { EfiReservedMemoryType, 0x004 },\r
48 { EfiRuntimeServicesData, 0x024 },\r
49 { EfiRuntimeServicesCode, 0x030 },\r
50 { EfiBootServicesCode, 0x180 },\r
51 { EfiBootServicesData, 0xF00 },\r
52 { EfiMaxMemoryType, 0x000 }\r
53};\r
54\r
55\r
56EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
57 {\r
58 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
59 &gEfiPeiMasterBootModePpiGuid,\r
60 NULL\r
61 }\r
62};\r
63\r
64\r
65UINT16 mHostBridgeDevId;\r
66\r
67EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
68\r
69BOOLEAN mS3Supported = FALSE;\r
70\r
71\r
72VOID\r
73AddIoMemoryBaseSizeHob (\r
74 EFI_PHYSICAL_ADDRESS MemoryBase,\r
75 UINT64 MemorySize\r
76 )\r
77{\r
78 BuildResourceDescriptorHob (\r
79 EFI_RESOURCE_MEMORY_MAPPED_IO,\r
80 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
81 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
82 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
83 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
84 MemoryBase,\r
85 MemorySize\r
86 );\r
87}\r
88\r
89VOID\r
90AddReservedMemoryBaseSizeHob (\r
91 EFI_PHYSICAL_ADDRESS MemoryBase,\r
92 UINT64 MemorySize,\r
93 BOOLEAN Cacheable\r
94 )\r
95{\r
96 BuildResourceDescriptorHob (\r
97 EFI_RESOURCE_MEMORY_RESERVED,\r
98 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
99 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
100 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
101 (Cacheable ?\r
102 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
103 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
104 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
105 0\r
106 ) |\r
107 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
108 MemoryBase,\r
109 MemorySize\r
110 );\r
111}\r
112\r
113VOID\r
114AddIoMemoryRangeHob (\r
115 EFI_PHYSICAL_ADDRESS MemoryBase,\r
116 EFI_PHYSICAL_ADDRESS MemoryLimit\r
117 )\r
118{\r
119 AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
120}\r
121\r
122\r
123VOID\r
124AddMemoryBaseSizeHob (\r
125 EFI_PHYSICAL_ADDRESS MemoryBase,\r
126 UINT64 MemorySize\r
127 )\r
128{\r
129 BuildResourceDescriptorHob (\r
130 EFI_RESOURCE_SYSTEM_MEMORY,\r
131 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
132 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
133 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
134 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
135 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
136 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
137 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
138 MemoryBase,\r
139 MemorySize\r
140 );\r
141}\r
142\r
143\r
144VOID\r
145AddMemoryRangeHob (\r
146 EFI_PHYSICAL_ADDRESS MemoryBase,\r
147 EFI_PHYSICAL_ADDRESS MemoryLimit\r
148 )\r
149{\r
150 AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
151}\r
152\r
153\r
154VOID\r
155AddUntestedMemoryBaseSizeHob (\r
156 EFI_PHYSICAL_ADDRESS MemoryBase,\r
157 UINT64 MemorySize\r
158 )\r
159{\r
160 BuildResourceDescriptorHob (\r
161 EFI_RESOURCE_SYSTEM_MEMORY,\r
162 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
163 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
164 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
165 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
166 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
167 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
168 MemoryBase,\r
169 MemorySize\r
170 );\r
171}\r
172\r
173\r
174VOID\r
175AddUntestedMemoryRangeHob (\r
176 EFI_PHYSICAL_ADDRESS MemoryBase,\r
177 EFI_PHYSICAL_ADDRESS MemoryLimit\r
178 )\r
179{\r
180 AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
181}\r
182\r
183VOID\r
184MemMapInitialization (\r
185 VOID\r
186 )\r
187{\r
188 //\r
189 // Create Memory Type Information HOB\r
190 //\r
191 BuildGuidDataHob (\r
192 &gEfiMemoryTypeInformationGuid,\r
193 mDefaultMemoryTypeInformation,\r
194 sizeof(mDefaultMemoryTypeInformation)\r
195 );\r
196\r
197 //\r
198 // Add PCI IO Port space available for PCI resource allocations.\r
199 //\r
200 BuildResourceDescriptorHob (\r
201 EFI_RESOURCE_IO,\r
202 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
203 EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
204 PcdGet64 (PcdPciIoBase),\r
205 PcdGet64 (PcdPciIoSize)\r
206 );\r
207\r
208 //\r
209 // Video memory + Legacy BIOS region\r
210 //\r
211 AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
212\r
213 if (!mXen) {\r
214 UINT32 TopOfLowRam;\r
215 UINT64 PciExBarBase;\r
216 UINT32 PciBase;\r
217 UINT32 PciSize;\r
218\r
219 TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
220 PciExBarBase = 0;\r
221 if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
222 //\r
223 // The MMCONFIG area is expected to fall between the top of low RAM and\r
224 // the base of the 32-bit PCI host aperture.\r
225 //\r
226 PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
227 ASSERT (TopOfLowRam <= PciExBarBase);\r
228 ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
229 PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
230 } else {\r
231 PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
232 }\r
233\r
234 //\r
235 // address purpose size\r
236 // ------------ -------- -------------------------\r
237 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
238 // 0xFC000000 gap 44 MB\r
239 // 0xFEC00000 IO-APIC 4 KB\r
240 // 0xFEC01000 gap 1020 KB\r
241 // 0xFED00000 HPET 1 KB\r
242 // 0xFED00400 gap 111 KB\r
243 // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r
244 // 0xFED20000 gap 896 KB\r
245 // 0xFEE00000 LAPIC 1 MB\r
246 //\r
247 PciSize = 0xFC000000 - PciBase;\r
248 AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
249 PcdSet64 (PcdPciMmio32Base, PciBase);\r
250 PcdSet64 (PcdPciMmio32Size, PciSize);\r
251 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
252 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
253 if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
254 AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
255 //\r
256 // Note: there should be an\r
257 //\r
258 // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r
259 //\r
260 // call below, just like the one above for RCBA. However, Linux insists\r
261 // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r
262 // "reserved memory" -- Linux does not content itself with a simple gap\r
263 // in the memory map wherever the MCFG ACPI table points to.\r
264 //\r
265 // This appears to be a safety measure. The PCI Firmware Specification\r
266 // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can\r
267 // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory\r
268 // [...]". (Emphasis added here.)\r
269 //\r
270 // Normally we add memory resource descriptor HOBs in\r
271 // QemuInitializeRam(), and pre-allocate from those with memory\r
272 // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area\r
273 // is most definitely not RAM; so, as an exception, cover it with\r
274 // uncacheable reserved memory right here.\r
275 //\r
276 AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r
277 BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,\r
278 EfiReservedMemoryType);\r
279 }\r
280 AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
281 }\r
282}\r
283\r
284EFI_STATUS\r
285GetNamedFwCfgBoolean (\r
286 IN CHAR8 *FwCfgFileName,\r
287 OUT BOOLEAN *Setting\r
288 )\r
289{\r
290 EFI_STATUS Status;\r
291 FIRMWARE_CONFIG_ITEM FwCfgItem;\r
292 UINTN FwCfgSize;\r
293 UINT8 Value[3];\r
294\r
295 Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r
296 if (EFI_ERROR (Status)) {\r
297 return Status;\r
298 }\r
299 if (FwCfgSize > sizeof Value) {\r
300 return EFI_BAD_BUFFER_SIZE;\r
301 }\r
302 QemuFwCfgSelectItem (FwCfgItem);\r
303 QemuFwCfgReadBytes (FwCfgSize, Value);\r
304\r
305 if ((FwCfgSize == 1) ||\r
306 (FwCfgSize == 2 && Value[1] == '\n') ||\r
307 (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r
308 switch (Value[0]) {\r
309 case '0':\r
310 case 'n':\r
311 case 'N':\r
312 *Setting = FALSE;\r
313 return EFI_SUCCESS;\r
314\r
315 case '1':\r
316 case 'y':\r
317 case 'Y':\r
318 *Setting = TRUE;\r
319 return EFI_SUCCESS;\r
320\r
321 default:\r
322 break;\r
323 }\r
324 }\r
325 return EFI_PROTOCOL_ERROR;\r
326}\r
327\r
328#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r
329 do { \\r
330 BOOLEAN Setting; \\r
331 \\r
332 if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r
333 "opt/ovmf/" #TokenName, &Setting))) { \\r
334 PcdSetBool (TokenName, Setting); \\r
335 } \\r
336 } while (0)\r
337\r
338VOID\r
339NoexecDxeInitialization (\r
340 VOID\r
341 )\r
342{\r
343 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r
344 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r
345}\r
346\r
347VOID\r
348PciExBarInitialization (\r
349 VOID\r
350 )\r
351{\r
352 union {\r
353 UINT64 Uint64;\r
354 UINT32 Uint32[2];\r
355 } PciExBarBase;\r
356\r
357 //\r
358 // We only support the 256MB size for the MMCONFIG area:\r
359 // 256 buses * 32 devices * 8 functions * 4096 bytes config space.\r
360 //\r
361 // The masks used below enforce the Q35 requirements that the MMCONFIG area\r
362 // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.\r
363 //\r
364 // Note that (b) also ensures that the minimum address width we have\r
365 // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r
366 // for DXE's page tables to cover the MMCONFIG area.\r
367 //\r
368 PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
369 ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r
370 ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r
371\r
372 //\r
373 // Clear the PCIEXBAREN bit first, before programming the high register.\r
374 //\r
375 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);\r
376\r
377 //\r
378 // Program the high register. Then program the low register, setting the\r
379 // MMCONFIG area size and enabling decoding at once.\r
380 //\r
381 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);\r
382 PciWrite32 (\r
383 DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),\r
384 PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN\r
385 );\r
386}\r
387\r
388VOID\r
389MiscInitialization (\r
390 VOID\r
391 )\r
392{\r
393 UINTN PmCmd;\r
394 UINTN Pmba;\r
395 UINTN AcpiCtlReg;\r
396 UINT8 AcpiEnBit;\r
397\r
398 //\r
399 // Disable A20 Mask\r
400 //\r
401 IoOr8 (0x92, BIT1);\r
402\r
403 //\r
404 // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
405 // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
406 // S3 resume as well, so we build it unconditionally.)\r
407 //\r
408 BuildCpuHob (mPhysMemAddressWidth, 16);\r
409\r
410 //\r
411 // Determine platform type and save Host Bridge DID to PCD\r
412 //\r
413 switch (mHostBridgeDevId) {\r
414 case INTEL_82441_DEVICE_ID:\r
415 PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
416 Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
417 AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
418 AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
419 break;\r
420 case INTEL_Q35_MCH_DEVICE_ID:\r
421 PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
422 Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
423 AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
424 AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
425 break;\r
426 default:\r
427 DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
428 __FUNCTION__, mHostBridgeDevId));\r
429 ASSERT (FALSE);\r
430 return;\r
431 }\r
432 PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
433\r
434 //\r
435 // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
436 // has been configured (e.g., by Xen) and skip the setup here.\r
437 // This matches the logic in AcpiTimerLibConstructor ().\r
438 //\r
439 if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
440 //\r
441 // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
442 // 1. set PMBA\r
443 //\r
444 PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
445\r
446 //\r
447 // 2. set PCICMD/IOSE\r
448 //\r
449 PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
450\r
451 //\r
452 // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
453 //\r
454 PciOr8 (AcpiCtlReg, AcpiEnBit);\r
455 }\r
456\r
457 if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
458 //\r
459 // Set Root Complex Register Block BAR\r
460 //\r
461 PciWrite32 (\r
462 POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
463 ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
464 );\r
465\r
466 //\r
467 // Set PCI Express Register Range Base Address\r
468 //\r
469 PciExBarInitialization ();\r
470 }\r
471}\r
472\r
473\r
474VOID\r
475BootModeInitialization (\r
476 VOID\r
477 )\r
478{\r
479 EFI_STATUS Status;\r
480\r
481 if (CmosRead8 (0xF) == 0xFE) {\r
482 mBootMode = BOOT_ON_S3_RESUME;\r
483 }\r
484 CmosWrite8 (0xF, 0x00);\r
485\r
486 Status = PeiServicesSetBootMode (mBootMode);\r
487 ASSERT_EFI_ERROR (Status);\r
488\r
489 Status = PeiServicesInstallPpi (mPpiBootMode);\r
490 ASSERT_EFI_ERROR (Status);\r
491}\r
492\r
493\r
494VOID\r
495ReserveEmuVariableNvStore (\r
496 )\r
497{\r
498 EFI_PHYSICAL_ADDRESS VariableStore;\r
499\r
500 //\r
501 // Allocate storage for NV variables early on so it will be\r
502 // at a consistent address. Since VM memory is preserved\r
503 // across reboots, this allows the NV variable storage to survive\r
504 // a VM reboot.\r
505 //\r
506 VariableStore =\r
507 (EFI_PHYSICAL_ADDRESS)(UINTN)\r
508 AllocateAlignedRuntimePages (\r
509 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
510 PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
511 );\r
512 DEBUG ((EFI_D_INFO,\r
513 "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
514 VariableStore,\r
515 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
516 ));\r
517 PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
518}\r
519\r
520\r
521VOID\r
522DebugDumpCmos (\r
523 VOID\r
524 )\r
525{\r
526 UINT32 Loop;\r
527\r
528 DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
529\r
530 for (Loop = 0; Loop < 0x80; Loop++) {\r
531 if ((Loop % 0x10) == 0) {\r
532 DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
533 }\r
534 DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
535 if ((Loop % 0x10) == 0xf) {\r
536 DEBUG ((EFI_D_INFO, "\n"));\r
537 }\r
538 }\r
539}\r
540\r
541\r
542VOID\r
543S3Verification (\r
544 VOID\r
545 )\r
546{\r
547#if defined (MDE_CPU_X64)\r
548 if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r
549 DEBUG ((EFI_D_ERROR,\r
550 "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r
551 DEBUG ((EFI_D_ERROR,\r
552 "%a: Please disable S3 on the QEMU command line (see the README),\n",\r
553 __FUNCTION__));\r
554 DEBUG ((EFI_D_ERROR,\r
555 "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r
556 ASSERT (FALSE);\r
557 CpuDeadLoop ();\r
558 }\r
559#endif\r
560}\r
561\r
562\r
563/**\r
564 Perform Platform PEI initialization.\r
565\r
566 @param FileHandle Handle of the file being invoked.\r
567 @param PeiServices Describes the list of possible PEI Services.\r
568\r
569 @return EFI_SUCCESS The PEIM initialized successfully.\r
570\r
571**/\r
572EFI_STATUS\r
573EFIAPI\r
574InitializePlatform (\r
575 IN EFI_PEI_FILE_HANDLE FileHandle,\r
576 IN CONST EFI_PEI_SERVICES **PeiServices\r
577 )\r
578{\r
579 DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
580\r
581 DebugDumpCmos ();\r
582\r
583 XenDetect ();\r
584\r
585 if (QemuFwCfgS3Enabled ()) {\r
586 DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
587 mS3Supported = TRUE;\r
588 }\r
589\r
590 S3Verification ();\r
591 BootModeInitialization ();\r
592 AddressWidthInitialization ();\r
593\r
594 PublishPeiMemory ();\r
595\r
596 InitializeRamRegions ();\r
597\r
598 if (mXen) {\r
599 DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
600 InitializeXen ();\r
601 }\r
602\r
603 //\r
604 // Query Host Bridge DID\r
605 //\r
606 mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
607\r
608 if (mBootMode != BOOT_ON_S3_RESUME) {\r
609 ReserveEmuVariableNvStore ();\r
610 PeiFvInitialization ();\r
611 MemMapInitialization ();\r
612 NoexecDxeInitialization ();\r
613 }\r
614\r
615 MiscInitialization ();\r
616\r
617 return EFI_SUCCESS;\r
618}\r
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