[mirror_edk2.git] / OvmfPkg / SmmAccess / SmmAccessPei.c

/** @file\r
\r
  A PEIM with the following responsibilities:\r
\r
  - verify & configure the Q35 TSEG in the entry point,\r
  - provide SMRAM access by producing PEI_SMM_ACCESS_PPI,\r
  - set aside the SMM_S3_RESUME_STATE object at the bottom of TSEG, and expose\r
    it via the gEfiAcpiVariableGuid GUID HOB.\r
\r
  This PEIM runs from RAM, so we can write to variables with static storage\r
  duration.\r
\r
  Copyright (C) 2013, 2015, Red Hat, Inc.<BR>\r
  Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <Guid/AcpiS3Context.h>\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Ppi/SmmAccess.h>\r
\r
#include <OvmfPlatforms.h>\r
\r
#include "SmramInternal.h"\r
\r
//\r
// PEI_SMM_ACCESS_PPI implementation.\r
//\r
\r
/**\r
  Opens the SMRAM area to be accessible by a PEIM driver.\r
\r
  This function "opens" SMRAM so that it is visible while not inside of SMM.\r
  The function should return EFI_UNSUPPORTED if the hardware does not support\r
  hiding of SMRAM. The function should return EFI_DEVICE_ERROR if the SMRAM\r
  configuration is locked.\r
\r
  @param  PeiServices            General purpose services available to every\r
                                 PEIM.\r
  @param  This                   The pointer to the SMM Access Interface.\r
  @param  DescriptorIndex        The region of SMRAM to Open.\r
\r
  @retval EFI_SUCCESS            The region was successfully opened.\r
  @retval EFI_DEVICE_ERROR       The region could not be opened because locked\r
                                 by chipset.\r
  @retval EFI_INVALID_PARAMETER  The descriptor index was out of bounds.\r
\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
SmmAccessPeiOpen (\r
  IN EFI_PEI_SERVICES    **PeiServices,\r
  IN PEI_SMM_ACCESS_PPI  *This,\r
  IN UINTN               DescriptorIndex\r
  )\r
{\r
  if (DescriptorIndex >= DescIdxCount) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // According to current practice, DescriptorIndex is not considered at all,\r
  // beyond validating it.\r
  //\r
  return SmramAccessOpen (&This->LockState, &This->OpenState);\r
}\r
\r
/**\r
  Inhibits access to the SMRAM.\r
\r
  This function "closes" SMRAM so that it is not visible while outside of SMM.\r
  The function should return EFI_UNSUPPORTED if the hardware does not support\r
  hiding of SMRAM.\r
\r
  @param  PeiServices              General purpose services available to every\r
                                   PEIM.\r
  @param  This                     The pointer to the SMM Access Interface.\r
  @param  DescriptorIndex          The region of SMRAM to Close.\r
\r
  @retval EFI_SUCCESS              The region was successfully closed.\r
  @retval EFI_DEVICE_ERROR         The region could not be closed because\r
                                   locked by chipset.\r
  @retval EFI_INVALID_PARAMETER    The descriptor index was out of bounds.\r
\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
SmmAccessPeiClose (\r
  IN EFI_PEI_SERVICES    **PeiServices,\r
  IN PEI_SMM_ACCESS_PPI  *This,\r
  IN UINTN               DescriptorIndex\r
  )\r
{\r
  if (DescriptorIndex >= DescIdxCount) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // According to current practice, DescriptorIndex is not considered at all,\r
  // beyond validating it.\r
  //\r
  return SmramAccessClose (&This->LockState, &This->OpenState);\r
}\r
\r
/**\r
  Inhibits access to the SMRAM.\r
\r
  This function prohibits access to the SMRAM region.  This function is usually\r
  implemented such that it is a write-once operation.\r
\r
  @param  PeiServices              General purpose services available to every\r
                                   PEIM.\r
  @param  This                     The pointer to the SMM Access Interface.\r
  @param  DescriptorIndex          The region of SMRAM to Close.\r
\r
  @retval EFI_SUCCESS            The region was successfully locked.\r
  @retval EFI_DEVICE_ERROR       The region could not be locked because at\r
                                 least one range is still open.\r
  @retval EFI_INVALID_PARAMETER  The descriptor index was out of bounds.\r
\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
SmmAccessPeiLock (\r
  IN EFI_PEI_SERVICES    **PeiServices,\r
  IN PEI_SMM_ACCESS_PPI  *This,\r
  IN UINTN               DescriptorIndex\r
  )\r
{\r
  if (DescriptorIndex >= DescIdxCount) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // According to current practice, DescriptorIndex is not considered at all,\r
  // beyond validating it.\r
  //\r
  return SmramAccessLock (&This->LockState, &This->OpenState);\r
}\r
\r
/**\r
  Queries the memory controller for the possible regions that will support\r
  SMRAM.\r
\r
  @param  PeiServices           General purpose services available to every\r
                                PEIM.\r
  @param This                   The pointer to the SmmAccessPpi Interface.\r
  @param SmramMapSize           The pointer to the variable containing size of\r
                                the buffer to contain the description\r
                                information.\r
  @param SmramMap               The buffer containing the data describing the\r
                                Smram region descriptors.\r
\r
  @retval EFI_BUFFER_TOO_SMALL  The user did not provide a sufficient buffer.\r
  @retval EFI_SUCCESS           The user provided a sufficiently-sized buffer.\r
\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
SmmAccessPeiGetCapabilities (\r
  IN EFI_PEI_SERVICES          **PeiServices,\r
  IN PEI_SMM_ACCESS_PPI        *This,\r
  IN OUT UINTN                 *SmramMapSize,\r
  IN OUT EFI_SMRAM_DESCRIPTOR  *SmramMap\r
  )\r
{\r
  return SmramAccessGetCapabilities (\r
           This->LockState,\r
           This->OpenState,\r
           SmramMapSize,\r
           SmramMap\r
           );\r
}\r
\r
//\r
// LockState and OpenState will be filled in by the entry point.\r
//\r
STATIC PEI_SMM_ACCESS_PPI  mAccess = {\r
  &SmmAccessPeiOpen,\r
  &SmmAccessPeiClose,\r
  &SmmAccessPeiLock,\r
  &SmmAccessPeiGetCapabilities\r
};\r
\r
STATIC EFI_PEI_PPI_DESCRIPTOR  mPpiList[] = {\r
  {\r
    EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
    &gPeiSmmAccessPpiGuid, &mAccess\r
  }\r
};\r
\r
//\r
// Utility functions.\r
//\r
STATIC\r
UINT8\r
CmosRead8 (\r
  IN UINT8  Index\r
  )\r
{\r
  IoWrite8 (0x70, Index);\r
  return IoRead8 (0x71);\r
}\r
\r
STATIC\r
UINT32\r
GetSystemMemorySizeBelow4gb (\r
  VOID\r
  )\r
{\r
  UINT32  Cmos0x34;\r
  UINT32  Cmos0x35;\r
\r
  Cmos0x34 = CmosRead8 (0x34);\r
  Cmos0x35 = CmosRead8 (0x35);\r
\r
  return ((Cmos0x35 << 8 | Cmos0x34) << 16) + SIZE_16MB;\r
}\r
\r
//\r
// Entry point of this driver.\r
//\r
EFI_STATUS\r
EFIAPI\r
SmmAccessPeiEntryPoint (\r
  IN       EFI_PEI_FILE_HANDLE  FileHandle,\r
  IN CONST EFI_PEI_SERVICES     **PeiServices\r
  )\r
{\r
  UINT16                HostBridgeDevId;\r
  UINT8                 EsmramcVal;\r
  UINT8                 RegMask8;\r
  UINT32                TopOfLowRam, TopOfLowRamMb;\r
  EFI_STATUS            Status;\r
  UINTN                 SmramMapSize;\r
  EFI_SMRAM_DESCRIPTOR  SmramMap[DescIdxCount];\r
  VOID                  *GuidHob;\r
\r
  //\r
  // This module should only be included if SMRAM support is required.\r
  //\r
  ASSERT (FeaturePcdGet (PcdSmmSmramRequire));\r
\r
  //\r
  // Verify if we're running on a Q35 machine type.\r
  //\r
  HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
  if (HostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {\r
    DEBUG ((\r
      DEBUG_ERROR,\r
      "%a: no SMRAM with host bridge DID=0x%04x; only "\r
      "DID=0x%04x (Q35) is supported\n",\r
      __FUNCTION__,\r
      HostBridgeDevId,\r
      INTEL_Q35_MCH_DEVICE_ID\r
      ));\r
    goto WrongConfig;\r
  }\r
\r
  //\r
  // Confirm if QEMU supports SMRAM.\r
  //\r
  // With no support for it, the ESMRAMC (Extended System Management RAM\r
  // Control) register reads as zero. If there is support, the cache-enable\r
  // bits are hard-coded as 1 by QEMU.\r
  //\r
  EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));\r
  RegMask8   = MCH_ESMRAMC_SM_CACHE | MCH_ESMRAMC_SM_L1 | MCH_ESMRAMC_SM_L2;\r
  if ((EsmramcVal & RegMask8) != RegMask8) {\r
    DEBUG ((\r
      DEBUG_ERROR,\r
      "%a: this Q35 implementation lacks SMRAM\n",\r
      __FUNCTION__\r
      ));\r
    goto WrongConfig;\r
  }\r
\r
  TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
  ASSERT ((TopOfLowRam & (SIZE_1MB - 1)) == 0);\r
  TopOfLowRamMb = TopOfLowRam >> 20;\r
\r
  //\r
  // Some of the following registers are no-ops for QEMU at the moment, but it\r
  // is recommended to set them correctly, since the ESMRAMC that we ultimately\r
  // care about is in the same set of registers.\r
  //\r
  // First, we disable the integrated VGA, and set both the GTT Graphics Memory\r
  // Size and the Graphics Mode Select memory pre-allocation fields to zero.\r
  // This takes just one write to the Graphics Control Register.\r
  //\r
  PciWrite16 (DRAMC_REGISTER_Q35 (MCH_GGC), MCH_GGC_IVD);\r
\r
  //\r
  // Set Top of Low Usable DRAM.\r
  //\r
  PciWrite16 (\r
    DRAMC_REGISTER_Q35 (MCH_TOLUD),\r
    (UINT16)(TopOfLowRamMb << MCH_TOLUD_MB_SHIFT)\r
    );\r
\r
  //\r
  // Given the zero graphics memory sizes configured above, set the\r
  // graphics-related stolen memory bases to the same as TOLUD.\r
  //\r
  PciWrite32 (\r
    DRAMC_REGISTER_Q35 (MCH_GBSM),\r
    TopOfLowRamMb << MCH_GBSM_MB_SHIFT\r
    );\r
  PciWrite32 (\r
    DRAMC_REGISTER_Q35 (MCH_BGSM),\r
    TopOfLowRamMb << MCH_BGSM_MB_SHIFT\r
    );\r
\r
  //\r
  // Set TSEG Memory Base.\r
  //\r
  InitQ35TsegMbytes ();\r
  PciWrite32 (\r
    DRAMC_REGISTER_Q35 (MCH_TSEGMB),\r
    (TopOfLowRamMb - mQ35TsegMbytes) << MCH_TSEGMB_MB_SHIFT\r
    );\r
\r
  //\r
  // Set TSEG size, and disable TSEG visibility outside of SMM. Note that the\r
  // T_EN bit has inverse meaning; when T_EN is set, then TSEG visibility is\r
  // *restricted* to SMM.\r
  //\r
  EsmramcVal &= ~(UINT32)MCH_ESMRAMC_TSEG_MASK;\r
  EsmramcVal |= mQ35TsegMbytes == 8 ? MCH_ESMRAMC_TSEG_8MB :\r
                mQ35TsegMbytes == 2 ? MCH_ESMRAMC_TSEG_2MB :\r
                mQ35TsegMbytes == 1 ? MCH_ESMRAMC_TSEG_1MB :\r
                MCH_ESMRAMC_TSEG_EXT;\r
  EsmramcVal |= MCH_ESMRAMC_T_EN;\r
  PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal);\r
\r
  //\r
  // TSEG should be closed (see above), but unlocked, initially. Set G_SMRAME\r
  // (Global SMRAM Enable) too, as both D_LCK and T_EN depend on it.\r
  //\r
  PciAndThenOr8 (\r
    DRAMC_REGISTER_Q35 (MCH_SMRAM),\r
    (UINT8)((~(UINT32)MCH_SMRAM_D_LCK) & 0xff),\r
    MCH_SMRAM_G_SMRAME\r
    );\r
\r
  //\r
  // Create the GUID HOB and point it to the first SMRAM range.\r
  //\r
  GetStates (&mAccess.LockState, &mAccess.OpenState);\r
  SmramMapSize = sizeof SmramMap;\r
  Status       = SmramAccessGetCapabilities (\r
                   mAccess.LockState,\r
                   mAccess.OpenState,\r
                   &SmramMapSize,\r
                   SmramMap\r
                   );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  DEBUG_CODE_BEGIN ();\r
  {\r
    UINTN  Count;\r
    UINTN  Idx;\r
\r
    Count = SmramMapSize / sizeof SmramMap[0];\r
    DEBUG ((\r
      DEBUG_VERBOSE,\r
      "%a: SMRAM map follows, %d entries\n",\r
      __FUNCTION__,\r
      (INT32)Count\r
      ));\r
    DEBUG ((\r
      DEBUG_VERBOSE,\r
      "% 20a % 20a % 20a % 20a\n",\r
      "PhysicalStart(0x)",\r
      "PhysicalSize(0x)",\r
      "CpuStart(0x)",\r
      "RegionState(0x)"\r
      ));\r
    for (Idx = 0; Idx < Count; ++Idx) {\r
      DEBUG ((\r
        DEBUG_VERBOSE,\r
        "% 20Lx % 20Lx % 20Lx % 20Lx\n",\r
        SmramMap[Idx].PhysicalStart,\r
        SmramMap[Idx].PhysicalSize,\r
        SmramMap[Idx].CpuStart,\r
        SmramMap[Idx].RegionState\r
        ));\r
    }\r
  }\r
  DEBUG_CODE_END ();\r
\r
  GuidHob = BuildGuidHob (\r
              &gEfiAcpiVariableGuid,\r
              sizeof SmramMap[DescIdxSmmS3ResumeState]\r
              );\r
  if (GuidHob == NULL) {\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
\r
  CopyMem (\r
    GuidHob,\r
    &SmramMap[DescIdxSmmS3ResumeState],\r
    sizeof SmramMap[DescIdxSmmS3ResumeState]\r
    );\r
\r
  //\r
  // SmramAccessLock() depends on "mQ35SmramAtDefaultSmbase"; init the latter\r
  // just before exposing the former via PEI_SMM_ACCESS_PPI.Lock().\r
  //\r
  InitQ35SmramAtDefaultSmbase ();\r
\r
  //\r
  // We're done. The next step should succeed, but even if it fails, we can't\r
  // roll back the above BuildGuidHob() allocation, because PEI doesn't support\r
  // releasing memory.\r
  //\r
  return PeiServicesInstallPpi (mPpiList);\r
\r
WrongConfig:\r
  //\r
  // We really don't want to continue in this case.\r
  //\r
  ASSERT (FALSE);\r
  CpuDeadLoop ();\r
  return EFI_UNSUPPORTED;\r
}\r
Commit	Line	Data
	1	/** @file\r
	2	\r
	3	A PEIM with the following responsibilities:\r
	4	\r
	5	- verify & configure the Q35 TSEG in the entry point,\r
	6	- provide SMRAM access by producing PEI_SMM_ACCESS_PPI,\r
	7	- set aside the SMM_S3_RESUME_STATE object at the bottom of TSEG, and expose\r
	8	it via the gEfiAcpiVariableGuid GUID HOB.\r
	9	\r
	10	This PEIM runs from RAM, so we can write to variables with static storage\r
	11	duration.\r
	12	\r
	13	Copyright (C) 2013, 2015, Red Hat, Inc.<BR>\r
	14	Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
	15	\r
	16	SPDX-License-Identifier: BSD-2-Clause-Patent\r
	17	\r
	18	**/\r
	19	\r
	20	#include <Guid/AcpiS3Context.h>\r
	21	#include <Library/BaseLib.h>\r
	22	#include <Library/BaseMemoryLib.h>\r
	23	#include <Library/DebugLib.h>\r
	24	#include <Library/HobLib.h>\r
	25	#include <Library/IoLib.h>\r
	26	#include <Library/PcdLib.h>\r
	27	#include <Library/PciLib.h>\r
	28	#include <Library/PeiServicesLib.h>\r
	29	#include <Ppi/SmmAccess.h>\r
	30	\r
	31	#include <OvmfPlatforms.h>\r
	32	\r
	33	#include "SmramInternal.h"\r
	34	\r
	35	//\r
	36	// PEI_SMM_ACCESS_PPI implementation.\r
	37	//\r
	38	\r
	39	/**\r
	40	Opens the SMRAM area to be accessible by a PEIM driver.\r
	41	\r
	42	This function "opens" SMRAM so that it is visible while not inside of SMM.\r
	43	The function should return EFI_UNSUPPORTED if the hardware does not support\r
	44	hiding of SMRAM. The function should return EFI_DEVICE_ERROR if the SMRAM\r
	45	configuration is locked.\r
	46	\r
	47	@param PeiServices General purpose services available to every\r
	48	PEIM.\r
	49	@param This The pointer to the SMM Access Interface.\r
	50	@param DescriptorIndex The region of SMRAM to Open.\r
	51	\r
	52	@retval EFI_SUCCESS The region was successfully opened.\r
	53	@retval EFI_DEVICE_ERROR The region could not be opened because locked\r
	54	by chipset.\r
	55	@retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.\r
	56	\r
	57	**/\r
	58	STATIC\r
	59	EFI_STATUS\r
	60	EFIAPI\r
	61	SmmAccessPeiOpen (\r
	62	IN EFI_PEI_SERVICES **PeiServices,\r
	63	IN PEI_SMM_ACCESS_PPI *This,\r
	64	IN UINTN DescriptorIndex\r
	65	)\r
	66	{\r
	67	if (DescriptorIndex >= DescIdxCount) {\r
	68	return EFI_INVALID_PARAMETER;\r
	69	}\r
	70	\r
	71	//\r
	72	// According to current practice, DescriptorIndex is not considered at all,\r
	73	// beyond validating it.\r
	74	//\r
	75	return SmramAccessOpen (&This->LockState, &This->OpenState);\r
	76	}\r
	77	\r
	78	/**\r
	79	Inhibits access to the SMRAM.\r
	80	\r
	81	This function "closes" SMRAM so that it is not visible while outside of SMM.\r
	82	The function should return EFI_UNSUPPORTED if the hardware does not support\r
	83	hiding of SMRAM.\r
	84	\r
	85	@param PeiServices General purpose services available to every\r
	86	PEIM.\r
	87	@param This The pointer to the SMM Access Interface.\r
	88	@param DescriptorIndex The region of SMRAM to Close.\r
	89	\r
	90	@retval EFI_SUCCESS The region was successfully closed.\r
	91	@retval EFI_DEVICE_ERROR The region could not be closed because\r
	92	locked by chipset.\r
	93	@retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.\r
	94	\r
	95	**/\r
	96	STATIC\r
	97	EFI_STATUS\r
	98	EFIAPI\r
	99	SmmAccessPeiClose (\r
	100	IN EFI_PEI_SERVICES **PeiServices,\r
	101	IN PEI_SMM_ACCESS_PPI *This,\r
	102	IN UINTN DescriptorIndex\r
	103	)\r
	104	{\r
	105	if (DescriptorIndex >= DescIdxCount) {\r
	106	return EFI_INVALID_PARAMETER;\r
	107	}\r
	108	\r
	109	//\r
	110	// According to current practice, DescriptorIndex is not considered at all,\r
	111	// beyond validating it.\r
	112	//\r
	113	return SmramAccessClose (&This->LockState, &This->OpenState);\r
	114	}\r
	115	\r
	116	/**\r
	117	Inhibits access to the SMRAM.\r
	118	\r
	119	This function prohibits access to the SMRAM region. This function is usually\r
	120	implemented such that it is a write-once operation.\r
	121	\r
	122	@param PeiServices General purpose services available to every\r
	123	PEIM.\r
	124	@param This The pointer to the SMM Access Interface.\r
	125	@param DescriptorIndex The region of SMRAM to Close.\r
	126	\r
	127	@retval EFI_SUCCESS The region was successfully locked.\r
	128	@retval EFI_DEVICE_ERROR The region could not be locked because at\r
	129	least one range is still open.\r
	130	@retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.\r
	131	\r
	132	**/\r
	133	STATIC\r
	134	EFI_STATUS\r
	135	EFIAPI\r
	136	SmmAccessPeiLock (\r
	137	IN EFI_PEI_SERVICES **PeiServices,\r
	138	IN PEI_SMM_ACCESS_PPI *This,\r
	139	IN UINTN DescriptorIndex\r
	140	)\r
	141	{\r
	142	if (DescriptorIndex >= DescIdxCount) {\r
	143	return EFI_INVALID_PARAMETER;\r
	144	}\r
	145	\r
	146	//\r
	147	// According to current practice, DescriptorIndex is not considered at all,\r
	148	// beyond validating it.\r
	149	//\r
	150	return SmramAccessLock (&This->LockState, &This->OpenState);\r
	151	}\r
	152	\r
	153	/**\r
	154	Queries the memory controller for the possible regions that will support\r
	155	SMRAM.\r
	156	\r
	157	@param PeiServices General purpose services available to every\r
	158	PEIM.\r
	159	@param This The pointer to the SmmAccessPpi Interface.\r
	160	@param SmramMapSize The pointer to the variable containing size of\r
	161	the buffer to contain the description\r
	162	information.\r
	163	@param SmramMap The buffer containing the data describing the\r
	164	Smram region descriptors.\r
	165	\r
	166	@retval EFI_BUFFER_TOO_SMALL The user did not provide a sufficient buffer.\r
	167	@retval EFI_SUCCESS The user provided a sufficiently-sized buffer.\r
	168	\r
	169	**/\r
	170	STATIC\r
	171	EFI_STATUS\r
	172	EFIAPI\r
	173	SmmAccessPeiGetCapabilities (\r
	174	IN EFI_PEI_SERVICES **PeiServices,\r
	175	IN PEI_SMM_ACCESS_PPI *This,\r
	176	IN OUT UINTN *SmramMapSize,\r
	177	IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap\r
	178	)\r
	179	{\r
	180	return SmramAccessGetCapabilities (\r
	181	This->LockState,\r
	182	This->OpenState,\r
	183	SmramMapSize,\r
	184	SmramMap\r
	185	);\r
	186	}\r
	187	\r
	188	//\r
	189	// LockState and OpenState will be filled in by the entry point.\r
	190	//\r
	191	STATIC PEI_SMM_ACCESS_PPI mAccess = {\r
	192	&SmmAccessPeiOpen,\r
	193	&SmmAccessPeiClose,\r
	194	&SmmAccessPeiLock,\r
	195	&SmmAccessPeiGetCapabilities\r
	196	};\r
	197	\r
	198	STATIC EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {\r
	199	{\r
	200	EFI_PEI_PPI_DESCRIPTOR_PPI \| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
	201	&gPeiSmmAccessPpiGuid, &mAccess\r
	202	}\r
	203	};\r
	204	\r
	205	//\r
	206	// Utility functions.\r
	207	//\r
	208	STATIC\r
	209	UINT8\r
	210	CmosRead8 (\r
	211	IN UINT8 Index\r
	212	)\r
	213	{\r
	214	IoWrite8 (0x70, Index);\r
	215	return IoRead8 (0x71);\r
	216	}\r
	217	\r
	218	STATIC\r
	219	UINT32\r
	220	GetSystemMemorySizeBelow4gb (\r
	221	VOID\r
	222	)\r
	223	{\r
	224	UINT32 Cmos0x34;\r
	225	UINT32 Cmos0x35;\r
	226	\r
	227	Cmos0x34 = CmosRead8 (0x34);\r
	228	Cmos0x35 = CmosRead8 (0x35);\r
	229	\r
	230	return ((Cmos0x35 << 8 \| Cmos0x34) << 16) + SIZE_16MB;\r
	231	}\r
	232	\r
	233	//\r
	234	// Entry point of this driver.\r
	235	//\r
	236	EFI_STATUS\r
	237	EFIAPI\r
	238	SmmAccessPeiEntryPoint (\r
	239	IN EFI_PEI_FILE_HANDLE FileHandle,\r
	240	IN CONST EFI_PEI_SERVICES **PeiServices\r
	241	)\r
	242	{\r
	243	UINT16 HostBridgeDevId;\r
	244	UINT8 EsmramcVal;\r
	245	UINT8 RegMask8;\r
	246	UINT32 TopOfLowRam, TopOfLowRamMb;\r
	247	EFI_STATUS Status;\r
	248	UINTN SmramMapSize;\r
	249	EFI_SMRAM_DESCRIPTOR SmramMap[DescIdxCount];\r
	250	VOID *GuidHob;\r
	251	\r
	252	//\r
	253	// This module should only be included if SMRAM support is required.\r
	254	//\r
	255	ASSERT (FeaturePcdGet (PcdSmmSmramRequire));\r
	256	\r
	257	//\r
	258	// Verify if we're running on a Q35 machine type.\r
	259	//\r
	260	HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
	261	if (HostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {\r
	262	DEBUG ((\r
	263	DEBUG_ERROR,\r
	264	"%a: no SMRAM with host bridge DID=0x%04x; only "\r
	265	"DID=0x%04x (Q35) is supported\n",\r
	266	__FUNCTION__,\r
	267	HostBridgeDevId,\r
	268	INTEL_Q35_MCH_DEVICE_ID\r
	269	));\r
	270	goto WrongConfig;\r
	271	}\r
	272	\r
	273	//\r
	274	// Confirm if QEMU supports SMRAM.\r
	275	//\r
	276	// With no support for it, the ESMRAMC (Extended System Management RAM\r
	277	// Control) register reads as zero. If there is support, the cache-enable\r
	278	// bits are hard-coded as 1 by QEMU.\r
	279	//\r
	280	EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));\r
	281	RegMask8 = MCH_ESMRAMC_SM_CACHE \| MCH_ESMRAMC_SM_L1 \| MCH_ESMRAMC_SM_L2;\r
	282	if ((EsmramcVal & RegMask8) != RegMask8) {\r
	283	DEBUG ((\r
	284	DEBUG_ERROR,\r
	285	"%a: this Q35 implementation lacks SMRAM\n",\r
	286	__FUNCTION__\r
	287	));\r
	288	goto WrongConfig;\r
	289	}\r
	290	\r
	291	TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
	292	ASSERT ((TopOfLowRam & (SIZE_1MB - 1)) == 0);\r
	293	TopOfLowRamMb = TopOfLowRam >> 20;\r
	294	\r
	295	//\r
	296	// Some of the following registers are no-ops for QEMU at the moment, but it\r
	297	// is recommended to set them correctly, since the ESMRAMC that we ultimately\r
	298	// care about is in the same set of registers.\r
	299	//\r
	300	// First, we disable the integrated VGA, and set both the GTT Graphics Memory\r
	301	// Size and the Graphics Mode Select memory pre-allocation fields to zero.\r
	302	// This takes just one write to the Graphics Control Register.\r
	303	//\r
	304	PciWrite16 (DRAMC_REGISTER_Q35 (MCH_GGC), MCH_GGC_IVD);\r
	305	\r
	306	//\r
	307	// Set Top of Low Usable DRAM.\r
	308	//\r
	309	PciWrite16 (\r
	310	DRAMC_REGISTER_Q35 (MCH_TOLUD),\r
	311	(UINT16)(TopOfLowRamMb << MCH_TOLUD_MB_SHIFT)\r
	312	);\r
	313	\r
	314	//\r
	315	// Given the zero graphics memory sizes configured above, set the\r
	316	// graphics-related stolen memory bases to the same as TOLUD.\r
	317	//\r
	318	PciWrite32 (\r
	319	DRAMC_REGISTER_Q35 (MCH_GBSM),\r
	320	TopOfLowRamMb << MCH_GBSM_MB_SHIFT\r
	321	);\r
	322	PciWrite32 (\r
	323	DRAMC_REGISTER_Q35 (MCH_BGSM),\r
	324	TopOfLowRamMb << MCH_BGSM_MB_SHIFT\r
	325	);\r
	326	\r
	327	//\r
	328	// Set TSEG Memory Base.\r
	329	//\r
	330	InitQ35TsegMbytes ();\r
	331	PciWrite32 (\r
	332	DRAMC_REGISTER_Q35 (MCH_TSEGMB),\r
	333	(TopOfLowRamMb - mQ35TsegMbytes) << MCH_TSEGMB_MB_SHIFT\r
	334	);\r
	335	\r
	336	//\r
	337	// Set TSEG size, and disable TSEG visibility outside of SMM. Note that the\r
	338	// T_EN bit has inverse meaning; when T_EN is set, then TSEG visibility is\r
	339	// restricted to SMM.\r
	340	//\r
	341	EsmramcVal &= ~(UINT32)MCH_ESMRAMC_TSEG_MASK;\r
	342	EsmramcVal \|= mQ35TsegMbytes == 8 ? MCH_ESMRAMC_TSEG_8MB :\r
	343	mQ35TsegMbytes == 2 ? MCH_ESMRAMC_TSEG_2MB :\r
	344	mQ35TsegMbytes == 1 ? MCH_ESMRAMC_TSEG_1MB :\r
	345	MCH_ESMRAMC_TSEG_EXT;\r
	346	EsmramcVal \|= MCH_ESMRAMC_T_EN;\r
	347	PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal);\r
	348	\r
	349	//\r
	350	// TSEG should be closed (see above), but unlocked, initially. Set G_SMRAME\r
	351	// (Global SMRAM Enable) too, as both D_LCK and T_EN depend on it.\r
	352	//\r
	353	PciAndThenOr8 (\r
	354	DRAMC_REGISTER_Q35 (MCH_SMRAM),\r
	355	(UINT8)((~(UINT32)MCH_SMRAM_D_LCK) & 0xff),\r
	356	MCH_SMRAM_G_SMRAME\r
	357	);\r
	358	\r
	359	//\r
	360	// Create the GUID HOB and point it to the first SMRAM range.\r
	361	//\r
	362	GetStates (&mAccess.LockState, &mAccess.OpenState);\r
	363	SmramMapSize = sizeof SmramMap;\r
	364	Status = SmramAccessGetCapabilities (\r
	365	mAccess.LockState,\r
	366	mAccess.OpenState,\r
	367	&SmramMapSize,\r
	368	SmramMap\r
	369	);\r
	370	ASSERT_EFI_ERROR (Status);\r
	371	\r
	372	DEBUG_CODE_BEGIN ();\r
	373	{\r
	374	UINTN Count;\r
	375	UINTN Idx;\r
	376	\r
	377	Count = SmramMapSize / sizeof SmramMap[0];\r
	378	DEBUG ((\r
	379	DEBUG_VERBOSE,\r
	380	"%a: SMRAM map follows, %d entries\n",\r
	381	__FUNCTION__,\r
	382	(INT32)Count\r
	383	));\r
	384	DEBUG ((\r
	385	DEBUG_VERBOSE,\r
	386	"% 20a % 20a % 20a % 20a\n",\r
	387	"PhysicalStart(0x)",\r
	388	"PhysicalSize(0x)",\r
	389	"CpuStart(0x)",\r
	390	"RegionState(0x)"\r
	391	));\r
	392	for (Idx = 0; Idx < Count; ++Idx) {\r
	393	DEBUG ((\r
	394	DEBUG_VERBOSE,\r
	395	"% 20Lx % 20Lx % 20Lx % 20Lx\n",\r
	396	SmramMap[Idx].PhysicalStart,\r
	397	SmramMap[Idx].PhysicalSize,\r
	398	SmramMap[Idx].CpuStart,\r
	399	SmramMap[Idx].RegionState\r
	400	));\r
	401	}\r
	402	}\r
	403	DEBUG_CODE_END ();\r
	404	\r
	405	GuidHob = BuildGuidHob (\r
	406	&gEfiAcpiVariableGuid,\r
	407	sizeof SmramMap[DescIdxSmmS3ResumeState]\r
	408	);\r
	409	if (GuidHob == NULL) {\r
	410	return EFI_OUT_OF_RESOURCES;\r
	411	}\r
	412	\r
	413	CopyMem (\r
	414	GuidHob,\r
	415	&SmramMap[DescIdxSmmS3ResumeState],\r
	416	sizeof SmramMap[DescIdxSmmS3ResumeState]\r
	417	);\r
	418	\r
	419	//\r
	420	// SmramAccessLock() depends on "mQ35SmramAtDefaultSmbase"; init the latter\r
	421	// just before exposing the former via PEI_SMM_ACCESS_PPI.Lock().\r
	422	//\r
	423	InitQ35SmramAtDefaultSmbase ();\r
	424	\r
	425	//\r
	426	// We're done. The next step should succeed, but even if it fails, we can't\r
	427	// roll back the above BuildGuidHob() allocation, because PEI doesn't support\r
	428	// releasing memory.\r
	429	//\r
	430	return PeiServicesInstallPpi (mPpiList);\r
	431	\r
	432	WrongConfig:\r
	433	//\r
	434	// We really don't want to continue in this case.\r
	435	//\r
	436	ASSERT (FALSE);\r
	437	CpuDeadLoop ();\r
	438	return EFI_UNSUPPORTED;\r
	439	}\r