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1 | ## @file\r | |
2 | # Public definitions for PcAtChipset package.\r | |
3 | #\r | |
4 | # This package is designed to public interfaces and implementation which follows\r | |
5 | # PcAt defacto standard.\r | |
6 | #\r | |
7 | # Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r | |
8 | # Copyright (c) 2017, AMD Inc. All rights reserved.<BR>\r | |
9 | #\r | |
10 | # This program and the accompanying materials\r | |
11 | # are licensed and made available under the terms and conditions of the BSD License\r | |
12 | # which accompanies this distribution. The full text of the license may be found at\r | |
13 | # http://opensource.org/licenses/bsd-license.php\r | |
14 | #\r | |
15 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | #\r | |
18 | ##\r | |
19 | \r | |
20 | [Defines]\r | |
21 | DEC_SPECIFICATION = 0x00010005\r | |
22 | PACKAGE_NAME = PcAtChipsetPkg\r | |
23 | PACKAGE_UNI_FILE = PcAtChipsetPkg.uni\r | |
24 | PACKAGE_GUID = B728689A-52D3-4b8c-AE89-2CE5514CC6DC\r | |
25 | PACKAGE_VERSION = 0.3\r | |
26 | \r | |
27 | [Includes]\r | |
28 | Include\r | |
29 | \r | |
30 | [LibraryClasses]\r | |
31 | ## @libraryclass Provides functions to manage I/O APIC Redirection Table Entries.\r | |
32 | #\r | |
33 | IoApicLib|Include/Library/IoApicLib.h\r | |
34 | \r | |
35 | [Guids]\r | |
36 | gPcAtChipsetPkgTokenSpaceGuid = { 0x326ae723, 0xae32, 0x4589, { 0x98, 0xb8, 0xca, 0xc2, 0x3c, 0xdc, 0xc1, 0xb1 } }\r | |
37 | \r | |
38 | #\r | |
39 | # [Error.gPcAtChipsetPkgTokenSpaceGuid]\r | |
40 | # 0x80000001 | Invalid value provided.\r | |
41 | #\r | |
42 | \r | |
43 | [PcdsFeatureFlag]\r | |
44 | ## Indicates the HPET Timer will be configured to use MSI interrupts if the HPET timer supports them, or use I/O APIC interrupts.<BR><BR>\r | |
45 | # TRUE - Configures the HPET Timer to use MSI interrupts if the HPET Timer supports them.<BR>\r | |
46 | # FALSE - Configures the HPET Timer to use I/O APIC interrupts.<BR>\r | |
47 | # @Prompt Configure HPET to use MSI.\r | |
48 | gPcAtChipsetPkgTokenSpaceGuid.PcdHpetMsiEnable|TRUE|BOOLEAN|0x00001000\r | |
49 | \r | |
50 | [PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx, PcdsPatchableInModule]\r | |
51 | ## Pcd8259LegacyModeMask defines the default mask value for platform. This value is determined<BR><BR>\r | |
52 | # 1) If platform only support pure UEFI, value should be set to 0xFFFF or 0xFFFE;\r | |
53 | # Because only clock interrupt is allowed in legacy mode in pure UEFI platform.<BR>\r | |
54 | # 2) If platform install CSM and use thunk module:<BR>\r | |
55 | # a) If thunk call provided by CSM binary requires some legacy interrupt support, the corresponding bit\r | |
56 | # should be opened as 0.<BR>\r | |
57 | # For example, if keyboard interfaces provided CSM binary use legacy keyboard interrupt in 8259 bit 1, then\r | |
58 | # the value should be set to 0xFFFC.<BR>\r | |
59 | # b) If all thunk call provied by CSM binary do not require legacy interrupt support, value should be set\r | |
60 | # to 0xFFFF or 0xFFFE.<BR>\r | |
61 | #\r | |
62 | # The default value of legacy mode mask could be changed by EFI_LEGACY_8259_PROTOCOL->SetMask(). But it is rarely\r | |
63 | # need change it except some special cases such as when initializing the CSM binary, it should be set to 0xFFFF to\r | |
64 | # mask all legacy interrupt. Please restore the original legacy mask value if changing is made for these special case.<BR>\r | |
65 | # @Prompt 8259 Legacy Mode mask.\r | |
66 | gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0xFFFF|UINT16|0x00000001\r | |
67 | \r | |
68 | ## Pcd8259LegacyModeEdgeLevel defines the default edge level for legacy mode's interrrupt controller.\r | |
69 | # For the corresponding bits, 0 = Edge triggered and 1 = Level triggered.\r | |
70 | # @Prompt 8259 Legacy Mode edge level.\r | |
71 | gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel|0x0000|UINT16|0x00000002\r | |
72 | \r | |
73 | ## Indicates if we need enable IsaAcpiCom1 device.<BR><BR>\r | |
74 | # TRUE - Enables IsaAcpiCom1 device.<BR>\r | |
75 | # FALSE - Doesn't enable IsaAcpiCom1 device.<BR>\r | |
76 | # @Prompt Enable IsaAcpiCom1 device.\r | |
77 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiCom1Enable|TRUE|BOOLEAN|0x00000003\r | |
78 | \r | |
79 | ## Indicates if we need enable IsaAcpiCom2 device.<BR><BR>\r | |
80 | # TRUE - Enables IsaAcpiCom2 device.<BR>\r | |
81 | # FALSE - Doesn't enable IsaAcpiCom2 device.<BR>\r | |
82 | # @Prompt Enable IsaAcpiCom12 device.\r | |
83 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiCom2Enable|TRUE|BOOLEAN|0x00000004\r | |
84 | \r | |
85 | ## Indicates if we need enable IsaAcpiPs2Keyboard device.<BR><BR>\r | |
86 | # TRUE - Enables IsaAcpiPs2Keyboard device.<BR>\r | |
87 | # FALSE - Doesn't enable IsaAcpiPs2Keyboard device.<BR>\r | |
88 | # @Prompt Enable IsaAcpiPs2Keyboard device.\r | |
89 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiPs2KeyboardEnable|TRUE|BOOLEAN|0x00000005\r | |
90 | \r | |
91 | ## Indicates if we need enable IsaAcpiPs2Mouse device.<BR><BR>\r | |
92 | # TRUE - Enables IsaAcpiPs2Mouse device.<BR>\r | |
93 | # FALSE - Doesn't enable IsaAcpiPs2Mouse device.<BR>\r | |
94 | # @Prompt Enable IsaAcpiPs2Mouse device.\r | |
95 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiPs2MouseEnable|TRUE|BOOLEAN|0x00000006\r | |
96 | \r | |
97 | ## Indicates if we need enable IsaAcpiFloppyA device.<BR><BR>\r | |
98 | # TRUE - Enables IsaAcpiFloppyA device.<BR>\r | |
99 | # FALSE - Doesn't enable IsaAcpiFloppyA device.<BR>\r | |
100 | # @Prompt Enable IsaAcpiFloppyA device.\r | |
101 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiFloppyAEnable|TRUE|BOOLEAN|0x00000007\r | |
102 | \r | |
103 | ## Indicates if we need enable IsaAcpiFloppyB device.<BR><BR>\r | |
104 | # TRUE - Enables IsaAcpiFloppyB device.<BR>\r | |
105 | # FALSE - Doesn't enable IsaAcpiFloppyB device.<BR>\r | |
106 | # @Prompt Enable IsaAcpiFloppyB device.\r | |
107 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiFloppyBEnable|TRUE|BOOLEAN|0x00000008\r | |
108 | \r | |
109 | ## This PCD specifies the base address of the HPET timer.\r | |
110 | # @Prompt HPET base address.\r | |
111 | gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000|UINT32|0x00000009\r | |
112 | \r | |
113 | ## This PCD specifies the Local APIC Interrupt Vector for the HPET Timer.\r | |
114 | # @Prompt HPET local APIC vector.\r | |
115 | gPcAtChipsetPkgTokenSpaceGuid.PcdHpetLocalApicVector|0x40|UINT8|0x0000000A\r | |
116 | \r | |
117 | ## This PCD specifies the defaut period of the HPET Timer in 100 ns units.\r | |
118 | # The default value of 100000 100 ns units is the same as 10 ms.\r | |
119 | # @Prompt Default period of HPET timer.\r | |
120 | gPcAtChipsetPkgTokenSpaceGuid.PcdHpetDefaultTimerPeriod|100000|UINT64|0x0000000B\r | |
121 | \r | |
122 | ## This PCD specifies the base address of the IO APIC.\r | |
123 | # @Prompt IO APIC base address.\r | |
124 | gPcAtChipsetPkgTokenSpaceGuid.PcdIoApicBaseAddress|0xFEC00000|UINT32|0x0000000C\r | |
125 | \r | |
126 | ## This PCD specifies the minimal valid year in RTC.\r | |
127 | # @Prompt Minimal valid year in RTC.\r | |
128 | gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|1998|UINT16|0x0000000D\r | |
129 | \r | |
130 | ## This PCD specifies the maximal valid year in RTC.\r | |
131 | # @Prompt Maximal valid year in RTC.\r | |
132 | # @Expression 0x80000001 | gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear < gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear + 100\r | |
133 | gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2097|UINT16|0x0000000E\r | |
134 | \r | |
135 | [PcdsFixedAtBuild, PcdsPatchableInModule]\r | |
136 | ## Defines the ACPI register set base address.\r | |
137 | # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r | |
138 | # @Prompt ACPI Timer IO Port Address\r | |
139 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress |0xFFFF|UINT16|0x00000010\r | |
140 | \r | |
141 | ## Defines the PCI Bus Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r | |
142 | # @Prompt ACPI Hardware PCI Bus Number\r | |
143 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00| UINT8|0x00000011\r | |
144 | \r | |
145 | ## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r | |
146 | # The invalid 0xFF is as its default value. It must be configured to the real value.\r | |
147 | # @Prompt ACPI Hardware PCI Device Number\r | |
148 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0xFF| UINT8|0x00000012\r | |
149 | \r | |
150 | ## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r | |
151 | # The invalid 0xFF is as its default value. It must be configured to the real value.\r | |
152 | # @Prompt ACPI Hardware PCI Function Number\r | |
153 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0xFF| UINT8|0x00000013\r | |
154 | \r | |
155 | ## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers.\r | |
156 | # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r | |
157 | # @Prompt ACPI Hardware PCI Register Offset\r | |
158 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0xFFFF|UINT16|0x00000014\r | |
159 | \r | |
160 | ## Defines the bit mask that must be set to enable the APIC hardware register BAR.\r | |
161 | # @Prompt ACPI Hardware PCI Bar Enable BitMask\r | |
162 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x00| UINT8|0x00000015\r | |
163 | \r | |
164 | ## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers.\r | |
165 | # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r | |
166 | # @Prompt ACPI Hardware PCI Bar Register Offset\r | |
167 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0xFFFF|UINT16|0x00000016\r | |
168 | \r | |
169 | ## Defines the offset to the 32-bit Timer Value register that resides within the ACPI BAR.\r | |
170 | # @Prompt Offset to 32-bit Timer register in ACPI BAR\r | |
171 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008|UINT16|0x00000017\r | |
172 | \r | |
173 | ## Defines the bit mask to retrieve ACPI IO Port Base Address\r | |
174 | # @Prompt ACPI IO Port Base Address Mask\r | |
175 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask |0xFFFE|UINT16|0x00000018\r | |
176 | \r | |
177 | ## Reset Control Register address in I/O space.\r | |
178 | # @Prompt Reset Control Register address\r | |
179 | gPcAtChipsetPkgTokenSpaceGuid.PcdResetControlRegister|0x64|UINT64|0x00000019\r | |
180 | \r | |
181 | ## 8bit Reset Control Register value for cold reset.\r | |
182 | # @Prompt Reset Control Register value for cold reset\r | |
183 | gPcAtChipsetPkgTokenSpaceGuid.PcdResetControlValueColdReset|0xFE|UINT8|0x0000001A\r | |
184 | \r | |
185 | ## Specifies the initial value for Register_A in RTC.\r | |
186 | # @Prompt Initial value for Register_A in RTC.\r | |
187 | gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterA|0x26|UINT8|0x0000001B\r | |
188 | \r | |
189 | ## Specifies the initial value for Register_B in RTC.\r | |
190 | # @Prompt Initial value for Register_B in RTC.\r | |
191 | gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterB|0x02|UINT8|0x0000001C\r | |
192 | \r | |
193 | ## Specifies the initial value for Register_D in RTC.\r | |
194 | # @Prompt Initial value for Register_D in RTC.\r | |
195 | gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD|0x00|UINT8|0x0000001D\r | |
196 | \r | |
197 | ## Specifies RTC Index Register address in I/O space.\r | |
198 | # @Prompt RTC Index Register address\r | |
199 | gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|0x70|UINT8|0x0000001E\r | |
200 | \r | |
201 | ## Specifies RTC Target Register address in I/O space.\r | |
202 | # @Prompt RTC Target Register address\r | |
203 | gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x71|UINT8|0x0000001F\r | |
204 | \r | |
205 | [UserExtensions.TianoCore."ExtraFiles"]\r | |
206 | PcAtChipsetPkgExtra.uni\r |