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1 | /** @file\r | |
2 | PCI Host Bridge Definitions\r | |
3 | \r | |
4 | Copyright (c) 2013-2015 Intel Corporation.\r | |
5 | \r | |
6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
7 | \r | |
8 | **/\r | |
9 | \r | |
10 | \r | |
11 | Name(PBRS, ResourceTemplate() {\r | |
12 | WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses\r | |
13 | ResourceProducer, // bit 0 of general flags is 1\r | |
14 | MinFixed, // Range is fixed\r | |
15 | MaxFixed, // Range is fixed\r | |
16 | PosDecode, // PosDecode\r | |
17 | 0x0000, // Granularity\r | |
18 | 0x0000, // Min\r | |
19 | 0x001f, // Max\r | |
20 | 0x0000, // Translation\r | |
21 | 0x0020 // Range Length = Max-Min+1\r | |
22 | )\r | |
23 | \r | |
24 | WORDIO( //Consumed-and-produced resource (all I/O below CF8)\r | |
25 | ResourceProducer, // bit 0 of general flags is 0\r | |
26 | MinFixed, // Range is fixed\r | |
27 | MaxFixed, // Range is fixed\r | |
28 | PosDecode,\r | |
29 | EntireRange,\r | |
30 | 0x0000, // Granularity\r | |
31 | 0x0000, // Min\r | |
32 | 0x0cf7, // Max\r | |
33 | 0x0000, // Translation\r | |
34 | 0x0cf8 // Range Length\r | |
35 | )\r | |
36 | \r | |
37 | IO( //Consumed resource (CF8-CFF)\r | |
38 | Decode16,\r | |
39 | 0x0cf8,\r | |
40 | 0xcf8,\r | |
41 | 1,\r | |
42 | 8\r | |
43 | )\r | |
44 | \r | |
45 | WORDIO( //Consumed-and-produced resource (all I/O above CFF)\r | |
46 | ResourceProducer, // bit 0 of general flags is 0\r | |
47 | MinFixed, // Range is fixed\r | |
48 | MaxFixed, // Range is fixed\r | |
49 | PosDecode,\r | |
50 | EntireRange,\r | |
51 | 0x0000, // Granularity\r | |
52 | 0x0d00, // Min\r | |
53 | 0xffff, // Max\r | |
54 | 0x0000, // Translation\r | |
55 | 0xf300 // Range Length\r | |
56 | )\r | |
57 | \r | |
58 | DWORDMEMORY( // descriptor for dos area(0->0xa0000)\r | |
59 | ResourceProducer, // bit 0 of general flags is 0\r | |
60 | PosDecode,\r | |
61 | MinFixed, // Range is fixed\r | |
62 | MaxFixed, // Range is Fixed\r | |
63 | Cacheable,\r | |
64 | ReadWrite,\r | |
65 | 0x00000000, // Granularity\r | |
66 | 0x000a0000, // Min\r | |
67 | 0x000bffff, // Max\r | |
68 | 0x00000000, // Translation\r | |
69 | 0x00020000 // Range Length\r | |
70 | )\r | |
71 | \r | |
72 | DWORDMemory( // Consumed-and-produced resource for pci memory mapped memory\r | |
73 | ResourceProducer, // bit 0 of general flags is 0\r | |
74 | PosDecode, // positive Decode\r | |
75 | MinFixed, // Range is fixed\r | |
76 | MaxFixed, // Range is fixed\r | |
77 | Cacheable,\r | |
78 | ReadWrite,\r | |
79 | 0x00000000, // Granularity\r | |
80 | 0x00000000, // Min (calculated dynamically)\r | |
81 | \r | |
82 | 0xfebfffff, // Max = IO Apic base address - 1\r | |
83 | 0x00000000, // Translation\r | |
84 | 0xfec00000, // Range Length (calculated dynamically)\r | |
85 | , // Optional field left blank\r | |
86 | , // Optional field left blank\r | |
87 | MEM1 // Name declaration for this descriptor\r | |
88 | )\r | |
89 | \r | |
90 | }) // end of CRES Buffer\r | |
91 | \r | |
92 | \r | |
93 | Method(_CRS, 0x0, NotSerialized)\r | |
94 | {\r | |
95 | CreateDWordField(PBRS, \_SB.PCI0.MEM1._MIN, MMIN)\r | |
96 | CreateDWordField(PBRS, \_SB.PCI0.MEM1._MAX, MMAX)\r | |
97 | CreateDWordField(PBRS, \_SB.PCI0.MEM1._LEN, MLEN)\r | |
98 | \r | |
99 | // HMBOUND is PCI memory base\r | |
100 | And(MNRD(0x03, 0x08), 0xFFFFF000, MMIN)\r | |
101 | Add(Subtract(MMAX, MMIN), 1, MLEN)\r | |
102 | \r | |
103 | Return(PBRS)\r | |
104 | }\r | |
105 | \r | |
106 | // Message Nework Registers\r | |
107 | OperationRegion(MNR, PCI_Config, 0xD0, 0x10)\r | |
108 | Field(MNR, DWordAcc, NoLock, Preserve)\r | |
109 | {\r | |
110 | MCR, 32, // Message Control Register\r | |
111 | MDR, 32 // Message Data Register\r | |
112 | }\r | |
113 | \r | |
114 | // Message Nework Read Method\r | |
115 | // Arg0 = Port\r | |
116 | // Arg1 = RegAddress\r | |
117 | // return 32 bit register value\r | |
118 | Method(MNRD, 2, Serialized)\r | |
119 | {\r | |
120 | Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)\r | |
121 | Or(Local0, 0x100000F0, Local0)\r | |
122 | Store(Local0, MCR)\r | |
123 | Return(MDR)\r | |
124 | }\r | |
125 | \r | |
126 | // Message Nework Write Method\r | |
127 | // Arg0 = Port\r | |
128 | // Arg1 = RegAddress\r | |
129 | // Arg2 = 32 bit write value\r | |
130 | Method(MNWR, 3, Serialized)\r | |
131 | {\r | |
132 | Store(Arg2, MDR)\r | |
133 | Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)\r | |
134 | Or(Local0, 0x110000F0, Local0)\r | |
135 | Store(Local0, MCR)\r | |
136 | }\r | |
137 | \r | |
138 | Method(_PRT, 0, NotSerialized)\r | |
139 | {\r | |
140 | If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing\r | |
141 | {\r | |
142 | Return (\r | |
143 | Package()\r | |
144 | {\r | |
145 | // Bus 0, Device 20 - IOSFAHB Bridge\r | |
146 | Package() {0x0014ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA\r | |
147 | Package() {0x0014ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB\r | |
148 | Package() {0x0014ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC\r | |
149 | Package() {0x0014ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD\r | |
150 | \r | |
151 | // Bus 0, Device 21 - IOSFAHB Bridge\r | |
152 | Package() {0x0015ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA\r | |
153 | Package() {0x0015ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB\r | |
154 | Package() {0x0015ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC\r | |
155 | Package() {0x0015ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD\r | |
156 | \r | |
157 | // Bus 0, Device 23 - PCIe port 0\r | |
158 | Package() {0x0017ffff, 0, \_SB.PCI0.LPC.LNKE, 0}, // INTA\r | |
159 | Package() {0x0017ffff, 1, \_SB.PCI0.LPC.LNKF, 0}, // INTB\r | |
160 | Package() {0x0017ffff, 2, \_SB.PCI0.LPC.LNKG, 0}, // INTC\r | |
161 | Package() {0x0017ffff, 3, \_SB.PCI0.LPC.LNKH, 0}, // INTD\r | |
162 | \r | |
163 | // Bus 0, Device 31\r | |
164 | Package() {0x001fffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // LPC Bridge\r | |
165 | }\r | |
166 | )\r | |
167 | }\r | |
168 | else {\r | |
169 | Return (\r | |
170 | Package()\r | |
171 | {\r | |
172 | // Bus 0, Device 20 - IOSFAHB Bridge\r | |
173 | Package() {0x0014ffff, 0, 0, 16}, // INTA\r | |
174 | Package() {0x0014ffff, 1, 0, 17}, // INTB\r | |
175 | Package() {0x0014ffff, 2, 0, 18}, // INTC\r | |
176 | Package() {0x0014ffff, 3, 0, 19}, // INTD\r | |
177 | \r | |
178 | // Bus 0, Device 21 - IOSFAHB Bridge\r | |
179 | Package() {0x0015ffff, 0, 0, 16}, // INTA\r | |
180 | Package() {0x0015ffff, 1, 0, 17}, // INTB\r | |
181 | Package() {0x0015ffff, 2, 0, 18}, // INTC\r | |
182 | Package() {0x0015ffff, 3, 0, 19}, // INTD\r | |
183 | \r | |
184 | // Bus 0, Device 23 - PCIe port 0\r | |
185 | Package() {0x0017ffff, 0, 0, 20}, // INTA\r | |
186 | Package() {0x0017ffff, 1, 0, 21}, // INTB\r | |
187 | Package() {0x0017ffff, 2, 0, 22}, // INTC\r | |
188 | Package() {0x0017ffff, 3, 0, 23}, // INTD\r | |
189 | \r | |
190 | // Bus 0, Device 31\r | |
191 | Package() {0x001fffff, 0, 0, 16}, // LPC Bridge\r | |
192 | }\r | |
193 | )\r | |
194 | }\r | |
195 | }\r |