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1 | ## @file\r | |
2 | # FDF file of Clanton Peak CRB platform with 32-bit DXE\r | |
3 | #\r | |
4 | # This package provides QuarkNcSocId platform specific modules.\r | |
5 | # Copyright (c) 2013 - 2018 Intel Corporation.\r | |
6 | #\r | |
7 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
8 | #\r | |
9 | ##\r | |
10 | \r | |
11 | ################################################################################\r | |
12 | #\r | |
13 | # Defines Section - statements that will be processed to create a Makefile.\r | |
14 | #\r | |
15 | ################################################################################\r | |
16 | [Defines]\r | |
17 | # Address 0x100000000 (4 GB reset address)\r | |
18 | # Base Size\r | |
19 | # +---------------------------+\r | |
20 | # FLASH_BASE | FD.Quark: | 0x800000 (8 MB)\r | |
21 | # 0xFF800000 | BaseAddress |\r | |
22 | # +---------------------------+\r | |
23 | #\r | |
24 | # Flash offsets are 0 based, but are relative to FD.Quark BaseAddress, e.g. Payload Base is at 0x400000, Flash Base is at 0xFF800000 for 8 MB SPI part.\r | |
25 | # 0xFF800000 + 0x400000 = 0xFFC00000.\r | |
26 | #\r | |
27 | # Address 0x0 (0xFF800000 for 8 MB SPI part)\r | |
28 | # +---------------------------+\r | |
29 | # FLASH_FV_PAYLOAD_BASE | Payload Image | FLASH_FV_PAYLOAD_SIZE\r | |
30 | # 0x00400000 | | 0x00100000\r | |
31 | # +---------------------------+\r | |
32 | # FLASH_FV_MAIN_BASE | FvMain Image (Compressed) | FLASH_FV_MAIN_SIZE\r | |
33 | # 0x00500000 | | 0x001E0000\r | |
34 | # +---------------------------+\r | |
35 | # NVRAM_AREA_BASE | NVRAM Area= | NVRAM_AREA_SIZE\r | |
36 | # 0x006E0000 | Variable + FTW Working + |\r | |
37 | # | FTW Spare |\r | |
38 | # +---+-------------------+---+\r | |
39 | # NVRAM_AREA_VARIABLE_BASE | | NVRAM_AREA_VARIABLE_SIZE\r | |
40 | # | |\r | |
41 | # +-------------------+\r | |
42 | # FTW_WORKING_BASE | | FTW_WORKING_SIZE\r | |
43 | # | |\r | |
44 | # +-------------------+\r | |
45 | # FTW_SPARE_BASE | | FTW_SPARE_SIZE\r | |
46 | # | |\r | |
47 | # +---+-------------------+---+\r | |
48 | # RMU_BINARY_BASE | RMU Binary | RMU_BINARY_SIZE\r | |
49 | # 0x00700000 | | 0x00008000\r | |
50 | # +---------------------------+\r | |
51 | # PLATFORM_DATA_BASE | PlatformData Binary | PLATFORM_DATA_SIZE\r | |
52 | # 0x00710000 | | 0x00001000\r | |
53 | # +---------------------------+\r | |
54 | # FVRECOVERY_IMAGE_BASE | FVRECOVERY Image | FVRECOVERY_IMAGE_SIZE\r | |
55 | # 0x720000 | | 0x000E0000\r | |
56 | # +---------------------------+\r | |
57 | \r | |
58 | #\r | |
59 | # Define value used to compute FLASH regions below reset vector location just below 4GB\r | |
60 | #\r | |
61 | DEFINE RESET_ADDRESS = 0x100000000 # 4 GB\r | |
62 | \r | |
63 | #\r | |
64 | # Set size of FLASH to 8MB\r | |
65 | #\r | |
66 | DEFINE FLASH_SIZE = 0x800000\r | |
67 | DEFINE FLASH_BASE = $(RESET_ADDRESS) - $(FLASH_SIZE) # The base address of the Flash Device\r | |
68 | \r | |
69 | #\r | |
70 | # Set FLASH block size to 4KB\r | |
71 | #\r | |
72 | DEFINE FLASH_BLOCKSIZE = 0x1000 # 4 KB\r | |
73 | \r | |
74 | #\r | |
75 | # Misc settings\r | |
76 | #\r | |
77 | DEFINE FLASH_BLOCKSIZE_DATA = 0x00, 0x10, 0x00, 0x00 # equivalent for DATA blocks\r | |
78 | \r | |
79 | #\r | |
80 | # Start PAYLOAD at 4MB into 8MB FLASH\r | |
81 | #\r | |
82 | DEFINE FLASH_FV_PAYLOAD_BASE = 0x00400000\r | |
83 | DEFINE FLASH_FV_PAYLOAD_SIZE = 0x00100000\r | |
84 | \r | |
85 | #\r | |
86 | # Put FVMAIN between PAYLOAD and RMU Binary\r | |
87 | #\r | |
88 | DEFINE FLASH_FV_MAIN_BASE = 0x00500000\r | |
89 | DEFINE FLASH_FV_MAIN_SIZE = 0x001E0000\r | |
90 | \r | |
91 | #\r | |
92 | # Place NV Storage just above Platform Data Base\r | |
93 | #\r | |
94 | DEFINE NVRAM_AREA_VARIABLE_BASE = 0x006E0000\r | |
95 | DEFINE NVRAM_AREA_SIZE = 0x00020000\r | |
96 | \r | |
97 | DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x0000E000\r | |
98 | DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)\r | |
99 | DEFINE FTW_WORKING_SIZE = 0x00002000\r | |
100 | DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)\r | |
101 | DEFINE FTW_SPARE_SIZE = $(NVRAM_AREA_SIZE) - $(NVRAM_AREA_VARIABLE_SIZE) - $(FTW_WORKING_SIZE)\r | |
102 | \r | |
103 | #\r | |
104 | # RMU Binary must be at fixed address 1MB below 4GB (0xFFF00000)\r | |
105 | #\r | |
106 | DEFINE RMU_BINARY_BASE = 0x00700000 # HW fixed address\r | |
107 | DEFINE RMU_BINARY_SIZE = 0x00008000 # HW fixed address, so fixed size\r | |
108 | \r | |
109 | #\r | |
110 | # Platform Data Base must be 64KB above RMU\r | |
111 | #\r | |
112 | DEFINE VPD_BASE = 0x00708000\r | |
113 | DEFINE VPD_SIZE = 0x00001000\r | |
114 | \r | |
115 | #\r | |
116 | # Place FV Recovery above NV Storage\r | |
117 | #\r | |
118 | DEFINE FVRECOVERY_IMAGE_SIZE = 0x000F0000\r | |
119 | DEFINE FVRECOVERY_IMAGE_BASE = $(FLASH_SIZE) - $(FVRECOVERY_IMAGE_SIZE)\r | |
120 | \r | |
121 | ################################################################################\r | |
122 | #\r | |
123 | # FD Section\r | |
124 | # The [FD] Section is made up of the definition statements and a\r | |
125 | # description of what goes into the Flash Device Image. Each FD section\r | |
126 | # defines one flash "device" image. A flash device image may be one of\r | |
127 | # the following: Removable media bootable image (like a boot floppy\r | |
128 | # image,) an Option ROM image (that would be "flashed" into an add-in\r | |
129 | # card,) a System "Flash" image (that would be burned into a system's\r | |
130 | # flash) or an Update ("Capsule") image that will be used to update and\r | |
131 | # existing system flash.\r | |
132 | #\r | |
133 | ################################################################################\r | |
134 | [FD.Quark]\r | |
135 | BaseAddress = 0xFF800000 #The base address of the Flash Device; set to same value as FLASH_BASE.\r | |
136 | Size = 0x800000 #The size in bytes of the Flash Device; set to same value as FLASH_SIZE.\r | |
137 | ErasePolarity = 1\r | |
138 | BlockSize = $(FLASH_BLOCKSIZE)\r | |
139 | NumBlocks = 0x800 #The number of blocks for the Flash Device.\r | |
140 | \r | |
141 | SET gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress = $(FLASH_BASE)\r | |
142 | SET gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize = $(FLASH_SIZE)\r | |
143 | \r | |
144 | ################################################################################\r | |
145 | #\r | |
146 | # Following are lists of FD Region layout which correspond to the locations of different\r | |
147 | # images within the flash device.\r | |
148 | #\r | |
149 | # Regions must be defined in ascending order and may not overlap.\r | |
150 | #\r | |
151 | # A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r | |
152 | # the pipe "|" character, followed by the size of the region, also in hex with the leading\r | |
153 | # "0x" characters. Like:\r | |
154 | # Offset|Size\r | |
155 | # PcdOffsetCName|PcdSizeCName\r | |
156 | # RegionType <FV, DATA, or FILE>\r | |
157 | #\r | |
158 | ################################################################################\r | |
159 | \r | |
160 | ########################################################\r | |
161 | # Quark Payload Image\r | |
162 | ########################################################\r | |
163 | $(FLASH_FV_PAYLOAD_BASE)|$(FLASH_FV_PAYLOAD_SIZE)\r | |
164 | gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase|gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize\r | |
165 | FV = PAYLOAD\r | |
166 | \r | |
167 | ########################################################\r | |
168 | # Quark FVMAIN Image (Compressed)\r | |
169 | ########################################################\r | |
170 | $(FLASH_FV_MAIN_BASE)|$(FLASH_FV_MAIN_SIZE)\r | |
171 | gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase|gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize\r | |
172 | FV = FVMAIN_COMPACT\r | |
173 | \r | |
174 | #############################################################################\r | |
175 | # Quark NVRAM Area\r | |
176 | # Quark NVRAM Area contains: Variable + FTW Working + FTW Spare\r | |
177 | #############################################################################\r | |
178 | $(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)\r | |
179 | gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r | |
180 | #NV_VARIABLE_STORE\r | |
181 | DATA = {\r | |
182 | ## This is the EFI_FIRMWARE_VOLUME_HEADER\r | |
183 | # ZeroVector []\r | |
184 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r | |
185 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r | |
186 | # FileSystemGuid: gEfiSystemNvDataFvGuid =\r | |
187 | # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}\r | |
188 | 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,\r | |
189 | 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,\r | |
190 | # FvLength: 0x20000\r | |
191 | 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,\r | |
192 | #Signature "_FVH" #Attributes\r | |
193 | 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,\r | |
194 | #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision\r | |
195 | 0x48, 0x00, 0x19, 0xF9, 0x00, 0x00, 0x00, 0x02,\r | |
196 | #Blockmap[0]: 32 Blocks * 0x1000 Bytes / Block\r | |
197 | 0x20, 0x00, 0x00, 0x00, $(FLASH_BLOCKSIZE_DATA),\r | |
198 | #Blockmap[1]: End\r | |
199 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r | |
200 | ## This is the VARIABLE_STORE_HEADER\r | |
201 | !if $(SECURE_BOOT_ENABLE)\r | |
202 | # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 } }\r | |
203 | 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,\r | |
204 | 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,\r | |
205 | !else\r | |
206 | # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}\r | |
207 | 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,\r | |
208 | 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,\r | |
209 | !endif\r | |
210 | #Size: 0x0E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x0DFB8\r | |
211 | # This can speed up the Variable Dispatch a bit.\r | |
212 | 0xB8, 0xDF, 0x00, 0x00,\r | |
213 | #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32\r | |
214 | 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\r | |
215 | }\r | |
216 | \r | |
217 | $(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)\r | |
218 | gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize\r | |
219 | #NV_FTW_WORKING\r | |
220 | DATA = {\r | |
221 | # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =\r | |
222 | # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}\r | |
223 | 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,\r | |
224 | 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,\r | |
225 | # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved\r | |
226 | 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,\r | |
227 | # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0\r | |
228 | 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\r | |
229 | }\r | |
230 | \r | |
231 | $(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)\r | |
232 | gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize\r | |
233 | #NV_FTW_SPARE\r | |
234 | \r | |
235 | #########################################################\r | |
236 | # Quark Remote Management Unit Binary\r | |
237 | #########################################################\r | |
238 | $(RMU_BINARY_BASE)|$(RMU_BINARY_SIZE)\r | |
239 | INF QuarkSocBinPkg/QuarkNorthCluster/Binary/QuarkMicrocode/QuarkMicrocode.inf\r | |
240 | \r | |
241 | #########################################################\r | |
242 | # PlatformData Binary, default for standalone is none built-in so user selects.\r | |
243 | #########################################################\r | |
244 | $(VPD_BASE)|$(VPD_SIZE)\r | |
245 | gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress\r | |
246 | FILE = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-850A-24F7A8D38E08.bin\r | |
247 | \r | |
248 | #######################\r | |
249 | # Quark FVRECOVERY Image\r | |
250 | #######################\r | |
251 | $(FVRECOVERY_IMAGE_BASE)|$(FVRECOVERY_IMAGE_SIZE)\r | |
252 | gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase|gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize\r | |
253 | FV = FVRECOVERY\r | |
254 | \r | |
255 | ################################################################################\r | |
256 | #\r | |
257 | # FV Section\r | |
258 | #\r | |
259 | # [FV] section is used to define what components or modules are placed within a flash\r | |
260 | # device file. This section also defines order the components and modules are positioned\r | |
261 | # within the image. The [FV] section consists of define statements, set statements and\r | |
262 | # module statements.\r | |
263 | #\r | |
264 | ################################################################################\r | |
265 | [FV.FVRECOVERY]\r | |
266 | BlockSize = $(FLASH_BLOCKSIZE)\r | |
267 | FvAlignment = 16 #FV alignment and FV attributes setting.\r | |
268 | ERASE_POLARITY = 1\r | |
269 | MEMORY_MAPPED = TRUE\r | |
270 | STICKY_WRITE = TRUE\r | |
271 | LOCK_CAP = TRUE\r | |
272 | LOCK_STATUS = TRUE\r | |
273 | WRITE_DISABLED_CAP = TRUE\r | |
274 | WRITE_ENABLED_CAP = TRUE\r | |
275 | WRITE_STATUS = TRUE\r | |
276 | WRITE_LOCK_CAP = TRUE\r | |
277 | WRITE_LOCK_STATUS = TRUE\r | |
278 | READ_DISABLED_CAP = TRUE\r | |
279 | READ_ENABLED_CAP = TRUE\r | |
280 | READ_STATUS = TRUE\r | |
281 | READ_LOCK_CAP = TRUE\r | |
282 | READ_LOCK_STATUS = TRUE\r | |
283 | FvNameGuid = 18D6D9F4-2EEF-4913-AEE6-BE61C6DA6CC8\r | |
284 | \r | |
285 | ################################################################################\r | |
286 | #\r | |
287 | # The INF statements point to EDK component and EDK II module INF files, which will be placed into this FV image.\r | |
288 | # Parsing tools will scan the INF file to determine the type of component or module.\r | |
289 | # The component or module type is used to reference the standard rules\r | |
290 | # defined elsewhere in the FDF file.\r | |
291 | #\r | |
292 | # The format for INF statements is:\r | |
293 | # INF $(PathAndInfFileName)\r | |
294 | #\r | |
295 | ################################################################################\r | |
296 | \r | |
297 | ##\r | |
298 | # PEI Apriori file example, more PEIM module added later.\r | |
299 | ##\r | |
300 | APRIORI PEI {\r | |
301 | INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r | |
302 | # PlatformConfigPei should be immediately after Pcd driver.\r | |
303 | INF QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf\r | |
304 | INF MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf\r | |
305 | INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf\r | |
306 | INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf\r | |
307 | }\r | |
308 | \r | |
309 | ##\r | |
310 | # SEC Phase modules\r | |
311 | ##\r | |
312 | INF UefiCpuPkg/SecCore/SecCore.inf\r | |
313 | \r | |
314 | !if $(CAPSULE_ENABLE) || $(RECOVERY_ENABLE)\r | |
315 | # FMP image decriptor\r | |
316 | INF RuleOverride = FMP_IMAGE_DESC QuarkPlatformPkg/Feature/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf\r | |
317 | !endif\r | |
318 | \r | |
319 | INF MdeModulePkg/Core/Pei/PeiMain.inf\r | |
320 | \r | |
321 | ##\r | |
322 | # PEI Phase RAW Data files.\r | |
323 | ##\r | |
324 | FILE FREEFORM = PCD(gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkMicrocodeFile) {\r | |
325 | SECTION RAW = QuarkSocBinPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin\r | |
326 | }\r | |
327 | \r | |
328 | INF RuleOverride = NORELOC MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r | |
329 | INF QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf\r | |
330 | INF RuleOverride = NORELOC MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf\r | |
331 | INF RuleOverride = NORELOC MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf\r | |
332 | INF RuleOverride = NORELOC MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf\r | |
333 | INF RuleOverride = NORELOC MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r | |
334 | INF RuleOverride = NORELOC UefiCpuPkg/CpuMpPei/CpuMpPei.inf\r | |
335 | INF RuleOverride = NORELOC MdeModulePkg/Universal/CapsulePei/CapsulePei.inf\r | |
336 | INF RuleOverride = NORELOC QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/MemoryInitPei.inf\r | |
337 | INF RuleOverride = NORELOC QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmAccessPei/SmmAccessPei.inf\r | |
338 | INF RuleOverride = NORELOC QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmControlPei/SmmControlPei.inf\r | |
339 | INF QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf\r | |
340 | INF MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf\r | |
341 | INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r | |
342 | INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf\r | |
343 | INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf\r | |
344 | !if $(MEASURED_BOOT_ENABLE)\r | |
345 | INF SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigPei.inf\r | |
346 | INF SecurityPkg/Tcg/TcgPei/TcgPei.inf\r | |
347 | !endif\r | |
348 | \r | |
349 | !if $(RECOVERY_ENABLE)\r | |
350 | FILE FV_IMAGE = 1E9D7604-EF45-46a0-BD8A-71AC78C17AC1 {\r | |
351 | SECTION PEI_DEPEX_EXP = {gEfiPeiMemoryDiscoveredPpiGuid AND gEfiPeiBootInRecoveryModePpiGuid}\r | |
352 | SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779 { # TIANO COMPRESS GUID\r | |
353 | SECTION FV_IMAGE = FVRECOVERY_COMPONENTS\r | |
354 | }\r | |
355 | }\r | |
356 | !endif\r | |
357 | \r | |
358 | !if $(RECOVERY_ENABLE)\r | |
359 | \r | |
360 | ################################################################################\r | |
361 | #\r | |
362 | # FV Section\r | |
363 | #\r | |
364 | # [FV] section is used to define what components or modules are placed within a flash\r | |
365 | # device file. This section also defines order the components and modules are positioned\r | |
366 | # within the image. The [FV] section consists of define statements, set statements and\r | |
367 | # module statements.\r | |
368 | #\r | |
369 | ################################################################################\r | |
370 | [FV.FVRECOVERY_COMPONENTS]\r | |
371 | BlockSize = $(FLASH_BLOCKSIZE)\r | |
372 | FvAlignment = 16 #FV alignment and FV attributes setting.\r | |
373 | ERASE_POLARITY = 1\r | |
374 | MEMORY_MAPPED = TRUE\r | |
375 | STICKY_WRITE = TRUE\r | |
376 | LOCK_CAP = TRUE\r | |
377 | LOCK_STATUS = TRUE\r | |
378 | WRITE_DISABLED_CAP = TRUE\r | |
379 | WRITE_ENABLED_CAP = TRUE\r | |
380 | WRITE_STATUS = TRUE\r | |
381 | WRITE_LOCK_CAP = TRUE\r | |
382 | WRITE_LOCK_STATUS = TRUE\r | |
383 | READ_DISABLED_CAP = TRUE\r | |
384 | READ_ENABLED_CAP = TRUE\r | |
385 | READ_STATUS = TRUE\r | |
386 | READ_LOCK_CAP = TRUE\r | |
387 | READ_LOCK_STATUS = TRUE\r | |
388 | \r | |
389 | INF QuarkSocPkg/QuarkSouthCluster/Usb/Common/Pei/UsbPei.inf\r | |
390 | INF MdeModulePkg/Bus/Pci/EhciPei/EhciPei.inf\r | |
391 | INF QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/OhciPei.inf\r | |
392 | INF MdeModulePkg/Bus/Usb/UsbBusPei/UsbBusPei.inf\r | |
393 | INF MdeModulePkg/Bus/Usb/UsbBotPei/UsbBotPei.inf\r | |
394 | INF FatPkg/FatPei/FatPei.inf\r | |
395 | INF MdeModulePkg/Universal/Disk/CdExpressPei/CdExpressPei.inf\r | |
396 | INF SignedCapsulePkg/Universal/RecoveryModuleLoadPei/RecoveryModuleLoadPei.inf\r | |
397 | \r | |
398 | !endif\r | |
399 | \r | |
400 | ################################################################################\r | |
401 | #\r | |
402 | # FV Section\r | |
403 | #\r | |
404 | # [FV] section is used to define what components or modules are placed within a flash\r | |
405 | # device file. This section also defines order the components and modules are positioned\r | |
406 | # within the image. The [FV] section consists of define statements, set statements and\r | |
407 | # module statements.\r | |
408 | #\r | |
409 | ################################################################################\r | |
410 | [FV.FVMAIN]\r | |
411 | BlockSize = $(FLASH_BLOCKSIZE)\r | |
412 | FvAlignment = 16\r | |
413 | ERASE_POLARITY = 1\r | |
414 | MEMORY_MAPPED = TRUE\r | |
415 | STICKY_WRITE = TRUE\r | |
416 | LOCK_CAP = TRUE\r | |
417 | LOCK_STATUS = TRUE\r | |
418 | WRITE_DISABLED_CAP = TRUE\r | |
419 | WRITE_ENABLED_CAP = TRUE\r | |
420 | WRITE_STATUS = TRUE\r | |
421 | WRITE_LOCK_CAP = TRUE\r | |
422 | WRITE_LOCK_STATUS = TRUE\r | |
423 | READ_DISABLED_CAP = TRUE\r | |
424 | READ_ENABLED_CAP = TRUE\r | |
425 | READ_STATUS = TRUE\r | |
426 | READ_LOCK_CAP = TRUE\r | |
427 | READ_LOCK_STATUS = TRUE\r | |
428 | FvNameGuid = 30D9ED01-38D2-418a-90D5-C561750BF80F\r | |
429 | \r | |
430 | ##\r | |
431 | # DXE Phase modules\r | |
432 | ##\r | |
433 | INF MdeModulePkg/Core/Dxe/DxeMain.inf\r | |
434 | INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r | |
435 | \r | |
436 | !if $(SOURCE_DEBUG_ENABLE)\r | |
437 | INF SourceLevelDebugPkg/DebugAgentDxe/DebugAgentDxe.inf\r | |
438 | !endif\r | |
439 | \r | |
440 | #\r | |
441 | # Early SoC / Platform modules\r | |
442 | #\r | |
443 | INF QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf\r | |
444 | \r | |
445 | ##\r | |
446 | # EDK Core modules\r | |
447 | ##\r | |
448 | INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf\r | |
449 | INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf\r | |
450 | INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf\r | |
451 | INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf\r | |
452 | INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf\r | |
453 | INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf\r | |
454 | \r | |
455 | INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r | |
456 | INF UefiCpuPkg/CpuDxe/CpuDxe.inf\r | |
457 | INF MdeModulePkg/Universal/Metronome/Metronome.inf\r | |
458 | INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r | |
459 | INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r | |
460 | INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf\r | |
461 | !if $(SECURE_BOOT_ENABLE)\r | |
462 | INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf\r | |
463 | !endif\r | |
464 | INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf\r | |
465 | INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf\r | |
466 | INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r | |
467 | INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r | |
468 | INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf\r | |
469 | INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf\r | |
470 | INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r | |
471 | INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf\r | |
472 | \r | |
473 | #\r | |
474 | # Platform\r | |
475 | #\r | |
476 | INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf\r | |
477 | INF MdeModulePkg/Application/UiApp/UiApp.inf\r | |
478 | \r | |
479 | INF QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.inf\r | |
480 | INF QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSpi.inf\r | |
481 | INF QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSmmSpi.inf\r | |
482 | INF QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/QNCInitDxe.inf\r | |
483 | INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf\r | |
484 | INF QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmAccessDxe/SmmAccess.inf\r | |
485 | INF QuarkSocPkg/QuarkNorthCluster/S3Support/Dxe/QncS3Support.inf\r | |
486 | INF QuarkSocPkg/QuarkNorthCluster/Spi/PchSpiRuntime.inf\r | |
487 | INF QuarkSocPkg/QuarkNorthCluster/Spi/PchSpiSmm.inf\r | |
488 | INF QuarkPlatformPkg/Platform/Dxe/Setup/DxePlatform.inf\r | |
489 | \r | |
490 | #\r | |
491 | # ACPI\r | |
492 | #\r | |
493 | INF QuarkPlatformPkg/Platform/Dxe/SaveMemoryConfig/SaveMemoryConfig.inf\r | |
494 | INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf\r | |
495 | #INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf\r | |
496 | INF QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/BootScriptExecutorDxe.inf\r | |
497 | INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r | |
498 | INF IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf\r | |
499 | INF QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf\r | |
500 | INF RuleOverride = ACPITABLE QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf\r | |
501 | \r | |
502 | #\r | |
503 | # SMM\r | |
504 | #\r | |
505 | INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf\r | |
506 | INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf\r | |
507 | INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf\r | |
508 | INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf\r | |
509 | INF QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmControlDxe/SmmControlDxe.inf\r | |
510 | INF QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNCSmmDispatcher.inf\r | |
511 | INF QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.inf\r | |
512 | INF QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.inf\r | |
513 | INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf\r | |
514 | INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf\r | |
515 | \r | |
516 | #\r | |
517 | # SMBIOS\r | |
518 | #\r | |
519 | INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf\r | |
520 | INF QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscDxe.inf\r | |
521 | INF QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.inf\r | |
522 | \r | |
523 | #\r | |
524 | # PCI\r | |
525 | #\r | |
526 | INF QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.inf\r | |
527 | INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r | |
528 | INF QuarkSocPkg/QuarkSouthCluster/IohInit/Dxe/IohInitDxe.inf\r | |
529 | !if $(SOURCE_DEBUG_ENABLE)\r | |
530 | !else\r | |
531 | INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf\r | |
532 | !endif\r | |
533 | \r | |
534 | #\r | |
535 | # USB\r | |
536 | #\r | |
537 | !if $(PERFORMANCE_ENABLE)\r | |
538 | !else\r | |
539 | INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r | |
540 | INF QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciDxe.inf\r | |
541 | INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r | |
542 | INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf\r | |
543 | INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf\r | |
544 | INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf\r | |
545 | !endif\r | |
546 | \r | |
547 | #\r | |
548 | # SDIO\r | |
549 | #\r | |
550 | !if $(PERFORMANCE_ENABLE)\r | |
551 | !else\r | |
552 | INF QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDControllerDxe.inf\r | |
553 | INF QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/SDMediaDeviceDxe.inf\r | |
554 | !endif\r | |
555 | \r | |
556 | #\r | |
557 | # Console\r | |
558 | #\r | |
559 | INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r | |
560 | INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r | |
561 | INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r | |
562 | \r | |
563 | INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r | |
564 | INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r | |
565 | INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r | |
566 | INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r | |
567 | \r | |
568 | #\r | |
569 | # File System Modules\r | |
570 | #\r | |
571 | !if $(PERFORMANCE_ENABLE)\r | |
572 | !else\r | |
573 | INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r | |
574 | INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r | |
575 | INF FatPkg/EnhancedFatDxe/Fat.inf\r | |
576 | !endif\r | |
577 | \r | |
578 | #\r | |
579 | # Performance Application\r | |
580 | #\r | |
581 | !if $(PERFORMANCE_ENABLE)\r | |
582 | INF ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf\r | |
583 | !endif\r | |
584 | \r | |
585 | #\r | |
586 | # Trusted Platform Module\r | |
587 | #\r | |
588 | !if $(MEASURED_BOOT_ENABLE)\r | |
589 | INF SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf\r | |
590 | INF SecurityPkg/Tcg/TcgDxe/TcgDxe.inf\r | |
591 | INF RuleOverride = DRIVER_ACPITABLE SecurityPkg/Tcg/TcgSmm/TcgSmm.inf\r | |
592 | !endif\r | |
593 | \r | |
594 | !if $(CAPSULE_ENABLE)\r | |
595 | INF MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf\r | |
596 | INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf\r | |
597 | !endif\r | |
598 | \r | |
599 | !if $(RECOVERY_ENABLE)\r | |
600 | FILE FREEFORM = PCD(gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiRsa2048Sha256TestPublicKeyFileGuid) {\r | |
601 | SECTION RAW = BaseTools/Source/Python/Rsa2048Sha256Sign/TestSigningPublicKey.bin\r | |
602 | SECTION UI = "Rsa2048Sha256TestSigningPublicKey"\r | |
603 | }\r | |
604 | !endif\r | |
605 | \r | |
606 | !if $(CAPSULE_ENABLE)\r | |
607 | FILE FREEFORM = PCD(gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiPkcs7TestPublicKeyFileGuid) {\r | |
608 | SECTION RAW = BaseTools/Source/Python/Pkcs7Sign/TestRoot.cer\r | |
609 | SECTION UI = "Pkcs7TestRoot"\r | |
610 | }\r | |
611 | !endif\r | |
612 | \r | |
613 | ################################################################################\r | |
614 | #\r | |
615 | # FV Section\r | |
616 | #\r | |
617 | # [FV] section is used to define what components or modules are placed within a flash\r | |
618 | # device file. This section also defines order the components and modules are positioned\r | |
619 | # within the image. The [FV] section consists of define statements, set statements and\r | |
620 | # module statements.\r | |
621 | #\r | |
622 | ################################################################################\r | |
623 | [FV.FVMAIN_COMPACT]\r | |
624 | FvAlignment = 16\r | |
625 | ERASE_POLARITY = 1\r | |
626 | MEMORY_MAPPED = TRUE\r | |
627 | STICKY_WRITE = TRUE\r | |
628 | LOCK_CAP = TRUE\r | |
629 | LOCK_STATUS = TRUE\r | |
630 | WRITE_DISABLED_CAP = TRUE\r | |
631 | WRITE_ENABLED_CAP = TRUE\r | |
632 | WRITE_STATUS = TRUE\r | |
633 | WRITE_LOCK_CAP = TRUE\r | |
634 | WRITE_LOCK_STATUS = TRUE\r | |
635 | READ_DISABLED_CAP = TRUE\r | |
636 | READ_ENABLED_CAP = TRUE\r | |
637 | READ_STATUS = TRUE\r | |
638 | READ_LOCK_CAP = TRUE\r | |
639 | READ_LOCK_STATUS = TRUE\r | |
640 | \r | |
641 | FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r | |
642 | SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779 { # TIANO COMPRESS GUID\r | |
643 | SECTION FV_IMAGE = FVMAIN\r | |
644 | }\r | |
645 | }\r | |
646 | \r | |
647 | ################################################################################\r | |
648 | #\r | |
649 | # FV Section\r | |
650 | #\r | |
651 | # [FV] section is used to define what components or modules are placed within a flash\r | |
652 | # device file. This section also defines order the components and modules are positioned\r | |
653 | # within the image. The [FV] section consists of define statements, set statements and\r | |
654 | # module statements.\r | |
655 | #\r | |
656 | ################################################################################\r | |
657 | [FV.PAYLOAD]\r | |
658 | BlockSize = $(FLASH_BLOCKSIZE)\r | |
659 | FvAlignment = 16 #FV alignment and FV attributes setting.\r | |
660 | ERASE_POLARITY = 1\r | |
661 | MEMORY_MAPPED = TRUE\r | |
662 | STICKY_WRITE = TRUE\r | |
663 | LOCK_CAP = TRUE\r | |
664 | LOCK_STATUS = TRUE\r | |
665 | WRITE_DISABLED_CAP = TRUE\r | |
666 | WRITE_ENABLED_CAP = TRUE\r | |
667 | WRITE_STATUS = TRUE\r | |
668 | WRITE_LOCK_CAP = TRUE\r | |
669 | WRITE_LOCK_STATUS = TRUE\r | |
670 | READ_DISABLED_CAP = TRUE\r | |
671 | READ_ENABLED_CAP = TRUE\r | |
672 | READ_STATUS = TRUE\r | |
673 | READ_LOCK_CAP = TRUE\r | |
674 | READ_LOCK_STATUS = TRUE\r | |
675 | \r | |
676 | #\r | |
677 | # Shell and Applications\r | |
678 | #\r | |
679 | INF RuleOverride = TIANOCOMPRESSED ShellPkg/Application/Shell/Shell.inf\r | |
680 | \r | |
681 | !if $(CAPSULE_ENABLE) || $(RECOVERY_ENABLE)\r | |
682 | \r | |
683 | [FV.CapsuleDispatchFv]\r | |
684 | FvAlignment = 16\r | |
685 | ERASE_POLARITY = 1\r | |
686 | MEMORY_MAPPED = TRUE\r | |
687 | STICKY_WRITE = TRUE\r | |
688 | LOCK_CAP = TRUE\r | |
689 | LOCK_STATUS = TRUE\r | |
690 | WRITE_DISABLED_CAP = TRUE\r | |
691 | WRITE_ENABLED_CAP = TRUE\r | |
692 | WRITE_STATUS = TRUE\r | |
693 | WRITE_LOCK_CAP = TRUE\r | |
694 | WRITE_LOCK_STATUS = TRUE\r | |
695 | READ_DISABLED_CAP = TRUE\r | |
696 | READ_ENABLED_CAP = TRUE\r | |
697 | READ_STATUS = TRUE\r | |
698 | READ_LOCK_CAP = TRUE\r | |
699 | READ_LOCK_STATUS = TRUE\r | |
700 | \r | |
701 | !if $(CAPSULE_ENABLE)\r | |
702 | INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf\r | |
703 | !endif\r | |
704 | \r | |
705 | [FV.SystemFirmwareUpdateCargo]\r | |
706 | FvAlignment = 16\r | |
707 | ERASE_POLARITY = 1\r | |
708 | MEMORY_MAPPED = TRUE\r | |
709 | STICKY_WRITE = TRUE\r | |
710 | LOCK_CAP = TRUE\r | |
711 | LOCK_STATUS = TRUE\r | |
712 | WRITE_DISABLED_CAP = TRUE\r | |
713 | WRITE_ENABLED_CAP = TRUE\r | |
714 | WRITE_STATUS = TRUE\r | |
715 | WRITE_LOCK_CAP = TRUE\r | |
716 | WRITE_LOCK_STATUS = TRUE\r | |
717 | READ_DISABLED_CAP = TRUE\r | |
718 | READ_ENABLED_CAP = TRUE\r | |
719 | READ_STATUS = TRUE\r | |
720 | READ_LOCK_CAP = TRUE\r | |
721 | READ_LOCK_STATUS = TRUE\r | |
722 | \r | |
723 | FILE RAW = 14D83A59-A810-4556-8192-1C0A593C065C { # PcdEdkiiSystemFirmwareFileGuid\r | |
724 | FD = Quark\r | |
725 | }\r | |
726 | \r | |
727 | FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid\r | |
728 | FV = CapsuleDispatchFv\r | |
729 | }\r | |
730 | \r | |
731 | FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfigFileGuid\r | |
732 | QuarkPlatformPkg/Feature/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini\r | |
733 | }\r | |
734 | \r | |
735 | !endif\r | |
736 | \r | |
737 | !if $(CAPSULE_ENABLE)\r | |
738 | [FmpPayload.FmpPayloadSystemFirmwarePkcs7]\r | |
739 | IMAGE_HEADER_INIT_VERSION = 0x02\r | |
740 | IMAGE_TYPE_ID = 62af20c0-7016-424a-9bf8-9ccc86584090 # PcdSystemFmpCapsuleImageTypeIdGuid\r | |
741 | IMAGE_INDEX = 0x1\r | |
742 | HARDWARE_INSTANCE = 0x0\r | |
743 | MONOTONIC_COUNT = 0x2\r | |
744 | CERTIFICATE_GUID = 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7\r | |
745 | \r | |
746 | FV = SystemFirmwareUpdateCargo\r | |
747 | \r | |
748 | [Capsule.QuarkFirmwareUpdateCapsuleFmpPkcs7]\r | |
749 | CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid\r | |
750 | CAPSULE_FLAGS = PersistAcrossReset,InitiateReset\r | |
751 | CAPSULE_HEADER_SIZE = 0x20\r | |
752 | CAPSULE_HEADER_INIT_VERSION = 0x1\r | |
753 | \r | |
754 | FMP_PAYLOAD = FmpPayloadSystemFirmwarePkcs7\r | |
755 | !endif\r | |
756 | \r | |
757 | !if $(RECOVERY_ENABLE)\r | |
758 | [FmpPayload.FmpPayloadSystemFirmwareRsa2048]\r | |
759 | IMAGE_HEADER_INIT_VERSION = 0x02\r | |
760 | IMAGE_TYPE_ID = 62af20c0-7016-424a-9bf8-9ccc86584090 # PcdSystemFmpCapsuleImageTypeIdGuid\r | |
761 | IMAGE_INDEX = 0x1\r | |
762 | HARDWARE_INSTANCE = 0x0\r | |
763 | MONOTONIC_COUNT = 0x2\r | |
764 | CERTIFICATE_GUID = A7717414-C616-4977-9420-844712A735BF # RSA2048SHA256\r | |
765 | \r | |
766 | FV = SystemFirmwareUpdateCargo\r | |
767 | \r | |
768 | [Capsule.QuarkRec]\r | |
769 | CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid\r | |
770 | CAPSULE_FLAGS = PersistAcrossReset,InitiateReset\r | |
771 | CAPSULE_HEADER_SIZE = 0x20\r | |
772 | CAPSULE_HEADER_INIT_VERSION = 0x1\r | |
773 | \r | |
774 | FMP_PAYLOAD = FmpPayloadSystemFirmwareRsa2048\r | |
775 | !endif\r | |
776 | \r | |
777 | ################################################################################\r | |
778 | #\r | |
779 | # Rules are use with the [FV] section's module INF type to define\r | |
780 | # how an FFS file is created for a given INF file. The following Rule are the default\r | |
781 | # rules for the different module type. User can add the customized rules to define the\r | |
782 | # content of the FFS file.\r | |
783 | #\r | |
784 | ################################################################################\r | |
785 | [Rule.Common.SEC]\r | |
786 | FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r | |
787 | TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi\r | |
788 | RAW BIN Align = 16 |.com\r | |
789 | }\r | |
790 | \r | |
791 | [Rule.Common.PEI_CORE]\r | |
792 | FILE PEI_CORE = $(NAMED_GUID) {\r | |
793 | TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r | |
794 | UI STRING="$(MODULE_NAME)" Optional\r | |
795 | VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r | |
796 | }\r | |
797 | \r | |
798 | [Rule.Common.PEIM.NORELOC]\r | |
799 | FILE PEIM = $(NAMED_GUID) RELOCS_STRIPPED {\r | |
800 | PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r | |
801 | TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r | |
802 | UI STRING="$(MODULE_NAME)" Optional\r | |
803 | VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r | |
804 | }\r | |
805 | \r | |
806 | [Rule.Common.PEIM]\r | |
807 | FILE PEIM = $(NAMED_GUID) {\r | |
808 | PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r | |
809 | TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r | |
810 | UI STRING="$(MODULE_NAME)" Optional\r | |
811 | VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r | |
812 | }\r | |
813 | \r | |
814 | [Rule.Common.DXE_CORE]\r | |
815 | FILE DXE_CORE = $(NAMED_GUID) {\r | |
816 | PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r | |
817 | UI STRING="$(MODULE_NAME)" Optional\r | |
818 | VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r | |
819 | }\r | |
820 | \r | |
821 | [Rule.Common.UEFI_DRIVER]\r | |
822 | FILE DRIVER = $(NAMED_GUID) {\r | |
823 | DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r | |
824 | PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r | |
825 | UI STRING="$(MODULE_NAME)" Optional\r | |
826 | VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r | |
827 | }\r | |
828 | \r | |
829 | [Rule.Common.DXE_DRIVER]\r | |
830 | FILE DRIVER = $(NAMED_GUID) {\r | |
831 | DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r | |
832 | PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r | |
833 | UI STRING="$(MODULE_NAME)" Optional\r | |
834 | VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r | |
835 | }\r | |
836 | \r | |
837 | [Rule.Common.DXE_RUNTIME_DRIVER]\r | |
838 | FILE DRIVER = $(NAMED_GUID) {\r | |
839 | DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r | |
840 | PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r | |
841 | UI STRING="$(MODULE_NAME)" Optional\r | |
842 | VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r | |
843 | }\r | |
844 | \r | |
845 | [Rule.Common.DXE_SMM_DRIVER]\r | |
846 | FILE SMM = $(NAMED_GUID) {\r | |
847 | SMM_DEPEX SMM_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r | |
848 | PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r | |
849 | UI STRING="$(MODULE_NAME)" Optional\r | |
850 | VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r | |
851 | }\r | |
852 | \r | |
853 | [Rule.Common.DXE_SMM_DRIVER.DRIVER_ACPITABLE]\r | |
854 | FILE SMM = $(NAMED_GUID) {\r | |
855 | DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r | |
856 | PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r | |
857 | RAW ACPI Optional |.acpi\r | |
858 | RAW ASL Optional |.aml\r | |
859 | UI STRING="$(MODULE_NAME)" Optional\r | |
860 | VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r | |
861 | }\r | |
862 | \r | |
863 | [Rule.Common.SMM_CORE]\r | |
864 | FILE SMM_CORE = $(NAMED_GUID) {\r | |
865 | PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r | |
866 | UI STRING="$(MODULE_NAME)" Optional\r | |
867 | VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r | |
868 | }\r | |
869 | \r | |
870 | [Rule.Common.UEFI_APPLICATION]\r | |
871 | FILE APPLICATION = $(NAMED_GUID) {\r | |
872 | PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r | |
873 | UI STRING="$(MODULE_NAME)" Optional\r | |
874 | VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r | |
875 | }\r | |
876 | \r | |
877 | [Rule.Common.UEFI_APPLICATION.TIANOCOMPRESSED]\r | |
878 | FILE APPLICATION = $(NAMED_GUID) {\r | |
879 | UI STRING="$(MODULE_NAME)" Optional\r | |
880 | VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r | |
881 | SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { # TIANO COMPRESS GUID\r | |
882 | PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r | |
883 | }\r | |
884 | }\r | |
885 | \r | |
886 | [Rule.Common.UEFI_APPLICATION.UI]\r | |
887 | FILE APPLICATION = $(NAMED_GUID) {\r | |
888 | PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r | |
889 | UI STRING="Enter Setup"\r | |
890 | VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r | |
891 | }\r | |
892 | \r | |
893 | [Rule.Common.USER_DEFINED.ACPITABLE]\r | |
894 | FILE FREEFORM = $(NAMED_GUID) {\r | |
895 | RAW ACPI |.acpi\r | |
896 | RAW ASL |.aml\r | |
897 | }\r | |
898 | \r | |
899 | [Rule.Common.PEIM.FMP_IMAGE_DESC]\r | |
900 | FILE PEIM = $(NAMED_GUID) {\r | |
901 | RAW BIN |.acpi\r | |
902 | PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r | |
903 | PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi\r | |
904 | UI STRING="$(MODULE_NAME)" Optional\r | |
905 | VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r | |
906 | }\r | |
907 | \r |