]>
Commit | Line | Data |
---|---|---|
1 | /** @file\r | |
2 | Header file for AHCI mode of ATA host controller.\r | |
3 | \r | |
4 | Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | \r | |
16 | #ifndef __OPAL_PASSWORD_AHCI_MODE_H__\r | |
17 | #define __OPAL_PASSWORD_AHCI_MODE_H__\r | |
18 | \r | |
19 | //\r | |
20 | // OPAL LIBRARY CALLBACKS\r | |
21 | //\r | |
22 | #define ATA_COMMAND_TRUSTED_RECEIVE 0x5C\r | |
23 | #define ATA_COMMAND_TRUSTED_SEND 0x5E\r | |
24 | \r | |
25 | //\r | |
26 | // ATA TRUSTED commands express transfer Length in 512 byte multiple\r | |
27 | //\r | |
28 | #define ATA_TRUSTED_TRANSFER_LENGTH_MULTIPLE 512\r | |
29 | #define ATA_DEVICE_LBA 0x40 ///< Set for commands with LBA (rather than CHS) addresses\r | |
30 | \r | |
31 | \r | |
32 | #define EFI_AHCI_BAR_INDEX 0x05\r | |
33 | \r | |
34 | #define EFI_AHCI_CAPABILITY_OFFSET 0x0000\r | |
35 | #define EFI_AHCI_CAP_SAM BIT18\r | |
36 | #define EFI_AHCI_GHC_OFFSET 0x0004\r | |
37 | #define EFI_AHCI_GHC_RESET BIT0\r | |
38 | #define EFI_AHCI_GHC_IE BIT1\r | |
39 | #define EFI_AHCI_GHC_ENABLE BIT31\r | |
40 | #define EFI_AHCI_IS_OFFSET 0x0008\r | |
41 | #define EFI_AHCI_PI_OFFSET 0x000C\r | |
42 | \r | |
43 | typedef struct {\r | |
44 | UINT32 Lower32;\r | |
45 | UINT32 Upper32;\r | |
46 | } DATA_32;\r | |
47 | \r | |
48 | typedef union {\r | |
49 | DATA_32 Uint32;\r | |
50 | UINT64 Uint64;\r | |
51 | } DATA_64;\r | |
52 | \r | |
53 | //\r | |
54 | // Each PRDT entry can point to a memory block up to 4M byte\r | |
55 | //\r | |
56 | #define EFI_AHCI_MAX_DATA_PER_PRDT 0x400000\r | |
57 | \r | |
58 | #define EFI_AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device\r | |
59 | #define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20\r | |
60 | #define EFI_AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host\r | |
61 | #define EFI_AHCI_FIS_REGISTER_D2H_LENGTH 20\r | |
62 | #define EFI_AHCI_FIS_DMA_ACTIVATE 0x39 //DMA Activate FIS - Device to Host\r | |
63 | #define EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH 4\r | |
64 | #define EFI_AHCI_FIS_DMA_SETUP 0x41 //DMA Setup FIS - Bi-directional\r | |
65 | #define EFI_AHCI_FIS_DMA_SETUP_LENGTH 28\r | |
66 | #define EFI_AHCI_FIS_DATA 0x46 //Data FIS - Bi-directional\r | |
67 | #define EFI_AHCI_FIS_BIST 0x58 //BIST Activate FIS - Bi-directional\r | |
68 | #define EFI_AHCI_FIS_BIST_LENGTH 12\r | |
69 | #define EFI_AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host\r | |
70 | #define EFI_AHCI_FIS_PIO_SETUP_LENGTH 20\r | |
71 | #define EFI_AHCI_FIS_SET_DEVICE 0xA1 //Set Device Bits FIS - Device to Host\r | |
72 | #define EFI_AHCI_FIS_SET_DEVICE_LENGTH 8\r | |
73 | \r | |
74 | #define EFI_AHCI_D2H_FIS_OFFSET 0x40\r | |
75 | #define EFI_AHCI_DMA_FIS_OFFSET 0x00\r | |
76 | #define EFI_AHCI_PIO_FIS_OFFSET 0x20\r | |
77 | #define EFI_AHCI_SDB_FIS_OFFSET 0x58\r | |
78 | #define EFI_AHCI_FIS_TYPE_MASK 0xFF\r | |
79 | #define EFI_AHCI_U_FIS_OFFSET 0x60\r | |
80 | \r | |
81 | //\r | |
82 | // Port register\r | |
83 | //\r | |
84 | #define EFI_AHCI_PORT_START 0x0100\r | |
85 | #define EFI_AHCI_PORT_REG_WIDTH 0x0080\r | |
86 | #define EFI_AHCI_PORT_CLB 0x0000\r | |
87 | #define EFI_AHCI_PORT_CLBU 0x0004\r | |
88 | #define EFI_AHCI_PORT_FB 0x0008\r | |
89 | #define EFI_AHCI_PORT_FBU 0x000C\r | |
90 | #define EFI_AHCI_PORT_IS 0x0010\r | |
91 | #define EFI_AHCI_PORT_IS_DHRS BIT0\r | |
92 | #define EFI_AHCI_PORT_IS_PSS BIT1\r | |
93 | #define EFI_AHCI_PORT_IS_SSS BIT2\r | |
94 | #define EFI_AHCI_PORT_IS_SDBS BIT3\r | |
95 | #define EFI_AHCI_PORT_IS_UFS BIT4\r | |
96 | #define EFI_AHCI_PORT_IS_DPS BIT5\r | |
97 | #define EFI_AHCI_PORT_IS_PCS BIT6\r | |
98 | #define EFI_AHCI_PORT_IS_DIS BIT7\r | |
99 | #define EFI_AHCI_PORT_IS_PRCS BIT22\r | |
100 | #define EFI_AHCI_PORT_IS_IPMS BIT23\r | |
101 | #define EFI_AHCI_PORT_IS_OFS BIT24\r | |
102 | #define EFI_AHCI_PORT_IS_INFS BIT26\r | |
103 | #define EFI_AHCI_PORT_IS_IFS BIT27\r | |
104 | #define EFI_AHCI_PORT_IS_HBDS BIT28\r | |
105 | #define EFI_AHCI_PORT_IS_HBFS BIT29\r | |
106 | #define EFI_AHCI_PORT_IS_TFES BIT30\r | |
107 | #define EFI_AHCI_PORT_IS_CPDS BIT31\r | |
108 | #define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF\r | |
109 | #define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F\r | |
110 | \r | |
111 | #define EFI_AHCI_PORT_IE 0x0014\r | |
112 | #define EFI_AHCI_PORT_CMD 0x0018\r | |
113 | #define EFI_AHCI_PORT_CMD_ST_MASK 0xFFFFFFFE\r | |
114 | #define EFI_AHCI_PORT_CMD_ST BIT0\r | |
115 | #define EFI_AHCI_PORT_CMD_SUD BIT1\r | |
116 | #define EFI_AHCI_PORT_CMD_POD BIT2\r | |
117 | #define EFI_AHCI_PORT_CMD_COL BIT3\r | |
118 | #define EFI_AHCI_PORT_CMD_CR BIT15\r | |
119 | #define EFI_AHCI_PORT_CMD_FRE BIT4\r | |
120 | #define EFI_AHCI_PORT_CMD_FR BIT14\r | |
121 | #define EFI_AHCI_PORT_CMD_MASK ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)\r | |
122 | #define EFI_AHCI_PORT_CMD_PMA BIT17\r | |
123 | #define EFI_AHCI_PORT_CMD_HPCP BIT18\r | |
124 | #define EFI_AHCI_PORT_CMD_MPSP BIT19\r | |
125 | #define EFI_AHCI_PORT_CMD_CPD BIT20\r | |
126 | #define EFI_AHCI_PORT_CMD_ESP BIT21\r | |
127 | #define EFI_AHCI_PORT_CMD_ATAPI BIT24\r | |
128 | #define EFI_AHCI_PORT_CMD_DLAE BIT25\r | |
129 | #define EFI_AHCI_PORT_CMD_ALPE BIT26\r | |
130 | #define EFI_AHCI_PORT_CMD_ASP BIT27\r | |
131 | #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)\r | |
132 | #define EFI_AHCI_PORT_CMD_ACTIVE (1 << 28 )\r | |
133 | #define EFI_AHCI_PORT_TFD 0x0020\r | |
134 | #define EFI_AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)\r | |
135 | #define EFI_AHCI_PORT_TFD_BSY BIT7\r | |
136 | #define EFI_AHCI_PORT_TFD_DRQ BIT3\r | |
137 | #define EFI_AHCI_PORT_TFD_ERR BIT0\r | |
138 | #define EFI_AHCI_PORT_TFD_ERR_MASK 0x00FF00\r | |
139 | #define EFI_AHCI_PORT_SIG 0x0024\r | |
140 | #define EFI_AHCI_PORT_SSTS 0x0028\r | |
141 | #define EFI_AHCI_PORT_SSTS_DET_MASK 0x000F\r | |
142 | #define EFI_AHCI_PORT_SSTS_DET 0x0001\r | |
143 | #define EFI_AHCI_PORT_SSTS_DET_PCE 0x0003\r | |
144 | #define EFI_AHCI_PORT_SSTS_SPD_MASK 0x00F0\r | |
145 | #define EFI_AHCI_PORT_SCTL 0x002C\r | |
146 | #define EFI_AHCI_PORT_SCTL_DET_MASK 0x000F\r | |
147 | #define EFI_AHCI_PORT_SCTL_MASK (~EFI_AHCI_PORT_SCTL_DET_MASK)\r | |
148 | #define EFI_AHCI_PORT_SCTL_DET_INIT 0x0001\r | |
149 | #define EFI_AHCI_PORT_SCTL_DET_PHYCOMM 0x0003\r | |
150 | #define EFI_AHCI_PORT_SCTL_SPD_MASK 0x00F0\r | |
151 | #define EFI_AHCI_PORT_SCTL_IPM_MASK 0x0F00\r | |
152 | #define EFI_AHCI_PORT_SCTL_IPM_INIT 0x0300\r | |
153 | #define EFI_AHCI_PORT_SCTL_IPM_PSD 0x0100\r | |
154 | #define EFI_AHCI_PORT_SCTL_IPM_SSD 0x0200\r | |
155 | #define EFI_AHCI_PORT_SERR 0x0030\r | |
156 | #define EFI_AHCI_PORT_SERR_RDIE BIT0\r | |
157 | #define EFI_AHCI_PORT_SERR_RCE BIT1\r | |
158 | #define EFI_AHCI_PORT_SERR_TDIE BIT8\r | |
159 | #define EFI_AHCI_PORT_SERR_PCDIE BIT9\r | |
160 | #define EFI_AHCI_PORT_SERR_PE BIT10\r | |
161 | #define EFI_AHCI_PORT_SERR_IE BIT11\r | |
162 | #define EFI_AHCI_PORT_SERR_PRC BIT16\r | |
163 | #define EFI_AHCI_PORT_SERR_PIE BIT17\r | |
164 | #define EFI_AHCI_PORT_SERR_CW BIT18\r | |
165 | #define EFI_AHCI_PORT_SERR_BDE BIT19\r | |
166 | #define EFI_AHCI_PORT_SERR_DE BIT20\r | |
167 | #define EFI_AHCI_PORT_SERR_CRCE BIT21\r | |
168 | #define EFI_AHCI_PORT_SERR_HE BIT22\r | |
169 | #define EFI_AHCI_PORT_SERR_LSE BIT23\r | |
170 | #define EFI_AHCI_PORT_SERR_TSTE BIT24\r | |
171 | #define EFI_AHCI_PORT_SERR_UFT BIT25\r | |
172 | #define EFI_AHCI_PORT_SERR_EX BIT26\r | |
173 | #define EFI_AHCI_PORT_ERR_CLEAR 0xFFFFFFFF\r | |
174 | #define EFI_AHCI_PORT_SACT 0x0034\r | |
175 | #define EFI_AHCI_PORT_CI 0x0038\r | |
176 | #define EFI_AHCI_PORT_SNTF 0x003C\r | |
177 | \r | |
178 | \r | |
179 | #pragma pack(1)\r | |
180 | //\r | |
181 | // Command List structure includes total 32 entries.\r | |
182 | // The entry Data structure is listed at the following.\r | |
183 | //\r | |
184 | typedef struct {\r | |
185 | UINT32 AhciCmdCfl:5; //Command FIS Length\r | |
186 | UINT32 AhciCmdA:1; //ATAPI\r | |
187 | UINT32 AhciCmdW:1; //Write\r | |
188 | UINT32 AhciCmdP:1; //Prefetchable\r | |
189 | UINT32 AhciCmdR:1; //Reset\r | |
190 | UINT32 AhciCmdB:1; //BIST\r | |
191 | UINT32 AhciCmdC:1; //Clear Busy upon R_OK\r | |
192 | UINT32 AhciCmdRsvd:1;\r | |
193 | UINT32 AhciCmdPmp:4; //Port Multiplier Port\r | |
194 | UINT32 AhciCmdPrdtl:16; //Physical Region Descriptor Table Length\r | |
195 | UINT32 AhciCmdPrdbc; //Physical Region Descriptor Byte Count\r | |
196 | UINT32 AhciCmdCtba; //Command Table Descriptor Base Address\r | |
197 | UINT32 AhciCmdCtbau; //Command Table Descriptor Base Address Upper 32-BITs\r | |
198 | UINT32 AhciCmdRsvd1[4];\r | |
199 | } EFI_AHCI_COMMAND_LIST;\r | |
200 | \r | |
201 | //\r | |
202 | // This is a software constructed FIS.\r | |
203 | // For Data transfer operations, this is the H2D Register FIS format as\r | |
204 | // specified in the Serial ATA Revision 2.6 specification.\r | |
205 | //\r | |
206 | typedef struct {\r | |
207 | UINT8 AhciCFisType;\r | |
208 | UINT8 AhciCFisPmNum:4;\r | |
209 | UINT8 AhciCFisRsvd:1;\r | |
210 | UINT8 AhciCFisRsvd1:1;\r | |
211 | UINT8 AhciCFisRsvd2:1;\r | |
212 | UINT8 AhciCFisCmdInd:1;\r | |
213 | UINT8 AhciCFisCmd;\r | |
214 | UINT8 AhciCFisFeature;\r | |
215 | UINT8 AhciCFisSecNum;\r | |
216 | UINT8 AhciCFisClyLow;\r | |
217 | UINT8 AhciCFisClyHigh;\r | |
218 | UINT8 AhciCFisDevHead;\r | |
219 | UINT8 AhciCFisSecNumExp;\r | |
220 | UINT8 AhciCFisClyLowExp;\r | |
221 | UINT8 AhciCFisClyHighExp;\r | |
222 | UINT8 AhciCFisFeatureExp;\r | |
223 | UINT8 AhciCFisSecCount;\r | |
224 | UINT8 AhciCFisSecCountExp;\r | |
225 | UINT8 AhciCFisRsvd3;\r | |
226 | UINT8 AhciCFisControl;\r | |
227 | UINT8 AhciCFisRsvd4[4];\r | |
228 | UINT8 AhciCFisRsvd5[44];\r | |
229 | } EFI_AHCI_COMMAND_FIS;\r | |
230 | \r | |
231 | //\r | |
232 | // ACMD: ATAPI command (12 or 16 bytes)\r | |
233 | //\r | |
234 | typedef struct {\r | |
235 | UINT8 AtapiCmd[0x10];\r | |
236 | } EFI_AHCI_ATAPI_COMMAND;\r | |
237 | \r | |
238 | //\r | |
239 | // Physical Region Descriptor Table includes up to 65535 entries\r | |
240 | // The entry Data structure is listed at the following.\r | |
241 | // the actual entry number comes from the PRDTL field in the command\r | |
242 | // list entry for this command slot.\r | |
243 | //\r | |
244 | typedef struct {\r | |
245 | UINT32 AhciPrdtDba; //Data Base Address\r | |
246 | UINT32 AhciPrdtDbau; //Data Base Address Upper 32-BITs\r | |
247 | UINT32 AhciPrdtRsvd;\r | |
248 | UINT32 AhciPrdtDbc:22; //Data Byte Count\r | |
249 | UINT32 AhciPrdtRsvd1:9;\r | |
250 | UINT32 AhciPrdtIoc:1; //Interrupt on Completion\r | |
251 | } EFI_AHCI_COMMAND_PRDT;\r | |
252 | \r | |
253 | //\r | |
254 | // Command table Data strucute which is pointed to by the entry in the command list\r | |
255 | //\r | |
256 | typedef struct {\r | |
257 | EFI_AHCI_COMMAND_FIS CommandFis; // A software constructed FIS.\r | |
258 | EFI_AHCI_ATAPI_COMMAND AtapiCmd; // 12 or 16 bytes ATAPI cmd.\r | |
259 | UINT8 Reserved[0x30];\r | |
260 | EFI_AHCI_COMMAND_PRDT PrdtTable; // The scatter/gather list for Data transfer\r | |
261 | } EFI_AHCI_COMMAND_TABLE;\r | |
262 | \r | |
263 | //\r | |
264 | // Received FIS structure\r | |
265 | //\r | |
266 | typedef struct {\r | |
267 | UINT8 AhciDmaSetupFis[0x1C]; // Dma Setup Fis: offset 0x00\r | |
268 | UINT8 AhciDmaSetupFisRsvd[0x04];\r | |
269 | UINT8 AhciPioSetupFis[0x14]; // Pio Setup Fis: offset 0x20\r | |
270 | UINT8 AhciPioSetupFisRsvd[0x0C];\r | |
271 | UINT8 AhciD2HRegisterFis[0x14]; // D2H Register Fis: offset 0x40\r | |
272 | UINT8 AhciD2HRegisterFisRsvd[0x04];\r | |
273 | UINT64 AhciSetDeviceBitsFis; // Set Device Bits Fix: offset 0x58\r | |
274 | UINT8 AhciUnknownFis[0x40]; // Unkonwn Fis: offset 0x60\r | |
275 | UINT8 AhciUnknownFisRsvd[0x60];\r | |
276 | } EFI_AHCI_RECEIVED_FIS;\r | |
277 | \r | |
278 | #pragma pack()\r | |
279 | \r | |
280 | typedef struct {\r | |
281 | EFI_AHCI_RECEIVED_FIS *AhciRFis;\r | |
282 | VOID *AhciRFisMapping;\r | |
283 | EFI_AHCI_COMMAND_LIST *AhciCmdList;\r | |
284 | VOID *AhciCmdListMapping;\r | |
285 | EFI_AHCI_COMMAND_TABLE *AhciCommandTable;\r | |
286 | VOID *AhciCommandTableMapping;\r | |
287 | } EFI_AHCI_REGISTERS;\r | |
288 | \r | |
289 | typedef struct {\r | |
290 | VOID *Buffer;\r | |
291 | VOID *BufferMapping;\r | |
292 | EFI_AHCI_REGISTERS AhciRegisters;\r | |
293 | UINT32 AhciBar;\r | |
294 | } AHCI_CONTEXT;\r | |
295 | \r | |
296 | /**\r | |
297 | Send Buffer cmd to specific device.\r | |
298 | \r | |
299 | @param AhciContext The pointer to the AHCI_CONTEXT.\r | |
300 | @param Port The number of port.\r | |
301 | @param PortMultiplier The timeout Value of stop.\r | |
302 | @param Buffer The Data Buffer to store IDENTIFY PACKET Data.\r | |
303 | \r | |
304 | @retval EFI_DEVICE_ERROR The cmd abort with error occurs.\r | |
305 | @retval EFI_TIMEOUT The operation is time out.\r | |
306 | @retval EFI_UNSUPPORTED The device is not ready for executing.\r | |
307 | @retval EFI_SUCCESS The cmd executes successfully.\r | |
308 | \r | |
309 | **/\r | |
310 | EFI_STATUS\r | |
311 | EFIAPI\r | |
312 | AhciIdentify (\r | |
313 | IN AHCI_CONTEXT *AhciContext,\r | |
314 | IN UINT8 Port,\r | |
315 | IN UINT8 PortMultiplier,\r | |
316 | IN OUT ATA_IDENTIFY_DATA *Buffer\r | |
317 | );\r | |
318 | \r | |
319 | /**\r | |
320 | Allocate transfer-related data struct which is used at AHCI mode.\r | |
321 | \r | |
322 | @param[in, out] AhciContext The pointer to the AHCI_CONTEXT.\r | |
323 | \r | |
324 | @retval EFI_OUT_OF_RESOURCE No enough resource.\r | |
325 | @retval EFI_SUCCESS Successful to allocate resource.\r | |
326 | \r | |
327 | **/\r | |
328 | EFI_STATUS\r | |
329 | EFIAPI\r | |
330 | AhciAllocateResource (\r | |
331 | IN OUT AHCI_CONTEXT *AhciContext\r | |
332 | );\r | |
333 | \r | |
334 | /**\r | |
335 | Free allocated transfer-related data struct which is used at AHCI mode.\r | |
336 | \r | |
337 | @param[in, out] AhciContext The pointer to the AHCI_CONTEXT.\r | |
338 | \r | |
339 | **/\r | |
340 | VOID\r | |
341 | EFIAPI\r | |
342 | AhciFreeResource (\r | |
343 | IN OUT AHCI_CONTEXT *AhciContext\r | |
344 | );\r | |
345 | \r | |
346 | /**\r | |
347 | Initialize ATA host controller at AHCI mode.\r | |
348 | \r | |
349 | The function is designed to initialize ATA host controller.\r | |
350 | \r | |
351 | @param[in] AhciContext The pointer to the AHCI_CONTEXT.\r | |
352 | @param[in] Port The port number to do initialization.\r | |
353 | \r | |
354 | **/\r | |
355 | EFI_STATUS\r | |
356 | EFIAPI\r | |
357 | AhciModeInitialize (\r | |
358 | IN AHCI_CONTEXT *AhciContext,\r | |
359 | IN UINT8 Port\r | |
360 | );\r | |
361 | \r | |
362 | typedef struct _EFI_ATA_COMMAND_BLOCK {\r | |
363 | UINT8 Reserved1[2];\r | |
364 | UINT8 AtaCommand;\r | |
365 | UINT8 AtaFeatures;\r | |
366 | UINT8 AtaSectorNumber;\r | |
367 | UINT8 AtaCylinderLow;\r | |
368 | UINT8 AtaCylinderHigh;\r | |
369 | UINT8 AtaDeviceHead;\r | |
370 | UINT8 AtaSectorNumberExp;\r | |
371 | UINT8 AtaCylinderLowExp;\r | |
372 | UINT8 AtaCylinderHighExp; \r | |
373 | UINT8 AtaFeaturesExp;\r | |
374 | UINT8 AtaSectorCount;\r | |
375 | UINT8 AtaSectorCountExp;\r | |
376 | UINT8 Reserved2[6];\r | |
377 | } EFI_ATA_COMMAND_BLOCK;\r | |
378 | \r | |
379 | typedef struct _EFI_ATA_STATUS_BLOCK {\r | |
380 | UINT8 Reserved1[2];\r | |
381 | UINT8 AtaStatus;\r | |
382 | UINT8 AtaError;\r | |
383 | UINT8 AtaSectorNumber;\r | |
384 | UINT8 AtaCylinderLow;\r | |
385 | UINT8 AtaCylinderHigh;\r | |
386 | UINT8 AtaDeviceHead;\r | |
387 | UINT8 AtaSectorNumberExp;\r | |
388 | UINT8 AtaCylinderLowExp;\r | |
389 | UINT8 AtaCylinderHighExp; \r | |
390 | UINT8 Reserved2;\r | |
391 | UINT8 AtaSectorCount;\r | |
392 | UINT8 AtaSectorCountExp;\r | |
393 | UINT8 Reserved3[6];\r | |
394 | } EFI_ATA_STATUS_BLOCK;\r | |
395 | \r | |
396 | /**\r | |
397 | Start a PIO Data transfer on specific port.\r | |
398 | \r | |
399 | @param AhciContext The pointer to the AHCI_CONTEXT.\r | |
400 | @param Port The number of port.\r | |
401 | @param PortMultiplier The timeout Value of stop.\r | |
402 | @param AtapiCommand The atapi command will be used for the transfer.\r | |
403 | @param AtapiCommandLength The Length of the atapi command.\r | |
404 | @param Read The transfer direction.\r | |
405 | @param AtaCommandBlock The EFI_ATA_COMMAND_BLOCK Data.\r | |
406 | @param AtaStatusBlock The EFI_ATA_STATUS_BLOCK Data.\r | |
407 | @param MemoryAddr The pointer to the Data Buffer.\r | |
408 | @param DataCount The Data count to be transferred.\r | |
409 | @param Timeout The timeout Value of non Data transfer.\r | |
410 | \r | |
411 | @retval EFI_DEVICE_ERROR The PIO Data transfer abort with error occurs.\r | |
412 | @retval EFI_TIMEOUT The operation is time out.\r | |
413 | @retval EFI_UNSUPPORTED The device is not ready for transfer.\r | |
414 | @retval EFI_SUCCESS The PIO Data transfer executes successfully.\r | |
415 | \r | |
416 | **/\r | |
417 | EFI_STATUS\r | |
418 | EFIAPI\r | |
419 | AhciPioTransfer (\r | |
420 | IN AHCI_CONTEXT *AhciContext,\r | |
421 | IN UINT8 Port,\r | |
422 | IN UINT8 PortMultiplier,\r | |
423 | IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,\r | |
424 | IN UINT8 AtapiCommandLength,\r | |
425 | IN BOOLEAN Read,\r | |
426 | IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r | |
427 | IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r | |
428 | IN OUT VOID *MemoryAddr,\r | |
429 | IN UINT32 DataCount,\r | |
430 | IN UINT64 Timeout\r | |
431 | );\r | |
432 | \r | |
433 | \r | |
434 | #endif\r | |
435 | \r |