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1 | /** @file\r | |
2 | Architectural MSR Definitions.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
9 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
10 | This program and the accompanying materials\r | |
11 | are licensed and made available under the terms and conditions of the BSD License\r | |
12 | which accompanies this distribution. The full text of the license may be found at\r | |
13 | http://opensource.org/licenses/bsd-license.php\r | |
14 | \r | |
15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | \r | |
18 | @par Specification Reference:\r | |
19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
20 | December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1.\r | |
21 | \r | |
22 | **/\r | |
23 | \r | |
24 | #ifndef __ARCHITECTURAL_MSR_H__\r | |
25 | #define __ARCHITECTURAL_MSR_H__\r | |
26 | \r | |
27 | /**\r | |
28 | See Section 35.20, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r | |
29 | \r | |
30 | @param ECX MSR_IA32_P5_MC_ADDR (0x00000000)\r | |
31 | @param EAX Lower 32-bits of MSR value.\r | |
32 | @param EDX Upper 32-bits of MSR value.\r | |
33 | \r | |
34 | <b>Example usage</b>\r | |
35 | @code\r | |
36 | UINT64 Msr;\r | |
37 | \r | |
38 | Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);\r | |
39 | AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);\r | |
40 | @endcode\r | |
41 | **/\r | |
42 | #define MSR_IA32_P5_MC_ADDR 0x00000000\r | |
43 | \r | |
44 | \r | |
45 | /**\r | |
46 | See Section 35.20, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r | |
47 | \r | |
48 | @param ECX MSR_IA32_P5_MC_TYPE (0x00000001)\r | |
49 | @param EAX Lower 32-bits of MSR value.\r | |
50 | @param EDX Upper 32-bits of MSR value.\r | |
51 | \r | |
52 | <b>Example usage</b>\r | |
53 | @code\r | |
54 | UINT64 Msr;\r | |
55 | \r | |
56 | Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);\r | |
57 | AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);\r | |
58 | @endcode\r | |
59 | **/\r | |
60 | #define MSR_IA32_P5_MC_TYPE 0x00000001\r | |
61 | \r | |
62 | \r | |
63 | /**\r | |
64 | See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced\r | |
65 | at Display Family / Display Model 0F_03H.\r | |
66 | \r | |
67 | @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)\r | |
68 | @param EAX Lower 32-bits of MSR value.\r | |
69 | @param EDX Upper 32-bits of MSR value.\r | |
70 | \r | |
71 | <b>Example usage</b>\r | |
72 | @code\r | |
73 | UINT64 Msr;\r | |
74 | \r | |
75 | Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);\r | |
76 | AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);\r | |
77 | @endcode\r | |
78 | **/\r | |
79 | #define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006\r | |
80 | \r | |
81 | \r | |
82 | /**\r | |
83 | See Section 17.14, "Time-Stamp Counter.". Introduced at Display Family /\r | |
84 | Display Model 05_01H.\r | |
85 | \r | |
86 | @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)\r | |
87 | @param EAX Lower 32-bits of MSR value.\r | |
88 | @param EDX Upper 32-bits of MSR value.\r | |
89 | \r | |
90 | <b>Example usage</b>\r | |
91 | @code\r | |
92 | UINT64 Msr;\r | |
93 | \r | |
94 | Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);\r | |
95 | AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);\r | |
96 | @endcode\r | |
97 | **/\r | |
98 | #define MSR_IA32_TIME_STAMP_COUNTER 0x00000010\r | |
99 | \r | |
100 | \r | |
101 | /**\r | |
102 | Platform ID (RO) The operating system can use this MSR to determine "slot"\r | |
103 | information for the processor and the proper microcode update to load.\r | |
104 | Introduced at Display Family / Display Model 06_01H.\r | |
105 | \r | |
106 | @param ECX MSR_IA32_PLATFORM_ID (0x00000017)\r | |
107 | @param EAX Lower 32-bits of MSR value.\r | |
108 | Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r | |
109 | @param EDX Upper 32-bits of MSR value.\r | |
110 | Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r | |
111 | \r | |
112 | <b>Example usage</b>\r | |
113 | @code\r | |
114 | MSR_IA32_PLATFORM_ID_REGISTER Msr;\r | |
115 | \r | |
116 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);\r | |
117 | @endcode\r | |
118 | **/\r | |
119 | #define MSR_IA32_PLATFORM_ID 0x00000017\r | |
120 | \r | |
121 | /**\r | |
122 | MSR information returned for MSR index #MSR_IA32_PLATFORM_ID\r | |
123 | **/\r | |
124 | typedef union {\r | |
125 | ///\r | |
126 | /// Individual bit fields\r | |
127 | ///\r | |
128 | struct {\r | |
129 | UINT32 Reserved1:32;\r | |
130 | UINT32 Reserved2:18;\r | |
131 | ///\r | |
132 | /// [Bits 52:50] Platform Id (RO) Contains information concerning the\r | |
133 | /// intended platform for the processor.\r | |
134 | /// 52 51 50\r | |
135 | /// -- -- --\r | |
136 | /// 0 0 0 Processor Flag 0.\r | |
137 | /// 0 0 1 Processor Flag 1\r | |
138 | /// 0 1 0 Processor Flag 2\r | |
139 | /// 0 1 1 Processor Flag 3\r | |
140 | /// 1 0 0 Processor Flag 4\r | |
141 | /// 1 0 1 Processor Flag 5\r | |
142 | /// 1 1 0 Processor Flag 6\r | |
143 | /// 1 1 1 Processor Flag 7\r | |
144 | ///\r | |
145 | UINT32 PlatformId:3;\r | |
146 | UINT32 Reserved3:11;\r | |
147 | } Bits;\r | |
148 | ///\r | |
149 | /// All bit fields as a 64-bit value\r | |
150 | ///\r | |
151 | UINT64 Uint64;\r | |
152 | } MSR_IA32_PLATFORM_ID_REGISTER;\r | |
153 | \r | |
154 | \r | |
155 | /**\r | |
156 | 06_01H.\r | |
157 | \r | |
158 | @param ECX MSR_IA32_APIC_BASE (0x0000001B)\r | |
159 | @param EAX Lower 32-bits of MSR value.\r | |
160 | Described by the type MSR_IA32_APIC_BASE_REGISTER.\r | |
161 | @param EDX Upper 32-bits of MSR value.\r | |
162 | Described by the type MSR_IA32_APIC_BASE_REGISTER.\r | |
163 | \r | |
164 | <b>Example usage</b>\r | |
165 | @code\r | |
166 | MSR_IA32_APIC_BASE_REGISTER Msr;\r | |
167 | \r | |
168 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r | |
169 | AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);\r | |
170 | @endcode\r | |
171 | **/\r | |
172 | #define MSR_IA32_APIC_BASE 0x0000001B\r | |
173 | \r | |
174 | /**\r | |
175 | MSR information returned for MSR index #MSR_IA32_APIC_BASE\r | |
176 | **/\r | |
177 | typedef union {\r | |
178 | ///\r | |
179 | /// Individual bit fields\r | |
180 | ///\r | |
181 | struct {\r | |
182 | UINT32 Reserved1:8;\r | |
183 | ///\r | |
184 | /// [Bit 8] BSP flag (R/W).\r | |
185 | ///\r | |
186 | UINT32 BSP:1;\r | |
187 | UINT32 Reserved2:1;\r | |
188 | ///\r | |
189 | /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display\r | |
190 | /// Model 06_1AH.\r | |
191 | ///\r | |
192 | UINT32 EXTD:1;\r | |
193 | ///\r | |
194 | /// [Bit 11] APIC Global Enable (R/W).\r | |
195 | ///\r | |
196 | UINT32 EN:1;\r | |
197 | ///\r | |
198 | /// [Bits 31:12] APIC Base (R/W).\r | |
199 | ///\r | |
200 | UINT32 ApicBase:20;\r | |
201 | ///\r | |
202 | /// [Bits 63:32] APIC Base (R/W).\r | |
203 | ///\r | |
204 | UINT32 ApicBaseHi:32;\r | |
205 | } Bits;\r | |
206 | ///\r | |
207 | /// All bit fields as a 64-bit value\r | |
208 | ///\r | |
209 | UINT64 Uint64;\r | |
210 | } MSR_IA32_APIC_BASE_REGISTER;\r | |
211 | \r | |
212 | \r | |
213 | /**\r | |
214 | Control Features in Intel 64 Processor (R/W). If any one enumeration\r | |
215 | condition for defined bit field holds.\r | |
216 | \r | |
217 | @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)\r | |
218 | @param EAX Lower 32-bits of MSR value.\r | |
219 | Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r | |
220 | @param EDX Upper 32-bits of MSR value.\r | |
221 | Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r | |
222 | \r | |
223 | <b>Example usage</b>\r | |
224 | @code\r | |
225 | MSR_IA32_FEATURE_CONTROL_REGISTER Msr;\r | |
226 | \r | |
227 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);\r | |
228 | AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);\r | |
229 | @endcode\r | |
230 | **/\r | |
231 | #define MSR_IA32_FEATURE_CONTROL 0x0000003A\r | |
232 | \r | |
233 | /**\r | |
234 | MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL\r | |
235 | **/\r | |
236 | typedef union {\r | |
237 | ///\r | |
238 | /// Individual bit fields\r | |
239 | ///\r | |
240 | struct {\r | |
241 | ///\r | |
242 | /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from\r | |
243 | /// being written, writes to this bit will result in GP(0). Note: Once the\r | |
244 | /// Lock bit is set, the contents of this register cannot be modified.\r | |
245 | /// Therefore the lock bit must be set after configuring support for Intel\r | |
246 | /// Virtualization Technology and prior to transferring control to an\r | |
247 | /// option ROM or the OS. Hence, once the Lock bit is set, the entire\r | |
248 | /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD\r | |
249 | /// is not deasserted. If any one enumeration condition for defined bit\r | |
250 | /// field position greater than bit 0 holds.\r | |
251 | ///\r | |
252 | UINT32 Lock:1;\r | |
253 | ///\r | |
254 | /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a\r | |
255 | /// system executive to use VMX in conjunction with SMX to support\r | |
256 | /// Intel(R) Trusted Execution Technology. BIOS must set this bit only\r | |
257 | /// when the CPUID function 1 returns VMX feature flag and SMX feature\r | |
258 | /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&\r | |
259 | /// CPUID.01H:ECX[6] = 1.\r | |
260 | ///\r | |
261 | UINT32 EnableVmxInsideSmx:1;\r | |
262 | ///\r | |
263 | /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX\r | |
264 | /// for system executive that do not require SMX. BIOS must set this bit\r | |
265 | /// only when the CPUID function 1 returns VMX feature flag set (ECX bit\r | |
266 | /// 5). If CPUID.01H:ECX[5] = 1.\r | |
267 | ///\r | |
268 | UINT32 EnableVmxOutsideSmx:1;\r | |
269 | UINT32 Reserved1:5;\r | |
270 | ///\r | |
271 | /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit\r | |
272 | /// in the field represents an enable control for a corresponding SENTER\r | |
273 | /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If\r | |
274 | /// CPUID.01H:ECX[6] = 1.\r | |
275 | ///\r | |
276 | UINT32 SenterLocalFunctionEnables:7;\r | |
277 | ///\r | |
278 | /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable\r | |
279 | /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit\r | |
280 | /// 6] is set. If CPUID.01H:ECX[6] = 1.\r | |
281 | ///\r | |
282 | UINT32 SenterGlobalEnable:1;\r | |
283 | UINT32 Reserved2:2;\r | |
284 | ///\r | |
285 | /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX\r | |
286 | /// leaf functions. This bit is supported only if CPUID.1:ECX.[bit 6] is\r | |
287 | /// set. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r | |
288 | ///\r | |
289 | UINT32 SgxEnable:1;\r | |
290 | UINT32 Reserved3:1;\r | |
291 | ///\r | |
292 | /// [Bit 20] LMCE On (R/WL): When set, system software can program the\r | |
293 | /// MSRs associated with LMCE to configure delivery of some machine check\r | |
294 | /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.\r | |
295 | ///\r | |
296 | UINT32 LmceOn:1;\r | |
297 | UINT32 Reserved4:11;\r | |
298 | UINT32 Reserved5:32;\r | |
299 | } Bits;\r | |
300 | ///\r | |
301 | /// All bit fields as a 32-bit value\r | |
302 | ///\r | |
303 | UINT32 Uint32;\r | |
304 | ///\r | |
305 | /// All bit fields as a 64-bit value\r | |
306 | ///\r | |
307 | UINT64 Uint64;\r | |
308 | } MSR_IA32_FEATURE_CONTROL_REGISTER;\r | |
309 | \r | |
310 | \r | |
311 | /**\r | |
312 | Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,\r | |
313 | ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for\r | |
314 | a logical processor. Reset value is Zero. A write to IA32_TSC will modify\r | |
315 | the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does\r | |
316 | not affect the internal invariant TSC hardware.\r | |
317 | \r | |
318 | @param ECX MSR_IA32_TSC_ADJUST (0x0000003B)\r | |
319 | @param EAX Lower 32-bits of MSR value.\r | |
320 | @param EDX Upper 32-bits of MSR value.\r | |
321 | \r | |
322 | <b>Example usage</b>\r | |
323 | @code\r | |
324 | UINT64 Msr;\r | |
325 | \r | |
326 | Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);\r | |
327 | AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);\r | |
328 | @endcode\r | |
329 | **/\r | |
330 | #define MSR_IA32_TSC_ADJUST 0x0000003B\r | |
331 | \r | |
332 | \r | |
333 | /**\r | |
334 | BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a\r | |
335 | microcode update to be loaded into the processor. See Section 9.11.6,\r | |
336 | "Microcode Update Loader." A processor may prevent writing to this MSR when\r | |
337 | loading guest states on VM entries or saving guest states on VM exits.\r | |
338 | Introduced at Display Family / Display Model 06_01H.\r | |
339 | \r | |
340 | @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)\r | |
341 | @param EAX Lower 32-bits of MSR value.\r | |
342 | @param EDX Upper 32-bits of MSR value.\r | |
343 | \r | |
344 | <b>Example usage</b>\r | |
345 | @code\r | |
346 | UINT64 Msr;\r | |
347 | \r | |
348 | Msr = 0;\r | |
349 | AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);\r | |
350 | @endcode\r | |
351 | **/\r | |
352 | #define MSR_IA32_BIOS_UPDT_TRIG 0x00000079\r | |
353 | \r | |
354 | \r | |
355 | /**\r | |
356 | BIOS Update Signature (RO) Returns the microcode update signature following\r | |
357 | the execution of CPUID.01H. A processor may prevent writing to this MSR when\r | |
358 | loading guest states on VM entries or saving guest states on VM exits.\r | |
359 | Introduced at Display Family / Display Model 06_01H.\r | |
360 | \r | |
361 | @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)\r | |
362 | @param EAX Lower 32-bits of MSR value.\r | |
363 | Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r | |
364 | @param EDX Upper 32-bits of MSR value.\r | |
365 | Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r | |
366 | \r | |
367 | <b>Example usage</b>\r | |
368 | @code\r | |
369 | MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;\r | |
370 | \r | |
371 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);\r | |
372 | @endcode\r | |
373 | **/\r | |
374 | #define MSR_IA32_BIOS_SIGN_ID 0x0000008B\r | |
375 | \r | |
376 | /**\r | |
377 | MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID\r | |
378 | **/\r | |
379 | typedef union {\r | |
380 | ///\r | |
381 | /// Individual bit fields\r | |
382 | ///\r | |
383 | struct {\r | |
384 | UINT32 Reserved:32;\r | |
385 | ///\r | |
386 | /// [Bits 63:32] Microcode update signature. This field contains the\r | |
387 | /// signature of the currently loaded microcode update when read following\r | |
388 | /// the execution of the CPUID instruction, function 1. It is required\r | |
389 | /// that this register field be pre-loaded with zero prior to executing\r | |
390 | /// the CPUID, function 1. If the field remains equal to zero, then there\r | |
391 | /// is no microcode update loaded. Another nonzero value will be the\r | |
392 | /// signature.\r | |
393 | ///\r | |
394 | UINT32 MicrocodeUpdateSignature:32;\r | |
395 | } Bits;\r | |
396 | ///\r | |
397 | /// All bit fields as a 64-bit value\r | |
398 | ///\r | |
399 | UINT64 Uint64;\r | |
400 | } MSR_IA32_BIOS_SIGN_ID_REGISTER;\r | |
401 | \r | |
402 | \r | |
403 | /**\r | |
404 | SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1. CPUID.01H: ECX[6] =\r | |
405 | 1.\r | |
406 | \r | |
407 | @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)\r | |
408 | @param EAX Lower 32-bits of MSR value.\r | |
409 | Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r | |
410 | @param EDX Upper 32-bits of MSR value.\r | |
411 | Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r | |
412 | \r | |
413 | <b>Example usage</b>\r | |
414 | @code\r | |
415 | MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;\r | |
416 | \r | |
417 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);\r | |
418 | AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);\r | |
419 | @endcode\r | |
420 | **/\r | |
421 | #define MSR_IA32_SMM_MONITOR_CTL 0x0000009B\r | |
422 | \r | |
423 | /**\r | |
424 | MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL\r | |
425 | **/\r | |
426 | typedef union {\r | |
427 | ///\r | |
428 | /// Individual bit fields\r | |
429 | ///\r | |
430 | struct {\r | |
431 | ///\r | |
432 | /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this\r | |
433 | /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment\r | |
434 | /// (see Section 34.15.6), the dual-monitor treatment cannot be activated\r | |
435 | /// if the bit is 0. This bit is cleared when the logical processor is\r | |
436 | /// reset.\r | |
437 | ///\r | |
438 | UINT32 Valid:1;\r | |
439 | UINT32 Reserved1:1;\r | |
440 | ///\r | |
441 | /// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the\r | |
442 | /// default treatment of SMIs and SMM. Executions of VMXOFF unblock SMIs\r | |
443 | /// unless bit 2 is 1 (the value of bit 0 is irrelevant).\r | |
444 | ///\r | |
445 | UINT32 BlockSmi:1;\r | |
446 | UINT32 Reserved2:9;\r | |
447 | ///\r | |
448 | /// [Bits 31:12] MSEG Base (R/W).\r | |
449 | ///\r | |
450 | UINT32 MsegBase:20;\r | |
451 | UINT32 Reserved3:32;\r | |
452 | } Bits;\r | |
453 | ///\r | |
454 | /// All bit fields as a 32-bit value\r | |
455 | ///\r | |
456 | UINT32 Uint32;\r | |
457 | ///\r | |
458 | /// All bit fields as a 64-bit value\r | |
459 | ///\r | |
460 | UINT64 Uint64;\r | |
461 | } MSR_IA32_SMM_MONITOR_CTL_REGISTER;\r | |
462 | \r | |
463 | \r | |
464 | /**\r | |
465 | Base address of the logical processor's SMRAM image (RO, SMM only). If\r | |
466 | IA32_VMX_MISC[15].\r | |
467 | \r | |
468 | @param ECX MSR_IA32_SMBASE (0x0000009E)\r | |
469 | @param EAX Lower 32-bits of MSR value.\r | |
470 | @param EDX Upper 32-bits of MSR value.\r | |
471 | \r | |
472 | <b>Example usage</b>\r | |
473 | @code\r | |
474 | UINT64 Msr;\r | |
475 | \r | |
476 | Msr = AsmReadMsr64 (MSR_IA32_SMBASE);\r | |
477 | @endcode\r | |
478 | **/\r | |
479 | #define MSR_IA32_SMBASE 0x0000009E\r | |
480 | \r | |
481 | \r | |
482 | /**\r | |
483 | General Performance Counters (R/W).\r | |
484 | MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.\r | |
485 | \r | |
486 | @param ECX MSR_IA32_PMCn\r | |
487 | @param EAX Lower 32-bits of MSR value.\r | |
488 | @param EDX Upper 32-bits of MSR value.\r | |
489 | \r | |
490 | <b>Example usage</b>\r | |
491 | @code\r | |
492 | UINT64 Msr;\r | |
493 | \r | |
494 | Msr = AsmReadMsr64 (MSR_IA32_PMC0);\r | |
495 | AsmWriteMsr64 (MSR_IA32_PMC0, Msr);\r | |
496 | @endcode\r | |
497 | @{\r | |
498 | **/\r | |
499 | #define MSR_IA32_PMC0 0x000000C1\r | |
500 | #define MSR_IA32_PMC1 0x000000C2\r | |
501 | #define MSR_IA32_PMC2 0x000000C3\r | |
502 | #define MSR_IA32_PMC3 0x000000C4\r | |
503 | #define MSR_IA32_PMC4 0x000000C5\r | |
504 | #define MSR_IA32_PMC5 0x000000C6\r | |
505 | #define MSR_IA32_PMC6 0x000000C7\r | |
506 | #define MSR_IA32_PMC7 0x000000C8\r | |
507 | /// @}\r | |
508 | \r | |
509 | \r | |
510 | /**\r | |
511 | TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.\r | |
512 | C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative\r | |
513 | to TSC freq.) when the logical processor is in C0. Cleared upon overflow /\r | |
514 | wrap-around of IA32_APERF.\r | |
515 | \r | |
516 | @param ECX MSR_IA32_MPERF (0x000000E7)\r | |
517 | @param EAX Lower 32-bits of MSR value.\r | |
518 | @param EDX Upper 32-bits of MSR value.\r | |
519 | \r | |
520 | <b>Example usage</b>\r | |
521 | @code\r | |
522 | UINT64 Msr;\r | |
523 | \r | |
524 | Msr = AsmReadMsr64 (MSR_IA32_MPERF);\r | |
525 | AsmWriteMsr64 (MSR_IA32_MPERF, Msr);\r | |
526 | @endcode\r | |
527 | **/\r | |
528 | #define MSR_IA32_MPERF 0x000000E7\r | |
529 | \r | |
530 | \r | |
531 | /**\r | |
532 | Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =\r | |
533 | 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at\r | |
534 | the coordinated clock frequency, when the logical processor is in C0.\r | |
535 | Cleared upon overflow / wrap-around of IA32_MPERF.\r | |
536 | \r | |
537 | @param ECX MSR_IA32_APERF (0x000000E8)\r | |
538 | @param EAX Lower 32-bits of MSR value.\r | |
539 | @param EDX Upper 32-bits of MSR value.\r | |
540 | \r | |
541 | <b>Example usage</b>\r | |
542 | @code\r | |
543 | UINT64 Msr;\r | |
544 | \r | |
545 | Msr = AsmReadMsr64 (MSR_IA32_APERF);\r | |
546 | AsmWriteMsr64 (MSR_IA32_APERF, Msr);\r | |
547 | @endcode\r | |
548 | **/\r | |
549 | #define MSR_IA32_APERF 0x000000E8\r | |
550 | \r | |
551 | \r | |
552 | /**\r | |
553 | MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".\r | |
554 | Introduced at Display Family / Display Model 06_01H.\r | |
555 | \r | |
556 | @param ECX MSR_IA32_MTRRCAP (0x000000FE)\r | |
557 | @param EAX Lower 32-bits of MSR value.\r | |
558 | Described by the type MSR_IA32_MTRRCAP_REGISTER.\r | |
559 | @param EDX Upper 32-bits of MSR value.\r | |
560 | Described by the type MSR_IA32_MTRRCAP_REGISTER.\r | |
561 | \r | |
562 | <b>Example usage</b>\r | |
563 | @code\r | |
564 | MSR_IA32_MTRRCAP_REGISTER Msr;\r | |
565 | \r | |
566 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);\r | |
567 | @endcode\r | |
568 | **/\r | |
569 | #define MSR_IA32_MTRRCAP 0x000000FE\r | |
570 | \r | |
571 | /**\r | |
572 | MSR information returned for MSR index #MSR_IA32_MTRRCAP\r | |
573 | **/\r | |
574 | typedef union {\r | |
575 | ///\r | |
576 | /// Individual bit fields\r | |
577 | ///\r | |
578 | struct {\r | |
579 | ///\r | |
580 | /// [Bits 7:0] VCNT: The number of variable memory type ranges in the\r | |
581 | /// processor.\r | |
582 | ///\r | |
583 | UINT32 VCNT:8;\r | |
584 | ///\r | |
585 | /// [Bit 8] Fixed range MTRRs are supported when set.\r | |
586 | ///\r | |
587 | UINT32 FIX:1;\r | |
588 | UINT32 Reserved1:1;\r | |
589 | ///\r | |
590 | /// [Bit 10] WC Supported when set.\r | |
591 | ///\r | |
592 | UINT32 WC:1;\r | |
593 | ///\r | |
594 | /// [Bit 11] SMRR Supported when set.\r | |
595 | ///\r | |
596 | UINT32 SMRR:1;\r | |
597 | UINT32 Reserved2:20;\r | |
598 | UINT32 Reserved3:32;\r | |
599 | } Bits;\r | |
600 | ///\r | |
601 | /// All bit fields as a 32-bit value\r | |
602 | ///\r | |
603 | UINT32 Uint32;\r | |
604 | ///\r | |
605 | /// All bit fields as a 64-bit value\r | |
606 | ///\r | |
607 | UINT64 Uint64;\r | |
608 | } MSR_IA32_MTRRCAP_REGISTER;\r | |
609 | \r | |
610 | \r | |
611 | /**\r | |
612 | SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r | |
613 | \r | |
614 | @param ECX MSR_IA32_SYSENTER_CS (0x00000174)\r | |
615 | @param EAX Lower 32-bits of MSR value.\r | |
616 | Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r | |
617 | @param EDX Upper 32-bits of MSR value.\r | |
618 | Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r | |
619 | \r | |
620 | <b>Example usage</b>\r | |
621 | @code\r | |
622 | MSR_IA32_SYSENTER_CS_REGISTER Msr;\r | |
623 | \r | |
624 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);\r | |
625 | AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);\r | |
626 | @endcode\r | |
627 | **/\r | |
628 | #define MSR_IA32_SYSENTER_CS 0x00000174\r | |
629 | \r | |
630 | /**\r | |
631 | MSR information returned for MSR index #MSR_IA32_SYSENTER_CS\r | |
632 | **/\r | |
633 | typedef union {\r | |
634 | ///\r | |
635 | /// Individual bit fields\r | |
636 | ///\r | |
637 | struct {\r | |
638 | ///\r | |
639 | /// [Bits 15:0] CS Selector.\r | |
640 | ///\r | |
641 | UINT32 CS:16;\r | |
642 | UINT32 Reserved1:16;\r | |
643 | UINT32 Reserved2:32;\r | |
644 | } Bits;\r | |
645 | ///\r | |
646 | /// All bit fields as a 32-bit value\r | |
647 | ///\r | |
648 | UINT32 Uint32;\r | |
649 | ///\r | |
650 | /// All bit fields as a 64-bit value\r | |
651 | ///\r | |
652 | UINT64 Uint64;\r | |
653 | } MSR_IA32_SYSENTER_CS_REGISTER;\r | |
654 | \r | |
655 | \r | |
656 | /**\r | |
657 | SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r | |
658 | \r | |
659 | @param ECX MSR_IA32_SYSENTER_ESP (0x00000175)\r | |
660 | @param EAX Lower 32-bits of MSR value.\r | |
661 | @param EDX Upper 32-bits of MSR value.\r | |
662 | \r | |
663 | <b>Example usage</b>\r | |
664 | @code\r | |
665 | UINT64 Msr;\r | |
666 | \r | |
667 | Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);\r | |
668 | AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);\r | |
669 | @endcode\r | |
670 | **/\r | |
671 | #define MSR_IA32_SYSENTER_ESP 0x00000175\r | |
672 | \r | |
673 | \r | |
674 | /**\r | |
675 | SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r | |
676 | \r | |
677 | @param ECX MSR_IA32_SYSENTER_EIP (0x00000176)\r | |
678 | @param EAX Lower 32-bits of MSR value.\r | |
679 | @param EDX Upper 32-bits of MSR value.\r | |
680 | \r | |
681 | <b>Example usage</b>\r | |
682 | @code\r | |
683 | UINT64 Msr;\r | |
684 | \r | |
685 | Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);\r | |
686 | AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);\r | |
687 | @endcode\r | |
688 | **/\r | |
689 | #define MSR_IA32_SYSENTER_EIP 0x00000176\r | |
690 | \r | |
691 | \r | |
692 | /**\r | |
693 | Global Machine Check Capability (RO). Introduced at Display Family / Display\r | |
694 | Model 06_01H.\r | |
695 | \r | |
696 | @param ECX MSR_IA32_MCG_CAP (0x00000179)\r | |
697 | @param EAX Lower 32-bits of MSR value.\r | |
698 | Described by the type MSR_IA32_MCG_CAP_REGISTER.\r | |
699 | @param EDX Upper 32-bits of MSR value.\r | |
700 | Described by the type MSR_IA32_MCG_CAP_REGISTER.\r | |
701 | \r | |
702 | <b>Example usage</b>\r | |
703 | @code\r | |
704 | MSR_IA32_MCG_CAP_REGISTER Msr;\r | |
705 | \r | |
706 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r | |
707 | @endcode\r | |
708 | **/\r | |
709 | #define MSR_IA32_MCG_CAP 0x00000179\r | |
710 | \r | |
711 | /**\r | |
712 | MSR information returned for MSR index #MSR_IA32_MCG_CAP\r | |
713 | **/\r | |
714 | typedef union {\r | |
715 | ///\r | |
716 | /// Individual bit fields\r | |
717 | ///\r | |
718 | struct {\r | |
719 | ///\r | |
720 | /// [Bits 7:0] Count: Number of reporting banks.\r | |
721 | ///\r | |
722 | UINT32 Count:8;\r | |
723 | ///\r | |
724 | /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.\r | |
725 | ///\r | |
726 | UINT32 MCG_CTL_P:1;\r | |
727 | ///\r | |
728 | /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present\r | |
729 | /// if this bit is set.\r | |
730 | ///\r | |
731 | UINT32 MCG_EXT_P:1;\r | |
732 | ///\r | |
733 | /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.\r | |
734 | /// Introduced at Display Family / Display Model 06_01H.\r | |
735 | ///\r | |
736 | UINT32 MCP_CMCI_P:1;\r | |
737 | ///\r | |
738 | /// [Bit 11] MCG_TES_P: Threshold-based error status register are present\r | |
739 | /// if this bit is set.\r | |
740 | ///\r | |
741 | UINT32 MCG_TES_P:1;\r | |
742 | UINT32 Reserved1:4;\r | |
743 | ///\r | |
744 | /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state\r | |
745 | /// registers present.\r | |
746 | ///\r | |
747 | UINT32 MCG_EXT_CNT:8;\r | |
748 | ///\r | |
749 | /// [Bit 24] MCG_SER_P: The processor supports software error recovery if\r | |
750 | /// this bit is set.\r | |
751 | ///\r | |
752 | UINT32 MCG_SER_P:1;\r | |
753 | UINT32 Reserved2:1;\r | |
754 | ///\r | |
755 | /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform\r | |
756 | /// firmware to be invoked when an error is detected so that it may\r | |
757 | /// provide additional platform specific information in an ACPI format\r | |
758 | /// "Generic Error Data Entry" that augments the data included in machine\r | |
759 | /// check bank registers. Introduced at Display Family / Display Model\r | |
760 | /// 06_3EH.\r | |
761 | ///\r | |
762 | UINT32 MCG_ELOG_P:1;\r | |
763 | ///\r | |
764 | /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended\r | |
765 | /// state in IA32_MCG_STATUS and associated MSR necessary to configure\r | |
766 | /// Local Machine Check Exception (LMCE). Introduced at Display Family /\r | |
767 | /// Display Model 06_3EH.\r | |
768 | ///\r | |
769 | UINT32 MCG_LMCE_P:1;\r | |
770 | UINT32 Reserved3:4;\r | |
771 | UINT32 Reserved4:32;\r | |
772 | } Bits;\r | |
773 | ///\r | |
774 | /// All bit fields as a 32-bit value\r | |
775 | ///\r | |
776 | UINT32 Uint32;\r | |
777 | ///\r | |
778 | /// All bit fields as a 64-bit value\r | |
779 | ///\r | |
780 | UINT64 Uint64;\r | |
781 | } MSR_IA32_MCG_CAP_REGISTER;\r | |
782 | \r | |
783 | \r | |
784 | /**\r | |
785 | Global Machine Check Status (R/W0). Introduced at Display Family / Display\r | |
786 | Model 06_01H.\r | |
787 | \r | |
788 | @param ECX MSR_IA32_MCG_STATUS (0x0000017A)\r | |
789 | @param EAX Lower 32-bits of MSR value.\r | |
790 | Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r | |
791 | @param EDX Upper 32-bits of MSR value.\r | |
792 | Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r | |
793 | \r | |
794 | <b>Example usage</b>\r | |
795 | @code\r | |
796 | MSR_IA32_MCG_STATUS_REGISTER Msr;\r | |
797 | \r | |
798 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);\r | |
799 | AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);\r | |
800 | @endcode\r | |
801 | **/\r | |
802 | #define MSR_IA32_MCG_STATUS 0x0000017A\r | |
803 | \r | |
804 | /**\r | |
805 | MSR information returned for MSR index #MSR_IA32_MCG_STATUS\r | |
806 | **/\r | |
807 | typedef union {\r | |
808 | ///\r | |
809 | /// Individual bit fields\r | |
810 | ///\r | |
811 | struct {\r | |
812 | ///\r | |
813 | /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display\r | |
814 | /// Model 06_01H.\r | |
815 | ///\r | |
816 | UINT32 RIPV:1;\r | |
817 | ///\r | |
818 | /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display\r | |
819 | /// Model 06_01H.\r | |
820 | ///\r | |
821 | UINT32 EIPV:1;\r | |
822 | ///\r | |
823 | /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family\r | |
824 | /// / Display Model 06_01H.\r | |
825 | ///\r | |
826 | UINT32 MCIP:1;\r | |
827 | ///\r | |
828 | /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.\r | |
829 | ///\r | |
830 | UINT32 LMCE_S:1;\r | |
831 | UINT32 Reserved1:28;\r | |
832 | UINT32 Reserved2:32;\r | |
833 | } Bits;\r | |
834 | ///\r | |
835 | /// All bit fields as a 32-bit value\r | |
836 | ///\r | |
837 | UINT32 Uint32;\r | |
838 | ///\r | |
839 | /// All bit fields as a 64-bit value\r | |
840 | ///\r | |
841 | UINT64 Uint64;\r | |
842 | } MSR_IA32_MCG_STATUS_REGISTER;\r | |
843 | \r | |
844 | \r | |
845 | /**\r | |
846 | Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.\r | |
847 | \r | |
848 | @param ECX MSR_IA32_MCG_CTL (0x0000017B)\r | |
849 | @param EAX Lower 32-bits of MSR value.\r | |
850 | @param EDX Upper 32-bits of MSR value.\r | |
851 | \r | |
852 | <b>Example usage</b>\r | |
853 | @code\r | |
854 | UINT64 Msr;\r | |
855 | \r | |
856 | Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);\r | |
857 | AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);\r | |
858 | @endcode\r | |
859 | **/\r | |
860 | #define MSR_IA32_MCG_CTL 0x0000017B\r | |
861 | \r | |
862 | \r | |
863 | /**\r | |
864 | Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.\r | |
865 | \r | |
866 | @param ECX MSR_IA32_PERFEVTSELn\r | |
867 | @param EAX Lower 32-bits of MSR value.\r | |
868 | Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r | |
869 | @param EDX Upper 32-bits of MSR value.\r | |
870 | Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r | |
871 | \r | |
872 | <b>Example usage</b>\r | |
873 | @code\r | |
874 | MSR_IA32_PERFEVTSEL_REGISTER Msr;\r | |
875 | \r | |
876 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);\r | |
877 | AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);\r | |
878 | @endcode\r | |
879 | @{\r | |
880 | **/\r | |
881 | #define MSR_IA32_PERFEVTSEL0 0x00000186\r | |
882 | #define MSR_IA32_PERFEVTSEL1 0x00000187\r | |
883 | #define MSR_IA32_PERFEVTSEL2 0x00000188\r | |
884 | #define MSR_IA32_PERFEVTSEL3 0x00000189\r | |
885 | /// @}\r | |
886 | \r | |
887 | /**\r | |
888 | MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to\r | |
889 | #MSR_IA32_PERFEVTSEL3\r | |
890 | **/\r | |
891 | typedef union {\r | |
892 | ///\r | |
893 | /// Individual bit fields\r | |
894 | ///\r | |
895 | struct {\r | |
896 | ///\r | |
897 | /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r | |
898 | ///\r | |
899 | UINT32 EventSelect:8;\r | |
900 | ///\r | |
901 | /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r | |
902 | /// detect on the selected event logic.\r | |
903 | ///\r | |
904 | UINT32 UMASK:8;\r | |
905 | ///\r | |
906 | /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r | |
907 | ///\r | |
908 | UINT32 USR:1;\r | |
909 | ///\r | |
910 | /// [Bit 17] OS: Counts while in privilege level is ring 0.\r | |
911 | ///\r | |
912 | UINT32 OS:1;\r | |
913 | ///\r | |
914 | /// [Bit 18] Edge: Enables edge detection if set.\r | |
915 | ///\r | |
916 | UINT32 E:1;\r | |
917 | ///\r | |
918 | /// [Bit 19] PC: enables pin control.\r | |
919 | ///\r | |
920 | UINT32 PC:1;\r | |
921 | ///\r | |
922 | /// [Bit 20] INT: enables interrupt on counter overflow.\r | |
923 | ///\r | |
924 | UINT32 INT:1;\r | |
925 | ///\r | |
926 | /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r | |
927 | /// event conditions occurring across all logical processors sharing a\r | |
928 | /// processor core. When set to 0, the counter only increments the\r | |
929 | /// associated event conditions occurring in the logical processor which\r | |
930 | /// programmed the MSR.\r | |
931 | ///\r | |
932 | UINT32 ANY:1;\r | |
933 | ///\r | |
934 | /// [Bit 22] EN: enables the corresponding performance counter to commence\r | |
935 | /// counting when this bit is set.\r | |
936 | ///\r | |
937 | UINT32 EN:1;\r | |
938 | ///\r | |
939 | /// [Bit 23] INV: invert the CMASK.\r | |
940 | ///\r | |
941 | UINT32 INV:1;\r | |
942 | ///\r | |
943 | /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r | |
944 | /// performance counter increments each cycle if the event count is\r | |
945 | /// greater than or equal to the CMASK.\r | |
946 | ///\r | |
947 | UINT32 CMASK:8;\r | |
948 | UINT32 Reserved:32;\r | |
949 | } Bits;\r | |
950 | ///\r | |
951 | /// All bit fields as a 32-bit value\r | |
952 | ///\r | |
953 | UINT32 Uint32;\r | |
954 | ///\r | |
955 | /// All bit fields as a 64-bit value\r | |
956 | ///\r | |
957 | UINT64 Uint64;\r | |
958 | } MSR_IA32_PERFEVTSEL_REGISTER;\r | |
959 | \r | |
960 | \r | |
961 | /**\r | |
962 | Current performance state(P-State) operating point (RO). Introduced at\r | |
963 | Display Family / Display Model 0F_03H.\r | |
964 | \r | |
965 | @param ECX MSR_IA32_PERF_STATUS (0x00000198)\r | |
966 | @param EAX Lower 32-bits of MSR value.\r | |
967 | Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r | |
968 | @param EDX Upper 32-bits of MSR value.\r | |
969 | Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r | |
970 | \r | |
971 | <b>Example usage</b>\r | |
972 | @code\r | |
973 | MSR_IA32_PERF_STATUS_REGISTER Msr;\r | |
974 | \r | |
975 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);\r | |
976 | @endcode\r | |
977 | **/\r | |
978 | #define MSR_IA32_PERF_STATUS 0x00000198\r | |
979 | \r | |
980 | /**\r | |
981 | MSR information returned for MSR index #MSR_IA32_PERF_STATUS\r | |
982 | **/\r | |
983 | typedef union {\r | |
984 | ///\r | |
985 | /// Individual bit fields\r | |
986 | ///\r | |
987 | struct {\r | |
988 | ///\r | |
989 | /// [Bits 15:0] Current performance State Value.\r | |
990 | ///\r | |
991 | UINT32 State:16;\r | |
992 | UINT32 Reserved1:16;\r | |
993 | UINT32 Reserved2:32;\r | |
994 | } Bits;\r | |
995 | ///\r | |
996 | /// All bit fields as a 32-bit value\r | |
997 | ///\r | |
998 | UINT32 Uint32;\r | |
999 | ///\r | |
1000 | /// All bit fields as a 64-bit value\r | |
1001 | ///\r | |
1002 | UINT64 Uint64;\r | |
1003 | } MSR_IA32_PERF_STATUS_REGISTER;\r | |
1004 | \r | |
1005 | \r | |
1006 | /**\r | |
1007 | (R/W). Introduced at Display Family / Display Model 0F_03H.\r | |
1008 | \r | |
1009 | @param ECX MSR_IA32_PERF_CTL (0x00000199)\r | |
1010 | @param EAX Lower 32-bits of MSR value.\r | |
1011 | Described by the type MSR_IA32_PERF_CTL_REGISTER.\r | |
1012 | @param EDX Upper 32-bits of MSR value.\r | |
1013 | Described by the type MSR_IA32_PERF_CTL_REGISTER.\r | |
1014 | \r | |
1015 | <b>Example usage</b>\r | |
1016 | @code\r | |
1017 | MSR_IA32_PERF_CTL_REGISTER Msr;\r | |
1018 | \r | |
1019 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);\r | |
1020 | AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);\r | |
1021 | @endcode\r | |
1022 | **/\r | |
1023 | #define MSR_IA32_PERF_CTL 0x00000199\r | |
1024 | \r | |
1025 | /**\r | |
1026 | MSR information returned for MSR index #MSR_IA32_PERF_CTL\r | |
1027 | **/\r | |
1028 | typedef union {\r | |
1029 | ///\r | |
1030 | /// Individual bit fields\r | |
1031 | ///\r | |
1032 | struct {\r | |
1033 | ///\r | |
1034 | /// [Bits 15:0] Target performance State Value.\r | |
1035 | ///\r | |
1036 | UINT32 TargetState:16;\r | |
1037 | UINT32 Reserved1:16;\r | |
1038 | ///\r | |
1039 | /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH\r | |
1040 | /// (Mobile only).\r | |
1041 | ///\r | |
1042 | UINT32 IDA:1;\r | |
1043 | UINT32 Reserved2:31;\r | |
1044 | } Bits;\r | |
1045 | ///\r | |
1046 | /// All bit fields as a 64-bit value\r | |
1047 | ///\r | |
1048 | UINT64 Uint64;\r | |
1049 | } MSR_IA32_PERF_CTL_REGISTER;\r | |
1050 | \r | |
1051 | \r | |
1052 | /**\r | |
1053 | Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled\r | |
1054 | Clock Modulation.". Introduced at Display Family / Display Model 0F_0H.\r | |
1055 | \r | |
1056 | @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)\r | |
1057 | @param EAX Lower 32-bits of MSR value.\r | |
1058 | Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r | |
1059 | @param EDX Upper 32-bits of MSR value.\r | |
1060 | Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r | |
1061 | \r | |
1062 | <b>Example usage</b>\r | |
1063 | @code\r | |
1064 | MSR_IA32_CLOCK_MODULATION_REGISTER Msr;\r | |
1065 | \r | |
1066 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);\r | |
1067 | AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);\r | |
1068 | @endcode\r | |
1069 | **/\r | |
1070 | #define MSR_IA32_CLOCK_MODULATION 0x0000019A\r | |
1071 | \r | |
1072 | /**\r | |
1073 | MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION\r | |
1074 | **/\r | |
1075 | typedef union {\r | |
1076 | ///\r | |
1077 | /// Individual bit fields\r | |
1078 | ///\r | |
1079 | struct {\r | |
1080 | ///\r | |
1081 | /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If\r | |
1082 | /// CPUID.06H:EAX[5] = 1.\r | |
1083 | ///\r | |
1084 | UINT32 ExtendedOnDemandClockModulationDutyCycle:1;\r | |
1085 | ///\r | |
1086 | /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded\r | |
1087 | /// values for target duty cycle modulation.\r | |
1088 | ///\r | |
1089 | UINT32 OnDemandClockModulationDutyCycle:3;\r | |
1090 | ///\r | |
1091 | /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.\r | |
1092 | ///\r | |
1093 | UINT32 OnDemandClockModulationEnable:1;\r | |
1094 | UINT32 Reserved1:27;\r | |
1095 | UINT32 Reserved2:32;\r | |
1096 | } Bits;\r | |
1097 | ///\r | |
1098 | /// All bit fields as a 32-bit value\r | |
1099 | ///\r | |
1100 | UINT32 Uint32;\r | |
1101 | ///\r | |
1102 | /// All bit fields as a 64-bit value\r | |
1103 | ///\r | |
1104 | UINT64 Uint64;\r | |
1105 | } MSR_IA32_CLOCK_MODULATION_REGISTER;\r | |
1106 | \r | |
1107 | \r | |
1108 | /**\r | |
1109 | Thermal Interrupt Control (R/W) Enables and disables the generation of an\r | |
1110 | interrupt on temperature transitions detected with the processor's thermal\r | |
1111 | sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".\r | |
1112 | Introduced at Display Family / Display Model 0F_0H.\r | |
1113 | \r | |
1114 | @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)\r | |
1115 | @param EAX Lower 32-bits of MSR value.\r | |
1116 | Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r | |
1117 | @param EDX Upper 32-bits of MSR value.\r | |
1118 | Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r | |
1119 | \r | |
1120 | <b>Example usage</b>\r | |
1121 | @code\r | |
1122 | MSR_IA32_THERM_INTERRUPT_REGISTER Msr;\r | |
1123 | \r | |
1124 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);\r | |
1125 | AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);\r | |
1126 | @endcode\r | |
1127 | **/\r | |
1128 | #define MSR_IA32_THERM_INTERRUPT 0x0000019B\r | |
1129 | \r | |
1130 | /**\r | |
1131 | MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT\r | |
1132 | **/\r | |
1133 | typedef union {\r | |
1134 | ///\r | |
1135 | /// Individual bit fields\r | |
1136 | ///\r | |
1137 | struct {\r | |
1138 | ///\r | |
1139 | /// [Bit 0] High-Temperature Interrupt Enable.\r | |
1140 | ///\r | |
1141 | UINT32 HighTempEnable:1;\r | |
1142 | ///\r | |
1143 | /// [Bit 1] Low-Temperature Interrupt Enable.\r | |
1144 | ///\r | |
1145 | UINT32 LowTempEnable:1;\r | |
1146 | ///\r | |
1147 | /// [Bit 2] PROCHOT# Interrupt Enable.\r | |
1148 | ///\r | |
1149 | UINT32 PROCHOT_Enable:1;\r | |
1150 | ///\r | |
1151 | /// [Bit 3] FORCEPR# Interrupt Enable.\r | |
1152 | ///\r | |
1153 | UINT32 FORCEPR_Enable:1;\r | |
1154 | ///\r | |
1155 | /// [Bit 4] Critical Temperature Interrupt Enable.\r | |
1156 | ///\r | |
1157 | UINT32 CriticalTempEnable:1;\r | |
1158 | UINT32 Reserved1:3;\r | |
1159 | ///\r | |
1160 | /// [Bits 14:8] Threshold #1 Value.\r | |
1161 | ///\r | |
1162 | UINT32 Threshold1:7;\r | |
1163 | ///\r | |
1164 | /// [Bit 15] Threshold #1 Interrupt Enable.\r | |
1165 | ///\r | |
1166 | UINT32 Threshold1Enable:1;\r | |
1167 | ///\r | |
1168 | /// [Bits 22:16] Threshold #2 Value.\r | |
1169 | ///\r | |
1170 | UINT32 Threshold2:7;\r | |
1171 | ///\r | |
1172 | /// [Bit 23] Threshold #2 Interrupt Enable.\r | |
1173 | ///\r | |
1174 | UINT32 Threshold2Enable:1;\r | |
1175 | ///\r | |
1176 | /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.\r | |
1177 | ///\r | |
1178 | UINT32 PowerLimitNotificationEnable:1;\r | |
1179 | UINT32 Reserved2:7;\r | |
1180 | UINT32 Reserved3:32;\r | |
1181 | } Bits;\r | |
1182 | ///\r | |
1183 | /// All bit fields as a 32-bit value\r | |
1184 | ///\r | |
1185 | UINT32 Uint32;\r | |
1186 | ///\r | |
1187 | /// All bit fields as a 64-bit value\r | |
1188 | ///\r | |
1189 | UINT64 Uint64;\r | |
1190 | } MSR_IA32_THERM_INTERRUPT_REGISTER;\r | |
1191 | \r | |
1192 | \r | |
1193 | /**\r | |
1194 | Thermal Status Information (RO) Contains status information about the\r | |
1195 | processor's thermal sensor and automatic thermal monitoring facilities. See\r | |
1196 | Section 14.7.2, "Thermal Monitor". Introduced at Display Family / Display\r | |
1197 | Model 0F_0H.\r | |
1198 | \r | |
1199 | @param ECX MSR_IA32_THERM_STATUS (0x0000019C)\r | |
1200 | @param EAX Lower 32-bits of MSR value.\r | |
1201 | Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r | |
1202 | @param EDX Upper 32-bits of MSR value.\r | |
1203 | Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r | |
1204 | \r | |
1205 | <b>Example usage</b>\r | |
1206 | @code\r | |
1207 | MSR_IA32_THERM_STATUS_REGISTER Msr;\r | |
1208 | \r | |
1209 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);\r | |
1210 | @endcode\r | |
1211 | **/\r | |
1212 | #define MSR_IA32_THERM_STATUS 0x0000019C\r | |
1213 | \r | |
1214 | /**\r | |
1215 | MSR information returned for MSR index #MSR_IA32_THERM_STATUS\r | |
1216 | **/\r | |
1217 | typedef union {\r | |
1218 | ///\r | |
1219 | /// Individual bit fields\r | |
1220 | ///\r | |
1221 | struct {\r | |
1222 | ///\r | |
1223 | /// [Bit 0] Thermal Status (RO):.\r | |
1224 | ///\r | |
1225 | UINT32 ThermalStatus:1;\r | |
1226 | ///\r | |
1227 | /// [Bit 1] Thermal Status Log (R/W):.\r | |
1228 | ///\r | |
1229 | UINT32 ThermalStatusLog:1;\r | |
1230 | ///\r | |
1231 | /// [Bit 2] PROCHOT # or FORCEPR# event (RO).\r | |
1232 | ///\r | |
1233 | UINT32 PROCHOT_FORCEPR_Event:1;\r | |
1234 | ///\r | |
1235 | /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0).\r | |
1236 | ///\r | |
1237 | UINT32 PROCHOT_FORCEPR_Log:1;\r | |
1238 | ///\r | |
1239 | /// [Bit 4] Critical Temperature Status (RO).\r | |
1240 | ///\r | |
1241 | UINT32 CriticalTempStatus:1;\r | |
1242 | ///\r | |
1243 | /// [Bit 5] Critical Temperature Status log (R/WC0).\r | |
1244 | ///\r | |
1245 | UINT32 CriticalTempStatusLog:1;\r | |
1246 | ///\r | |
1247 | /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.\r | |
1248 | ///\r | |
1249 | UINT32 ThermalThreshold1Status:1;\r | |
1250 | ///\r | |
1251 | /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r | |
1252 | ///\r | |
1253 | UINT32 ThermalThreshold1Log:1;\r | |
1254 | ///\r | |
1255 | /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.\r | |
1256 | ///\r | |
1257 | UINT32 ThermalThreshold2Status:1;\r | |
1258 | ///\r | |
1259 | /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r | |
1260 | ///\r | |
1261 | UINT32 ThermalThreshold2Log:1;\r | |
1262 | ///\r | |
1263 | /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.\r | |
1264 | ///\r | |
1265 | UINT32 PowerLimitStatus:1;\r | |
1266 | ///\r | |
1267 | /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.\r | |
1268 | ///\r | |
1269 | UINT32 PowerLimitLog:1;\r | |
1270 | ///\r | |
1271 | /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r | |
1272 | ///\r | |
1273 | UINT32 CurrentLimitStatus:1;\r | |
1274 | ///\r | |
1275 | /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r | |
1276 | ///\r | |
1277 | UINT32 CurrentLimitLog:1;\r | |
1278 | ///\r | |
1279 | /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r | |
1280 | ///\r | |
1281 | UINT32 CrossDomainLimitStatus:1;\r | |
1282 | ///\r | |
1283 | /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r | |
1284 | ///\r | |
1285 | UINT32 CrossDomainLimitLog:1;\r | |
1286 | ///\r | |
1287 | /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.\r | |
1288 | ///\r | |
1289 | UINT32 DigitalReadout:7;\r | |
1290 | UINT32 Reserved1:4;\r | |
1291 | ///\r | |
1292 | /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =\r | |
1293 | /// 1.\r | |
1294 | ///\r | |
1295 | UINT32 ResolutionInDegreesCelsius:4;\r | |
1296 | ///\r | |
1297 | /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.\r | |
1298 | ///\r | |
1299 | UINT32 ReadingValid:1;\r | |
1300 | UINT32 Reserved2:32;\r | |
1301 | } Bits;\r | |
1302 | ///\r | |
1303 | /// All bit fields as a 32-bit value\r | |
1304 | ///\r | |
1305 | UINT32 Uint32;\r | |
1306 | ///\r | |
1307 | /// All bit fields as a 64-bit value\r | |
1308 | ///\r | |
1309 | UINT64 Uint64;\r | |
1310 | } MSR_IA32_THERM_STATUS_REGISTER;\r | |
1311 | \r | |
1312 | \r | |
1313 | /**\r | |
1314 | Enable Misc. Processor Features (R/W) Allows a variety of processor\r | |
1315 | functions to be enabled and disabled.\r | |
1316 | \r | |
1317 | @param ECX MSR_IA32_MISC_ENABLE (0x000001A0)\r | |
1318 | @param EAX Lower 32-bits of MSR value.\r | |
1319 | Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r | |
1320 | @param EDX Upper 32-bits of MSR value.\r | |
1321 | Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r | |
1322 | \r | |
1323 | <b>Example usage</b>\r | |
1324 | @code\r | |
1325 | MSR_IA32_MISC_ENABLE_REGISTER Msr;\r | |
1326 | \r | |
1327 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);\r | |
1328 | AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);\r | |
1329 | @endcode\r | |
1330 | **/\r | |
1331 | #define MSR_IA32_MISC_ENABLE 0x000001A0\r | |
1332 | \r | |
1333 | /**\r | |
1334 | MSR information returned for MSR index #MSR_IA32_MISC_ENABLE\r | |
1335 | **/\r | |
1336 | typedef union {\r | |
1337 | ///\r | |
1338 | /// Individual bit fields\r | |
1339 | ///\r | |
1340 | struct {\r | |
1341 | ///\r | |
1342 | /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for\r | |
1343 | /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings\r | |
1344 | /// are disabled. Introduced at Display Family / Display Model 0F_0H.\r | |
1345 | ///\r | |
1346 | UINT32 FastStrings:1;\r | |
1347 | UINT32 Reserved1:2;\r | |
1348 | ///\r | |
1349 | /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting\r | |
1350 | /// this bit enables the thermal control circuit (TCC) portion of the\r | |
1351 | /// Intel Thermal Monitor feature. This allows the processor to\r | |
1352 | /// automatically reduce power consumption in response to TCC activation.\r | |
1353 | /// 0 = Disabled. Note: In some products clearing this bit might be\r | |
1354 | /// ignored in critical thermal conditions, and TM1, TM2 and adaptive\r | |
1355 | /// thermal throttling will still be activated. Introduced at Display\r | |
1356 | /// Family / Display Model 0F_0H.\r | |
1357 | ///\r | |
1358 | UINT32 AutomaticThermalControlCircuit:1;\r | |
1359 | UINT32 Reserved2:3;\r | |
1360 | ///\r | |
1361 | /// [Bit 7] Performance Monitoring Available (R) 1 = Performance\r | |
1362 | /// monitoring enabled 0 = Performance monitoring disabled. Introduced at\r | |
1363 | /// Display Family / Display Model 0F_0H.\r | |
1364 | ///\r | |
1365 | UINT32 PerformanceMonitoring:1;\r | |
1366 | UINT32 Reserved3:3;\r | |
1367 | ///\r | |
1368 | /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't\r | |
1369 | /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at\r | |
1370 | /// Display Family / Display Model 0F_0H.\r | |
1371 | ///\r | |
1372 | UINT32 BTS:1;\r | |
1373 | ///\r | |
1374 | /// [Bit 12] Precise Event Based Sampling (PEBS) Unavailable (RO) 1 =\r | |
1375 | /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display\r | |
1376 | /// Family / Display Model 06_0FH.\r | |
1377 | ///\r | |
1378 | UINT32 PEBS:1;\r | |
1379 | UINT32 Reserved4:3;\r | |
1380 | ///\r | |
1381 | /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced\r | |
1382 | /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep\r | |
1383 | /// Technology enabled. If CPUID.01H: ECX[7] =1.\r | |
1384 | ///\r | |
1385 | UINT32 EIST:1;\r | |
1386 | UINT32 Reserved5:1;\r | |
1387 | ///\r | |
1388 | /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the\r | |
1389 | /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This\r | |
1390 | /// indicates that MONITOR/MWAIT are not supported. Software attempts to\r | |
1391 | /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit\r | |
1392 | /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit\r | |
1393 | /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit\r | |
1394 | /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it\r | |
1395 | /// in the default state. Writing this bit when the SSE3 feature flag is\r | |
1396 | /// set to 0 may generate a #GP exception. Introduced at Display Family /\r | |
1397 | /// Display Model 0F_03H.\r | |
1398 | ///\r | |
1399 | UINT32 MONITOR:1;\r | |
1400 | UINT32 Reserved6:3;\r | |
1401 | ///\r | |
1402 | /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H\r | |
1403 | /// returns a maximum value in EAX[7:0] of 3. BIOS should contain a setup\r | |
1404 | /// question that allows users to specify when the installed OS does not\r | |
1405 | /// support CPUID functions greater than 3. Before setting this bit, BIOS\r | |
1406 | /// must execute the CPUID.0H and examine the maximum value returned in\r | |
1407 | /// EAX[7:0]. If the maximum value is greater than 3, the bit is\r | |
1408 | /// supported. Otherwise, the bit is not supported. Writing to this bit\r | |
1409 | /// when the maximum value is greater than 3 may generate a #GP exception.\r | |
1410 | /// Setting this bit may cause unexpected behavior in software that\r | |
1411 | /// depends on the availability of CPUID leaves greater than 3. Introduced\r | |
1412 | /// at Display Family / Display Model 0F_03H.\r | |
1413 | ///\r | |
1414 | UINT32 LimitCpuidMaxval:1;\r | |
1415 | ///\r | |
1416 | /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are\r | |
1417 | /// disabled. xTPR messages are optional messages that allow the processor\r | |
1418 | /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.\r | |
1419 | ///\r | |
1420 | UINT32 xTPR_Message_Disable:1;\r | |
1421 | UINT32 Reserved7:8;\r | |
1422 | UINT32 Reserved8:2;\r | |
1423 | ///\r | |
1424 | /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit\r | |
1425 | /// feature (XD Bit) is disabled and the XD Bit extended feature flag will\r | |
1426 | /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the\r | |
1427 | /// Execute Disable Bit feature (if available) allows the OS to enable PAE\r | |
1428 | /// paging and take advantage of data only pages. BIOS must not alter the\r | |
1429 | /// contents of this bit location, if XD bit is not supported. Writing\r | |
1430 | /// this bit to 1 when the XD Bit extended feature flag is set to 0 may\r | |
1431 | /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.\r | |
1432 | ///\r | |
1433 | UINT32 XD:1;\r | |
1434 | UINT32 Reserved9:29;\r | |
1435 | } Bits;\r | |
1436 | ///\r | |
1437 | /// All bit fields as a 64-bit value\r | |
1438 | ///\r | |
1439 | UINT64 Uint64;\r | |
1440 | } MSR_IA32_MISC_ENABLE_REGISTER;\r | |
1441 | \r | |
1442 | \r | |
1443 | /**\r | |
1444 | Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.\r | |
1445 | \r | |
1446 | @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)\r | |
1447 | @param EAX Lower 32-bits of MSR value.\r | |
1448 | Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r | |
1449 | @param EDX Upper 32-bits of MSR value.\r | |
1450 | Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r | |
1451 | \r | |
1452 | <b>Example usage</b>\r | |
1453 | @code\r | |
1454 | MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr;\r | |
1455 | \r | |
1456 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);\r | |
1457 | AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);\r | |
1458 | @endcode\r | |
1459 | **/\r | |
1460 | #define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0\r | |
1461 | \r | |
1462 | /**\r | |
1463 | MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS\r | |
1464 | **/\r | |
1465 | typedef union {\r | |
1466 | ///\r | |
1467 | /// Individual bit fields\r | |
1468 | ///\r | |
1469 | struct {\r | |
1470 | ///\r | |
1471 | /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest\r | |
1472 | /// performance. 15 indicates preference to maximize energy saving.\r | |
1473 | ///\r | |
1474 | UINT32 PowerPolicyPreference:4;\r | |
1475 | UINT32 Reserved1:28;\r | |
1476 | UINT32 Reserved2:32;\r | |
1477 | } Bits;\r | |
1478 | ///\r | |
1479 | /// All bit fields as a 32-bit value\r | |
1480 | ///\r | |
1481 | UINT32 Uint32;\r | |
1482 | ///\r | |
1483 | /// All bit fields as a 64-bit value\r | |
1484 | ///\r | |
1485 | UINT64 Uint64;\r | |
1486 | } MSR_IA32_ENERGY_PERF_BIAS_REGISTER;\r | |
1487 | \r | |
1488 | \r | |
1489 | /**\r | |
1490 | Package Thermal Status Information (RO) Contains status information about\r | |
1491 | the package's thermal sensor. See Section 14.8, "Package Level Thermal\r | |
1492 | Management.". If CPUID.06H: EAX[6] = 1.\r | |
1493 | \r | |
1494 | @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)\r | |
1495 | @param EAX Lower 32-bits of MSR value.\r | |
1496 | Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r | |
1497 | @param EDX Upper 32-bits of MSR value.\r | |
1498 | Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r | |
1499 | \r | |
1500 | <b>Example usage</b>\r | |
1501 | @code\r | |
1502 | MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr;\r | |
1503 | \r | |
1504 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);\r | |
1505 | @endcode\r | |
1506 | **/\r | |
1507 | #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1\r | |
1508 | \r | |
1509 | /**\r | |
1510 | MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS\r | |
1511 | **/\r | |
1512 | typedef union {\r | |
1513 | ///\r | |
1514 | /// Individual bit fields\r | |
1515 | ///\r | |
1516 | struct {\r | |
1517 | ///\r | |
1518 | /// [Bit 0] Pkg Thermal Status (RO):.\r | |
1519 | ///\r | |
1520 | UINT32 ThermalStatus:1;\r | |
1521 | ///\r | |
1522 | /// [Bit 1] Pkg Thermal Status Log (R/W):.\r | |
1523 | ///\r | |
1524 | UINT32 ThermalStatusLog:1;\r | |
1525 | ///\r | |
1526 | /// [Bit 2] Pkg PROCHOT # event (RO).\r | |
1527 | ///\r | |
1528 | UINT32 PROCHOT_Event:1;\r | |
1529 | ///\r | |
1530 | /// [Bit 3] Pkg PROCHOT # log (R/WC0).\r | |
1531 | ///\r | |
1532 | UINT32 PROCHOT_Log:1;\r | |
1533 | ///\r | |
1534 | /// [Bit 4] Pkg Critical Temperature Status (RO).\r | |
1535 | ///\r | |
1536 | UINT32 CriticalTempStatus:1;\r | |
1537 | ///\r | |
1538 | /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).\r | |
1539 | ///\r | |
1540 | UINT32 CriticalTempStatusLog:1;\r | |
1541 | ///\r | |
1542 | /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).\r | |
1543 | ///\r | |
1544 | UINT32 ThermalThreshold1Status:1;\r | |
1545 | ///\r | |
1546 | /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).\r | |
1547 | ///\r | |
1548 | UINT32 ThermalThreshold1Log:1;\r | |
1549 | ///\r | |
1550 | /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).\r | |
1551 | ///\r | |
1552 | UINT32 ThermalThreshold2Status:1;\r | |
1553 | ///\r | |
1554 | /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).\r | |
1555 | ///\r | |
1556 | UINT32 ThermalThreshold2Log:1;\r | |
1557 | ///\r | |
1558 | /// [Bit 10] Pkg Power Limitation Status (RO).\r | |
1559 | ///\r | |
1560 | UINT32 PowerLimitStatus:1;\r | |
1561 | ///\r | |
1562 | /// [Bit 11] Pkg Power Limitation log (R/WC0).\r | |
1563 | ///\r | |
1564 | UINT32 PowerLimitLog:1;\r | |
1565 | UINT32 Reserved1:4;\r | |
1566 | ///\r | |
1567 | /// [Bits 22:16] Pkg Digital Readout (RO).\r | |
1568 | ///\r | |
1569 | UINT32 DigitalReadout:7;\r | |
1570 | UINT32 Reserved2:9;\r | |
1571 | UINT32 Reserved3:32;\r | |
1572 | } Bits;\r | |
1573 | ///\r | |
1574 | /// All bit fields as a 32-bit value\r | |
1575 | ///\r | |
1576 | UINT32 Uint32;\r | |
1577 | ///\r | |
1578 | /// All bit fields as a 64-bit value\r | |
1579 | ///\r | |
1580 | UINT64 Uint64;\r | |
1581 | } MSR_IA32_PACKAGE_THERM_STATUS_REGISTER;\r | |
1582 | \r | |
1583 | \r | |
1584 | /**\r | |
1585 | Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of\r | |
1586 | an interrupt on temperature transitions detected with the package's thermal\r | |
1587 | sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:\r | |
1588 | EAX[6] = 1.\r | |
1589 | \r | |
1590 | @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)\r | |
1591 | @param EAX Lower 32-bits of MSR value.\r | |
1592 | Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r | |
1593 | @param EDX Upper 32-bits of MSR value.\r | |
1594 | Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r | |
1595 | \r | |
1596 | <b>Example usage</b>\r | |
1597 | @code\r | |
1598 | MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr;\r | |
1599 | \r | |
1600 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);\r | |
1601 | AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);\r | |
1602 | @endcode\r | |
1603 | **/\r | |
1604 | #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2\r | |
1605 | \r | |
1606 | /**\r | |
1607 | MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT\r | |
1608 | **/\r | |
1609 | typedef union {\r | |
1610 | ///\r | |
1611 | /// Individual bit fields\r | |
1612 | ///\r | |
1613 | struct {\r | |
1614 | ///\r | |
1615 | /// [Bit 0] Pkg High-Temperature Interrupt Enable.\r | |
1616 | ///\r | |
1617 | UINT32 HighTempEnable:1;\r | |
1618 | ///\r | |
1619 | /// [Bit 1] Pkg Low-Temperature Interrupt Enable.\r | |
1620 | ///\r | |
1621 | UINT32 LowTempEnable:1;\r | |
1622 | ///\r | |
1623 | /// [Bit 2] Pkg PROCHOT# Interrupt Enable.\r | |
1624 | ///\r | |
1625 | UINT32 PROCHOT_Enable:1;\r | |
1626 | UINT32 Reserved1:1;\r | |
1627 | ///\r | |
1628 | /// [Bit 4] Pkg Overheat Interrupt Enable.\r | |
1629 | ///\r | |
1630 | UINT32 OverheatEnable:1;\r | |
1631 | UINT32 Reserved2:3;\r | |
1632 | ///\r | |
1633 | /// [Bits 14:8] Pkg Threshold #1 Value.\r | |
1634 | ///\r | |
1635 | UINT32 Threshold1:7;\r | |
1636 | ///\r | |
1637 | /// [Bit 15] Pkg Threshold #1 Interrupt Enable.\r | |
1638 | ///\r | |
1639 | UINT32 Threshold1Enable:1;\r | |
1640 | ///\r | |
1641 | /// [Bits 22:16] Pkg Threshold #2 Value.\r | |
1642 | ///\r | |
1643 | UINT32 Threshold2:7;\r | |
1644 | ///\r | |
1645 | /// [Bit 23] Pkg Threshold #2 Interrupt Enable.\r | |
1646 | ///\r | |
1647 | UINT32 Threshold2Enable:1;\r | |
1648 | ///\r | |
1649 | /// [Bit 24] Pkg Power Limit Notification Enable.\r | |
1650 | ///\r | |
1651 | UINT32 PowerLimitNotificationEnable:1;\r | |
1652 | UINT32 Reserved3:7;\r | |
1653 | UINT32 Reserved4:32;\r | |
1654 | } Bits;\r | |
1655 | ///\r | |
1656 | /// All bit fields as a 32-bit value\r | |
1657 | ///\r | |
1658 | UINT32 Uint32;\r | |
1659 | ///\r | |
1660 | /// All bit fields as a 64-bit value\r | |
1661 | ///\r | |
1662 | UINT64 Uint64;\r | |
1663 | } MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER;\r | |
1664 | \r | |
1665 | \r | |
1666 | /**\r | |
1667 | Trace/Profile Resource Control (R/W). Introduced at Display Family / Display\r | |
1668 | Model 06_0EH.\r | |
1669 | \r | |
1670 | @param ECX MSR_IA32_DEBUGCTL (0x000001D9)\r | |
1671 | @param EAX Lower 32-bits of MSR value.\r | |
1672 | Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r | |
1673 | @param EDX Upper 32-bits of MSR value.\r | |
1674 | Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r | |
1675 | \r | |
1676 | <b>Example usage</b>\r | |
1677 | @code\r | |
1678 | MSR_IA32_DEBUGCTL_REGISTER Msr;\r | |
1679 | \r | |
1680 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);\r | |
1681 | AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);\r | |
1682 | @endcode\r | |
1683 | **/\r | |
1684 | #define MSR_IA32_DEBUGCTL 0x000001D9\r | |
1685 | \r | |
1686 | /**\r | |
1687 | MSR information returned for MSR index #MSR_IA32_DEBUGCTL\r | |
1688 | **/\r | |
1689 | typedef union {\r | |
1690 | ///\r | |
1691 | /// Individual bit fields\r | |
1692 | ///\r | |
1693 | struct {\r | |
1694 | ///\r | |
1695 | /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a\r | |
1696 | /// running trace of the most recent branches taken by the processor in\r | |
1697 | /// the LBR stack. Introduced at Display Family / Display Model 06_01H.\r | |
1698 | ///\r | |
1699 | UINT32 LBR:1;\r | |
1700 | ///\r | |
1701 | /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat\r | |
1702 | /// EFLAGS.TF as single-step on branches instead of single-step on\r | |
1703 | /// instructions. Introduced at Display Family / Display Model 06_01H.\r | |
1704 | ///\r | |
1705 | UINT32 BTF:1;\r | |
1706 | UINT32 Reserved1:4;\r | |
1707 | ///\r | |
1708 | /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be\r | |
1709 | /// sent. Introduced at Display Family / Display Model 06_0EH.\r | |
1710 | ///\r | |
1711 | UINT32 TR:1;\r | |
1712 | ///\r | |
1713 | /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to\r | |
1714 | /// be logged in a BTS buffer. Introduced at Display Family / Display\r | |
1715 | /// Model 06_0EH.\r | |
1716 | ///\r | |
1717 | UINT32 BTS:1;\r | |
1718 | ///\r | |
1719 | /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular\r | |
1720 | /// fashion. When this bit is set, an interrupt is generated by the BTS\r | |
1721 | /// facility when the BTS buffer is full. Introduced at Display Family /\r | |
1722 | /// Display Model 06_0EH.\r | |
1723 | ///\r | |
1724 | UINT32 BTINT:1;\r | |
1725 | ///\r | |
1726 | /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.\r | |
1727 | /// Introduced at Display Family / Display Model 06_0FH.\r | |
1728 | ///\r | |
1729 | UINT32 BTS_OFF_OS:1;\r | |
1730 | ///\r | |
1731 | /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.\r | |
1732 | /// Introduced at Display Family / Display Model 06_0FH.\r | |
1733 | ///\r | |
1734 | UINT32 BTS_OFF_USR:1;\r | |
1735 | ///\r | |
1736 | /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a\r | |
1737 | /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r | |
1738 | ///\r | |
1739 | UINT32 FREEZE_LBRS_ON_PMI:1;\r | |
1740 | ///\r | |
1741 | /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the\r | |
1742 | /// global counter control MSR are frozen (address 38FH) on a PMI request.\r | |
1743 | /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r | |
1744 | ///\r | |
1745 | UINT32 FREEZE_PERFMON_ON_PMI:1;\r | |
1746 | ///\r | |
1747 | /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to\r | |
1748 | /// receive and generate PMI on behalf of the uncore. Introduced at\r | |
1749 | /// Display Family / Display Model 06_1AH.\r | |
1750 | ///\r | |
1751 | UINT32 ENABLE_UNCORE_PMI:1;\r | |
1752 | ///\r | |
1753 | /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace\r | |
1754 | /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.\r | |
1755 | ///\r | |
1756 | UINT32 FREEZE_WHILE_SMM:1;\r | |
1757 | ///\r | |
1758 | /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If\r | |
1759 | /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).\r | |
1760 | ///\r | |
1761 | UINT32 RTM_DEBUG:1;\r | |
1762 | UINT32 Reserved2:16;\r | |
1763 | UINT32 Reserved3:32;\r | |
1764 | } Bits;\r | |
1765 | ///\r | |
1766 | /// All bit fields as a 32-bit value\r | |
1767 | ///\r | |
1768 | UINT32 Uint32;\r | |
1769 | ///\r | |
1770 | /// All bit fields as a 64-bit value\r | |
1771 | ///\r | |
1772 | UINT64 Uint64;\r | |
1773 | } MSR_IA32_DEBUGCTL_REGISTER;\r | |
1774 | \r | |
1775 | \r | |
1776 | /**\r | |
1777 | SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.\r | |
1778 | If IA32_MTRRCAP.SMRR[11] = 1.\r | |
1779 | \r | |
1780 | @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2)\r | |
1781 | @param EAX Lower 32-bits of MSR value.\r | |
1782 | Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r | |
1783 | @param EDX Upper 32-bits of MSR value.\r | |
1784 | Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r | |
1785 | \r | |
1786 | <b>Example usage</b>\r | |
1787 | @code\r | |
1788 | MSR_IA32_SMRR_PHYSBASE_REGISTER Msr;\r | |
1789 | \r | |
1790 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);\r | |
1791 | AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);\r | |
1792 | @endcode\r | |
1793 | **/\r | |
1794 | #define MSR_IA32_SMRR_PHYSBASE 0x000001F2\r | |
1795 | \r | |
1796 | /**\r | |
1797 | MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE\r | |
1798 | **/\r | |
1799 | typedef union {\r | |
1800 | ///\r | |
1801 | /// Individual bit fields\r | |
1802 | ///\r | |
1803 | struct {\r | |
1804 | ///\r | |
1805 | /// [Bits 7:0] Type. Specifies memory type of the range.\r | |
1806 | ///\r | |
1807 | UINT32 Type:8;\r | |
1808 | UINT32 Reserved1:4;\r | |
1809 | ///\r | |
1810 | /// [Bits 31:12] PhysBase. SMRR physical Base Address.\r | |
1811 | ///\r | |
1812 | UINT32 PhysBase:20;\r | |
1813 | UINT32 Reserved2:32;\r | |
1814 | } Bits;\r | |
1815 | ///\r | |
1816 | /// All bit fields as a 32-bit value\r | |
1817 | ///\r | |
1818 | UINT32 Uint32;\r | |
1819 | ///\r | |
1820 | /// All bit fields as a 64-bit value\r | |
1821 | ///\r | |
1822 | UINT64 Uint64;\r | |
1823 | } MSR_IA32_SMRR_PHYSBASE_REGISTER;\r | |
1824 | \r | |
1825 | \r | |
1826 | /**\r | |
1827 | SMRR Range Mask. (Writeable only in SMM) Range Mask of SMM memory range. If\r | |
1828 | IA32_MTRRCAP[SMRR] = 1.\r | |
1829 | \r | |
1830 | @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)\r | |
1831 | @param EAX Lower 32-bits of MSR value.\r | |
1832 | Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r | |
1833 | @param EDX Upper 32-bits of MSR value.\r | |
1834 | Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r | |
1835 | \r | |
1836 | <b>Example usage</b>\r | |
1837 | @code\r | |
1838 | MSR_IA32_SMRR_PHYSMASK_REGISTER Msr;\r | |
1839 | \r | |
1840 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);\r | |
1841 | AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);\r | |
1842 | @endcode\r | |
1843 | **/\r | |
1844 | #define MSR_IA32_SMRR_PHYSMASK 0x000001F3\r | |
1845 | \r | |
1846 | /**\r | |
1847 | MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK\r | |
1848 | **/\r | |
1849 | typedef union {\r | |
1850 | ///\r | |
1851 | /// Individual bit fields\r | |
1852 | ///\r | |
1853 | struct {\r | |
1854 | UINT32 Reserved1:11;\r | |
1855 | ///\r | |
1856 | /// [Bit 11] Valid Enable range mask.\r | |
1857 | ///\r | |
1858 | UINT32 Valid:1;\r | |
1859 | ///\r | |
1860 | /// [Bits 31:12] PhysMask SMRR address range mask.\r | |
1861 | ///\r | |
1862 | UINT32 PhysMask:20;\r | |
1863 | UINT32 Reserved2:32;\r | |
1864 | } Bits;\r | |
1865 | ///\r | |
1866 | /// All bit fields as a 32-bit value\r | |
1867 | ///\r | |
1868 | UINT32 Uint32;\r | |
1869 | ///\r | |
1870 | /// All bit fields as a 64-bit value\r | |
1871 | ///\r | |
1872 | UINT64 Uint64;\r | |
1873 | } MSR_IA32_SMRR_PHYSMASK_REGISTER;\r | |
1874 | \r | |
1875 | \r | |
1876 | /**\r | |
1877 | DCA Capability (R). If CPUID.01H: ECX[18] = 1.\r | |
1878 | \r | |
1879 | @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)\r | |
1880 | @param EAX Lower 32-bits of MSR value.\r | |
1881 | @param EDX Upper 32-bits of MSR value.\r | |
1882 | \r | |
1883 | <b>Example usage</b>\r | |
1884 | @code\r | |
1885 | UINT64 Msr;\r | |
1886 | \r | |
1887 | Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);\r | |
1888 | @endcode\r | |
1889 | **/\r | |
1890 | #define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8\r | |
1891 | \r | |
1892 | \r | |
1893 | /**\r | |
1894 | If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.\r | |
1895 | \r | |
1896 | @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9)\r | |
1897 | @param EAX Lower 32-bits of MSR value.\r | |
1898 | @param EDX Upper 32-bits of MSR value.\r | |
1899 | \r | |
1900 | <b>Example usage</b>\r | |
1901 | @code\r | |
1902 | UINT64 Msr;\r | |
1903 | \r | |
1904 | Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);\r | |
1905 | AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);\r | |
1906 | @endcode\r | |
1907 | **/\r | |
1908 | #define MSR_IA32_CPU_DCA_CAP 0x000001F9\r | |
1909 | \r | |
1910 | \r | |
1911 | /**\r | |
1912 | DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.\r | |
1913 | \r | |
1914 | @param ECX MSR_IA32_DCA_0_CAP (0x000001FA)\r | |
1915 | @param EAX Lower 32-bits of MSR value.\r | |
1916 | Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r | |
1917 | @param EDX Upper 32-bits of MSR value.\r | |
1918 | Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r | |
1919 | \r | |
1920 | <b>Example usage</b>\r | |
1921 | @code\r | |
1922 | MSR_IA32_DCA_0_CAP_REGISTER Msr;\r | |
1923 | \r | |
1924 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);\r | |
1925 | AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);\r | |
1926 | @endcode\r | |
1927 | **/\r | |
1928 | #define MSR_IA32_DCA_0_CAP 0x000001FA\r | |
1929 | \r | |
1930 | /**\r | |
1931 | MSR information returned for MSR index #MSR_IA32_DCA_0_CAP\r | |
1932 | **/\r | |
1933 | typedef union {\r | |
1934 | ///\r | |
1935 | /// Individual bit fields\r | |
1936 | ///\r | |
1937 | struct {\r | |
1938 | ///\r | |
1939 | /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no\r | |
1940 | /// defeatures are set.\r | |
1941 | ///\r | |
1942 | UINT32 DCA_ACTIVE:1;\r | |
1943 | ///\r | |
1944 | /// [Bits 2:1] TRANSACTION.\r | |
1945 | ///\r | |
1946 | UINT32 TRANSACTION:2;\r | |
1947 | ///\r | |
1948 | /// [Bits 6:3] DCA_TYPE.\r | |
1949 | ///\r | |
1950 | UINT32 DCA_TYPE:4;\r | |
1951 | ///\r | |
1952 | /// [Bits 10:7] DCA_QUEUE_SIZE.\r | |
1953 | ///\r | |
1954 | UINT32 DCA_QUEUE_SIZE:4;\r | |
1955 | UINT32 Reserved1:2;\r | |
1956 | ///\r | |
1957 | /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW\r | |
1958 | /// side-effect.\r | |
1959 | ///\r | |
1960 | UINT32 DCA_DELAY:4;\r | |
1961 | UINT32 Reserved2:7;\r | |
1962 | ///\r | |
1963 | /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.\r | |
1964 | ///\r | |
1965 | UINT32 SW_BLOCK:1;\r | |
1966 | UINT32 Reserved3:1;\r | |
1967 | ///\r | |
1968 | /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).\r | |
1969 | ///\r | |
1970 | UINT32 HW_BLOCK:1;\r | |
1971 | UINT32 Reserved4:5;\r | |
1972 | UINT32 Reserved5:32;\r | |
1973 | } Bits;\r | |
1974 | ///\r | |
1975 | /// All bit fields as a 32-bit value\r | |
1976 | ///\r | |
1977 | UINT32 Uint32;\r | |
1978 | ///\r | |
1979 | /// All bit fields as a 64-bit value\r | |
1980 | ///\r | |
1981 | UINT64 Uint64;\r | |
1982 | } MSR_IA32_DCA_0_CAP_REGISTER;\r | |
1983 | \r | |
1984 | \r | |
1985 | /**\r | |
1986 | MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".\r | |
1987 | If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r | |
1988 | \r | |
1989 | @param ECX MSR_IA32_MTRR_PHYSBASEn\r | |
1990 | @param EAX Lower 32-bits of MSR value.\r | |
1991 | Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r | |
1992 | @param EDX Upper 32-bits of MSR value.\r | |
1993 | Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r | |
1994 | \r | |
1995 | <b>Example usage</b>\r | |
1996 | @code\r | |
1997 | MSR_IA32_MTRR_PHYSBASE_REGISTER Msr;\r | |
1998 | \r | |
1999 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);\r | |
2000 | AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);\r | |
2001 | @endcode\r | |
2002 | @{\r | |
2003 | **/\r | |
2004 | #define MSR_IA32_MTRR_PHYSBASE0 0x00000200\r | |
2005 | #define MSR_IA32_MTRR_PHYSBASE1 0x00000202\r | |
2006 | #define MSR_IA32_MTRR_PHYSBASE2 0x00000204\r | |
2007 | #define MSR_IA32_MTRR_PHYSBASE3 0x00000206\r | |
2008 | #define MSR_IA32_MTRR_PHYSBASE4 0x00000208\r | |
2009 | #define MSR_IA32_MTRR_PHYSBASE5 0x0000020A\r | |
2010 | #define MSR_IA32_MTRR_PHYSBASE6 0x0000020C\r | |
2011 | #define MSR_IA32_MTRR_PHYSBASE7 0x0000020E\r | |
2012 | #define MSR_IA32_MTRR_PHYSBASE8 0x00000210\r | |
2013 | #define MSR_IA32_MTRR_PHYSBASE9 0x00000212\r | |
2014 | /// @}\r | |
2015 | \r | |
2016 | /**\r | |
2017 | MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to\r | |
2018 | #MSR_IA32_MTRR_PHYSBASE9\r | |
2019 | **/\r | |
2020 | typedef union {\r | |
2021 | ///\r | |
2022 | /// Individual bit fields\r | |
2023 | ///\r | |
2024 | struct {\r | |
2025 | ///\r | |
2026 | /// [Bits 7:0] Type. Specifies memory type of the range.\r | |
2027 | ///\r | |
2028 | UINT32 Type:8;\r | |
2029 | UINT32 Reserved1:4;\r | |
2030 | ///\r | |
2031 | /// [Bits 31:12] PhysBase. MTRR physical Base Address.\r | |
2032 | ///\r | |
2033 | UINT32 PhysBase:20;\r | |
2034 | ///\r | |
2035 | /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.\r | |
2036 | /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r | |
2037 | /// maximum physical address range supported by the processor. It is\r | |
2038 | /// reported by CPUID leaf function 80000008H. If CPUID does not support\r | |
2039 | /// leaf 80000008H, the processor supports 36-bit physical address size,\r | |
2040 | /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r | |
2041 | ///\r | |
2042 | UINT32 PhysBaseHi:32;\r | |
2043 | } Bits;\r | |
2044 | ///\r | |
2045 | /// All bit fields as a 64-bit value\r | |
2046 | ///\r | |
2047 | UINT64 Uint64;\r | |
2048 | } MSR_IA32_MTRR_PHYSBASE_REGISTER;\r | |
2049 | \r | |
2050 | \r | |
2051 | /**\r | |
2052 | MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".\r | |
2053 | If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r | |
2054 | \r | |
2055 | @param ECX MSR_IA32_MTRR_PHYSMASKn\r | |
2056 | @param EAX Lower 32-bits of MSR value.\r | |
2057 | Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r | |
2058 | @param EDX Upper 32-bits of MSR value.\r | |
2059 | Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r | |
2060 | \r | |
2061 | <b>Example usage</b>\r | |
2062 | @code\r | |
2063 | MSR_IA32_MTRR_PHYSMASK_REGISTER Msr;\r | |
2064 | \r | |
2065 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);\r | |
2066 | AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);\r | |
2067 | @endcode\r | |
2068 | @{\r | |
2069 | **/\r | |
2070 | #define MSR_IA32_MTRR_PHYSMASK0 0x00000201\r | |
2071 | #define MSR_IA32_MTRR_PHYSMASK1 0x00000203\r | |
2072 | #define MSR_IA32_MTRR_PHYSMASK2 0x00000205\r | |
2073 | #define MSR_IA32_MTRR_PHYSMASK3 0x00000207\r | |
2074 | #define MSR_IA32_MTRR_PHYSMASK4 0x00000209\r | |
2075 | #define MSR_IA32_MTRR_PHYSMASK5 0x0000020B\r | |
2076 | #define MSR_IA32_MTRR_PHYSMASK6 0x0000020D\r | |
2077 | #define MSR_IA32_MTRR_PHYSMASK7 0x0000020F\r | |
2078 | #define MSR_IA32_MTRR_PHYSMASK8 0x00000211\r | |
2079 | #define MSR_IA32_MTRR_PHYSMASK9 0x00000213\r | |
2080 | /// @}\r | |
2081 | \r | |
2082 | /**\r | |
2083 | MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to\r | |
2084 | #MSR_IA32_MTRR_PHYSMASK9\r | |
2085 | **/\r | |
2086 | typedef union {\r | |
2087 | ///\r | |
2088 | /// Individual bit fields\r | |
2089 | ///\r | |
2090 | struct {\r | |
2091 | UINT32 Reserved1:11;\r | |
2092 | ///\r | |
2093 | /// [Bit 11] Valid Enable range mask.\r | |
2094 | ///\r | |
2095 | UINT32 V:1;\r | |
2096 | ///\r | |
2097 | /// [Bits 31:12] PhysMask. MTRR address range mask.\r | |
2098 | ///\r | |
2099 | UINT32 PhysMask:20;\r | |
2100 | ///\r | |
2101 | /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.\r | |
2102 | /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r | |
2103 | /// maximum physical address range supported by the processor. It is\r | |
2104 | /// reported by CPUID leaf function 80000008H. If CPUID does not support\r | |
2105 | /// leaf 80000008H, the processor supports 36-bit physical address size,\r | |
2106 | /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r | |
2107 | ///\r | |
2108 | UINT32 PhysMaskHi:32;\r | |
2109 | } Bits;\r | |
2110 | ///\r | |
2111 | /// All bit fields as a 64-bit value\r | |
2112 | ///\r | |
2113 | UINT64 Uint64;\r | |
2114 | } MSR_IA32_MTRR_PHYSMASK_REGISTER;\r | |
2115 | \r | |
2116 | \r | |
2117 | /**\r | |
2118 | MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
2119 | \r | |
2120 | @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250)\r | |
2121 | @param EAX Lower 32-bits of MSR value.\r | |
2122 | @param EDX Upper 32-bits of MSR value.\r | |
2123 | \r | |
2124 | <b>Example usage</b>\r | |
2125 | @code\r | |
2126 | UINT64 Msr;\r | |
2127 | \r | |
2128 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);\r | |
2129 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);\r | |
2130 | @endcode\r | |
2131 | **/\r | |
2132 | #define MSR_IA32_MTRR_FIX64K_00000 0x00000250\r | |
2133 | \r | |
2134 | \r | |
2135 | /**\r | |
2136 | MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
2137 | \r | |
2138 | @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258)\r | |
2139 | @param EAX Lower 32-bits of MSR value.\r | |
2140 | @param EDX Upper 32-bits of MSR value.\r | |
2141 | \r | |
2142 | <b>Example usage</b>\r | |
2143 | @code\r | |
2144 | UINT64 Msr;\r | |
2145 | \r | |
2146 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);\r | |
2147 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);\r | |
2148 | @endcode\r | |
2149 | **/\r | |
2150 | #define MSR_IA32_MTRR_FIX16K_80000 0x00000258\r | |
2151 | \r | |
2152 | \r | |
2153 | /**\r | |
2154 | MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
2155 | \r | |
2156 | @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)\r | |
2157 | @param EAX Lower 32-bits of MSR value.\r | |
2158 | @param EDX Upper 32-bits of MSR value.\r | |
2159 | \r | |
2160 | <b>Example usage</b>\r | |
2161 | @code\r | |
2162 | UINT64 Msr;\r | |
2163 | \r | |
2164 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);\r | |
2165 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);\r | |
2166 | @endcode\r | |
2167 | **/\r | |
2168 | #define MSR_IA32_MTRR_FIX16K_A0000 0x00000259\r | |
2169 | \r | |
2170 | \r | |
2171 | /**\r | |
2172 | See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.\r | |
2173 | \r | |
2174 | @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)\r | |
2175 | @param EAX Lower 32-bits of MSR value.\r | |
2176 | @param EDX Upper 32-bits of MSR value.\r | |
2177 | \r | |
2178 | <b>Example usage</b>\r | |
2179 | @code\r | |
2180 | UINT64 Msr;\r | |
2181 | \r | |
2182 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);\r | |
2183 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);\r | |
2184 | @endcode\r | |
2185 | **/\r | |
2186 | #define MSR_IA32_MTRR_FIX4K_C0000 0x00000268\r | |
2187 | \r | |
2188 | \r | |
2189 | /**\r | |
2190 | MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
2191 | \r | |
2192 | @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)\r | |
2193 | @param EAX Lower 32-bits of MSR value.\r | |
2194 | @param EDX Upper 32-bits of MSR value.\r | |
2195 | \r | |
2196 | <b>Example usage</b>\r | |
2197 | @code\r | |
2198 | UINT64 Msr;\r | |
2199 | \r | |
2200 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);\r | |
2201 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);\r | |
2202 | @endcode\r | |
2203 | **/\r | |
2204 | #define MSR_IA32_MTRR_FIX4K_C8000 0x00000269\r | |
2205 | \r | |
2206 | \r | |
2207 | /**\r | |
2208 | MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
2209 | \r | |
2210 | @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)\r | |
2211 | @param EAX Lower 32-bits of MSR value.\r | |
2212 | @param EDX Upper 32-bits of MSR value.\r | |
2213 | \r | |
2214 | <b>Example usage</b>\r | |
2215 | @code\r | |
2216 | UINT64 Msr;\r | |
2217 | \r | |
2218 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);\r | |
2219 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);\r | |
2220 | @endcode\r | |
2221 | **/\r | |
2222 | #define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A\r | |
2223 | \r | |
2224 | \r | |
2225 | /**\r | |
2226 | MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
2227 | \r | |
2228 | @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)\r | |
2229 | @param EAX Lower 32-bits of MSR value.\r | |
2230 | @param EDX Upper 32-bits of MSR value.\r | |
2231 | \r | |
2232 | <b>Example usage</b>\r | |
2233 | @code\r | |
2234 | UINT64 Msr;\r | |
2235 | \r | |
2236 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);\r | |
2237 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);\r | |
2238 | @endcode\r | |
2239 | **/\r | |
2240 | #define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B\r | |
2241 | \r | |
2242 | \r | |
2243 | /**\r | |
2244 | MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
2245 | \r | |
2246 | @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)\r | |
2247 | @param EAX Lower 32-bits of MSR value.\r | |
2248 | @param EDX Upper 32-bits of MSR value.\r | |
2249 | \r | |
2250 | <b>Example usage</b>\r | |
2251 | @code\r | |
2252 | UINT64 Msr;\r | |
2253 | \r | |
2254 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);\r | |
2255 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);\r | |
2256 | @endcode\r | |
2257 | **/\r | |
2258 | #define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C\r | |
2259 | \r | |
2260 | \r | |
2261 | /**\r | |
2262 | MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
2263 | \r | |
2264 | @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)\r | |
2265 | @param EAX Lower 32-bits of MSR value.\r | |
2266 | @param EDX Upper 32-bits of MSR value.\r | |
2267 | \r | |
2268 | <b>Example usage</b>\r | |
2269 | @code\r | |
2270 | UINT64 Msr;\r | |
2271 | \r | |
2272 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);\r | |
2273 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);\r | |
2274 | @endcode\r | |
2275 | **/\r | |
2276 | #define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D\r | |
2277 | \r | |
2278 | \r | |
2279 | /**\r | |
2280 | MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
2281 | \r | |
2282 | @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)\r | |
2283 | @param EAX Lower 32-bits of MSR value.\r | |
2284 | @param EDX Upper 32-bits of MSR value.\r | |
2285 | \r | |
2286 | <b>Example usage</b>\r | |
2287 | @code\r | |
2288 | UINT64 Msr;\r | |
2289 | \r | |
2290 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);\r | |
2291 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);\r | |
2292 | @endcode\r | |
2293 | **/\r | |
2294 | #define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E\r | |
2295 | \r | |
2296 | \r | |
2297 | /**\r | |
2298 | MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
2299 | \r | |
2300 | @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)\r | |
2301 | @param EAX Lower 32-bits of MSR value.\r | |
2302 | @param EDX Upper 32-bits of MSR value.\r | |
2303 | \r | |
2304 | <b>Example usage</b>\r | |
2305 | @code\r | |
2306 | UINT64 Msr;\r | |
2307 | \r | |
2308 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);\r | |
2309 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);\r | |
2310 | @endcode\r | |
2311 | **/\r | |
2312 | #define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F\r | |
2313 | \r | |
2314 | \r | |
2315 | /**\r | |
2316 | IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.\r | |
2317 | \r | |
2318 | @param ECX MSR_IA32_PAT (0x00000277)\r | |
2319 | @param EAX Lower 32-bits of MSR value.\r | |
2320 | Described by the type MSR_IA32_PAT_REGISTER.\r | |
2321 | @param EDX Upper 32-bits of MSR value.\r | |
2322 | Described by the type MSR_IA32_PAT_REGISTER.\r | |
2323 | \r | |
2324 | <b>Example usage</b>\r | |
2325 | @code\r | |
2326 | MSR_IA32_PAT_REGISTER Msr;\r | |
2327 | \r | |
2328 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);\r | |
2329 | AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);\r | |
2330 | @endcode\r | |
2331 | **/\r | |
2332 | #define MSR_IA32_PAT 0x00000277\r | |
2333 | \r | |
2334 | /**\r | |
2335 | MSR information returned for MSR index #MSR_IA32_PAT\r | |
2336 | **/\r | |
2337 | typedef union {\r | |
2338 | ///\r | |
2339 | /// Individual bit fields\r | |
2340 | ///\r | |
2341 | struct {\r | |
2342 | ///\r | |
2343 | /// [Bits 2:0] PA0.\r | |
2344 | ///\r | |
2345 | UINT32 PA0:3;\r | |
2346 | UINT32 Reserved1:5;\r | |
2347 | ///\r | |
2348 | /// [Bits 10:8] PA1.\r | |
2349 | ///\r | |
2350 | UINT32 PA1:3;\r | |
2351 | UINT32 Reserved2:5;\r | |
2352 | ///\r | |
2353 | /// [Bits 18:16] PA2.\r | |
2354 | ///\r | |
2355 | UINT32 PA2:3;\r | |
2356 | UINT32 Reserved3:5;\r | |
2357 | ///\r | |
2358 | /// [Bits 26:24] PA3.\r | |
2359 | ///\r | |
2360 | UINT32 PA3:3;\r | |
2361 | UINT32 Reserved4:5;\r | |
2362 | ///\r | |
2363 | /// [Bits 34:32] PA4.\r | |
2364 | ///\r | |
2365 | UINT32 PA4:3;\r | |
2366 | UINT32 Reserved5:5;\r | |
2367 | ///\r | |
2368 | /// [Bits 42:40] PA5.\r | |
2369 | ///\r | |
2370 | UINT32 PA5:3;\r | |
2371 | UINT32 Reserved6:5;\r | |
2372 | ///\r | |
2373 | /// [Bits 50:48] PA6.\r | |
2374 | ///\r | |
2375 | UINT32 PA6:3;\r | |
2376 | UINT32 Reserved7:5;\r | |
2377 | ///\r | |
2378 | /// [Bits 58:56] PA7.\r | |
2379 | ///\r | |
2380 | UINT32 PA7:3;\r | |
2381 | UINT32 Reserved8:5;\r | |
2382 | } Bits;\r | |
2383 | ///\r | |
2384 | /// All bit fields as a 64-bit value\r | |
2385 | ///\r | |
2386 | UINT64 Uint64;\r | |
2387 | } MSR_IA32_PAT_REGISTER;\r | |
2388 | \r | |
2389 | \r | |
2390 | /**\r | |
2391 | Provides the programming interface to use corrected MC error signaling\r | |
2392 | capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.\r | |
2393 | \r | |
2394 | @param ECX MSR_IA32_MCn_CTL2\r | |
2395 | @param EAX Lower 32-bits of MSR value.\r | |
2396 | Described by the type MSR_IA32_MC_CTL2_REGISTER.\r | |
2397 | @param EDX Upper 32-bits of MSR value.\r | |
2398 | Described by the type MSR_IA32_MC_CTL2_REGISTER.\r | |
2399 | \r | |
2400 | <b>Example usage</b>\r | |
2401 | @code\r | |
2402 | MSR_IA32_MC_CTL2_REGISTER Msr;\r | |
2403 | \r | |
2404 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);\r | |
2405 | AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);\r | |
2406 | @endcode\r | |
2407 | @{\r | |
2408 | **/\r | |
2409 | #define MSR_IA32_MC0_CTL2 0x00000280\r | |
2410 | #define MSR_IA32_MC1_CTL2 0x00000281\r | |
2411 | #define MSR_IA32_MC2_CTL2 0x00000282\r | |
2412 | #define MSR_IA32_MC3_CTL2 0x00000283\r | |
2413 | #define MSR_IA32_MC4_CTL2 0x00000284\r | |
2414 | #define MSR_IA32_MC5_CTL2 0x00000285\r | |
2415 | #define MSR_IA32_MC6_CTL2 0x00000286\r | |
2416 | #define MSR_IA32_MC7_CTL2 0x00000287\r | |
2417 | #define MSR_IA32_MC8_CTL2 0x00000288\r | |
2418 | #define MSR_IA32_MC9_CTL2 0x00000289\r | |
2419 | #define MSR_IA32_MC10_CTL2 0x0000028A\r | |
2420 | #define MSR_IA32_MC11_CTL2 0x0000028B\r | |
2421 | #define MSR_IA32_MC12_CTL2 0x0000028C\r | |
2422 | #define MSR_IA32_MC13_CTL2 0x0000028D\r | |
2423 | #define MSR_IA32_MC14_CTL2 0x0000028E\r | |
2424 | #define MSR_IA32_MC15_CTL2 0x0000028F\r | |
2425 | #define MSR_IA32_MC16_CTL2 0x00000290\r | |
2426 | #define MSR_IA32_MC17_CTL2 0x00000291\r | |
2427 | #define MSR_IA32_MC18_CTL2 0x00000292\r | |
2428 | #define MSR_IA32_MC19_CTL2 0x00000293\r | |
2429 | #define MSR_IA32_MC20_CTL2 0x00000294\r | |
2430 | #define MSR_IA32_MC21_CTL2 0x00000295\r | |
2431 | #define MSR_IA32_MC22_CTL2 0x00000296\r | |
2432 | #define MSR_IA32_MC23_CTL2 0x00000297\r | |
2433 | #define MSR_IA32_MC24_CTL2 0x00000298\r | |
2434 | #define MSR_IA32_MC25_CTL2 0x00000299\r | |
2435 | #define MSR_IA32_MC26_CTL2 0x0000029A\r | |
2436 | #define MSR_IA32_MC27_CTL2 0x0000029B\r | |
2437 | #define MSR_IA32_MC28_CTL2 0x0000029C\r | |
2438 | #define MSR_IA32_MC29_CTL2 0x0000029D\r | |
2439 | #define MSR_IA32_MC30_CTL2 0x0000029E\r | |
2440 | #define MSR_IA32_MC31_CTL2 0x0000029F\r | |
2441 | /// @}\r | |
2442 | \r | |
2443 | /**\r | |
2444 | MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2\r | |
2445 | to #MSR_IA32_MC31_CTL2\r | |
2446 | **/\r | |
2447 | typedef union {\r | |
2448 | ///\r | |
2449 | /// Individual bit fields\r | |
2450 | ///\r | |
2451 | struct {\r | |
2452 | ///\r | |
2453 | /// [Bits 14:0] Corrected error count threshold.\r | |
2454 | ///\r | |
2455 | UINT32 CorrectedErrorCountThreshold:15;\r | |
2456 | UINT32 Reserved1:15;\r | |
2457 | ///\r | |
2458 | /// [Bit 30] CMCI_EN.\r | |
2459 | ///\r | |
2460 | UINT32 CMCI_EN:1;\r | |
2461 | UINT32 Reserved2:1;\r | |
2462 | UINT32 Reserved3:32;\r | |
2463 | } Bits;\r | |
2464 | ///\r | |
2465 | /// All bit fields as a 32-bit value\r | |
2466 | ///\r | |
2467 | UINT32 Uint32;\r | |
2468 | ///\r | |
2469 | /// All bit fields as a 64-bit value\r | |
2470 | ///\r | |
2471 | UINT64 Uint64;\r | |
2472 | } MSR_IA32_MC_CTL2_REGISTER;\r | |
2473 | \r | |
2474 | \r | |
2475 | /**\r | |
2476 | MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.\r | |
2477 | \r | |
2478 | @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF)\r | |
2479 | @param EAX Lower 32-bits of MSR value.\r | |
2480 | Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r | |
2481 | @param EDX Upper 32-bits of MSR value.\r | |
2482 | Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r | |
2483 | \r | |
2484 | <b>Example usage</b>\r | |
2485 | @code\r | |
2486 | MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr;\r | |
2487 | \r | |
2488 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r | |
2489 | AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);\r | |
2490 | @endcode\r | |
2491 | **/\r | |
2492 | #define MSR_IA32_MTRR_DEF_TYPE 0x000002FF\r | |
2493 | \r | |
2494 | /**\r | |
2495 | MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE\r | |
2496 | **/\r | |
2497 | typedef union {\r | |
2498 | ///\r | |
2499 | /// Individual bit fields\r | |
2500 | ///\r | |
2501 | struct {\r | |
2502 | ///\r | |
2503 | /// [Bits 2:0] Default Memory Type.\r | |
2504 | ///\r | |
2505 | UINT32 Type:3;\r | |
2506 | UINT32 Reserved1:7;\r | |
2507 | ///\r | |
2508 | /// [Bit 10] Fixed Range MTRR Enable.\r | |
2509 | ///\r | |
2510 | UINT32 FE:1;\r | |
2511 | ///\r | |
2512 | /// [Bit 11] MTRR Enable.\r | |
2513 | ///\r | |
2514 | UINT32 E:1;\r | |
2515 | UINT32 Reserved2:20;\r | |
2516 | UINT32 Reserved3:32;\r | |
2517 | } Bits;\r | |
2518 | ///\r | |
2519 | /// All bit fields as a 32-bit value\r | |
2520 | ///\r | |
2521 | UINT32 Uint32;\r | |
2522 | ///\r | |
2523 | /// All bit fields as a 64-bit value\r | |
2524 | ///\r | |
2525 | UINT64 Uint64;\r | |
2526 | } MSR_IA32_MTRR_DEF_TYPE_REGISTER;\r | |
2527 | \r | |
2528 | \r | |
2529 | /**\r | |
2530 | Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If\r | |
2531 | CPUID.0AH: EDX[4:0] > 0.\r | |
2532 | \r | |
2533 | @param ECX MSR_IA32_FIXED_CTR0 (0x00000309)\r | |
2534 | @param EAX Lower 32-bits of MSR value.\r | |
2535 | @param EDX Upper 32-bits of MSR value.\r | |
2536 | \r | |
2537 | <b>Example usage</b>\r | |
2538 | @code\r | |
2539 | UINT64 Msr;\r | |
2540 | \r | |
2541 | Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);\r | |
2542 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);\r | |
2543 | @endcode\r | |
2544 | **/\r | |
2545 | #define MSR_IA32_FIXED_CTR0 0x00000309\r | |
2546 | \r | |
2547 | \r | |
2548 | /**\r | |
2549 | Fixed-Function Performance Counter 1 0 (R/W): Counts CPU_CLK_Unhalted.Core.\r | |
2550 | If CPUID.0AH: EDX[4:0] > 1.\r | |
2551 | \r | |
2552 | @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)\r | |
2553 | @param EAX Lower 32-bits of MSR value.\r | |
2554 | @param EDX Upper 32-bits of MSR value.\r | |
2555 | \r | |
2556 | <b>Example usage</b>\r | |
2557 | @code\r | |
2558 | UINT64 Msr;\r | |
2559 | \r | |
2560 | Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);\r | |
2561 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);\r | |
2562 | @endcode\r | |
2563 | **/\r | |
2564 | #define MSR_IA32_FIXED_CTR1 0x0000030A\r | |
2565 | \r | |
2566 | \r | |
2567 | /**\r | |
2568 | Fixed-Function Performance Counter 0 0 (R/W): Counts CPU_CLK_Unhalted.Ref.\r | |
2569 | If CPUID.0AH: EDX[4:0] > 2.\r | |
2570 | \r | |
2571 | @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)\r | |
2572 | @param EAX Lower 32-bits of MSR value.\r | |
2573 | @param EDX Upper 32-bits of MSR value.\r | |
2574 | \r | |
2575 | <b>Example usage</b>\r | |
2576 | @code\r | |
2577 | UINT64 Msr;\r | |
2578 | \r | |
2579 | Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);\r | |
2580 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);\r | |
2581 | @endcode\r | |
2582 | **/\r | |
2583 | #define MSR_IA32_FIXED_CTR2 0x0000030B\r | |
2584 | \r | |
2585 | \r | |
2586 | /**\r | |
2587 | RO. If CPUID.01H: ECX[15] = 1.\r | |
2588 | \r | |
2589 | @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345)\r | |
2590 | @param EAX Lower 32-bits of MSR value.\r | |
2591 | Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r | |
2592 | @param EDX Upper 32-bits of MSR value.\r | |
2593 | Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r | |
2594 | \r | |
2595 | <b>Example usage</b>\r | |
2596 | @code\r | |
2597 | MSR_IA32_PERF_CAPABILITIES_REGISTER Msr;\r | |
2598 | \r | |
2599 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);\r | |
2600 | AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);\r | |
2601 | @endcode\r | |
2602 | **/\r | |
2603 | #define MSR_IA32_PERF_CAPABILITIES 0x00000345\r | |
2604 | \r | |
2605 | /**\r | |
2606 | MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES\r | |
2607 | **/\r | |
2608 | typedef union {\r | |
2609 | ///\r | |
2610 | /// Individual bit fields\r | |
2611 | ///\r | |
2612 | struct {\r | |
2613 | ///\r | |
2614 | /// [Bits 5:0] LBR format.\r | |
2615 | ///\r | |
2616 | UINT32 LBR_FMT:6;\r | |
2617 | ///\r | |
2618 | /// [Bit 6] PEBS Trap.\r | |
2619 | ///\r | |
2620 | UINT32 PEBS_TRAP:1;\r | |
2621 | ///\r | |
2622 | /// [Bit 7] PEBSSaveArchRegs.\r | |
2623 | ///\r | |
2624 | UINT32 PEBS_ARCH_REG:1;\r | |
2625 | ///\r | |
2626 | /// [Bits 11:8] PEBS Record Format.\r | |
2627 | ///\r | |
2628 | UINT32 PEBS_REC_FMT:4;\r | |
2629 | ///\r | |
2630 | /// [Bit 12] 1: Freeze while SMM is supported.\r | |
2631 | ///\r | |
2632 | UINT32 SMM_FREEZE:1;\r | |
2633 | ///\r | |
2634 | /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.\r | |
2635 | ///\r | |
2636 | UINT32 FW_WRITE:1;\r | |
2637 | UINT32 Reserved1:18;\r | |
2638 | UINT32 Reserved2:32;\r | |
2639 | } Bits;\r | |
2640 | ///\r | |
2641 | /// All bit fields as a 32-bit value\r | |
2642 | ///\r | |
2643 | UINT32 Uint32;\r | |
2644 | ///\r | |
2645 | /// All bit fields as a 64-bit value\r | |
2646 | ///\r | |
2647 | UINT64 Uint64;\r | |
2648 | } MSR_IA32_PERF_CAPABILITIES_REGISTER;\r | |
2649 | \r | |
2650 | \r | |
2651 | /**\r | |
2652 | Fixed-Function Performance Counter Control (R/W) Counter increments while\r | |
2653 | the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with\r | |
2654 | the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]\r | |
2655 | > 1.\r | |
2656 | \r | |
2657 | @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D)\r | |
2658 | @param EAX Lower 32-bits of MSR value.\r | |
2659 | Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r | |
2660 | @param EDX Upper 32-bits of MSR value.\r | |
2661 | Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r | |
2662 | \r | |
2663 | <b>Example usage</b>\r | |
2664 | @code\r | |
2665 | MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr;\r | |
2666 | \r | |
2667 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);\r | |
2668 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);\r | |
2669 | @endcode\r | |
2670 | **/\r | |
2671 | #define MSR_IA32_FIXED_CTR_CTRL 0x0000038D\r | |
2672 | \r | |
2673 | /**\r | |
2674 | MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL\r | |
2675 | **/\r | |
2676 | typedef union {\r | |
2677 | ///\r | |
2678 | /// Individual bit fields\r | |
2679 | ///\r | |
2680 | struct {\r | |
2681 | ///\r | |
2682 | /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.\r | |
2683 | ///\r | |
2684 | UINT32 EN0_OS:1;\r | |
2685 | ///\r | |
2686 | /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.\r | |
2687 | ///\r | |
2688 | UINT32 EN0_Usr:1;\r | |
2689 | ///\r | |
2690 | /// [Bit 2] AnyThread: When set to 1, it enables counting the associated\r | |
2691 | /// event conditions occurring across all logical processors sharing a\r | |
2692 | /// processor core. When set to 0, the counter only increments the\r | |
2693 | /// associated event conditions occurring in the logical processor which\r | |
2694 | /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r | |
2695 | ///\r | |
2696 | UINT32 AnyThread0:1;\r | |
2697 | ///\r | |
2698 | /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.\r | |
2699 | ///\r | |
2700 | UINT32 EN0_PMI:1;\r | |
2701 | ///\r | |
2702 | /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.\r | |
2703 | ///\r | |
2704 | UINT32 EN1_OS:1;\r | |
2705 | ///\r | |
2706 | /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.\r | |
2707 | ///\r | |
2708 | UINT32 EN1_Usr:1;\r | |
2709 | ///\r | |
2710 | /// [Bit 6] AnyThread: When set to 1, it enables counting the associated\r | |
2711 | /// event conditions occurring across all logical processors sharing a\r | |
2712 | /// processor core. When set to 0, the counter only increments the\r | |
2713 | /// associated event conditions occurring in the logical processor which\r | |
2714 | /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r | |
2715 | ///\r | |
2716 | UINT32 AnyThread1:1;\r | |
2717 | ///\r | |
2718 | /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.\r | |
2719 | ///\r | |
2720 | UINT32 EN1_PMI:1;\r | |
2721 | ///\r | |
2722 | /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.\r | |
2723 | ///\r | |
2724 | UINT32 EN2_OS:1;\r | |
2725 | ///\r | |
2726 | /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.\r | |
2727 | ///\r | |
2728 | UINT32 EN2_Usr:1;\r | |
2729 | ///\r | |
2730 | /// [Bit 10] AnyThread: When set to 1, it enables counting the associated\r | |
2731 | /// event conditions occurring across all logical processors sharing a\r | |
2732 | /// processor core. When set to 0, the counter only increments the\r | |
2733 | /// associated event conditions occurring in the logical processor which\r | |
2734 | /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r | |
2735 | ///\r | |
2736 | UINT32 AnyThread2:1;\r | |
2737 | ///\r | |
2738 | /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.\r | |
2739 | ///\r | |
2740 | UINT32 EN2_PMI:1;\r | |
2741 | UINT32 Reserved1:20;\r | |
2742 | UINT32 Reserved2:32;\r | |
2743 | } Bits;\r | |
2744 | ///\r | |
2745 | /// All bit fields as a 32-bit value\r | |
2746 | ///\r | |
2747 | UINT32 Uint32;\r | |
2748 | ///\r | |
2749 | /// All bit fields as a 64-bit value\r | |
2750 | ///\r | |
2751 | UINT64 Uint64;\r | |
2752 | } MSR_IA32_FIXED_CTR_CTRL_REGISTER;\r | |
2753 | \r | |
2754 | \r | |
2755 | /**\r | |
2756 | Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.\r | |
2757 | \r | |
2758 | @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r | |
2759 | @param EAX Lower 32-bits of MSR value.\r | |
2760 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r | |
2761 | @param EDX Upper 32-bits of MSR value.\r | |
2762 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r | |
2763 | \r | |
2764 | <b>Example usage</b>\r | |
2765 | @code\r | |
2766 | MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r | |
2767 | \r | |
2768 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);\r | |
2769 | @endcode\r | |
2770 | **/\r | |
2771 | #define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E\r | |
2772 | \r | |
2773 | /**\r | |
2774 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS\r | |
2775 | **/\r | |
2776 | typedef union {\r | |
2777 | ///\r | |
2778 | /// Individual bit fields\r | |
2779 | ///\r | |
2780 | struct {\r | |
2781 | ///\r | |
2782 | /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:\r | |
2783 | /// EAX[15:8] > 0.\r | |
2784 | ///\r | |
2785 | UINT32 Ovf_PMC0:1;\r | |
2786 | ///\r | |
2787 | /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:\r | |
2788 | /// EAX[15:8] > 1.\r | |
2789 | ///\r | |
2790 | UINT32 Ovf_PMC1:1;\r | |
2791 | ///\r | |
2792 | /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:\r | |
2793 | /// EAX[15:8] > 2.\r | |
2794 | ///\r | |
2795 | UINT32 Ovf_PMC2:1;\r | |
2796 | ///\r | |
2797 | /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:\r | |
2798 | /// EAX[15:8] > 3.\r | |
2799 | ///\r | |
2800 | UINT32 Ovf_PMC3:1;\r | |
2801 | UINT32 Reserved1:28;\r | |
2802 | ///\r | |
2803 | /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If\r | |
2804 | /// CPUID.0AH: EAX[7:0] > 1.\r | |
2805 | ///\r | |
2806 | UINT32 Ovf_FixedCtr0:1;\r | |
2807 | ///\r | |
2808 | /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If\r | |
2809 | /// CPUID.0AH: EAX[7:0] > 1.\r | |
2810 | ///\r | |
2811 | UINT32 Ovf_FixedCtr1:1;\r | |
2812 | ///\r | |
2813 | /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If\r | |
2814 | /// CPUID.0AH: EAX[7:0] > 1.\r | |
2815 | ///\r | |
2816 | UINT32 Ovf_FixedCtr2:1;\r | |
2817 | UINT32 Reserved2:20;\r | |
2818 | ///\r | |
2819 | /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory\r | |
2820 | /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r | |
2821 | /// && IA32_RTIT_CTL.ToPA = 1.\r | |
2822 | ///\r | |
2823 | UINT32 Trace_ToPA_PMI:1;\r | |
2824 | UINT32 Reserved3:2;\r | |
2825 | ///\r | |
2826 | /// [Bit 58] LBR_Frz: LBRs are frozen due to -\r | |
2827 | /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If\r | |
2828 | /// CPUID.0AH: EAX[7:0] > 3.\r | |
2829 | ///\r | |
2830 | UINT32 LBR_Frz:1;\r | |
2831 | ///\r | |
2832 | /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due\r | |
2833 | /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU\r | |
2834 | /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.\r | |
2835 | ///\r | |
2836 | UINT32 CTR_Frz:1;\r | |
2837 | ///\r | |
2838 | /// [Bit 60] ASCI: Data in the performance counters in the core PMU may\r | |
2839 | /// include contributions from the direct or indirect operation intel SGX\r | |
2840 | /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.\r | |
2841 | ///\r | |
2842 | UINT32 ASCI:1;\r | |
2843 | ///\r | |
2844 | /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:\r | |
2845 | /// EAX[7:0] > 2.\r | |
2846 | ///\r | |
2847 | UINT32 Ovf_Uncore:1;\r | |
2848 | ///\r | |
2849 | /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:\r | |
2850 | /// EAX[7:0] > 0.\r | |
2851 | ///\r | |
2852 | UINT32 OvfBuf:1;\r | |
2853 | ///\r | |
2854 | /// [Bit 63] CondChgd: status bits of this register has changed. If\r | |
2855 | /// CPUID.0AH: EAX[7:0] > 0.\r | |
2856 | ///\r | |
2857 | UINT32 CondChgd:1;\r | |
2858 | } Bits;\r | |
2859 | ///\r | |
2860 | /// All bit fields as a 64-bit value\r | |
2861 | ///\r | |
2862 | UINT64 Uint64;\r | |
2863 | } MSR_IA32_PERF_GLOBAL_STATUS_REGISTER;\r | |
2864 | \r | |
2865 | \r | |
2866 | /**\r | |
2867 | Global Performance Counter Control (R/W) Counter increments while the result\r | |
2868 | of ANDing respective enable bit in this MSR with the corresponding OS or USR\r | |
2869 | bits in the general-purpose or fixed counter control MSR is true. If\r | |
2870 | CPUID.0AH: EAX[7:0] > 0.\r | |
2871 | \r | |
2872 | @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)\r | |
2873 | @param EAX Lower 32-bits of MSR value.\r | |
2874 | Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r | |
2875 | @param EDX Upper 32-bits of MSR value.\r | |
2876 | Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r | |
2877 | \r | |
2878 | <b>Example usage</b>\r | |
2879 | @code\r | |
2880 | MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;\r | |
2881 | \r | |
2882 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);\r | |
2883 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);\r | |
2884 | @endcode\r | |
2885 | **/\r | |
2886 | #define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F\r | |
2887 | \r | |
2888 | /**\r | |
2889 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL\r | |
2890 | **/\r | |
2891 | typedef union {\r | |
2892 | ///\r | |
2893 | /// Individual bit fields\r | |
2894 | ///\r | |
2895 | struct {\r | |
2896 | ///\r | |
2897 | /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.\r | |
2898 | /// Enable bitmask. Only the first n-1 bits are valid.\r | |
2899 | /// Bits n..31 are reserved.\r | |
2900 | ///\r | |
2901 | UINT32 EN_PMCn:32;\r | |
2902 | ///\r | |
2903 | /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.\r | |
2904 | /// Enable bitmask. Only the first n-1 bits are valid.\r | |
2905 | /// Bits 31:n are reserved.\r | |
2906 | ///\r | |
2907 | UINT32 EN_FIXED_CTRn:32;\r | |
2908 | } Bits;\r | |
2909 | ///\r | |
2910 | /// All bit fields as a 64-bit value\r | |
2911 | ///\r | |
2912 | UINT64 Uint64;\r | |
2913 | } MSR_IA32_PERF_GLOBAL_CTRL_REGISTER;\r | |
2914 | \r | |
2915 | \r | |
2916 | /**\r | |
2917 | Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >\r | |
2918 | 0 && CPUID.0AH: EAX[7:0] <= 3.\r | |
2919 | \r | |
2920 | @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)\r | |
2921 | @param EAX Lower 32-bits of MSR value.\r | |
2922 | Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r | |
2923 | @param EDX Upper 32-bits of MSR value.\r | |
2924 | Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r | |
2925 | \r | |
2926 | <b>Example usage</b>\r | |
2927 | @code\r | |
2928 | MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r | |
2929 | \r | |
2930 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);\r | |
2931 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r | |
2932 | @endcode\r | |
2933 | **/\r | |
2934 | #define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r | |
2935 | \r | |
2936 | /**\r | |
2937 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL\r | |
2938 | **/\r | |
2939 | typedef union {\r | |
2940 | ///\r | |
2941 | /// Individual bit fields\r | |
2942 | ///\r | |
2943 | struct {\r | |
2944 | ///\r | |
2945 | /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r | |
2946 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
2947 | /// Bits 31:n are reserved.\r | |
2948 | ///\r | |
2949 | UINT32 Ovf_PMCn:32;\r | |
2950 | ///\r | |
2951 | /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r | |
2952 | /// If CPUID.0AH: EDX[4:0] > n.\r | |
2953 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
2954 | /// Bits 22:n are reserved.\r | |
2955 | ///\r | |
2956 | UINT32 Ovf_FIXED_CTRn:23;\r | |
2957 | ///\r | |
2958 | /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r | |
2959 | /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.\r | |
2960 | ///\r | |
2961 | UINT32 Trace_ToPA_PMI:1;\r | |
2962 | UINT32 Reserved2:5;\r | |
2963 | ///\r | |
2964 | /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r | |
2965 | /// Display Model 06_2EH.\r | |
2966 | ///\r | |
2967 | UINT32 Ovf_Uncore:1;\r | |
2968 | ///\r | |
2969 | /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
2970 | ///\r | |
2971 | UINT32 OvfBuf:1;\r | |
2972 | ///\r | |
2973 | /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
2974 | ///\r | |
2975 | UINT32 CondChgd:1;\r | |
2976 | } Bits;\r | |
2977 | ///\r | |
2978 | /// All bit fields as a 64-bit value\r | |
2979 | ///\r | |
2980 | UINT64 Uint64;\r | |
2981 | } MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;\r | |
2982 | \r | |
2983 | \r | |
2984 | /**\r | |
2985 | Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:\r | |
2986 | EAX[7:0] > 3.\r | |
2987 | \r | |
2988 | @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r | |
2989 | @param EAX Lower 32-bits of MSR value.\r | |
2990 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r | |
2991 | @param EDX Upper 32-bits of MSR value.\r | |
2992 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r | |
2993 | \r | |
2994 | <b>Example usage</b>\r | |
2995 | @code\r | |
2996 | MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;\r | |
2997 | \r | |
2998 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);\r | |
2999 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r | |
3000 | @endcode\r | |
3001 | **/\r | |
3002 | #define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r | |
3003 | \r | |
3004 | /**\r | |
3005 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET\r | |
3006 | **/\r | |
3007 | typedef union {\r | |
3008 | ///\r | |
3009 | /// Individual bit fields\r | |
3010 | ///\r | |
3011 | struct {\r | |
3012 | ///\r | |
3013 | /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r | |
3014 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
3015 | /// Bits 31:n are reserved.\r | |
3016 | ///\r | |
3017 | UINT32 Ovf_PMCn:32;\r | |
3018 | ///\r | |
3019 | /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r | |
3020 | /// If CPUID.0AH: EDX[4:0] > n.\r | |
3021 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
3022 | /// Bits 22:n are reserved.\r | |
3023 | ///\r | |
3024 | UINT32 Ovf_FIXED_CTRn:23;\r | |
3025 | ///\r | |
3026 | /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r | |
3027 | /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.\r | |
3028 | ///\r | |
3029 | UINT32 Trace_ToPA_PMI:1;\r | |
3030 | UINT32 Reserved2:2;\r | |
3031 | ///\r | |
3032 | /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r | |
3033 | ///\r | |
3034 | UINT32 LBR_Frz:1;\r | |
3035 | ///\r | |
3036 | /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r | |
3037 | ///\r | |
3038 | UINT32 CTR_Frz:1;\r | |
3039 | ///\r | |
3040 | /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.\r | |
3041 | ///\r | |
3042 | UINT32 ASCI:1;\r | |
3043 | ///\r | |
3044 | /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r | |
3045 | /// Display Model 06_2EH.\r | |
3046 | ///\r | |
3047 | UINT32 Ovf_Uncore:1;\r | |
3048 | ///\r | |
3049 | /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
3050 | ///\r | |
3051 | UINT32 OvfBuf:1;\r | |
3052 | ///\r | |
3053 | /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
3054 | ///\r | |
3055 | UINT32 CondChgd:1;\r | |
3056 | } Bits;\r | |
3057 | ///\r | |
3058 | /// All bit fields as a 64-bit value\r | |
3059 | ///\r | |
3060 | UINT64 Uint64;\r | |
3061 | } MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r | |
3062 | \r | |
3063 | \r | |
3064 | /**\r | |
3065 | Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:\r | |
3066 | EAX[7:0] > 3.\r | |
3067 | \r | |
3068 | @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r | |
3069 | @param EAX Lower 32-bits of MSR value.\r | |
3070 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r | |
3071 | @param EDX Upper 32-bits of MSR value.\r | |
3072 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r | |
3073 | \r | |
3074 | <b>Example usage</b>\r | |
3075 | @code\r | |
3076 | MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;\r | |
3077 | \r | |
3078 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);\r | |
3079 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r | |
3080 | @endcode\r | |
3081 | **/\r | |
3082 | #define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r | |
3083 | \r | |
3084 | /**\r | |
3085 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET\r | |
3086 | **/\r | |
3087 | typedef union {\r | |
3088 | ///\r | |
3089 | /// Individual bit fields\r | |
3090 | ///\r | |
3091 | struct {\r | |
3092 | ///\r | |
3093 | /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.\r | |
3094 | /// Set bitmask. Only the first n-1 bits are valid.\r | |
3095 | /// Bits 31:n are reserved.\r | |
3096 | ///\r | |
3097 | UINT32 Ovf_PMCn:32;\r | |
3098 | ///\r | |
3099 | /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.\r | |
3100 | /// If CPUID.0AH: EAX[7:0] > n.\r | |
3101 | /// Set bitmask. Only the first n-1 bits are valid.\r | |
3102 | /// Bits 22:n are reserved.\r | |
3103 | ///\r | |
3104 | UINT32 Ovf_FIXED_CTRn:23;\r | |
3105 | ///\r | |
3106 | /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
3107 | ///\r | |
3108 | UINT32 Trace_ToPA_PMI:1;\r | |
3109 | UINT32 Reserved2:2;\r | |
3110 | ///\r | |
3111 | /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
3112 | ///\r | |
3113 | UINT32 LBR_Frz:1;\r | |
3114 | ///\r | |
3115 | /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
3116 | ///\r | |
3117 | UINT32 CTR_Frz:1;\r | |
3118 | ///\r | |
3119 | /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
3120 | ///\r | |
3121 | UINT32 ASCI:1;\r | |
3122 | ///\r | |
3123 | /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
3124 | ///\r | |
3125 | UINT32 Ovf_Uncore:1;\r | |
3126 | ///\r | |
3127 | /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
3128 | ///\r | |
3129 | UINT32 OvfBuf:1;\r | |
3130 | UINT32 Reserved3:1;\r | |
3131 | } Bits;\r | |
3132 | ///\r | |
3133 | /// All bit fields as a 64-bit value\r | |
3134 | ///\r | |
3135 | UINT64 Uint64;\r | |
3136 | } MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r | |
3137 | \r | |
3138 | \r | |
3139 | /**\r | |
3140 | Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >\r | |
3141 | 3.\r | |
3142 | \r | |
3143 | @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)\r | |
3144 | @param EAX Lower 32-bits of MSR value.\r | |
3145 | Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r | |
3146 | @param EDX Upper 32-bits of MSR value.\r | |
3147 | Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r | |
3148 | \r | |
3149 | <b>Example usage</b>\r | |
3150 | @code\r | |
3151 | MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr;\r | |
3152 | \r | |
3153 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);\r | |
3154 | @endcode\r | |
3155 | **/\r | |
3156 | #define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392\r | |
3157 | \r | |
3158 | /**\r | |
3159 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE\r | |
3160 | **/\r | |
3161 | typedef union {\r | |
3162 | ///\r | |
3163 | /// Individual bit fields\r | |
3164 | ///\r | |
3165 | struct {\r | |
3166 | ///\r | |
3167 | /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n.\r | |
3168 | /// Status bitmask. Only the first n-1 bits are valid.\r | |
3169 | /// Bits 31:n are reserved.\r | |
3170 | ///\r | |
3171 | UINT32 IA32_PERFEVTSELn:32;\r | |
3172 | ///\r | |
3173 | /// [Bits 62:32] IA32_FIXED_CTRn in use.\r | |
3174 | /// If CPUID.0AH: EAX[7:0] > n.\r | |
3175 | /// Status bitmask. Only the first n-1 bits are valid.\r | |
3176 | /// Bits 30:n are reserved.\r | |
3177 | ///\r | |
3178 | UINT32 IA32_FIXED_CTRn:31;\r | |
3179 | ///\r | |
3180 | /// [Bit 63] PMI in use.\r | |
3181 | ///\r | |
3182 | UINT32 PMI:1;\r | |
3183 | } Bits;\r | |
3184 | ///\r | |
3185 | /// All bit fields as a 64-bit value\r | |
3186 | ///\r | |
3187 | UINT64 Uint64;\r | |
3188 | } MSR_IA32_PERF_GLOBAL_INUSE_REGISTER;\r | |
3189 | \r | |
3190 | \r | |
3191 | /**\r | |
3192 | PEBS Control (R/W).\r | |
3193 | \r | |
3194 | @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1)\r | |
3195 | @param EAX Lower 32-bits of MSR value.\r | |
3196 | Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r | |
3197 | @param EDX Upper 32-bits of MSR value.\r | |
3198 | Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r | |
3199 | \r | |
3200 | <b>Example usage</b>\r | |
3201 | @code\r | |
3202 | MSR_IA32_PEBS_ENABLE_REGISTER Msr;\r | |
3203 | \r | |
3204 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);\r | |
3205 | AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);\r | |
3206 | @endcode\r | |
3207 | **/\r | |
3208 | #define MSR_IA32_PEBS_ENABLE 0x000003F1\r | |
3209 | \r | |
3210 | /**\r | |
3211 | MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE\r | |
3212 | **/\r | |
3213 | typedef union {\r | |
3214 | ///\r | |
3215 | /// Individual bit fields\r | |
3216 | ///\r | |
3217 | struct {\r | |
3218 | ///\r | |
3219 | /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /\r | |
3220 | /// Display Model 06_0FH.\r | |
3221 | ///\r | |
3222 | UINT32 Enable:1;\r | |
3223 | ///\r | |
3224 | /// [Bits 3:1] Reserved or Model specific.\r | |
3225 | ///\r | |
3226 | UINT32 Reserved1:3;\r | |
3227 | UINT32 Reserved2:28;\r | |
3228 | ///\r | |
3229 | /// [Bits 35:32] Reserved or Model specific.\r | |
3230 | ///\r | |
3231 | UINT32 Reserved3:4;\r | |
3232 | UINT32 Reserved4:28;\r | |
3233 | } Bits;\r | |
3234 | ///\r | |
3235 | /// All bit fields as a 64-bit value\r | |
3236 | ///\r | |
3237 | UINT64 Uint64;\r | |
3238 | } MSR_IA32_PEBS_ENABLE_REGISTER;\r | |
3239 | \r | |
3240 | \r | |
3241 | /**\r | |
3242 | MCn_CTL. If IA32_MCG_CAP.CNT > n.\r | |
3243 | \r | |
3244 | @param ECX MSR_IA32_MCn_CTL\r | |
3245 | @param EAX Lower 32-bits of MSR value.\r | |
3246 | @param EDX Upper 32-bits of MSR value.\r | |
3247 | \r | |
3248 | <b>Example usage</b>\r | |
3249 | @code\r | |
3250 | UINT64 Msr;\r | |
3251 | \r | |
3252 | Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);\r | |
3253 | AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);\r | |
3254 | @endcode\r | |
3255 | @{\r | |
3256 | **/\r | |
3257 | #define MSR_IA32_MC0_CTL 0x00000400\r | |
3258 | #define MSR_IA32_MC1_CTL 0x00000404\r | |
3259 | #define MSR_IA32_MC2_CTL 0x00000408\r | |
3260 | #define MSR_IA32_MC3_CTL 0x0000040C\r | |
3261 | #define MSR_IA32_MC4_CTL 0x00000410\r | |
3262 | #define MSR_IA32_MC5_CTL 0x00000414\r | |
3263 | #define MSR_IA32_MC6_CTL 0x00000418\r | |
3264 | #define MSR_IA32_MC7_CTL 0x0000041C\r | |
3265 | #define MSR_IA32_MC8_CTL 0x00000420\r | |
3266 | #define MSR_IA32_MC9_CTL 0x00000424\r | |
3267 | #define MSR_IA32_MC10_CTL 0x00000428\r | |
3268 | #define MSR_IA32_MC11_CTL 0x0000042C\r | |
3269 | #define MSR_IA32_MC12_CTL 0x00000430\r | |
3270 | #define MSR_IA32_MC13_CTL 0x00000434\r | |
3271 | #define MSR_IA32_MC14_CTL 0x00000438\r | |
3272 | #define MSR_IA32_MC15_CTL 0x0000043C\r | |
3273 | #define MSR_IA32_MC16_CTL 0x00000440\r | |
3274 | #define MSR_IA32_MC17_CTL 0x00000444\r | |
3275 | #define MSR_IA32_MC18_CTL 0x00000448\r | |
3276 | #define MSR_IA32_MC19_CTL 0x0000044C\r | |
3277 | #define MSR_IA32_MC20_CTL 0x00000450\r | |
3278 | #define MSR_IA32_MC21_CTL 0x00000454\r | |
3279 | #define MSR_IA32_MC22_CTL 0x00000458\r | |
3280 | #define MSR_IA32_MC23_CTL 0x0000045C\r | |
3281 | #define MSR_IA32_MC24_CTL 0x00000460\r | |
3282 | #define MSR_IA32_MC25_CTL 0x00000464\r | |
3283 | #define MSR_IA32_MC26_CTL 0x00000468\r | |
3284 | #define MSR_IA32_MC27_CTL 0x0000046C\r | |
3285 | #define MSR_IA32_MC28_CTL 0x00000470\r | |
3286 | /// @}\r | |
3287 | \r | |
3288 | \r | |
3289 | /**\r | |
3290 | MCn_STATUS. If IA32_MCG_CAP.CNT > n.\r | |
3291 | \r | |
3292 | @param ECX MSR_IA32_MCn_STATUS\r | |
3293 | @param EAX Lower 32-bits of MSR value.\r | |
3294 | @param EDX Upper 32-bits of MSR value.\r | |
3295 | \r | |
3296 | <b>Example usage</b>\r | |
3297 | @code\r | |
3298 | UINT64 Msr;\r | |
3299 | \r | |
3300 | Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);\r | |
3301 | AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);\r | |
3302 | @endcode\r | |
3303 | @{\r | |
3304 | **/\r | |
3305 | #define MSR_IA32_MC0_STATUS 0x00000401\r | |
3306 | #define MSR_IA32_MC1_STATUS 0x00000405\r | |
3307 | #define MSR_IA32_MC2_STATUS 0x00000409\r | |
3308 | #define MSR_IA32_MC3_STATUS 0x0000040D\r | |
3309 | #define MSR_IA32_MC4_STATUS 0x00000411\r | |
3310 | #define MSR_IA32_MC5_STATUS 0x00000415\r | |
3311 | #define MSR_IA32_MC6_STATUS 0x00000419\r | |
3312 | #define MSR_IA32_MC7_STATUS 0x0000041D\r | |
3313 | #define MSR_IA32_MC8_STATUS 0x00000421\r | |
3314 | #define MSR_IA32_MC9_STATUS 0x00000425\r | |
3315 | #define MSR_IA32_MC10_STATUS 0x00000429\r | |
3316 | #define MSR_IA32_MC11_STATUS 0x0000042D\r | |
3317 | #define MSR_IA32_MC12_STATUS 0x00000431\r | |
3318 | #define MSR_IA32_MC13_STATUS 0x00000435\r | |
3319 | #define MSR_IA32_MC14_STATUS 0x00000439\r | |
3320 | #define MSR_IA32_MC15_STATUS 0x0000043D\r | |
3321 | #define MSR_IA32_MC16_STATUS 0x00000441\r | |
3322 | #define MSR_IA32_MC17_STATUS 0x00000445\r | |
3323 | #define MSR_IA32_MC18_STATUS 0x00000449\r | |
3324 | #define MSR_IA32_MC19_STATUS 0x0000044D\r | |
3325 | #define MSR_IA32_MC20_STATUS 0x00000451\r | |
3326 | #define MSR_IA32_MC21_STATUS 0x00000455\r | |
3327 | #define MSR_IA32_MC22_STATUS 0x00000459\r | |
3328 | #define MSR_IA32_MC23_STATUS 0x0000045D\r | |
3329 | #define MSR_IA32_MC24_STATUS 0x00000461\r | |
3330 | #define MSR_IA32_MC25_STATUS 0x00000465\r | |
3331 | #define MSR_IA32_MC26_STATUS 0x00000469\r | |
3332 | #define MSR_IA32_MC27_STATUS 0x0000046D\r | |
3333 | #define MSR_IA32_MC28_STATUS 0x00000471\r | |
3334 | /// @}\r | |
3335 | \r | |
3336 | \r | |
3337 | /**\r | |
3338 | MCn_ADDR. If IA32_MCG_CAP.CNT > n.\r | |
3339 | \r | |
3340 | @param ECX MSR_IA32_MCn_ADDR\r | |
3341 | @param EAX Lower 32-bits of MSR value.\r | |
3342 | @param EDX Upper 32-bits of MSR value.\r | |
3343 | \r | |
3344 | <b>Example usage</b>\r | |
3345 | @code\r | |
3346 | UINT64 Msr;\r | |
3347 | \r | |
3348 | Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);\r | |
3349 | AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);\r | |
3350 | @endcode\r | |
3351 | @{\r | |
3352 | **/\r | |
3353 | #define MSR_IA32_MC0_ADDR 0x00000402\r | |
3354 | #define MSR_IA32_MC1_ADDR 0x00000406\r | |
3355 | #define MSR_IA32_MC2_ADDR 0x0000040A\r | |
3356 | #define MSR_IA32_MC3_ADDR 0x0000040E\r | |
3357 | #define MSR_IA32_MC4_ADDR 0x00000412\r | |
3358 | #define MSR_IA32_MC5_ADDR 0x00000416\r | |
3359 | #define MSR_IA32_MC6_ADDR 0x0000041A\r | |
3360 | #define MSR_IA32_MC7_ADDR 0x0000041E\r | |
3361 | #define MSR_IA32_MC8_ADDR 0x00000422\r | |
3362 | #define MSR_IA32_MC9_ADDR 0x00000426\r | |
3363 | #define MSR_IA32_MC10_ADDR 0x0000042A\r | |
3364 | #define MSR_IA32_MC11_ADDR 0x0000042E\r | |
3365 | #define MSR_IA32_MC12_ADDR 0x00000432\r | |
3366 | #define MSR_IA32_MC13_ADDR 0x00000436\r | |
3367 | #define MSR_IA32_MC14_ADDR 0x0000043A\r | |
3368 | #define MSR_IA32_MC15_ADDR 0x0000043E\r | |
3369 | #define MSR_IA32_MC16_ADDR 0x00000442\r | |
3370 | #define MSR_IA32_MC17_ADDR 0x00000446\r | |
3371 | #define MSR_IA32_MC18_ADDR 0x0000044A\r | |
3372 | #define MSR_IA32_MC19_ADDR 0x0000044E\r | |
3373 | #define MSR_IA32_MC20_ADDR 0x00000452\r | |
3374 | #define MSR_IA32_MC21_ADDR 0x00000456\r | |
3375 | #define MSR_IA32_MC22_ADDR 0x0000045A\r | |
3376 | #define MSR_IA32_MC23_ADDR 0x0000045E\r | |
3377 | #define MSR_IA32_MC24_ADDR 0x00000462\r | |
3378 | #define MSR_IA32_MC25_ADDR 0x00000466\r | |
3379 | #define MSR_IA32_MC26_ADDR 0x0000046A\r | |
3380 | #define MSR_IA32_MC27_ADDR 0x0000046E\r | |
3381 | #define MSR_IA32_MC28_ADDR 0x00000472\r | |
3382 | /// @}\r | |
3383 | \r | |
3384 | \r | |
3385 | /**\r | |
3386 | MCn_MISC. If IA32_MCG_CAP.CNT > n.\r | |
3387 | \r | |
3388 | @param ECX MSR_IA32_MCn_MISC\r | |
3389 | @param EAX Lower 32-bits of MSR value.\r | |
3390 | @param EDX Upper 32-bits of MSR value.\r | |
3391 | \r | |
3392 | <b>Example usage</b>\r | |
3393 | @code\r | |
3394 | UINT64 Msr;\r | |
3395 | \r | |
3396 | Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);\r | |
3397 | AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);\r | |
3398 | @endcode\r | |
3399 | @{\r | |
3400 | **/\r | |
3401 | #define MSR_IA32_MC0_MISC 0x00000403\r | |
3402 | #define MSR_IA32_MC1_MISC 0x00000407\r | |
3403 | #define MSR_IA32_MC2_MISC 0x0000040B\r | |
3404 | #define MSR_IA32_MC3_MISC 0x0000040F\r | |
3405 | #define MSR_IA32_MC4_MISC 0x00000413\r | |
3406 | #define MSR_IA32_MC5_MISC 0x00000417\r | |
3407 | #define MSR_IA32_MC6_MISC 0x0000041B\r | |
3408 | #define MSR_IA32_MC7_MISC 0x0000041F\r | |
3409 | #define MSR_IA32_MC8_MISC 0x00000423\r | |
3410 | #define MSR_IA32_MC9_MISC 0x00000427\r | |
3411 | #define MSR_IA32_MC10_MISC 0x0000042B\r | |
3412 | #define MSR_IA32_MC11_MISC 0x0000042F\r | |
3413 | #define MSR_IA32_MC12_MISC 0x00000433\r | |
3414 | #define MSR_IA32_MC13_MISC 0x00000437\r | |
3415 | #define MSR_IA32_MC14_MISC 0x0000043B\r | |
3416 | #define MSR_IA32_MC15_MISC 0x0000043F\r | |
3417 | #define MSR_IA32_MC16_MISC 0x00000443\r | |
3418 | #define MSR_IA32_MC17_MISC 0x00000447\r | |
3419 | #define MSR_IA32_MC18_MISC 0x0000044B\r | |
3420 | #define MSR_IA32_MC19_MISC 0x0000044F\r | |
3421 | #define MSR_IA32_MC20_MISC 0x00000453\r | |
3422 | #define MSR_IA32_MC21_MISC 0x00000457\r | |
3423 | #define MSR_IA32_MC22_MISC 0x0000045B\r | |
3424 | #define MSR_IA32_MC23_MISC 0x0000045F\r | |
3425 | #define MSR_IA32_MC24_MISC 0x00000463\r | |
3426 | #define MSR_IA32_MC25_MISC 0x00000467\r | |
3427 | #define MSR_IA32_MC26_MISC 0x0000046B\r | |
3428 | #define MSR_IA32_MC27_MISC 0x0000046F\r | |
3429 | #define MSR_IA32_MC28_MISC 0x00000473\r | |
3430 | /// @}\r | |
3431 | \r | |
3432 | \r | |
3433 | /**\r | |
3434 | Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic\r | |
3435 | VMX Information.". If CPUID.01H:ECX.[5] = 1.\r | |
3436 | \r | |
3437 | @param ECX MSR_IA32_VMX_BASIC (0x00000480)\r | |
3438 | @param EAX Lower 32-bits of MSR value.\r | |
3439 | @param EDX Upper 32-bits of MSR value.\r | |
3440 | \r | |
3441 | <b>Example usage</b>\r | |
3442 | @code\r | |
3443 | UINT64 Msr;\r | |
3444 | \r | |
3445 | Msr = AsmReadMsr64 (MSR_IA32_VMX_BASIC);\r | |
3446 | @endcode\r | |
3447 | **/\r | |
3448 | #define MSR_IA32_VMX_BASIC 0x00000480\r | |
3449 | \r | |
3450 | \r | |
3451 | /**\r | |
3452 | Capability Reporting Register of Pinbased VM-execution Controls (R/O) See\r | |
3453 | Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
3454 | \r | |
3455 | @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481)\r | |
3456 | @param EAX Lower 32-bits of MSR value.\r | |
3457 | @param EDX Upper 32-bits of MSR value.\r | |
3458 | \r | |
3459 | <b>Example usage</b>\r | |
3460 | @code\r | |
3461 | UINT64 Msr;\r | |
3462 | \r | |
3463 | Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);\r | |
3464 | @endcode\r | |
3465 | **/\r | |
3466 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481\r | |
3467 | \r | |
3468 | \r | |
3469 | /**\r | |
3470 | Capability Reporting Register of Primary Processor-based VM-execution\r | |
3471 | Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution\r | |
3472 | Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
3473 | \r | |
3474 | @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)\r | |
3475 | @param EAX Lower 32-bits of MSR value.\r | |
3476 | @param EDX Upper 32-bits of MSR value.\r | |
3477 | \r | |
3478 | <b>Example usage</b>\r | |
3479 | @code\r | |
3480 | UINT64 Msr;\r | |
3481 | \r | |
3482 | Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);\r | |
3483 | @endcode\r | |
3484 | **/\r | |
3485 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482\r | |
3486 | \r | |
3487 | \r | |
3488 | /**\r | |
3489 | Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,\r | |
3490 | "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
3491 | \r | |
3492 | @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483)\r | |
3493 | @param EAX Lower 32-bits of MSR value.\r | |
3494 | @param EDX Upper 32-bits of MSR value.\r | |
3495 | \r | |
3496 | <b>Example usage</b>\r | |
3497 | @code\r | |
3498 | UINT64 Msr;\r | |
3499 | \r | |
3500 | Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);\r | |
3501 | @endcode\r | |
3502 | **/\r | |
3503 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483\r | |
3504 | \r | |
3505 | \r | |
3506 | /**\r | |
3507 | Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,\r | |
3508 | "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
3509 | \r | |
3510 | @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484)\r | |
3511 | @param EAX Lower 32-bits of MSR value.\r | |
3512 | @param EDX Upper 32-bits of MSR value.\r | |
3513 | \r | |
3514 | <b>Example usage</b>\r | |
3515 | @code\r | |
3516 | UINT64 Msr;\r | |
3517 | \r | |
3518 | Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);\r | |
3519 | @endcode\r | |
3520 | **/\r | |
3521 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484\r | |
3522 | \r | |
3523 | \r | |
3524 | /**\r | |
3525 | Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,\r | |
3526 | "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.\r | |
3527 | \r | |
3528 | @param ECX MSR_IA32_VMX_MISC (0x00000485)\r | |
3529 | @param EAX Lower 32-bits of MSR value.\r | |
3530 | @param EDX Upper 32-bits of MSR value.\r | |
3531 | \r | |
3532 | <b>Example usage</b>\r | |
3533 | @code\r | |
3534 | UINT64 Msr;\r | |
3535 | \r | |
3536 | Msr = AsmReadMsr64 (MSR_IA32_VMX_MISC);\r | |
3537 | @endcode\r | |
3538 | **/\r | |
3539 | #define MSR_IA32_VMX_MISC 0x00000485\r | |
3540 | \r | |
3541 | \r | |
3542 | /**\r | |
3543 | Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,\r | |
3544 | "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.\r | |
3545 | \r | |
3546 | @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486)\r | |
3547 | @param EAX Lower 32-bits of MSR value.\r | |
3548 | @param EDX Upper 32-bits of MSR value.\r | |
3549 | \r | |
3550 | <b>Example usage</b>\r | |
3551 | @code\r | |
3552 | UINT64 Msr;\r | |
3553 | \r | |
3554 | Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);\r | |
3555 | @endcode\r | |
3556 | **/\r | |
3557 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486\r | |
3558 | \r | |
3559 | \r | |
3560 | /**\r | |
3561 | Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,\r | |
3562 | "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.\r | |
3563 | \r | |
3564 | @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487)\r | |
3565 | @param EAX Lower 32-bits of MSR value.\r | |
3566 | @param EDX Upper 32-bits of MSR value.\r | |
3567 | \r | |
3568 | <b>Example usage</b>\r | |
3569 | @code\r | |
3570 | UINT64 Msr;\r | |
3571 | \r | |
3572 | Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);\r | |
3573 | @endcode\r | |
3574 | **/\r | |
3575 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487\r | |
3576 | \r | |
3577 | \r | |
3578 | /**\r | |
3579 | Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,\r | |
3580 | "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.\r | |
3581 | \r | |
3582 | @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488)\r | |
3583 | @param EAX Lower 32-bits of MSR value.\r | |
3584 | @param EDX Upper 32-bits of MSR value.\r | |
3585 | \r | |
3586 | <b>Example usage</b>\r | |
3587 | @code\r | |
3588 | UINT64 Msr;\r | |
3589 | \r | |
3590 | Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);\r | |
3591 | @endcode\r | |
3592 | **/\r | |
3593 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488\r | |
3594 | \r | |
3595 | \r | |
3596 | /**\r | |
3597 | Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,\r | |
3598 | "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.\r | |
3599 | \r | |
3600 | @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489)\r | |
3601 | @param EAX Lower 32-bits of MSR value.\r | |
3602 | @param EDX Upper 32-bits of MSR value.\r | |
3603 | \r | |
3604 | <b>Example usage</b>\r | |
3605 | @code\r | |
3606 | UINT64 Msr;\r | |
3607 | \r | |
3608 | Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);\r | |
3609 | @endcode\r | |
3610 | **/\r | |
3611 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489\r | |
3612 | \r | |
3613 | \r | |
3614 | /**\r | |
3615 | Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix\r | |
3616 | A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.\r | |
3617 | \r | |
3618 | @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A)\r | |
3619 | @param EAX Lower 32-bits of MSR value.\r | |
3620 | @param EDX Upper 32-bits of MSR value.\r | |
3621 | \r | |
3622 | <b>Example usage</b>\r | |
3623 | @code\r | |
3624 | UINT64 Msr;\r | |
3625 | \r | |
3626 | Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);\r | |
3627 | @endcode\r | |
3628 | **/\r | |
3629 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048A\r | |
3630 | \r | |
3631 | \r | |
3632 | /**\r | |
3633 | Capability Reporting Register of Secondary Processor-based VM-execution\r | |
3634 | Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution\r | |
3635 | Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).\r | |
3636 | \r | |
3637 | @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)\r | |
3638 | @param EAX Lower 32-bits of MSR value.\r | |
3639 | @param EDX Upper 32-bits of MSR value.\r | |
3640 | \r | |
3641 | <b>Example usage</b>\r | |
3642 | @code\r | |
3643 | UINT64 Msr;\r | |
3644 | \r | |
3645 | Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);\r | |
3646 | @endcode\r | |
3647 | **/\r | |
3648 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B\r | |
3649 | \r | |
3650 | \r | |
3651 | /**\r | |
3652 | Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,\r | |
3653 | "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C\r | |
3654 | TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).\r | |
3655 | \r | |
3656 | @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)\r | |
3657 | @param EAX Lower 32-bits of MSR value.\r | |
3658 | @param EDX Upper 32-bits of MSR value.\r | |
3659 | \r | |
3660 | <b>Example usage</b>\r | |
3661 | @code\r | |
3662 | UINT64 Msr;\r | |
3663 | \r | |
3664 | Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);\r | |
3665 | @endcode\r | |
3666 | **/\r | |
3667 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C\r | |
3668 | \r | |
3669 | \r | |
3670 | /**\r | |
3671 | Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)\r | |
3672 | See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (\r | |
3673 | CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
3674 | \r | |
3675 | @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)\r | |
3676 | @param EAX Lower 32-bits of MSR value.\r | |
3677 | @param EDX Upper 32-bits of MSR value.\r | |
3678 | \r | |
3679 | <b>Example usage</b>\r | |
3680 | @code\r | |
3681 | UINT64 Msr;\r | |
3682 | \r | |
3683 | Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);\r | |
3684 | @endcode\r | |
3685 | **/\r | |
3686 | #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D\r | |
3687 | \r | |
3688 | \r | |
3689 | /**\r | |
3690 | Capability Reporting Register of Primary Processor-based VM-execution Flex\r | |
3691 | Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution\r | |
3692 | Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
3693 | \r | |
3694 | @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)\r | |
3695 | @param EAX Lower 32-bits of MSR value.\r | |
3696 | @param EDX Upper 32-bits of MSR value.\r | |
3697 | \r | |
3698 | <b>Example usage</b>\r | |
3699 | @code\r | |
3700 | UINT64 Msr;\r | |
3701 | \r | |
3702 | Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);\r | |
3703 | @endcode\r | |
3704 | **/\r | |
3705 | #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E\r | |
3706 | \r | |
3707 | \r | |
3708 | /**\r | |
3709 | Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix\r | |
3710 | A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
3711 | \r | |
3712 | @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)\r | |
3713 | @param EAX Lower 32-bits of MSR value.\r | |
3714 | @param EDX Upper 32-bits of MSR value.\r | |
3715 | \r | |
3716 | <b>Example usage</b>\r | |
3717 | @code\r | |
3718 | UINT64 Msr;\r | |
3719 | \r | |
3720 | Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);\r | |
3721 | @endcode\r | |
3722 | **/\r | |
3723 | #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F\r | |
3724 | \r | |
3725 | \r | |
3726 | /**\r | |
3727 | Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix\r | |
3728 | A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
3729 | \r | |
3730 | @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)\r | |
3731 | @param EAX Lower 32-bits of MSR value.\r | |
3732 | @param EDX Upper 32-bits of MSR value.\r | |
3733 | \r | |
3734 | <b>Example usage</b>\r | |
3735 | @code\r | |
3736 | UINT64 Msr;\r | |
3737 | \r | |
3738 | Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);\r | |
3739 | @endcode\r | |
3740 | **/\r | |
3741 | #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490\r | |
3742 | \r | |
3743 | \r | |
3744 | /**\r | |
3745 | Capability Reporting Register of VMfunction Controls (R/O). If(\r | |
3746 | CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
3747 | \r | |
3748 | @param ECX MSR_IA32_VMX_VMFUNC (0x00000491)\r | |
3749 | @param EAX Lower 32-bits of MSR value.\r | |
3750 | @param EDX Upper 32-bits of MSR value.\r | |
3751 | \r | |
3752 | <b>Example usage</b>\r | |
3753 | @code\r | |
3754 | UINT64 Msr;\r | |
3755 | \r | |
3756 | Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);\r | |
3757 | @endcode\r | |
3758 | **/\r | |
3759 | #define MSR_IA32_VMX_VMFUNC 0x00000491\r | |
3760 | \r | |
3761 | \r | |
3762 | /**\r | |
3763 | Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&\r | |
3764 | IA32_PERF_CAPABILITIES[ 13] = 1.\r | |
3765 | \r | |
3766 | @param ECX MSR_IA32_A_PMCn\r | |
3767 | @param EAX Lower 32-bits of MSR value.\r | |
3768 | @param EDX Upper 32-bits of MSR value.\r | |
3769 | \r | |
3770 | <b>Example usage</b>\r | |
3771 | @code\r | |
3772 | UINT64 Msr;\r | |
3773 | \r | |
3774 | Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);\r | |
3775 | AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);\r | |
3776 | @endcode\r | |
3777 | @{\r | |
3778 | **/\r | |
3779 | #define MSR_IA32_A_PMC0 0x000004C1\r | |
3780 | #define MSR_IA32_A_PMC1 0x000004C2\r | |
3781 | #define MSR_IA32_A_PMC2 0x000004C3\r | |
3782 | #define MSR_IA32_A_PMC3 0x000004C4\r | |
3783 | #define MSR_IA32_A_PMC4 0x000004C5\r | |
3784 | #define MSR_IA32_A_PMC5 0x000004C6\r | |
3785 | #define MSR_IA32_A_PMC6 0x000004C7\r | |
3786 | #define MSR_IA32_A_PMC7 0x000004C8\r | |
3787 | /// @}\r | |
3788 | \r | |
3789 | \r | |
3790 | /**\r | |
3791 | (R/W). If IA32_MCG_CAP.LMCE_P =1.\r | |
3792 | \r | |
3793 | @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0)\r | |
3794 | @param EAX Lower 32-bits of MSR value.\r | |
3795 | Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.\r | |
3796 | @param EDX Upper 32-bits of MSR value.\r | |
3797 | Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.\r | |
3798 | \r | |
3799 | <b>Example usage</b>\r | |
3800 | @code\r | |
3801 | MSR_IA32_MCG_EXT_CTL_REGISTER Msr;\r | |
3802 | \r | |
3803 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);\r | |
3804 | AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);\r | |
3805 | @endcode\r | |
3806 | **/\r | |
3807 | #define MSR_IA32_MCG_EXT_CTL 0x000004D0\r | |
3808 | \r | |
3809 | /**\r | |
3810 | MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL\r | |
3811 | **/\r | |
3812 | typedef union {\r | |
3813 | ///\r | |
3814 | /// Individual bit fields\r | |
3815 | ///\r | |
3816 | struct {\r | |
3817 | ///\r | |
3818 | /// [Bit 0] LMCE_EN.\r | |
3819 | ///\r | |
3820 | UINT32 LMCE_EN:1;\r | |
3821 | UINT32 Reserved1:31;\r | |
3822 | UINT32 Reserved2:32;\r | |
3823 | } Bits;\r | |
3824 | ///\r | |
3825 | /// All bit fields as a 32-bit value\r | |
3826 | ///\r | |
3827 | UINT32 Uint32;\r | |
3828 | ///\r | |
3829 | /// All bit fields as a 64-bit value\r | |
3830 | ///\r | |
3831 | UINT64 Uint64;\r | |
3832 | } MSR_IA32_MCG_EXT_CTL_REGISTER;\r | |
3833 | \r | |
3834 | \r | |
3835 | /**\r | |
3836 | Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,\r | |
3837 | ECX=0H): EBX[2] = 1.\r | |
3838 | \r | |
3839 | @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500)\r | |
3840 | @param EAX Lower 32-bits of MSR value.\r | |
3841 | Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.\r | |
3842 | @param EDX Upper 32-bits of MSR value.\r | |
3843 | Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.\r | |
3844 | \r | |
3845 | <b>Example usage</b>\r | |
3846 | @code\r | |
3847 | MSR_IA32_SGX_SVN_STATUS_REGISTER Msr;\r | |
3848 | \r | |
3849 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);\r | |
3850 | @endcode\r | |
3851 | **/\r | |
3852 | #define MSR_IA32_SGX_SVN_STATUS 0x00000500\r | |
3853 | \r | |
3854 | /**\r | |
3855 | MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS\r | |
3856 | **/\r | |
3857 | typedef union {\r | |
3858 | ///\r | |
3859 | /// Individual bit fields\r | |
3860 | ///\r | |
3861 | struct {\r | |
3862 | ///\r | |
3863 | /// [Bit 0] Lock. See Section 42.12.3, "Interactions with Authenticated\r | |
3864 | /// Code Modules (ACMs)".\r | |
3865 | ///\r | |
3866 | UINT32 Lock:1;\r | |
3867 | UINT32 Reserved1:15;\r | |
3868 | ///\r | |
3869 | /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.12.3, "Interactions with\r | |
3870 | /// Authenticated Code Modules (ACMs)".\r | |
3871 | ///\r | |
3872 | UINT32 SGX_SVN_SINIT:8;\r | |
3873 | UINT32 Reserved2:8;\r | |
3874 | UINT32 Reserved3:32;\r | |
3875 | } Bits;\r | |
3876 | ///\r | |
3877 | /// All bit fields as a 32-bit value\r | |
3878 | ///\r | |
3879 | UINT32 Uint32;\r | |
3880 | ///\r | |
3881 | /// All bit fields as a 64-bit value\r | |
3882 | ///\r | |
3883 | UINT64 Uint64;\r | |
3884 | } MSR_IA32_SGX_SVN_STATUS_REGISTER;\r | |
3885 | \r | |
3886 | \r | |
3887 | /**\r | |
3888 | Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r | |
3889 | && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)\r | |
3890 | ) ).\r | |
3891 | \r | |
3892 | @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)\r | |
3893 | @param EAX Lower 32-bits of MSR value.\r | |
3894 | Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.\r | |
3895 | @param EDX Upper 32-bits of MSR value.\r | |
3896 | Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.\r | |
3897 | \r | |
3898 | <b>Example usage</b>\r | |
3899 | @code\r | |
3900 | MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr;\r | |
3901 | \r | |
3902 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);\r | |
3903 | AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);\r | |
3904 | @endcode\r | |
3905 | **/\r | |
3906 | #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560\r | |
3907 | \r | |
3908 | /**\r | |
3909 | MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE\r | |
3910 | **/\r | |
3911 | typedef union {\r | |
3912 | ///\r | |
3913 | /// Individual bit fields\r | |
3914 | ///\r | |
3915 | struct {\r | |
3916 | UINT32 Reserved:7;\r | |
3917 | ///\r | |
3918 | /// [Bits 31:7] Base physical address.\r | |
3919 | ///\r | |
3920 | UINT32 Base:25;\r | |
3921 | ///\r | |
3922 | /// [Bits 63:32] Base physical address.\r | |
3923 | ///\r | |
3924 | UINT32 BaseHi:32;\r | |
3925 | } Bits;\r | |
3926 | ///\r | |
3927 | /// All bit fields as a 64-bit value\r | |
3928 | ///\r | |
3929 | UINT64 Uint64;\r | |
3930 | } MSR_IA32_RTIT_OUTPUT_BASE_REGISTER;\r | |
3931 | \r | |
3932 | \r | |
3933 | /**\r | |
3934 | Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,\r | |
3935 | ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)\r | |
3936 | (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).\r | |
3937 | \r | |
3938 | @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)\r | |
3939 | @param EAX Lower 32-bits of MSR value.\r | |
3940 | Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.\r | |
3941 | @param EDX Upper 32-bits of MSR value.\r | |
3942 | Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.\r | |
3943 | \r | |
3944 | <b>Example usage</b>\r | |
3945 | @code\r | |
3946 | MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr;\r | |
3947 | \r | |
3948 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);\r | |
3949 | AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);\r | |
3950 | @endcode\r | |
3951 | **/\r | |
3952 | #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561\r | |
3953 | \r | |
3954 | /**\r | |
3955 | MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS\r | |
3956 | **/\r | |
3957 | typedef union {\r | |
3958 | ///\r | |
3959 | /// Individual bit fields\r | |
3960 | ///\r | |
3961 | struct {\r | |
3962 | UINT32 Reserved:7;\r | |
3963 | ///\r | |
3964 | /// [Bits 31:7] MaskOrTableOffset.\r | |
3965 | ///\r | |
3966 | UINT32 MaskOrTableOffset:25;\r | |
3967 | ///\r | |
3968 | /// [Bits 63:32] Output Offset.\r | |
3969 | ///\r | |
3970 | UINT32 OutputOffset:32;\r | |
3971 | } Bits;\r | |
3972 | ///\r | |
3973 | /// All bit fields as a 64-bit value\r | |
3974 | ///\r | |
3975 | UINT64 Uint64;\r | |
3976 | } MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;\r | |
3977 | \r | |
3978 | \r | |
3979 | /**\r | |
3980 | Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r | |
3981 | \r | |
3982 | @param ECX MSR_IA32_RTIT_CTL (0x00000570)\r | |
3983 | @param EAX Lower 32-bits of MSR value.\r | |
3984 | Described by the type MSR_IA32_RTIT_CTL_REGISTER.\r | |
3985 | @param EDX Upper 32-bits of MSR value.\r | |
3986 | Described by the type MSR_IA32_RTIT_CTL_REGISTER.\r | |
3987 | \r | |
3988 | <b>Example usage</b>\r | |
3989 | @code\r | |
3990 | MSR_IA32_RTIT_CTL_REGISTER Msr;\r | |
3991 | \r | |
3992 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r | |
3993 | AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);\r | |
3994 | @endcode\r | |
3995 | **/\r | |
3996 | #define MSR_IA32_RTIT_CTL 0x00000570\r | |
3997 | \r | |
3998 | /**\r | |
3999 | MSR information returned for MSR index #MSR_IA32_RTIT_CTL\r | |
4000 | **/\r | |
4001 | typedef union {\r | |
4002 | ///\r | |
4003 | /// Individual bit fields\r | |
4004 | ///\r | |
4005 | struct {\r | |
4006 | ///\r | |
4007 | /// [Bit 0] TraceEn.\r | |
4008 | ///\r | |
4009 | UINT32 TraceEn:1;\r | |
4010 | ///\r | |
4011 | /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r | |
4012 | ///\r | |
4013 | UINT32 CYCEn:1;\r | |
4014 | ///\r | |
4015 | /// [Bit 2] OS.\r | |
4016 | ///\r | |
4017 | UINT32 OS:1;\r | |
4018 | ///\r | |
4019 | /// [Bit 3] User.\r | |
4020 | ///\r | |
4021 | UINT32 User:1;\r | |
4022 | UINT32 Reserved1:2;\r | |
4023 | ///\r | |
4024 | /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).\r | |
4025 | ///\r | |
4026 | UINT32 FabricEn:1;\r | |
4027 | ///\r | |
4028 | /// [Bit 7] CR3 filter.\r | |
4029 | ///\r | |
4030 | UINT32 CR3:1;\r | |
4031 | ///\r | |
4032 | /// [Bit 8] ToPA.\r | |
4033 | ///\r | |
4034 | UINT32 ToPA:1;\r | |
4035 | ///\r | |
4036 | /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r | |
4037 | ///\r | |
4038 | UINT32 MTCEn:1;\r | |
4039 | ///\r | |
4040 | /// [Bit 10] TSCEn.\r | |
4041 | ///\r | |
4042 | UINT32 TSCEn:1;\r | |
4043 | ///\r | |
4044 | /// [Bit 11] DisRETC.\r | |
4045 | ///\r | |
4046 | UINT32 DisRETC:1;\r | |
4047 | UINT32 Reserved2:1;\r | |
4048 | ///\r | |
4049 | /// [Bit 13] BranchEn.\r | |
4050 | ///\r | |
4051 | UINT32 BranchEn:1;\r | |
4052 | ///\r | |
4053 | /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r | |
4054 | ///\r | |
4055 | UINT32 MTCFreq:4;\r | |
4056 | UINT32 Reserved3:1;\r | |
4057 | ///\r | |
4058 | /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r | |
4059 | ///\r | |
4060 | UINT32 CYCThresh:4;\r | |
4061 | UINT32 Reserved4:1;\r | |
4062 | ///\r | |
4063 | /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r | |
4064 | ///\r | |
4065 | UINT32 PSBFreq:4;\r | |
4066 | UINT32 Reserved5:4;\r | |
4067 | ///\r | |
4068 | /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).\r | |
4069 | ///\r | |
4070 | UINT32 ADDR0_CFG:4;\r | |
4071 | ///\r | |
4072 | /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).\r | |
4073 | ///\r | |
4074 | UINT32 ADDR1_CFG:4;\r | |
4075 | ///\r | |
4076 | /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).\r | |
4077 | ///\r | |
4078 | UINT32 ADDR2_CFG:4;\r | |
4079 | ///\r | |
4080 | /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).\r | |
4081 | ///\r | |
4082 | UINT32 ADDR3_CFG:4;\r | |
4083 | UINT32 Reserved6:16;\r | |
4084 | } Bits;\r | |
4085 | ///\r | |
4086 | /// All bit fields as a 64-bit value\r | |
4087 | ///\r | |
4088 | UINT64 Uint64;\r | |
4089 | } MSR_IA32_RTIT_CTL_REGISTER;\r | |
4090 | \r | |
4091 | \r | |
4092 | /**\r | |
4093 | Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r | |
4094 | \r | |
4095 | @param ECX MSR_IA32_RTIT_STATUS (0x00000571)\r | |
4096 | @param EAX Lower 32-bits of MSR value.\r | |
4097 | Described by the type MSR_IA32_RTIT_STATUS_REGISTER.\r | |
4098 | @param EDX Upper 32-bits of MSR value.\r | |
4099 | Described by the type MSR_IA32_RTIT_STATUS_REGISTER.\r | |
4100 | \r | |
4101 | <b>Example usage</b>\r | |
4102 | @code\r | |
4103 | MSR_IA32_RTIT_STATUS_REGISTER Msr;\r | |
4104 | \r | |
4105 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);\r | |
4106 | AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);\r | |
4107 | @endcode\r | |
4108 | **/\r | |
4109 | #define MSR_IA32_RTIT_STATUS 0x00000571\r | |
4110 | \r | |
4111 | /**\r | |
4112 | MSR information returned for MSR index #MSR_IA32_RTIT_STATUS\r | |
4113 | **/\r | |
4114 | typedef union {\r | |
4115 | ///\r | |
4116 | /// Individual bit fields\r | |
4117 | ///\r | |
4118 | struct {\r | |
4119 | ///\r | |
4120 | /// [Bit 0] FilterEn, (writes ignored).\r | |
4121 | /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).\r | |
4122 | ///\r | |
4123 | UINT32 FilterEn:1;\r | |
4124 | ///\r | |
4125 | /// [Bit 1] ContexEn, (writes ignored).\r | |
4126 | ///\r | |
4127 | UINT32 ContexEn:1;\r | |
4128 | ///\r | |
4129 | /// [Bit 2] TriggerEn, (writes ignored).\r | |
4130 | ///\r | |
4131 | UINT32 TriggerEn:1;\r | |
4132 | UINT32 Reserved1:1;\r | |
4133 | ///\r | |
4134 | /// [Bit 4] Error.\r | |
4135 | ///\r | |
4136 | UINT32 Error:1;\r | |
4137 | ///\r | |
4138 | /// [Bit 5] Stopped.\r | |
4139 | ///\r | |
4140 | UINT32 Stopped:1;\r | |
4141 | UINT32 Reserved2:26;\r | |
4142 | ///\r | |
4143 | /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).\r | |
4144 | ///\r | |
4145 | UINT32 PacketByteCnt:17;\r | |
4146 | UINT32 Reserved3:15;\r | |
4147 | } Bits;\r | |
4148 | ///\r | |
4149 | /// All bit fields as a 64-bit value\r | |
4150 | ///\r | |
4151 | UINT64 Uint64;\r | |
4152 | } MSR_IA32_RTIT_STATUS_REGISTER;\r | |
4153 | \r | |
4154 | \r | |
4155 | /**\r | |
4156 | Trace Filter CR3 Match Register (R/W).\r | |
4157 | If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r | |
4158 | \r | |
4159 | @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572)\r | |
4160 | @param EAX Lower 32-bits of MSR value.\r | |
4161 | Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.\r | |
4162 | @param EDX Upper 32-bits of MSR value.\r | |
4163 | Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.\r | |
4164 | \r | |
4165 | <b>Example usage</b>\r | |
4166 | @code\r | |
4167 | MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr;\r | |
4168 | \r | |
4169 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);\r | |
4170 | AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);\r | |
4171 | @endcode\r | |
4172 | **/\r | |
4173 | #define MSR_IA32_RTIT_CR3_MATCH 0x00000572\r | |
4174 | \r | |
4175 | /**\r | |
4176 | MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH\r | |
4177 | **/\r | |
4178 | typedef union {\r | |
4179 | ///\r | |
4180 | /// Individual bit fields\r | |
4181 | ///\r | |
4182 | struct {\r | |
4183 | UINT32 Reserved:5;\r | |
4184 | ///\r | |
4185 | /// [Bits 31:5] CR3[63:5] value to match.\r | |
4186 | ///\r | |
4187 | UINT32 Cr3:27;\r | |
4188 | ///\r | |
4189 | /// [Bits 63:32] CR3[63:5] value to match.\r | |
4190 | ///\r | |
4191 | UINT32 Cr3Hi:32;\r | |
4192 | } Bits;\r | |
4193 | ///\r | |
4194 | /// All bit fields as a 64-bit value\r | |
4195 | ///\r | |
4196 | UINT64 Uint64;\r | |
4197 | } MSR_IA32_RTIT_CR3_MATCH_REGISTER;\r | |
4198 | \r | |
4199 | \r | |
4200 | /**\r | |
4201 | Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r | |
4202 | \r | |
4203 | @param ECX MSR_IA32_RTIT_ADDRn_A\r | |
4204 | @param EAX Lower 32-bits of MSR value.\r | |
4205 | Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r | |
4206 | @param EDX Upper 32-bits of MSR value.\r | |
4207 | Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r | |
4208 | \r | |
4209 | <b>Example usage</b>\r | |
4210 | @code\r | |
4211 | MSR_IA32_RTIT_ADDR_REGISTER Msr;\r | |
4212 | \r | |
4213 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);\r | |
4214 | AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);\r | |
4215 | @endcode\r | |
4216 | @{\r | |
4217 | **/\r | |
4218 | #define MSR_IA32_RTIT_ADDR0_A 0x00000580\r | |
4219 | #define MSR_IA32_RTIT_ADDR1_A 0x00000582\r | |
4220 | #define MSR_IA32_RTIT_ADDR2_A 0x00000584\r | |
4221 | #define MSR_IA32_RTIT_ADDR3_A 0x00000586\r | |
4222 | /// @}\r | |
4223 | \r | |
4224 | \r | |
4225 | /**\r | |
4226 | Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r | |
4227 | \r | |
4228 | @param ECX MSR_IA32_RTIT_ADDRn_B\r | |
4229 | @param EAX Lower 32-bits of MSR value.\r | |
4230 | Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r | |
4231 | @param EDX Upper 32-bits of MSR value.\r | |
4232 | Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r | |
4233 | \r | |
4234 | <b>Example usage</b>\r | |
4235 | @code\r | |
4236 | MSR_IA32_RTIT_ADDR_REGISTER Msr;\r | |
4237 | \r | |
4238 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);\r | |
4239 | AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);\r | |
4240 | @endcode\r | |
4241 | @{\r | |
4242 | **/\r | |
4243 | #define MSR_IA32_RTIT_ADDR0_B 0x00000581\r | |
4244 | #define MSR_IA32_RTIT_ADDR1_B 0x00000583\r | |
4245 | #define MSR_IA32_RTIT_ADDR2_B 0x00000585\r | |
4246 | #define MSR_IA32_RTIT_ADDR3_B 0x00000587\r | |
4247 | /// @}\r | |
4248 | \r | |
4249 | \r | |
4250 | /**\r | |
4251 | MSR information returned for MSR indexes\r | |
4252 | #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and\r | |
4253 | #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B\r | |
4254 | **/\r | |
4255 | typedef union {\r | |
4256 | ///\r | |
4257 | /// Individual bit fields\r | |
4258 | ///\r | |
4259 | struct {\r | |
4260 | ///\r | |
4261 | /// [Bits 31:0] Virtual Address.\r | |
4262 | ///\r | |
4263 | UINT32 VirtualAddress:32;\r | |
4264 | ///\r | |
4265 | /// [Bits 47:32] Virtual Address.\r | |
4266 | ///\r | |
4267 | UINT32 VirtualAddressHi:16;\r | |
4268 | ///\r | |
4269 | /// [Bits 63:48] SignExt_VA.\r | |
4270 | ///\r | |
4271 | UINT32 SignExt_VA:16;\r | |
4272 | } Bits;\r | |
4273 | ///\r | |
4274 | /// All bit fields as a 64-bit value\r | |
4275 | ///\r | |
4276 | UINT64 Uint64;\r | |
4277 | } MSR_IA32_RTIT_ADDR_REGISTER;\r | |
4278 | \r | |
4279 | \r | |
4280 | /**\r | |
4281 | DS Save Area (R/W) Points to the linear address of the first byte of the DS\r | |
4282 | buffer management area, which is used to manage the BTS and PEBS buffers.\r | |
4283 | See Section 18.12.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]\r | |
4284 | = 1.\r | |
4285 | \r | |
4286 | [Bits 31..0] The linear address of the first byte of the DS buffer\r | |
4287 | management area, if not in IA-32e mode.\r | |
4288 | \r | |
4289 | [Bits 63..0] The linear address of the first byte of the DS buffer\r | |
4290 | management area, if IA-32e mode is active.\r | |
4291 | \r | |
4292 | @param ECX MSR_IA32_DS_AREA (0x00000600)\r | |
4293 | @param EAX Lower 32-bits of MSR value.\r | |
4294 | Described by the type MSR_IA32_DS_AREA_REGISTER.\r | |
4295 | @param EDX Upper 32-bits of MSR value.\r | |
4296 | Described by the type MSR_IA32_DS_AREA_REGISTER.\r | |
4297 | \r | |
4298 | <b>Example usage</b>\r | |
4299 | @code\r | |
4300 | UINT64 Msr;\r | |
4301 | \r | |
4302 | Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);\r | |
4303 | AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);\r | |
4304 | @endcode\r | |
4305 | **/\r | |
4306 | #define MSR_IA32_DS_AREA 0x00000600\r | |
4307 | \r | |
4308 | \r | |
4309 | /**\r | |
4310 | TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =\r | |
4311 | 1.\r | |
4312 | \r | |
4313 | @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0)\r | |
4314 | @param EAX Lower 32-bits of MSR value.\r | |
4315 | @param EDX Upper 32-bits of MSR value.\r | |
4316 | \r | |
4317 | <b>Example usage</b>\r | |
4318 | @code\r | |
4319 | UINT64 Msr;\r | |
4320 | \r | |
4321 | Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);\r | |
4322 | AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);\r | |
4323 | @endcode\r | |
4324 | **/\r | |
4325 | #define MSR_IA32_TSC_DEADLINE 0x000006E0\r | |
4326 | \r | |
4327 | \r | |
4328 | /**\r | |
4329 | Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.\r | |
4330 | \r | |
4331 | @param ECX MSR_IA32_PM_ENABLE (0x00000770)\r | |
4332 | @param EAX Lower 32-bits of MSR value.\r | |
4333 | Described by the type MSR_IA32_PM_ENABLE_REGISTER.\r | |
4334 | @param EDX Upper 32-bits of MSR value.\r | |
4335 | Described by the type MSR_IA32_PM_ENABLE_REGISTER.\r | |
4336 | \r | |
4337 | <b>Example usage</b>\r | |
4338 | @code\r | |
4339 | MSR_IA32_PM_ENABLE_REGISTER Msr;\r | |
4340 | \r | |
4341 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);\r | |
4342 | AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);\r | |
4343 | @endcode\r | |
4344 | **/\r | |
4345 | #define MSR_IA32_PM_ENABLE 0x00000770\r | |
4346 | \r | |
4347 | /**\r | |
4348 | MSR information returned for MSR index #MSR_IA32_PM_ENABLE\r | |
4349 | **/\r | |
4350 | typedef union {\r | |
4351 | ///\r | |
4352 | /// Individual bit fields\r | |
4353 | ///\r | |
4354 | struct {\r | |
4355 | ///\r | |
4356 | /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If\r | |
4357 | /// CPUID.06H:EAX.[7] = 1.\r | |
4358 | ///\r | |
4359 | UINT32 HWP_ENABLE:1;\r | |
4360 | UINT32 Reserved1:31;\r | |
4361 | UINT32 Reserved2:32;\r | |
4362 | } Bits;\r | |
4363 | ///\r | |
4364 | /// All bit fields as a 32-bit value\r | |
4365 | ///\r | |
4366 | UINT32 Uint32;\r | |
4367 | ///\r | |
4368 | /// All bit fields as a 64-bit value\r | |
4369 | ///\r | |
4370 | UINT64 Uint64;\r | |
4371 | } MSR_IA32_PM_ENABLE_REGISTER;\r | |
4372 | \r | |
4373 | \r | |
4374 | /**\r | |
4375 | HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.\r | |
4376 | \r | |
4377 | @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771)\r | |
4378 | @param EAX Lower 32-bits of MSR value.\r | |
4379 | Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.\r | |
4380 | @param EDX Upper 32-bits of MSR value.\r | |
4381 | Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.\r | |
4382 | \r | |
4383 | <b>Example usage</b>\r | |
4384 | @code\r | |
4385 | MSR_IA32_HWP_CAPABILITIES_REGISTER Msr;\r | |
4386 | \r | |
4387 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);\r | |
4388 | @endcode\r | |
4389 | **/\r | |
4390 | #define MSR_IA32_HWP_CAPABILITIES 0x00000771\r | |
4391 | \r | |
4392 | /**\r | |
4393 | MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES\r | |
4394 | **/\r | |
4395 | typedef union {\r | |
4396 | ///\r | |
4397 | /// Individual bit fields\r | |
4398 | ///\r | |
4399 | struct {\r | |
4400 | ///\r | |
4401 | /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance\r | |
4402 | /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r | |
4403 | ///\r | |
4404 | UINT32 Highest_Performance:8;\r | |
4405 | ///\r | |
4406 | /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP\r | |
4407 | /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r | |
4408 | ///\r | |
4409 | UINT32 Guaranteed_Performance:8;\r | |
4410 | ///\r | |
4411 | /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP\r | |
4412 | /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r | |
4413 | ///\r | |
4414 | UINT32 Most_Efficient_Performance:8;\r | |
4415 | ///\r | |
4416 | /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance\r | |
4417 | /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r | |
4418 | ///\r | |
4419 | UINT32 Lowest_Performance:8;\r | |
4420 | UINT32 Reserved:32;\r | |
4421 | } Bits;\r | |
4422 | ///\r | |
4423 | /// All bit fields as a 32-bit value\r | |
4424 | ///\r | |
4425 | UINT32 Uint32;\r | |
4426 | ///\r | |
4427 | /// All bit fields as a 64-bit value\r | |
4428 | ///\r | |
4429 | UINT64 Uint64;\r | |
4430 | } MSR_IA32_HWP_CAPABILITIES_REGISTER;\r | |
4431 | \r | |
4432 | \r | |
4433 | /**\r | |
4434 | Power Management Control Hints for All Logical Processors in a Package\r | |
4435 | (R/W). If CPUID.06H:EAX.[11] = 1.\r | |
4436 | \r | |
4437 | @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772)\r | |
4438 | @param EAX Lower 32-bits of MSR value.\r | |
4439 | Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.\r | |
4440 | @param EDX Upper 32-bits of MSR value.\r | |
4441 | Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.\r | |
4442 | \r | |
4443 | <b>Example usage</b>\r | |
4444 | @code\r | |
4445 | MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr;\r | |
4446 | \r | |
4447 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);\r | |
4448 | AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);\r | |
4449 | @endcode\r | |
4450 | **/\r | |
4451 | #define MSR_IA32_HWP_REQUEST_PKG 0x00000772\r | |
4452 | \r | |
4453 | /**\r | |
4454 | MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG\r | |
4455 | **/\r | |
4456 | typedef union {\r | |
4457 | ///\r | |
4458 | /// Individual bit fields\r | |
4459 | ///\r | |
4460 | struct {\r | |
4461 | ///\r | |
4462 | /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r | |
4463 | /// CPUID.06H:EAX.[11] = 1.\r | |
4464 | ///\r | |
4465 | UINT32 Minimum_Performance:8;\r | |
4466 | ///\r | |
4467 | /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r | |
4468 | /// CPUID.06H:EAX.[11] = 1.\r | |
4469 | ///\r | |
4470 | UINT32 Maximum_Performance:8;\r | |
4471 | ///\r | |
4472 | /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r | |
4473 | /// If CPUID.06H:EAX.[11] = 1.\r | |
4474 | ///\r | |
4475 | UINT32 Desired_Performance:8;\r | |
4476 | ///\r | |
4477 | /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r | |
4478 | /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.\r | |
4479 | ///\r | |
4480 | UINT32 Energy_Performance_Preference:8;\r | |
4481 | ///\r | |
4482 | /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r | |
4483 | /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.\r | |
4484 | ///\r | |
4485 | UINT32 Activity_Window:10;\r | |
4486 | UINT32 Reserved:22;\r | |
4487 | } Bits;\r | |
4488 | ///\r | |
4489 | /// All bit fields as a 64-bit value\r | |
4490 | ///\r | |
4491 | UINT64 Uint64;\r | |
4492 | } MSR_IA32_HWP_REQUEST_PKG_REGISTER;\r | |
4493 | \r | |
4494 | \r | |
4495 | /**\r | |
4496 | Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.\r | |
4497 | \r | |
4498 | @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773)\r | |
4499 | @param EAX Lower 32-bits of MSR value.\r | |
4500 | Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.\r | |
4501 | @param EDX Upper 32-bits of MSR value.\r | |
4502 | Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.\r | |
4503 | \r | |
4504 | <b>Example usage</b>\r | |
4505 | @code\r | |
4506 | MSR_IA32_HWP_INTERRUPT_REGISTER Msr;\r | |
4507 | \r | |
4508 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);\r | |
4509 | AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);\r | |
4510 | @endcode\r | |
4511 | **/\r | |
4512 | #define MSR_IA32_HWP_INTERRUPT 0x00000773\r | |
4513 | \r | |
4514 | /**\r | |
4515 | MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT\r | |
4516 | **/\r | |
4517 | typedef union {\r | |
4518 | ///\r | |
4519 | /// Individual bit fields\r | |
4520 | ///\r | |
4521 | struct {\r | |
4522 | ///\r | |
4523 | /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP\r | |
4524 | /// Notifications". If CPUID.06H:EAX.[8] = 1.\r | |
4525 | ///\r | |
4526 | UINT32 EN_Guaranteed_Performance_Change:1;\r | |
4527 | ///\r | |
4528 | /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".\r | |
4529 | /// If CPUID.06H:EAX.[8] = 1.\r | |
4530 | ///\r | |
4531 | UINT32 EN_Excursion_Minimum:1;\r | |
4532 | UINT32 Reserved1:30;\r | |
4533 | UINT32 Reserved2:32;\r | |
4534 | } Bits;\r | |
4535 | ///\r | |
4536 | /// All bit fields as a 32-bit value\r | |
4537 | ///\r | |
4538 | UINT32 Uint32;\r | |
4539 | ///\r | |
4540 | /// All bit fields as a 64-bit value\r | |
4541 | ///\r | |
4542 | UINT64 Uint64;\r | |
4543 | } MSR_IA32_HWP_INTERRUPT_REGISTER;\r | |
4544 | \r | |
4545 | \r | |
4546 | /**\r | |
4547 | Power Management Control Hints to a Logical Processor (R/W). If\r | |
4548 | CPUID.06H:EAX.[7] = 1.\r | |
4549 | \r | |
4550 | @param ECX MSR_IA32_HWP_REQUEST (0x00000774)\r | |
4551 | @param EAX Lower 32-bits of MSR value.\r | |
4552 | Described by the type MSR_IA32_HWP_REQUEST_REGISTER.\r | |
4553 | @param EDX Upper 32-bits of MSR value.\r | |
4554 | Described by the type MSR_IA32_HWP_REQUEST_REGISTER.\r | |
4555 | \r | |
4556 | <b>Example usage</b>\r | |
4557 | @code\r | |
4558 | MSR_IA32_HWP_REQUEST_REGISTER Msr;\r | |
4559 | \r | |
4560 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);\r | |
4561 | AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);\r | |
4562 | @endcode\r | |
4563 | **/\r | |
4564 | #define MSR_IA32_HWP_REQUEST 0x00000774\r | |
4565 | \r | |
4566 | /**\r | |
4567 | MSR information returned for MSR index #MSR_IA32_HWP_REQUEST\r | |
4568 | **/\r | |
4569 | typedef union {\r | |
4570 | ///\r | |
4571 | /// Individual bit fields\r | |
4572 | ///\r | |
4573 | struct {\r | |
4574 | ///\r | |
4575 | /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r | |
4576 | /// CPUID.06H:EAX.[7] = 1.\r | |
4577 | ///\r | |
4578 | UINT32 Minimum_Performance:8;\r | |
4579 | ///\r | |
4580 | /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r | |
4581 | /// CPUID.06H:EAX.[7] = 1.\r | |
4582 | ///\r | |
4583 | UINT32 Maximum_Performance:8;\r | |
4584 | ///\r | |
4585 | /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r | |
4586 | /// If CPUID.06H:EAX.[7] = 1.\r | |
4587 | ///\r | |
4588 | UINT32 Desired_Performance:8;\r | |
4589 | ///\r | |
4590 | /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r | |
4591 | /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.\r | |
4592 | ///\r | |
4593 | UINT32 Energy_Performance_Preference:8;\r | |
4594 | ///\r | |
4595 | /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r | |
4596 | /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.\r | |
4597 | ///\r | |
4598 | UINT32 Activity_Window:10;\r | |
4599 | ///\r | |
4600 | /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If\r | |
4601 | /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.\r | |
4602 | ///\r | |
4603 | UINT32 Package_Control:1;\r | |
4604 | UINT32 Reserved:21;\r | |
4605 | } Bits;\r | |
4606 | ///\r | |
4607 | /// All bit fields as a 64-bit value\r | |
4608 | ///\r | |
4609 | UINT64 Uint64;\r | |
4610 | } MSR_IA32_HWP_REQUEST_REGISTER;\r | |
4611 | \r | |
4612 | \r | |
4613 | /**\r | |
4614 | Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If\r | |
4615 | CPUID.06H:EAX.[7] = 1.\r | |
4616 | \r | |
4617 | @param ECX MSR_IA32_HWP_STATUS (0x00000777)\r | |
4618 | @param EAX Lower 32-bits of MSR value.\r | |
4619 | Described by the type MSR_IA32_HWP_STATUS_REGISTER.\r | |
4620 | @param EDX Upper 32-bits of MSR value.\r | |
4621 | Described by the type MSR_IA32_HWP_STATUS_REGISTER.\r | |
4622 | \r | |
4623 | <b>Example usage</b>\r | |
4624 | @code\r | |
4625 | MSR_IA32_HWP_STATUS_REGISTER Msr;\r | |
4626 | \r | |
4627 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);\r | |
4628 | AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);\r | |
4629 | @endcode\r | |
4630 | **/\r | |
4631 | #define MSR_IA32_HWP_STATUS 0x00000777\r | |
4632 | \r | |
4633 | /**\r | |
4634 | MSR information returned for MSR index #MSR_IA32_HWP_STATUS\r | |
4635 | **/\r | |
4636 | typedef union {\r | |
4637 | ///\r | |
4638 | /// Individual bit fields\r | |
4639 | ///\r | |
4640 | struct {\r | |
4641 | ///\r | |
4642 | /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,\r | |
4643 | /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.\r | |
4644 | ///\r | |
4645 | UINT32 Guaranteed_Performance_Change:1;\r | |
4646 | UINT32 Reserved1:1;\r | |
4647 | ///\r | |
4648 | /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP\r | |
4649 | /// Feedback". If CPUID.06H:EAX.[7] = 1.\r | |
4650 | ///\r | |
4651 | UINT32 Excursion_To_Minimum:1;\r | |
4652 | UINT32 Reserved2:29;\r | |
4653 | UINT32 Reserved3:32;\r | |
4654 | } Bits;\r | |
4655 | ///\r | |
4656 | /// All bit fields as a 32-bit value\r | |
4657 | ///\r | |
4658 | UINT32 Uint32;\r | |
4659 | ///\r | |
4660 | /// All bit fields as a 64-bit value\r | |
4661 | ///\r | |
4662 | UINT64 Uint64;\r | |
4663 | } MSR_IA32_HWP_STATUS_REGISTER;\r | |
4664 | \r | |
4665 | \r | |
4666 | /**\r | |
4667 | x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1\r | |
4668 | && IA32_APIC_BASE.[10] = 1.\r | |
4669 | \r | |
4670 | @param ECX MSR_IA32_X2APIC_APICID (0x00000802)\r | |
4671 | @param EAX Lower 32-bits of MSR value.\r | |
4672 | @param EDX Upper 32-bits of MSR value.\r | |
4673 | \r | |
4674 | <b>Example usage</b>\r | |
4675 | @code\r | |
4676 | UINT64 Msr;\r | |
4677 | \r | |
4678 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);\r | |
4679 | @endcode\r | |
4680 | **/\r | |
4681 | #define MSR_IA32_X2APIC_APICID 0x00000802\r | |
4682 | \r | |
4683 | \r | |
4684 | /**\r | |
4685 | x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
4686 | IA32_APIC_BASE.[10] = 1.\r | |
4687 | \r | |
4688 | @param ECX MSR_IA32_X2APIC_VERSION (0x00000803)\r | |
4689 | @param EAX Lower 32-bits of MSR value.\r | |
4690 | @param EDX Upper 32-bits of MSR value.\r | |
4691 | \r | |
4692 | <b>Example usage</b>\r | |
4693 | @code\r | |
4694 | UINT64 Msr;\r | |
4695 | \r | |
4696 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);\r | |
4697 | @endcode\r | |
4698 | **/\r | |
4699 | #define MSR_IA32_X2APIC_VERSION 0x00000803\r | |
4700 | \r | |
4701 | \r | |
4702 | /**\r | |
4703 | x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
4704 | IA32_APIC_BASE.[10] = 1.\r | |
4705 | \r | |
4706 | @param ECX MSR_IA32_X2APIC_TPR (0x00000808)\r | |
4707 | @param EAX Lower 32-bits of MSR value.\r | |
4708 | @param EDX Upper 32-bits of MSR value.\r | |
4709 | \r | |
4710 | <b>Example usage</b>\r | |
4711 | @code\r | |
4712 | UINT64 Msr;\r | |
4713 | \r | |
4714 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);\r | |
4715 | AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);\r | |
4716 | @endcode\r | |
4717 | **/\r | |
4718 | #define MSR_IA32_X2APIC_TPR 0x00000808\r | |
4719 | \r | |
4720 | \r | |
4721 | /**\r | |
4722 | x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
4723 | IA32_APIC_BASE.[10] = 1.\r | |
4724 | \r | |
4725 | @param ECX MSR_IA32_X2APIC_PPR (0x0000080A)\r | |
4726 | @param EAX Lower 32-bits of MSR value.\r | |
4727 | @param EDX Upper 32-bits of MSR value.\r | |
4728 | \r | |
4729 | <b>Example usage</b>\r | |
4730 | @code\r | |
4731 | UINT64 Msr;\r | |
4732 | \r | |
4733 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);\r | |
4734 | @endcode\r | |
4735 | **/\r | |
4736 | #define MSR_IA32_X2APIC_PPR 0x0000080A\r | |
4737 | \r | |
4738 | \r | |
4739 | /**\r | |
4740 | x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]\r | |
4741 | = 1.\r | |
4742 | \r | |
4743 | @param ECX MSR_IA32_X2APIC_EOI (0x0000080B)\r | |
4744 | @param EAX Lower 32-bits of MSR value.\r | |
4745 | @param EDX Upper 32-bits of MSR value.\r | |
4746 | \r | |
4747 | <b>Example usage</b>\r | |
4748 | @code\r | |
4749 | UINT64 Msr;\r | |
4750 | \r | |
4751 | Msr = 0;\r | |
4752 | AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);\r | |
4753 | @endcode\r | |
4754 | **/\r | |
4755 | #define MSR_IA32_X2APIC_EOI 0x0000080B\r | |
4756 | \r | |
4757 | \r | |
4758 | /**\r | |
4759 | x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
4760 | IA32_APIC_BASE.[10] = 1.\r | |
4761 | \r | |
4762 | @param ECX MSR_IA32_X2APIC_LDR (0x0000080D)\r | |
4763 | @param EAX Lower 32-bits of MSR value.\r | |
4764 | @param EDX Upper 32-bits of MSR value.\r | |
4765 | \r | |
4766 | <b>Example usage</b>\r | |
4767 | @code\r | |
4768 | UINT64 Msr;\r | |
4769 | \r | |
4770 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);\r | |
4771 | @endcode\r | |
4772 | **/\r | |
4773 | #define MSR_IA32_X2APIC_LDR 0x0000080D\r | |
4774 | \r | |
4775 | \r | |
4776 | /**\r | |
4777 | x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1\r | |
4778 | && IA32_APIC_BASE.[10] = 1.\r | |
4779 | \r | |
4780 | @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F)\r | |
4781 | @param EAX Lower 32-bits of MSR value.\r | |
4782 | @param EDX Upper 32-bits of MSR value.\r | |
4783 | \r | |
4784 | <b>Example usage</b>\r | |
4785 | @code\r | |
4786 | UINT64 Msr;\r | |
4787 | \r | |
4788 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);\r | |
4789 | AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);\r | |
4790 | @endcode\r | |
4791 | **/\r | |
4792 | #define MSR_IA32_X2APIC_SIVR 0x0000080F\r | |
4793 | \r | |
4794 | \r | |
4795 | /**\r | |
4796 | x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).\r | |
4797 | If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
4798 | \r | |
4799 | @param ECX MSR_IA32_X2APIC_ISRn\r | |
4800 | @param EAX Lower 32-bits of MSR value.\r | |
4801 | @param EDX Upper 32-bits of MSR value.\r | |
4802 | \r | |
4803 | <b>Example usage</b>\r | |
4804 | @code\r | |
4805 | UINT64 Msr;\r | |
4806 | \r | |
4807 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);\r | |
4808 | @endcode\r | |
4809 | @{\r | |
4810 | **/\r | |
4811 | #define MSR_IA32_X2APIC_ISR0 0x00000810\r | |
4812 | #define MSR_IA32_X2APIC_ISR1 0x00000811\r | |
4813 | #define MSR_IA32_X2APIC_ISR2 0x00000812\r | |
4814 | #define MSR_IA32_X2APIC_ISR3 0x00000813\r | |
4815 | #define MSR_IA32_X2APIC_ISR4 0x00000814\r | |
4816 | #define MSR_IA32_X2APIC_ISR5 0x00000815\r | |
4817 | #define MSR_IA32_X2APIC_ISR6 0x00000816\r | |
4818 | #define MSR_IA32_X2APIC_ISR7 0x00000817\r | |
4819 | /// @}\r | |
4820 | \r | |
4821 | \r | |
4822 | /**\r | |
4823 | x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).\r | |
4824 | If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
4825 | \r | |
4826 | @param ECX MSR_IA32_X2APIC_TMRn\r | |
4827 | @param EAX Lower 32-bits of MSR value.\r | |
4828 | @param EDX Upper 32-bits of MSR value.\r | |
4829 | \r | |
4830 | <b>Example usage</b>\r | |
4831 | @code\r | |
4832 | UINT64 Msr;\r | |
4833 | \r | |
4834 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);\r | |
4835 | @endcode\r | |
4836 | @{\r | |
4837 | **/\r | |
4838 | #define MSR_IA32_X2APIC_TMR0 0x00000818\r | |
4839 | #define MSR_IA32_X2APIC_TMR1 0x00000819\r | |
4840 | #define MSR_IA32_X2APIC_TMR2 0x0000081A\r | |
4841 | #define MSR_IA32_X2APIC_TMR3 0x0000081B\r | |
4842 | #define MSR_IA32_X2APIC_TMR4 0x0000081C\r | |
4843 | #define MSR_IA32_X2APIC_TMR5 0x0000081D\r | |
4844 | #define MSR_IA32_X2APIC_TMR6 0x0000081E\r | |
4845 | #define MSR_IA32_X2APIC_TMR7 0x0000081F\r | |
4846 | /// @}\r | |
4847 | \r | |
4848 | \r | |
4849 | /**\r | |
4850 | x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).\r | |
4851 | If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
4852 | \r | |
4853 | @param ECX MSR_IA32_X2APIC_IRRn\r | |
4854 | @param EAX Lower 32-bits of MSR value.\r | |
4855 | @param EDX Upper 32-bits of MSR value.\r | |
4856 | \r | |
4857 | <b>Example usage</b>\r | |
4858 | @code\r | |
4859 | UINT64 Msr;\r | |
4860 | \r | |
4861 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);\r | |
4862 | @endcode\r | |
4863 | @{\r | |
4864 | **/\r | |
4865 | #define MSR_IA32_X2APIC_IRR0 0x00000820\r | |
4866 | #define MSR_IA32_X2APIC_IRR1 0x00000821\r | |
4867 | #define MSR_IA32_X2APIC_IRR2 0x00000822\r | |
4868 | #define MSR_IA32_X2APIC_IRR3 0x00000823\r | |
4869 | #define MSR_IA32_X2APIC_IRR4 0x00000824\r | |
4870 | #define MSR_IA32_X2APIC_IRR5 0x00000825\r | |
4871 | #define MSR_IA32_X2APIC_IRR6 0x00000826\r | |
4872 | #define MSR_IA32_X2APIC_IRR7 0x00000827\r | |
4873 | /// @}\r | |
4874 | \r | |
4875 | \r | |
4876 | /**\r | |
4877 | x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
4878 | IA32_APIC_BASE.[10] = 1.\r | |
4879 | \r | |
4880 | @param ECX MSR_IA32_X2APIC_ESR (0x00000828)\r | |
4881 | @param EAX Lower 32-bits of MSR value.\r | |
4882 | @param EDX Upper 32-bits of MSR value.\r | |
4883 | \r | |
4884 | <b>Example usage</b>\r | |
4885 | @code\r | |
4886 | UINT64 Msr;\r | |
4887 | \r | |
4888 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);\r | |
4889 | AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);\r | |
4890 | @endcode\r | |
4891 | **/\r | |
4892 | #define MSR_IA32_X2APIC_ESR 0x00000828\r | |
4893 | \r | |
4894 | \r | |
4895 | /**\r | |
4896 | x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If\r | |
4897 | CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
4898 | \r | |
4899 | @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)\r | |
4900 | @param EAX Lower 32-bits of MSR value.\r | |
4901 | @param EDX Upper 32-bits of MSR value.\r | |
4902 | \r | |
4903 | <b>Example usage</b>\r | |
4904 | @code\r | |
4905 | UINT64 Msr;\r | |
4906 | \r | |
4907 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);\r | |
4908 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);\r | |
4909 | @endcode\r | |
4910 | **/\r | |
4911 | #define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F\r | |
4912 | \r | |
4913 | \r | |
4914 | /**\r | |
4915 | x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
4916 | IA32_APIC_BASE.[10] = 1.\r | |
4917 | \r | |
4918 | @param ECX MSR_IA32_X2APIC_ICR (0x00000830)\r | |
4919 | @param EAX Lower 32-bits of MSR value.\r | |
4920 | @param EDX Upper 32-bits of MSR value.\r | |
4921 | \r | |
4922 | <b>Example usage</b>\r | |
4923 | @code\r | |
4924 | UINT64 Msr;\r | |
4925 | \r | |
4926 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);\r | |
4927 | AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);\r | |
4928 | @endcode\r | |
4929 | **/\r | |
4930 | #define MSR_IA32_X2APIC_ICR 0x00000830\r | |
4931 | \r | |
4932 | \r | |
4933 | /**\r | |
4934 | x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
4935 | IA32_APIC_BASE.[10] = 1.\r | |
4936 | \r | |
4937 | @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832)\r | |
4938 | @param EAX Lower 32-bits of MSR value.\r | |
4939 | @param EDX Upper 32-bits of MSR value.\r | |
4940 | \r | |
4941 | <b>Example usage</b>\r | |
4942 | @code\r | |
4943 | UINT64 Msr;\r | |
4944 | \r | |
4945 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);\r | |
4946 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);\r | |
4947 | @endcode\r | |
4948 | **/\r | |
4949 | #define MSR_IA32_X2APIC_LVT_TIMER 0x00000832\r | |
4950 | \r | |
4951 | \r | |
4952 | /**\r | |
4953 | x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =\r | |
4954 | 1 && IA32_APIC_BASE.[10] = 1.\r | |
4955 | \r | |
4956 | @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)\r | |
4957 | @param EAX Lower 32-bits of MSR value.\r | |
4958 | @param EDX Upper 32-bits of MSR value.\r | |
4959 | \r | |
4960 | <b>Example usage</b>\r | |
4961 | @code\r | |
4962 | UINT64 Msr;\r | |
4963 | \r | |
4964 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);\r | |
4965 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);\r | |
4966 | @endcode\r | |
4967 | **/\r | |
4968 | #define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833\r | |
4969 | \r | |
4970 | \r | |
4971 | /**\r | |
4972 | x2APIC LVT Performance Monitor Interrupt Register (R/W). If\r | |
4973 | CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
4974 | \r | |
4975 | @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834)\r | |
4976 | @param EAX Lower 32-bits of MSR value.\r | |
4977 | @param EDX Upper 32-bits of MSR value.\r | |
4978 | \r | |
4979 | <b>Example usage</b>\r | |
4980 | @code\r | |
4981 | UINT64 Msr;\r | |
4982 | \r | |
4983 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);\r | |
4984 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);\r | |
4985 | @endcode\r | |
4986 | **/\r | |
4987 | #define MSR_IA32_X2APIC_LVT_PMI 0x00000834\r | |
4988 | \r | |
4989 | \r | |
4990 | /**\r | |
4991 | x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
4992 | IA32_APIC_BASE.[10] = 1.\r | |
4993 | \r | |
4994 | @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)\r | |
4995 | @param EAX Lower 32-bits of MSR value.\r | |
4996 | @param EDX Upper 32-bits of MSR value.\r | |
4997 | \r | |
4998 | <b>Example usage</b>\r | |
4999 | @code\r | |
5000 | UINT64 Msr;\r | |
5001 | \r | |
5002 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);\r | |
5003 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);\r | |
5004 | @endcode\r | |
5005 | **/\r | |
5006 | #define MSR_IA32_X2APIC_LVT_LINT0 0x00000835\r | |
5007 | \r | |
5008 | \r | |
5009 | /**\r | |
5010 | x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
5011 | IA32_APIC_BASE.[10] = 1.\r | |
5012 | \r | |
5013 | @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)\r | |
5014 | @param EAX Lower 32-bits of MSR value.\r | |
5015 | @param EDX Upper 32-bits of MSR value.\r | |
5016 | \r | |
5017 | <b>Example usage</b>\r | |
5018 | @code\r | |
5019 | UINT64 Msr;\r | |
5020 | \r | |
5021 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);\r | |
5022 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);\r | |
5023 | @endcode\r | |
5024 | **/\r | |
5025 | #define MSR_IA32_X2APIC_LVT_LINT1 0x00000836\r | |
5026 | \r | |
5027 | \r | |
5028 | /**\r | |
5029 | x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
5030 | IA32_APIC_BASE.[10] = 1.\r | |
5031 | \r | |
5032 | @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837)\r | |
5033 | @param EAX Lower 32-bits of MSR value.\r | |
5034 | @param EDX Upper 32-bits of MSR value.\r | |
5035 | \r | |
5036 | <b>Example usage</b>\r | |
5037 | @code\r | |
5038 | UINT64 Msr;\r | |
5039 | \r | |
5040 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);\r | |
5041 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);\r | |
5042 | @endcode\r | |
5043 | **/\r | |
5044 | #define MSR_IA32_X2APIC_LVT_ERROR 0x00000837\r | |
5045 | \r | |
5046 | \r | |
5047 | /**\r | |
5048 | x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
5049 | IA32_APIC_BASE.[10] = 1.\r | |
5050 | \r | |
5051 | @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838)\r | |
5052 | @param EAX Lower 32-bits of MSR value.\r | |
5053 | @param EDX Upper 32-bits of MSR value.\r | |
5054 | \r | |
5055 | <b>Example usage</b>\r | |
5056 | @code\r | |
5057 | UINT64 Msr;\r | |
5058 | \r | |
5059 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);\r | |
5060 | AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);\r | |
5061 | @endcode\r | |
5062 | **/\r | |
5063 | #define MSR_IA32_X2APIC_INIT_COUNT 0x00000838\r | |
5064 | \r | |
5065 | \r | |
5066 | /**\r | |
5067 | x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
5068 | IA32_APIC_BASE.[10] = 1.\r | |
5069 | \r | |
5070 | @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839)\r | |
5071 | @param EAX Lower 32-bits of MSR value.\r | |
5072 | @param EDX Upper 32-bits of MSR value.\r | |
5073 | \r | |
5074 | <b>Example usage</b>\r | |
5075 | @code\r | |
5076 | UINT64 Msr;\r | |
5077 | \r | |
5078 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);\r | |
5079 | @endcode\r | |
5080 | **/\r | |
5081 | #define MSR_IA32_X2APIC_CUR_COUNT 0x00000839\r | |
5082 | \r | |
5083 | \r | |
5084 | /**\r | |
5085 | x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
5086 | IA32_APIC_BASE.[10] = 1.\r | |
5087 | \r | |
5088 | @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E)\r | |
5089 | @param EAX Lower 32-bits of MSR value.\r | |
5090 | @param EDX Upper 32-bits of MSR value.\r | |
5091 | \r | |
5092 | <b>Example usage</b>\r | |
5093 | @code\r | |
5094 | UINT64 Msr;\r | |
5095 | \r | |
5096 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);\r | |
5097 | AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);\r | |
5098 | @endcode\r | |
5099 | **/\r | |
5100 | #define MSR_IA32_X2APIC_DIV_CONF 0x0000083E\r | |
5101 | \r | |
5102 | \r | |
5103 | /**\r | |
5104 | x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
5105 | IA32_APIC_BASE.[10] = 1.\r | |
5106 | \r | |
5107 | @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F)\r | |
5108 | @param EAX Lower 32-bits of MSR value.\r | |
5109 | @param EDX Upper 32-bits of MSR value.\r | |
5110 | \r | |
5111 | <b>Example usage</b>\r | |
5112 | @code\r | |
5113 | UINT64 Msr;\r | |
5114 | \r | |
5115 | Msr = 0;\r | |
5116 | AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);\r | |
5117 | @endcode\r | |
5118 | **/\r | |
5119 | #define MSR_IA32_X2APIC_SELF_IPI 0x0000083F\r | |
5120 | \r | |
5121 | \r | |
5122 | /**\r | |
5123 | Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.\r | |
5124 | \r | |
5125 | @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80)\r | |
5126 | @param EAX Lower 32-bits of MSR value.\r | |
5127 | Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.\r | |
5128 | @param EDX Upper 32-bits of MSR value.\r | |
5129 | Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.\r | |
5130 | \r | |
5131 | <b>Example usage</b>\r | |
5132 | @code\r | |
5133 | MSR_IA32_DEBUG_INTERFACE_REGISTER Msr;\r | |
5134 | \r | |
5135 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);\r | |
5136 | AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);\r | |
5137 | @endcode\r | |
5138 | **/\r | |
5139 | #define MSR_IA32_DEBUG_INTERFACE 0x00000C80\r | |
5140 | \r | |
5141 | /**\r | |
5142 | MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE\r | |
5143 | **/\r | |
5144 | typedef union {\r | |
5145 | ///\r | |
5146 | /// Individual bit fields\r | |
5147 | ///\r | |
5148 | struct {\r | |
5149 | ///\r | |
5150 | /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.\r | |
5151 | /// Default is 0. If CPUID.01H:ECX.[11] = 1.\r | |
5152 | ///\r | |
5153 | UINT32 Enable:1;\r | |
5154 | UINT32 Reserved1:29;\r | |
5155 | ///\r | |
5156 | /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The\r | |
5157 | /// lock bit is set automatically on the first SMI assertion even if not\r | |
5158 | /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.\r | |
5159 | ///\r | |
5160 | UINT32 Lock:1;\r | |
5161 | ///\r | |
5162 | /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to\r | |
5163 | /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.\r | |
5164 | ///\r | |
5165 | UINT32 DebugOccurred:1;\r | |
5166 | UINT32 Reserved2:32;\r | |
5167 | } Bits;\r | |
5168 | ///\r | |
5169 | /// All bit fields as a 32-bit value\r | |
5170 | ///\r | |
5171 | UINT32 Uint32;\r | |
5172 | ///\r | |
5173 | /// All bit fields as a 64-bit value\r | |
5174 | ///\r | |
5175 | UINT64 Uint64;\r | |
5176 | } MSR_IA32_DEBUG_INTERFACE_REGISTER;\r | |
5177 | \r | |
5178 | \r | |
5179 | /**\r | |
5180 | L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).\r | |
5181 | \r | |
5182 | @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81)\r | |
5183 | @param EAX Lower 32-bits of MSR value.\r | |
5184 | Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.\r | |
5185 | @param EDX Upper 32-bits of MSR value.\r | |
5186 | Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.\r | |
5187 | \r | |
5188 | <b>Example usage</b>\r | |
5189 | @code\r | |
5190 | MSR_IA32_L3_QOS_CFG_REGISTER Msr;\r | |
5191 | \r | |
5192 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);\r | |
5193 | AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);\r | |
5194 | @endcode\r | |
5195 | **/\r | |
5196 | #define MSR_IA32_L3_QOS_CFG 0x00000C81\r | |
5197 | \r | |
5198 | /**\r | |
5199 | MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG\r | |
5200 | **/\r | |
5201 | typedef union {\r | |
5202 | ///\r | |
5203 | /// Individual bit fields\r | |
5204 | ///\r | |
5205 | struct {\r | |
5206 | ///\r | |
5207 | /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate\r | |
5208 | /// in Code and Data Prioritization (CDP) mode.\r | |
5209 | ///\r | |
5210 | UINT32 Enable:1;\r | |
5211 | UINT32 Reserved1:31;\r | |
5212 | UINT32 Reserved2:32;\r | |
5213 | } Bits;\r | |
5214 | ///\r | |
5215 | /// All bit fields as a 32-bit value\r | |
5216 | ///\r | |
5217 | UINT32 Uint32;\r | |
5218 | ///\r | |
5219 | /// All bit fields as a 64-bit value\r | |
5220 | ///\r | |
5221 | UINT64 Uint64;\r | |
5222 | } MSR_IA32_L3_QOS_CFG_REGISTER;\r | |
5223 | \r | |
5224 | \r | |
5225 | /**\r | |
5226 | Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]\r | |
5227 | = 1 ).\r | |
5228 | \r | |
5229 | @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D)\r | |
5230 | @param EAX Lower 32-bits of MSR value.\r | |
5231 | Described by the type MSR_IA32_QM_EVTSEL_REGISTER.\r | |
5232 | @param EDX Upper 32-bits of MSR value.\r | |
5233 | Described by the type MSR_IA32_QM_EVTSEL_REGISTER.\r | |
5234 | \r | |
5235 | <b>Example usage</b>\r | |
5236 | @code\r | |
5237 | MSR_IA32_QM_EVTSEL_REGISTER Msr;\r | |
5238 | \r | |
5239 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);\r | |
5240 | AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);\r | |
5241 | @endcode\r | |
5242 | **/\r | |
5243 | #define MSR_IA32_QM_EVTSEL 0x00000C8D\r | |
5244 | \r | |
5245 | /**\r | |
5246 | MSR information returned for MSR index #MSR_IA32_QM_EVTSEL\r | |
5247 | **/\r | |
5248 | typedef union {\r | |
5249 | ///\r | |
5250 | /// Individual bit fields\r | |
5251 | ///\r | |
5252 | struct {\r | |
5253 | ///\r | |
5254 | /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via\r | |
5255 | /// IA32_QM_CTR.\r | |
5256 | ///\r | |
5257 | UINT32 EventID:8;\r | |
5258 | UINT32 Reserved:24;\r | |
5259 | ///\r | |
5260 | /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to\r | |
5261 | /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (\r | |
5262 | /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r | |
5263 | ///\r | |
5264 | UINT32 ResourceMonitoringID:32;\r | |
5265 | } Bits;\r | |
5266 | ///\r | |
5267 | /// All bit fields as a 64-bit value\r | |
5268 | ///\r | |
5269 | UINT64 Uint64;\r | |
5270 | } MSR_IA32_QM_EVTSEL_REGISTER;\r | |
5271 | \r | |
5272 | \r | |
5273 | /**\r | |
5274 | Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1\r | |
5275 | ).\r | |
5276 | \r | |
5277 | @param ECX MSR_IA32_QM_CTR (0x00000C8E)\r | |
5278 | @param EAX Lower 32-bits of MSR value.\r | |
5279 | Described by the type MSR_IA32_QM_CTR_REGISTER.\r | |
5280 | @param EDX Upper 32-bits of MSR value.\r | |
5281 | Described by the type MSR_IA32_QM_CTR_REGISTER.\r | |
5282 | \r | |
5283 | <b>Example usage</b>\r | |
5284 | @code\r | |
5285 | MSR_IA32_QM_CTR_REGISTER Msr;\r | |
5286 | \r | |
5287 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);\r | |
5288 | @endcode\r | |
5289 | **/\r | |
5290 | #define MSR_IA32_QM_CTR 0x00000C8E\r | |
5291 | \r | |
5292 | /**\r | |
5293 | MSR information returned for MSR index #MSR_IA32_QM_CTR\r | |
5294 | **/\r | |
5295 | typedef union {\r | |
5296 | ///\r | |
5297 | /// Individual bit fields\r | |
5298 | ///\r | |
5299 | struct {\r | |
5300 | ///\r | |
5301 | /// [Bits 31:0] Resource Monitored Data.\r | |
5302 | ///\r | |
5303 | UINT32 ResourceMonitoredData:32;\r | |
5304 | ///\r | |
5305 | /// [Bits 61:32] Resource Monitored Data.\r | |
5306 | ///\r | |
5307 | UINT32 ResourceMonitoredDataHi:30;\r | |
5308 | ///\r | |
5309 | /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not\r | |
5310 | /// available or not monitored for this resource or RMID.\r | |
5311 | ///\r | |
5312 | UINT32 Unavailable:1;\r | |
5313 | ///\r | |
5314 | /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was\r | |
5315 | /// written to IA32_PQR_QM_EVTSEL.\r | |
5316 | ///\r | |
5317 | UINT32 Error:1;\r | |
5318 | } Bits;\r | |
5319 | ///\r | |
5320 | /// All bit fields as a 64-bit value\r | |
5321 | ///\r | |
5322 | UINT64 Uint64;\r | |
5323 | } MSR_IA32_QM_CTR_REGISTER;\r | |
5324 | \r | |
5325 | \r | |
5326 | /**\r | |
5327 | Resource Association Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] =\r | |
5328 | 1 ).\r | |
5329 | \r | |
5330 | @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)\r | |
5331 | @param EAX Lower 32-bits of MSR value.\r | |
5332 | Described by the type MSR_IA32_PQR_ASSOC_REGISTER.\r | |
5333 | @param EDX Upper 32-bits of MSR value.\r | |
5334 | Described by the type MSR_IA32_PQR_ASSOC_REGISTER.\r | |
5335 | \r | |
5336 | <b>Example usage</b>\r | |
5337 | @code\r | |
5338 | MSR_IA32_PQR_ASSOC_REGISTER Msr;\r | |
5339 | \r | |
5340 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);\r | |
5341 | AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);\r | |
5342 | @endcode\r | |
5343 | **/\r | |
5344 | #define MSR_IA32_PQR_ASSOC 0x00000C8F\r | |
5345 | \r | |
5346 | /**\r | |
5347 | MSR information returned for MSR index #MSR_IA32_PQR_ASSOC\r | |
5348 | **/\r | |
5349 | typedef union {\r | |
5350 | ///\r | |
5351 | /// Individual bit fields\r | |
5352 | ///\r | |
5353 | struct {\r | |
5354 | ///\r | |
5355 | /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware\r | |
5356 | /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`\r | |
5357 | /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r | |
5358 | ///\r | |
5359 | UINT32 ResourceMonitoringID:32;\r | |
5360 | ///\r | |
5361 | /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on\r | |
5362 | /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,\r | |
5363 | /// ECX=0):EBX.[15] = 1 ).\r | |
5364 | ///\r | |
5365 | UINT32 COS:32;\r | |
5366 | } Bits;\r | |
5367 | ///\r | |
5368 | /// All bit fields as a 64-bit value\r | |
5369 | ///\r | |
5370 | UINT64 Uint64;\r | |
5371 | } MSR_IA32_PQR_ASSOC_REGISTER;\r | |
5372 | \r | |
5373 | \r | |
5374 | /**\r | |
5375 | Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,\r | |
5376 | ECX=0H):EBX[14] = 1).\r | |
5377 | \r | |
5378 | @param ECX MSR_IA32_BNDCFGS (0x00000D90)\r | |
5379 | @param EAX Lower 32-bits of MSR value.\r | |
5380 | Described by the type MSR_IA32_BNDCFGS_REGISTER.\r | |
5381 | @param EDX Upper 32-bits of MSR value.\r | |
5382 | Described by the type MSR_IA32_BNDCFGS_REGISTER.\r | |
5383 | \r | |
5384 | <b>Example usage</b>\r | |
5385 | @code\r | |
5386 | MSR_IA32_BNDCFGS_REGISTER Msr;\r | |
5387 | \r | |
5388 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);\r | |
5389 | AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);\r | |
5390 | @endcode\r | |
5391 | **/\r | |
5392 | #define MSR_IA32_BNDCFGS 0x00000D90\r | |
5393 | \r | |
5394 | /**\r | |
5395 | MSR information returned for MSR index #MSR_IA32_BNDCFGS\r | |
5396 | **/\r | |
5397 | typedef union {\r | |
5398 | ///\r | |
5399 | /// Individual bit fields\r | |
5400 | ///\r | |
5401 | struct {\r | |
5402 | ///\r | |
5403 | /// [Bit 0] EN: Enable Intel MPX in supervisor mode.\r | |
5404 | ///\r | |
5405 | UINT32 EN:1;\r | |
5406 | ///\r | |
5407 | /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch\r | |
5408 | /// instructions in the absence of the BND prefix.\r | |
5409 | ///\r | |
5410 | UINT32 BNDPRESERVE:1;\r | |
5411 | UINT32 Reserved:10;\r | |
5412 | ///\r | |
5413 | /// [Bits 31:12] Base Address of Bound Directory.\r | |
5414 | ///\r | |
5415 | UINT32 Base:20;\r | |
5416 | ///\r | |
5417 | /// [Bits 63:32] Base Address of Bound Directory.\r | |
5418 | ///\r | |
5419 | UINT32 BaseHi:32;\r | |
5420 | } Bits;\r | |
5421 | ///\r | |
5422 | /// All bit fields as a 64-bit value\r | |
5423 | ///\r | |
5424 | UINT64 Uint64;\r | |
5425 | } MSR_IA32_BNDCFGS_REGISTER;\r | |
5426 | \r | |
5427 | \r | |
5428 | /**\r | |
5429 | Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.\r | |
5430 | \r | |
5431 | @param ECX MSR_IA32_XSS (0x00000DA0)\r | |
5432 | @param EAX Lower 32-bits of MSR value.\r | |
5433 | Described by the type MSR_IA32_XSS_REGISTER.\r | |
5434 | @param EDX Upper 32-bits of MSR value.\r | |
5435 | Described by the type MSR_IA32_XSS_REGISTER.\r | |
5436 | \r | |
5437 | <b>Example usage</b>\r | |
5438 | @code\r | |
5439 | MSR_IA32_XSS_REGISTER Msr;\r | |
5440 | \r | |
5441 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);\r | |
5442 | AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);\r | |
5443 | @endcode\r | |
5444 | **/\r | |
5445 | #define MSR_IA32_XSS 0x00000DA0\r | |
5446 | \r | |
5447 | /**\r | |
5448 | MSR information returned for MSR index #MSR_IA32_XSS\r | |
5449 | **/\r | |
5450 | typedef union {\r | |
5451 | ///\r | |
5452 | /// Individual bit fields\r | |
5453 | ///\r | |
5454 | struct {\r | |
5455 | UINT32 Reserved1:8;\r | |
5456 | ///\r | |
5457 | /// [Bit 8] Trace Packet Configuration State (R/W).\r | |
5458 | ///\r | |
5459 | UINT32 TracePacketConfigurationState:1;\r | |
5460 | UINT32 Reserved2:23;\r | |
5461 | UINT32 Reserved3:32;\r | |
5462 | } Bits;\r | |
5463 | ///\r | |
5464 | /// All bit fields as a 32-bit value\r | |
5465 | ///\r | |
5466 | UINT32 Uint32;\r | |
5467 | ///\r | |
5468 | /// All bit fields as a 64-bit value\r | |
5469 | ///\r | |
5470 | UINT64 Uint64;\r | |
5471 | } MSR_IA32_XSS_REGISTER;\r | |
5472 | \r | |
5473 | \r | |
5474 | /**\r | |
5475 | Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.\r | |
5476 | \r | |
5477 | @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0)\r | |
5478 | @param EAX Lower 32-bits of MSR value.\r | |
5479 | Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.\r | |
5480 | @param EDX Upper 32-bits of MSR value.\r | |
5481 | Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.\r | |
5482 | \r | |
5483 | <b>Example usage</b>\r | |
5484 | @code\r | |
5485 | MSR_IA32_PKG_HDC_CTL_REGISTER Msr;\r | |
5486 | \r | |
5487 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);\r | |
5488 | AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);\r | |
5489 | @endcode\r | |
5490 | **/\r | |
5491 | #define MSR_IA32_PKG_HDC_CTL 0x00000DB0\r | |
5492 | \r | |
5493 | /**\r | |
5494 | MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL\r | |
5495 | **/\r | |
5496 | typedef union {\r | |
5497 | ///\r | |
5498 | /// Individual bit fields\r | |
5499 | ///\r | |
5500 | struct {\r | |
5501 | ///\r | |
5502 | /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled\r | |
5503 | /// logical processors in the package. See Section 14.5.2, "Package level\r | |
5504 | /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.\r | |
5505 | ///\r | |
5506 | UINT32 HDC_Pkg_Enable:1;\r | |
5507 | UINT32 Reserved1:31;\r | |
5508 | UINT32 Reserved2:32;\r | |
5509 | } Bits;\r | |
5510 | ///\r | |
5511 | /// All bit fields as a 32-bit value\r | |
5512 | ///\r | |
5513 | UINT32 Uint32;\r | |
5514 | ///\r | |
5515 | /// All bit fields as a 64-bit value\r | |
5516 | ///\r | |
5517 | UINT64 Uint64;\r | |
5518 | } MSR_IA32_PKG_HDC_CTL_REGISTER;\r | |
5519 | \r | |
5520 | \r | |
5521 | /**\r | |
5522 | Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.\r | |
5523 | \r | |
5524 | @param ECX MSR_IA32_PM_CTL1 (0x00000DB1)\r | |
5525 | @param EAX Lower 32-bits of MSR value.\r | |
5526 | Described by the type MSR_IA32_PM_CTL1_REGISTER.\r | |
5527 | @param EDX Upper 32-bits of MSR value.\r | |
5528 | Described by the type MSR_IA32_PM_CTL1_REGISTER.\r | |
5529 | \r | |
5530 | <b>Example usage</b>\r | |
5531 | @code\r | |
5532 | MSR_IA32_PM_CTL1_REGISTER Msr;\r | |
5533 | \r | |
5534 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);\r | |
5535 | AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);\r | |
5536 | @endcode\r | |
5537 | **/\r | |
5538 | #define MSR_IA32_PM_CTL1 0x00000DB1\r | |
5539 | \r | |
5540 | /**\r | |
5541 | MSR information returned for MSR index #MSR_IA32_PM_CTL1\r | |
5542 | **/\r | |
5543 | typedef union {\r | |
5544 | ///\r | |
5545 | /// Individual bit fields\r | |
5546 | ///\r | |
5547 | struct {\r | |
5548 | ///\r | |
5549 | /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for\r | |
5550 | /// package level HDC control. See Section 14.5.3.\r | |
5551 | /// If CPUID.06H:EAX.[13] = 1.\r | |
5552 | ///\r | |
5553 | UINT32 HDC_Allow_Block:1;\r | |
5554 | UINT32 Reserved1:31;\r | |
5555 | UINT32 Reserved2:32;\r | |
5556 | } Bits;\r | |
5557 | ///\r | |
5558 | /// All bit fields as a 32-bit value\r | |
5559 | ///\r | |
5560 | UINT32 Uint32;\r | |
5561 | ///\r | |
5562 | /// All bit fields as a 64-bit value\r | |
5563 | ///\r | |
5564 | UINT64 Uint64;\r | |
5565 | } MSR_IA32_PM_CTL1_REGISTER;\r | |
5566 | \r | |
5567 | \r | |
5568 | /**\r | |
5569 | Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.\r | |
5570 | Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical\r | |
5571 | processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.\r | |
5572 | \r | |
5573 | @param ECX MSR_IA32_THREAD_STALL (0x00000DB2)\r | |
5574 | @param EAX Lower 32-bits of MSR value.\r | |
5575 | @param EDX Upper 32-bits of MSR value.\r | |
5576 | \r | |
5577 | <b>Example usage</b>\r | |
5578 | @code\r | |
5579 | UINT64 Msr;\r | |
5580 | \r | |
5581 | Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);\r | |
5582 | @endcode\r | |
5583 | **/\r | |
5584 | #define MSR_IA32_THREAD_STALL 0x00000DB2\r | |
5585 | \r | |
5586 | \r | |
5587 | /**\r | |
5588 | Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]\r | |
5589 | CPUID.80000001H:EDX.[2 9]).\r | |
5590 | \r | |
5591 | @param ECX MSR_IA32_EFER (0xC0000080)\r | |
5592 | @param EAX Lower 32-bits of MSR value.\r | |
5593 | Described by the type MSR_IA32_EFER_REGISTER.\r | |
5594 | @param EDX Upper 32-bits of MSR value.\r | |
5595 | Described by the type MSR_IA32_EFER_REGISTER.\r | |
5596 | \r | |
5597 | <b>Example usage</b>\r | |
5598 | @code\r | |
5599 | MSR_IA32_EFER_REGISTER Msr;\r | |
5600 | \r | |
5601 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);\r | |
5602 | AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);\r | |
5603 | @endcode\r | |
5604 | **/\r | |
5605 | #define MSR_IA32_EFER 0xC0000080\r | |
5606 | \r | |
5607 | /**\r | |
5608 | MSR information returned for MSR index #MSR_IA32_EFER\r | |
5609 | **/\r | |
5610 | typedef union {\r | |
5611 | ///\r | |
5612 | /// Individual bit fields\r | |
5613 | ///\r | |
5614 | struct {\r | |
5615 | ///\r | |
5616 | /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET\r | |
5617 | /// instructions in 64-bit mode.\r | |
5618 | ///\r | |
5619 | UINT32 SCE:1;\r | |
5620 | UINT32 Reserved1:7;\r | |
5621 | ///\r | |
5622 | /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode\r | |
5623 | /// operation.\r | |
5624 | ///\r | |
5625 | UINT32 LME:1;\r | |
5626 | UINT32 Reserved2:1;\r | |
5627 | ///\r | |
5628 | /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode\r | |
5629 | /// is active when set.\r | |
5630 | ///\r | |
5631 | UINT32 LMA:1;\r | |
5632 | ///\r | |
5633 | /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).\r | |
5634 | ///\r | |
5635 | UINT32 NXE:1;\r | |
5636 | UINT32 Reserved3:20;\r | |
5637 | UINT32 Reserved4:32;\r | |
5638 | } Bits;\r | |
5639 | ///\r | |
5640 | /// All bit fields as a 32-bit value\r | |
5641 | ///\r | |
5642 | UINT32 Uint32;\r | |
5643 | ///\r | |
5644 | /// All bit fields as a 64-bit value\r | |
5645 | ///\r | |
5646 | UINT64 Uint64;\r | |
5647 | } MSR_IA32_EFER_REGISTER;\r | |
5648 | \r | |
5649 | \r | |
5650 | /**\r | |
5651 | System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
5652 | \r | |
5653 | @param ECX MSR_IA32_STAR (0xC0000081)\r | |
5654 | @param EAX Lower 32-bits of MSR value.\r | |
5655 | @param EDX Upper 32-bits of MSR value.\r | |
5656 | \r | |
5657 | <b>Example usage</b>\r | |
5658 | @code\r | |
5659 | UINT64 Msr;\r | |
5660 | \r | |
5661 | Msr = AsmReadMsr64 (MSR_IA32_STAR);\r | |
5662 | AsmWriteMsr64 (MSR_IA32_STAR, Msr);\r | |
5663 | @endcode\r | |
5664 | **/\r | |
5665 | #define MSR_IA32_STAR 0xC0000081\r | |
5666 | \r | |
5667 | \r | |
5668 | /**\r | |
5669 | IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
5670 | \r | |
5671 | @param ECX MSR_IA32_LSTAR (0xC0000082)\r | |
5672 | @param EAX Lower 32-bits of MSR value.\r | |
5673 | @param EDX Upper 32-bits of MSR value.\r | |
5674 | \r | |
5675 | <b>Example usage</b>\r | |
5676 | @code\r | |
5677 | UINT64 Msr;\r | |
5678 | \r | |
5679 | Msr = AsmReadMsr64 (MSR_IA32_LSTAR);\r | |
5680 | AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);\r | |
5681 | @endcode\r | |
5682 | **/\r | |
5683 | #define MSR_IA32_LSTAR 0xC0000082\r | |
5684 | \r | |
5685 | \r | |
5686 | /**\r | |
5687 | System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
5688 | \r | |
5689 | @param ECX MSR_IA32_FMASK (0xC0000084)\r | |
5690 | @param EAX Lower 32-bits of MSR value.\r | |
5691 | @param EDX Upper 32-bits of MSR value.\r | |
5692 | \r | |
5693 | <b>Example usage</b>\r | |
5694 | @code\r | |
5695 | UINT64 Msr;\r | |
5696 | \r | |
5697 | Msr = AsmReadMsr64 (MSR_IA32_FMASK);\r | |
5698 | AsmWriteMsr64 (MSR_IA32_FMASK, Msr);\r | |
5699 | @endcode\r | |
5700 | **/\r | |
5701 | #define MSR_IA32_FMASK 0xC0000084\r | |
5702 | \r | |
5703 | \r | |
5704 | /**\r | |
5705 | Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
5706 | \r | |
5707 | @param ECX MSR_IA32_FS_BASE (0xC0000100)\r | |
5708 | @param EAX Lower 32-bits of MSR value.\r | |
5709 | @param EDX Upper 32-bits of MSR value.\r | |
5710 | \r | |
5711 | <b>Example usage</b>\r | |
5712 | @code\r | |
5713 | UINT64 Msr;\r | |
5714 | \r | |
5715 | Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);\r | |
5716 | AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);\r | |
5717 | @endcode\r | |
5718 | **/\r | |
5719 | #define MSR_IA32_FS_BASE 0xC0000100\r | |
5720 | \r | |
5721 | \r | |
5722 | /**\r | |
5723 | Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
5724 | \r | |
5725 | @param ECX MSR_IA32_GS_BASE (0xC0000101)\r | |
5726 | @param EAX Lower 32-bits of MSR value.\r | |
5727 | @param EDX Upper 32-bits of MSR value.\r | |
5728 | \r | |
5729 | <b>Example usage</b>\r | |
5730 | @code\r | |
5731 | UINT64 Msr;\r | |
5732 | \r | |
5733 | Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);\r | |
5734 | AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);\r | |
5735 | @endcode\r | |
5736 | **/\r | |
5737 | #define MSR_IA32_GS_BASE 0xC0000101\r | |
5738 | \r | |
5739 | \r | |
5740 | /**\r | |
5741 | Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
5742 | \r | |
5743 | @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102)\r | |
5744 | @param EAX Lower 32-bits of MSR value.\r | |
5745 | @param EDX Upper 32-bits of MSR value.\r | |
5746 | \r | |
5747 | <b>Example usage</b>\r | |
5748 | @code\r | |
5749 | UINT64 Msr;\r | |
5750 | \r | |
5751 | Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);\r | |
5752 | AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);\r | |
5753 | @endcode\r | |
5754 | **/\r | |
5755 | #define MSR_IA32_KERNEL_GS_BASE 0xC0000102\r | |
5756 | \r | |
5757 | \r | |
5758 | /**\r | |
5759 | Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.\r | |
5760 | \r | |
5761 | @param ECX MSR_IA32_TSC_AUX (0xC0000103)\r | |
5762 | @param EAX Lower 32-bits of MSR value.\r | |
5763 | Described by the type MSR_IA32_TSC_AUX_REGISTER.\r | |
5764 | @param EDX Upper 32-bits of MSR value.\r | |
5765 | Described by the type MSR_IA32_TSC_AUX_REGISTER.\r | |
5766 | \r | |
5767 | <b>Example usage</b>\r | |
5768 | @code\r | |
5769 | MSR_IA32_TSC_AUX_REGISTER Msr;\r | |
5770 | \r | |
5771 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);\r | |
5772 | AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);\r | |
5773 | @endcode\r | |
5774 | **/\r | |
5775 | #define MSR_IA32_TSC_AUX 0xC0000103\r | |
5776 | \r | |
5777 | /**\r | |
5778 | MSR information returned for MSR index #MSR_IA32_TSC_AUX\r | |
5779 | **/\r | |
5780 | typedef union {\r | |
5781 | ///\r | |
5782 | /// Individual bit fields\r | |
5783 | ///\r | |
5784 | struct {\r | |
5785 | ///\r | |
5786 | /// [Bits 31:0] AUX: Auxiliary signature of TSC.\r | |
5787 | ///\r | |
5788 | UINT32 AUX:32;\r | |
5789 | UINT32 Reserved:32;\r | |
5790 | } Bits;\r | |
5791 | ///\r | |
5792 | /// All bit fields as a 32-bit value\r | |
5793 | ///\r | |
5794 | UINT32 Uint32;\r | |
5795 | ///\r | |
5796 | /// All bit fields as a 64-bit value\r | |
5797 | ///\r | |
5798 | UINT64 Uint64;\r | |
5799 | } MSR_IA32_TSC_AUX_REGISTER;\r | |
5800 | \r | |
5801 | #endif\r |