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1 | /** @file\r | |
2 | MSR Definitions for the Intel(R) Core(TM) 2 Processor Family.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
9 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
10 | This program and the accompanying materials\r | |
11 | are licensed and made available under the terms and conditions of the BSD License\r | |
12 | which accompanies this distribution. The full text of the license may be found at\r | |
13 | http://opensource.org/licenses/bsd-license.php\r | |
14 | \r | |
15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | \r | |
18 | @par Specification Reference:\r | |
19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
20 | September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.2.\r | |
21 | \r | |
22 | **/\r | |
23 | \r | |
24 | #ifndef __CORE2_MSR_H__\r | |
25 | #define __CORE2_MSR_H__\r | |
26 | \r | |
27 | #include <Register/ArchitecturalMsr.h>\r | |
28 | \r | |
29 | /**\r | |
30 | Shared. Model Specific Platform ID (R).\r | |
31 | \r | |
32 | @param ECX MSR_CORE2_PLATFORM_ID (0x00000017)\r | |
33 | @param EAX Lower 32-bits of MSR value.\r | |
34 | Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.\r | |
35 | @param EDX Upper 32-bits of MSR value.\r | |
36 | Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.\r | |
37 | \r | |
38 | <b>Example usage</b>\r | |
39 | @code\r | |
40 | MSR_CORE2_PLATFORM_ID_REGISTER Msr;\r | |
41 | \r | |
42 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);\r | |
43 | @endcode\r | |
44 | @note MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r | |
45 | **/\r | |
46 | #define MSR_CORE2_PLATFORM_ID 0x00000017\r | |
47 | \r | |
48 | /**\r | |
49 | MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID\r | |
50 | **/\r | |
51 | typedef union {\r | |
52 | ///\r | |
53 | /// Individual bit fields\r | |
54 | ///\r | |
55 | struct {\r | |
56 | UINT32 Reserved1:8;\r | |
57 | ///\r | |
58 | /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r | |
59 | ///\r | |
60 | UINT32 MaximumQualifiedRatio:5;\r | |
61 | UINT32 Reserved2:19;\r | |
62 | UINT32 Reserved3:18;\r | |
63 | ///\r | |
64 | /// [Bits 52:50] See Table 35-2.\r | |
65 | ///\r | |
66 | UINT32 PlatformId:3;\r | |
67 | UINT32 Reserved4:11;\r | |
68 | } Bits;\r | |
69 | ///\r | |
70 | /// All bit fields as a 64-bit value\r | |
71 | ///\r | |
72 | UINT64 Uint64;\r | |
73 | } MSR_CORE2_PLATFORM_ID_REGISTER;\r | |
74 | \r | |
75 | \r | |
76 | /**\r | |
77 | Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r | |
78 | processor features; (R) indicates current processor configuration.\r | |
79 | \r | |
80 | @param ECX MSR_CORE2_EBL_CR_POWERON (0x0000002A)\r | |
81 | @param EAX Lower 32-bits of MSR value.\r | |
82 | Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.\r | |
83 | @param EDX Upper 32-bits of MSR value.\r | |
84 | Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.\r | |
85 | \r | |
86 | <b>Example usage</b>\r | |
87 | @code\r | |
88 | MSR_CORE2_EBL_CR_POWERON_REGISTER Msr;\r | |
89 | \r | |
90 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);\r | |
91 | AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);\r | |
92 | @endcode\r | |
93 | @note MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r | |
94 | **/\r | |
95 | #define MSR_CORE2_EBL_CR_POWERON 0x0000002A\r | |
96 | \r | |
97 | /**\r | |
98 | MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON\r | |
99 | **/\r | |
100 | typedef union {\r | |
101 | ///\r | |
102 | /// Individual bit fields\r | |
103 | ///\r | |
104 | struct {\r | |
105 | UINT32 Reserved1:1;\r | |
106 | ///\r | |
107 | /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r | |
108 | /// Note: Not all processor implements R/W.\r | |
109 | ///\r | |
110 | UINT32 DataErrorCheckingEnable:1;\r | |
111 | ///\r | |
112 | /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r | |
113 | /// Note: Not all processor implements R/W.\r | |
114 | ///\r | |
115 | UINT32 ResponseErrorCheckingEnable:1;\r | |
116 | ///\r | |
117 | /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r | |
118 | /// all processor implements R/W.\r | |
119 | ///\r | |
120 | UINT32 MCERR_DriveEnable:1;\r | |
121 | ///\r | |
122 | /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:\r | |
123 | /// Not all processor implements R/W.\r | |
124 | ///\r | |
125 | UINT32 AddressParityEnable:1;\r | |
126 | UINT32 Reserved2:1;\r | |
127 | UINT32 Reserved3:1;\r | |
128 | ///\r | |
129 | /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r | |
130 | /// all processor implements R/W.\r | |
131 | ///\r | |
132 | UINT32 BINIT_DriverEnable:1;\r | |
133 | ///\r | |
134 | /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r | |
135 | ///\r | |
136 | UINT32 OutputTriStateEnable:1;\r | |
137 | ///\r | |
138 | /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r | |
139 | ///\r | |
140 | UINT32 ExecuteBIST:1;\r | |
141 | ///\r | |
142 | /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r | |
143 | ///\r | |
144 | UINT32 MCERR_ObservationEnabled:1;\r | |
145 | ///\r | |
146 | /// [Bit 11] Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present.\r | |
147 | ///\r | |
148 | UINT32 IntelTXTCapableChipset:1;\r | |
149 | ///\r | |
150 | /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r | |
151 | ///\r | |
152 | UINT32 BINIT_ObservationEnabled:1;\r | |
153 | UINT32 Reserved4:1;\r | |
154 | ///\r | |
155 | /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r | |
156 | ///\r | |
157 | UINT32 ResetVector:1;\r | |
158 | UINT32 Reserved5:1;\r | |
159 | ///\r | |
160 | /// [Bits 17:16] APIC Cluster ID (R/O).\r | |
161 | ///\r | |
162 | UINT32 APICClusterID:2;\r | |
163 | ///\r | |
164 | /// [Bit 18] N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 =\r | |
165 | /// Non-integer ratio.\r | |
166 | ///\r | |
167 | UINT32 NonIntegerBusRatio:1;\r | |
168 | UINT32 Reserved6:1;\r | |
169 | ///\r | |
170 | /// [Bits 21:20] Symmetric Arbitration ID (R/O).\r | |
171 | ///\r | |
172 | UINT32 SymmetricArbitrationID:2;\r | |
173 | ///\r | |
174 | /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).\r | |
175 | ///\r | |
176 | UINT32 IntegerBusFrequencyRatio:5;\r | |
177 | UINT32 Reserved7:5;\r | |
178 | UINT32 Reserved8:32;\r | |
179 | } Bits;\r | |
180 | ///\r | |
181 | /// All bit fields as a 32-bit value\r | |
182 | ///\r | |
183 | UINT32 Uint32;\r | |
184 | ///\r | |
185 | /// All bit fields as a 64-bit value\r | |
186 | ///\r | |
187 | UINT64 Uint64;\r | |
188 | } MSR_CORE2_EBL_CR_POWERON_REGISTER;\r | |
189 | \r | |
190 | \r | |
191 | /**\r | |
192 | Unique. Control Features in Intel 64Processor (R/W) See Table 35-2.\r | |
193 | \r | |
194 | @param ECX MSR_CORE2_FEATURE_CONTROL (0x0000003A)\r | |
195 | @param EAX Lower 32-bits of MSR value.\r | |
196 | Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.\r | |
197 | @param EDX Upper 32-bits of MSR value.\r | |
198 | Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.\r | |
199 | \r | |
200 | <b>Example usage</b>\r | |
201 | @code\r | |
202 | MSR_CORE2_FEATURE_CONTROL_REGISTER Msr;\r | |
203 | \r | |
204 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL);\r | |
205 | AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64);\r | |
206 | @endcode\r | |
207 | @note MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM.\r | |
208 | **/\r | |
209 | #define MSR_CORE2_FEATURE_CONTROL 0x0000003A\r | |
210 | \r | |
211 | /**\r | |
212 | MSR information returned for MSR index #MSR_CORE2_FEATURE_CONTROL\r | |
213 | **/\r | |
214 | typedef union {\r | |
215 | ///\r | |
216 | /// Individual bit fields\r | |
217 | ///\r | |
218 | struct {\r | |
219 | UINT32 Reserved1:3;\r | |
220 | ///\r | |
221 | /// [Bit 3] Unique. SMRR Enable (R/WL) When this bit is set and the lock\r | |
222 | /// bit is set makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read\r | |
223 | /// visible and writeable while in SMM.\r | |
224 | ///\r | |
225 | UINT32 SMRREnable:1;\r | |
226 | UINT32 Reserved2:28;\r | |
227 | UINT32 Reserved3:32;\r | |
228 | } Bits;\r | |
229 | ///\r | |
230 | /// All bit fields as a 32-bit value\r | |
231 | ///\r | |
232 | UINT32 Uint32;\r | |
233 | ///\r | |
234 | /// All bit fields as a 64-bit value\r | |
235 | ///\r | |
236 | UINT64 Uint64;\r | |
237 | } MSR_CORE2_FEATURE_CONTROL_REGISTER;\r | |
238 | \r | |
239 | \r | |
240 | /**\r | |
241 | Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch\r | |
242 | record registers on the last branch record stack. The From_IP part of the\r | |
243 | stack contains pointers to the source instruction. See also: - Last Branch\r | |
244 | Record Stack TOS at 1C9H - Section 17.5.\r | |
245 | \r | |
246 | @param ECX MSR_CORE2_LASTBRANCH_n_FROM_IP\r | |
247 | @param EAX Lower 32-bits of MSR value.\r | |
248 | @param EDX Upper 32-bits of MSR value.\r | |
249 | \r | |
250 | <b>Example usage</b>\r | |
251 | @code\r | |
252 | UINT64 Msr;\r | |
253 | \r | |
254 | Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP);\r | |
255 | AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr);\r | |
256 | @endcode\r | |
257 | @note MSR_CORE2_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r | |
258 | MSR_CORE2_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r | |
259 | MSR_CORE2_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r | |
260 | MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r | |
261 | @{\r | |
262 | **/\r | |
263 | #define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040\r | |
264 | #define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x00000041\r | |
265 | #define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x00000042\r | |
266 | #define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x00000043\r | |
267 | /// @}\r | |
268 | \r | |
269 | \r | |
270 | /**\r | |
271 | Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch\r | |
272 | record registers on the last branch record stack. This To_IP part of the\r | |
273 | stack contains pointers to the destination instruction.\r | |
274 | \r | |
275 | @param ECX MSR_CORE2_LASTBRANCH_n_TO_IP\r | |
276 | @param EAX Lower 32-bits of MSR value.\r | |
277 | @param EDX Upper 32-bits of MSR value.\r | |
278 | \r | |
279 | <b>Example usage</b>\r | |
280 | @code\r | |
281 | UINT64 Msr;\r | |
282 | \r | |
283 | Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP);\r | |
284 | AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr);\r | |
285 | @endcode\r | |
286 | @note MSR_CORE2_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r | |
287 | MSR_CORE2_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r | |
288 | MSR_CORE2_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r | |
289 | MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r | |
290 | @{\r | |
291 | **/\r | |
292 | #define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060\r | |
293 | #define MSR_CORE2_LASTBRANCH_1_TO_IP 0x00000061\r | |
294 | #define MSR_CORE2_LASTBRANCH_2_TO_IP 0x00000062\r | |
295 | #define MSR_CORE2_LASTBRANCH_3_TO_IP 0x00000063\r | |
296 | /// @}\r | |
297 | \r | |
298 | \r | |
299 | /**\r | |
300 | Unique. System Management Mode Base Address register (WO in SMM)\r | |
301 | Model-specific implementation of SMRR-like interface, read visible and write\r | |
302 | only in SMM.\r | |
303 | \r | |
304 | @param ECX MSR_CORE2_SMRR_PHYSBASE (0x000000A0)\r | |
305 | @param EAX Lower 32-bits of MSR value.\r | |
306 | Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.\r | |
307 | @param EDX Upper 32-bits of MSR value.\r | |
308 | Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.\r | |
309 | \r | |
310 | <b>Example usage</b>\r | |
311 | @code\r | |
312 | MSR_CORE2_SMRR_PHYSBASE_REGISTER Msr;\r | |
313 | \r | |
314 | Msr.Uint64 = 0;\r | |
315 | AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64);\r | |
316 | @endcode\r | |
317 | @note MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM.\r | |
318 | **/\r | |
319 | #define MSR_CORE2_SMRR_PHYSBASE 0x000000A0\r | |
320 | \r | |
321 | /**\r | |
322 | MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSBASE\r | |
323 | **/\r | |
324 | typedef union {\r | |
325 | ///\r | |
326 | /// Individual bit fields\r | |
327 | ///\r | |
328 | struct {\r | |
329 | UINT32 Reserved1:12;\r | |
330 | ///\r | |
331 | /// [Bits 31:12] PhysBase. SMRR physical Base Address.\r | |
332 | ///\r | |
333 | UINT32 PhysBase:20;\r | |
334 | UINT32 Reserved2:32;\r | |
335 | } Bits;\r | |
336 | ///\r | |
337 | /// All bit fields as a 32-bit value\r | |
338 | ///\r | |
339 | UINT32 Uint32;\r | |
340 | ///\r | |
341 | /// All bit fields as a 64-bit value\r | |
342 | ///\r | |
343 | UINT64 Uint64;\r | |
344 | } MSR_CORE2_SMRR_PHYSBASE_REGISTER;\r | |
345 | \r | |
346 | \r | |
347 | /**\r | |
348 | Unique. System Management Mode Physical Address Mask register (WO in SMM)\r | |
349 | Model-specific implementation of SMRR-like interface, read visible and write\r | |
350 | only in SMM.\r | |
351 | \r | |
352 | @param ECX MSR_CORE2_SMRR_PHYSMASK (0x000000A1)\r | |
353 | @param EAX Lower 32-bits of MSR value.\r | |
354 | Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.\r | |
355 | @param EDX Upper 32-bits of MSR value.\r | |
356 | Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.\r | |
357 | \r | |
358 | <b>Example usage</b>\r | |
359 | @code\r | |
360 | MSR_CORE2_SMRR_PHYSMASK_REGISTER Msr;\r | |
361 | \r | |
362 | Msr.Uint64 = 0;\r | |
363 | AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64);\r | |
364 | @endcode\r | |
365 | @note MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM.\r | |
366 | **/\r | |
367 | #define MSR_CORE2_SMRR_PHYSMASK 0x000000A1\r | |
368 | \r | |
369 | /**\r | |
370 | MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSMASK\r | |
371 | **/\r | |
372 | typedef union {\r | |
373 | ///\r | |
374 | /// Individual bit fields\r | |
375 | ///\r | |
376 | struct {\r | |
377 | UINT32 Reserved1:11;\r | |
378 | ///\r | |
379 | /// [Bit 11] Valid. Physical address base and range mask are valid.\r | |
380 | ///\r | |
381 | UINT32 Valid:1;\r | |
382 | ///\r | |
383 | /// [Bits 31:12] PhysMask. SMRR physical address range mask.\r | |
384 | ///\r | |
385 | UINT32 PhysMask:20;\r | |
386 | UINT32 Reserved2:32;\r | |
387 | } Bits;\r | |
388 | ///\r | |
389 | /// All bit fields as a 32-bit value\r | |
390 | ///\r | |
391 | UINT32 Uint32;\r | |
392 | ///\r | |
393 | /// All bit fields as a 64-bit value\r | |
394 | ///\r | |
395 | UINT64 Uint64;\r | |
396 | } MSR_CORE2_SMRR_PHYSMASK_REGISTER;\r | |
397 | \r | |
398 | \r | |
399 | /**\r | |
400 | Shared. Scalable Bus Speed(RO) This field indicates the intended scalable\r | |
401 | bus clock speed for processors based on Intel Core microarchitecture:.\r | |
402 | \r | |
403 | @param ECX MSR_CORE2_FSB_FREQ (0x000000CD)\r | |
404 | @param EAX Lower 32-bits of MSR value.\r | |
405 | Described by the type MSR_CORE2_FSB_FREQ_REGISTER.\r | |
406 | @param EDX Upper 32-bits of MSR value.\r | |
407 | Described by the type MSR_CORE2_FSB_FREQ_REGISTER.\r | |
408 | \r | |
409 | <b>Example usage</b>\r | |
410 | @code\r | |
411 | MSR_CORE2_FSB_FREQ_REGISTER Msr;\r | |
412 | \r | |
413 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ);\r | |
414 | @endcode\r | |
415 | @note MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r | |
416 | **/\r | |
417 | #define MSR_CORE2_FSB_FREQ 0x000000CD\r | |
418 | \r | |
419 | /**\r | |
420 | MSR information returned for MSR index #MSR_CORE2_FSB_FREQ\r | |
421 | **/\r | |
422 | typedef union {\r | |
423 | ///\r | |
424 | /// Individual bit fields\r | |
425 | ///\r | |
426 | struct {\r | |
427 | ///\r | |
428 | /// [Bits 2:0] - Scalable Bus Speed\r | |
429 | /// 101B: 100 MHz (FSB 400)\r | |
430 | /// 001B: 133 MHz (FSB 533)\r | |
431 | /// 011B: 167 MHz (FSB 667)\r | |
432 | /// 010B: 200 MHz (FSB 800)\r | |
433 | /// 000B: 267 MHz (FSB 1067)\r | |
434 | /// 100B: 333 MHz (FSB 1333)\r | |
435 | ///\r | |
436 | /// 133.33 MHz should be utilized if performing calculation with System\r | |
437 | /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if\r | |
438 | /// performing calculation with System Bus Speed when encoding is 011B.\r | |
439 | /// 266.67 MHz should be utilized if performing calculation with System\r | |
440 | /// Bus Speed when encoding is 000B. 333.33 MHz should be utilized if\r | |
441 | /// performing calculation with System Bus Speed when encoding is 100B.\r | |
442 | ///\r | |
443 | UINT32 ScalableBusSpeed:3;\r | |
444 | UINT32 Reserved1:29;\r | |
445 | UINT32 Reserved2:32;\r | |
446 | } Bits;\r | |
447 | ///\r | |
448 | /// All bit fields as a 32-bit value\r | |
449 | ///\r | |
450 | UINT32 Uint32;\r | |
451 | ///\r | |
452 | /// All bit fields as a 64-bit value\r | |
453 | ///\r | |
454 | UINT64 Uint64;\r | |
455 | } MSR_CORE2_FSB_FREQ_REGISTER;\r | |
456 | \r | |
457 | \r | |
458 | /**\r | |
459 | Shared.\r | |
460 | \r | |
461 | @param ECX MSR_CORE2_BBL_CR_CTL3 (0x0000011E)\r | |
462 | @param EAX Lower 32-bits of MSR value.\r | |
463 | Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.\r | |
464 | @param EDX Upper 32-bits of MSR value.\r | |
465 | Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.\r | |
466 | \r | |
467 | <b>Example usage</b>\r | |
468 | @code\r | |
469 | MSR_CORE2_BBL_CR_CTL3_REGISTER Msr;\r | |
470 | \r | |
471 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_BBL_CR_CTL3);\r | |
472 | AsmWriteMsr64 (MSR_CORE2_BBL_CR_CTL3, Msr.Uint64);\r | |
473 | @endcode\r | |
474 | @note MSR_CORE2_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r | |
475 | **/\r | |
476 | #define MSR_CORE2_BBL_CR_CTL3 0x0000011E\r | |
477 | \r | |
478 | /**\r | |
479 | MSR information returned for MSR index #MSR_CORE2_BBL_CR_CTL3\r | |
480 | **/\r | |
481 | typedef union {\r | |
482 | ///\r | |
483 | /// Individual bit fields\r | |
484 | ///\r | |
485 | struct {\r | |
486 | ///\r | |
487 | /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r | |
488 | /// Indicates if the L2 is hardware-disabled.\r | |
489 | ///\r | |
490 | UINT32 L2HardwareEnabled:1;\r | |
491 | UINT32 Reserved1:7;\r | |
492 | ///\r | |
493 | /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =\r | |
494 | /// Disabled (default) Until this bit is set the processor will not\r | |
495 | /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r | |
496 | ///\r | |
497 | UINT32 L2Enabled:1;\r | |
498 | UINT32 Reserved2:14;\r | |
499 | ///\r | |
500 | /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r | |
501 | ///\r | |
502 | UINT32 L2NotPresent:1;\r | |
503 | UINT32 Reserved3:8;\r | |
504 | UINT32 Reserved4:32;\r | |
505 | } Bits;\r | |
506 | ///\r | |
507 | /// All bit fields as a 32-bit value\r | |
508 | ///\r | |
509 | UINT32 Uint32;\r | |
510 | ///\r | |
511 | /// All bit fields as a 64-bit value\r | |
512 | ///\r | |
513 | UINT64 Uint64;\r | |
514 | } MSR_CORE2_BBL_CR_CTL3_REGISTER;\r | |
515 | \r | |
516 | \r | |
517 | /**\r | |
518 | Shared.\r | |
519 | \r | |
520 | @param ECX MSR_CORE2_PERF_STATUS (0x00000198)\r | |
521 | @param EAX Lower 32-bits of MSR value.\r | |
522 | Described by the type MSR_CORE2_PERF_STATUS_REGISTER.\r | |
523 | @param EDX Upper 32-bits of MSR value.\r | |
524 | Described by the type MSR_CORE2_PERF_STATUS_REGISTER.\r | |
525 | \r | |
526 | <b>Example usage</b>\r | |
527 | @code\r | |
528 | MSR_CORE2_PERF_STATUS_REGISTER Msr;\r | |
529 | \r | |
530 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS);\r | |
531 | AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64);\r | |
532 | @endcode\r | |
533 | @note MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r | |
534 | **/\r | |
535 | #define MSR_CORE2_PERF_STATUS 0x00000198\r | |
536 | \r | |
537 | /**\r | |
538 | MSR information returned for MSR index #MSR_CORE2_PERF_STATUS\r | |
539 | **/\r | |
540 | typedef union {\r | |
541 | ///\r | |
542 | /// Individual bit fields\r | |
543 | ///\r | |
544 | struct {\r | |
545 | ///\r | |
546 | /// [Bits 15:0] Current Performance State Value.\r | |
547 | ///\r | |
548 | UINT32 CurrentPerformanceStateValue:16;\r | |
549 | UINT32 Reserved1:15;\r | |
550 | ///\r | |
551 | /// [Bit 31] XE Operation (R/O). If set, XE operation is enabled. Default\r | |
552 | /// is cleared.\r | |
553 | ///\r | |
554 | UINT32 XEOperation:1;\r | |
555 | UINT32 Reserved2:8;\r | |
556 | ///\r | |
557 | /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio\r | |
558 | /// configured for the processor.\r | |
559 | ///\r | |
560 | UINT32 MaximumBusRatio:5;\r | |
561 | UINT32 Reserved3:1;\r | |
562 | ///\r | |
563 | /// [Bit 46] Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio\r | |
564 | /// is enabled. Applies processors based on Enhanced Intel Core\r | |
565 | /// microarchitecture.\r | |
566 | ///\r | |
567 | UINT32 NonIntegerBusRatio:1;\r | |
568 | UINT32 Reserved4:17;\r | |
569 | } Bits;\r | |
570 | ///\r | |
571 | /// All bit fields as a 64-bit value\r | |
572 | ///\r | |
573 | UINT64 Uint64;\r | |
574 | } MSR_CORE2_PERF_STATUS_REGISTER;\r | |
575 | \r | |
576 | \r | |
577 | /**\r | |
578 | Unique.\r | |
579 | \r | |
580 | @param ECX MSR_CORE2_THERM2_CTL (0x0000019D)\r | |
581 | @param EAX Lower 32-bits of MSR value.\r | |
582 | Described by the type MSR_CORE2_THERM2_CTL_REGISTER.\r | |
583 | @param EDX Upper 32-bits of MSR value.\r | |
584 | Described by the type MSR_CORE2_THERM2_CTL_REGISTER.\r | |
585 | \r | |
586 | <b>Example usage</b>\r | |
587 | @code\r | |
588 | MSR_CORE2_THERM2_CTL_REGISTER Msr;\r | |
589 | \r | |
590 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL);\r | |
591 | AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64);\r | |
592 | @endcode\r | |
593 | @note MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r | |
594 | **/\r | |
595 | #define MSR_CORE2_THERM2_CTL 0x0000019D\r | |
596 | \r | |
597 | /**\r | |
598 | MSR information returned for MSR index #MSR_CORE2_THERM2_CTL\r | |
599 | **/\r | |
600 | typedef union {\r | |
601 | ///\r | |
602 | /// Individual bit fields\r | |
603 | ///\r | |
604 | struct {\r | |
605 | UINT32 Reserved1:16;\r | |
606 | ///\r | |
607 | /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r | |
608 | /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r | |
609 | /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r | |
610 | /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r | |
611 | /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.\r | |
612 | ///\r | |
613 | UINT32 TM_SELECT:1;\r | |
614 | UINT32 Reserved2:15;\r | |
615 | UINT32 Reserved3:32;\r | |
616 | } Bits;\r | |
617 | ///\r | |
618 | /// All bit fields as a 32-bit value\r | |
619 | ///\r | |
620 | UINT32 Uint32;\r | |
621 | ///\r | |
622 | /// All bit fields as a 64-bit value\r | |
623 | ///\r | |
624 | UINT64 Uint64;\r | |
625 | } MSR_CORE2_THERM2_CTL_REGISTER;\r | |
626 | \r | |
627 | \r | |
628 | /**\r | |
629 | Enable Misc. Processor Features (R/W) Allows a variety of processor\r | |
630 | functions to be enabled and disabled.\r | |
631 | \r | |
632 | @param ECX MSR_CORE2_IA32_MISC_ENABLE (0x000001A0)\r | |
633 | @param EAX Lower 32-bits of MSR value.\r | |
634 | Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.\r | |
635 | @param EDX Upper 32-bits of MSR value.\r | |
636 | Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.\r | |
637 | \r | |
638 | <b>Example usage</b>\r | |
639 | @code\r | |
640 | MSR_CORE2_IA32_MISC_ENABLE_REGISTER Msr;\r | |
641 | \r | |
642 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE);\r | |
643 | AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64);\r | |
644 | @endcode\r | |
645 | @note MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r | |
646 | **/\r | |
647 | #define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0\r | |
648 | \r | |
649 | /**\r | |
650 | MSR information returned for MSR index #MSR_CORE2_IA32_MISC_ENABLE\r | |
651 | **/\r | |
652 | typedef union {\r | |
653 | ///\r | |
654 | /// Individual bit fields\r | |
655 | ///\r | |
656 | struct {\r | |
657 | ///\r | |
658 | /// [Bit 0] Fast-Strings Enable See Table 35-2.\r | |
659 | ///\r | |
660 | UINT32 FastStrings:1;\r | |
661 | UINT32 Reserved1:2;\r | |
662 | ///\r | |
663 | /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r | |
664 | /// Table 35-2.\r | |
665 | ///\r | |
666 | UINT32 AutomaticThermalControlCircuit:1;\r | |
667 | UINT32 Reserved2:3;\r | |
668 | ///\r | |
669 | /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.\r | |
670 | ///\r | |
671 | UINT32 PerformanceMonitoring:1;\r | |
672 | UINT32 Reserved3:1;\r | |
673 | ///\r | |
674 | /// [Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the\r | |
675 | /// hardware prefetcher operation on streams of data. When clear\r | |
676 | /// (default), enables the prefetch queue. Disabling of the hardware\r | |
677 | /// prefetcher may impact processor performance.\r | |
678 | ///\r | |
679 | UINT32 HardwarePrefetcherDisable:1;\r | |
680 | ///\r | |
681 | /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r | |
682 | /// the processor to indicate a pending break event within the processor 0\r | |
683 | /// = Indicates compatible FERR# signaling behavior This bit must be set\r | |
684 | /// to 1 to support XAPIC interrupt model usage.\r | |
685 | ///\r | |
686 | UINT32 FERR:1;\r | |
687 | ///\r | |
688 | /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.\r | |
689 | ///\r | |
690 | UINT32 BTS:1;\r | |
691 | ///\r | |
692 | /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See\r | |
693 | /// Table 35-2.\r | |
694 | ///\r | |
695 | UINT32 PEBS:1;\r | |
696 | ///\r | |
697 | /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r | |
698 | /// thermal sensor indicates that the die temperature is at the\r | |
699 | /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.\r | |
700 | /// TM2 will reduce the bus to core ratio and voltage according to the\r | |
701 | /// value last written to MSR_THERM2_CTL bits 15:0.\r | |
702 | /// When this bit is clear (0, default), the processor does not change\r | |
703 | /// the VID signals or the bus to core ratio when the processor enters a\r | |
704 | /// thermally managed state. The BIOS must enable this feature if the\r | |
705 | /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is\r | |
706 | /// not set, this feature is not supported and BIOS must not alter the\r | |
707 | /// contents of the TM2 bit location. The processor is operating out of\r | |
708 | /// specification if both this bit and the TM1 bit are set to 0.\r | |
709 | ///\r | |
710 | UINT32 TM2:1;\r | |
711 | UINT32 Reserved4:2;\r | |
712 | ///\r | |
713 | /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See\r | |
714 | /// Table 35-2.\r | |
715 | ///\r | |
716 | UINT32 EIST:1;\r | |
717 | UINT32 Reserved5:1;\r | |
718 | ///\r | |
719 | /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.\r | |
720 | ///\r | |
721 | UINT32 MONITOR:1;\r | |
722 | ///\r | |
723 | /// [Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W) When set\r | |
724 | /// to 1, the processor fetches the cache line that contains data\r | |
725 | /// currently required by the processor. When set to 0, the processor\r | |
726 | /// fetches cache lines that comprise a cache line pair (128 bytes).\r | |
727 | /// Single processor platforms should not set this bit. Server platforms\r | |
728 | /// should set or clear this bit based on platform performance observed in\r | |
729 | /// validation and testing. BIOS may contain a setup option that controls\r | |
730 | /// the setting of this bit.\r | |
731 | ///\r | |
732 | UINT32 AdjacentCacheLinePrefetchDisable:1;\r | |
733 | ///\r | |
734 | /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock\r | |
735 | /// (R/WO) When set, this bit causes the following bits to become\r | |
736 | /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this\r | |
737 | /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must\r | |
738 | /// be set before an Enhanced Intel SpeedStep Technology transition is\r | |
739 | /// requested. This bit is cleared on reset.\r | |
740 | ///\r | |
741 | UINT32 EISTLock:1;\r | |
742 | UINT32 Reserved6:1;\r | |
743 | ///\r | |
744 | /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2.\r | |
745 | ///\r | |
746 | UINT32 LimitCpuidMaxval:1;\r | |
747 | ///\r | |
748 | /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.\r | |
749 | ///\r | |
750 | UINT32 xTPR_Message_Disable:1;\r | |
751 | UINT32 Reserved7:8;\r | |
752 | UINT32 Reserved8:2;\r | |
753 | ///\r | |
754 | /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.\r | |
755 | ///\r | |
756 | UINT32 XD:1;\r | |
757 | UINT32 Reserved9:2;\r | |
758 | ///\r | |
759 | /// [Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU\r | |
760 | /// L1 data cache prefetcher is disabled. The default value after reset is\r | |
761 | /// 0. BIOS may write '1' to disable this feature. The DCU prefetcher is\r | |
762 | /// an L1 data cache prefetcher. When the DCU prefetcher detects multiple\r | |
763 | /// loads from the same line done within a time limit, the DCU prefetcher\r | |
764 | /// assumes the next line will be required. The next line is prefetched in\r | |
765 | /// to the L1 data cache from memory or L2.\r | |
766 | ///\r | |
767 | UINT32 DCUPrefetcherDisable:1;\r | |
768 | ///\r | |
769 | /// [Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that\r | |
770 | /// support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled\r | |
771 | /// and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).\r | |
772 | /// When set to a 0 on processors that support IDA, CPUID.06H: EAX[1]\r | |
773 | /// reports the processor's support of IDA is enabled. Note: the power-on\r | |
774 | /// default value is used by BIOS to detect hardware support of IDA. If\r | |
775 | /// power-on default value is 1, IDA is available in the processor. If\r | |
776 | /// power-on default value is 0, IDA is not available.\r | |
777 | ///\r | |
778 | UINT32 IDADisable:1;\r | |
779 | ///\r | |
780 | /// [Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP\r | |
781 | /// prefetcher is disabled. The default value after reset is 0. BIOS may\r | |
782 | /// write '1' to disable this feature. The IP prefetcher is an L1 data\r | |
783 | /// cache prefetcher. The IP prefetcher looks for sequential load history\r | |
784 | /// to determine whether to prefetch the next expected data into the L1\r | |
785 | /// cache from memory or L2.\r | |
786 | ///\r | |
787 | UINT32 IPPrefetcherDisable:1;\r | |
788 | UINT32 Reserved10:24;\r | |
789 | } Bits;\r | |
790 | ///\r | |
791 | /// All bit fields as a 64-bit value\r | |
792 | ///\r | |
793 | UINT64 Uint64;\r | |
794 | } MSR_CORE2_IA32_MISC_ENABLE_REGISTER;\r | |
795 | \r | |
796 | \r | |
797 | /**\r | |
798 | Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r | |
799 | that points to the MSR containing the most recent branch record. See\r | |
800 | MSR_LASTBRANCH_0_FROM_IP (at 40H).\r | |
801 | \r | |
802 | @param ECX MSR_CORE2_LASTBRANCH_TOS (0x000001C9)\r | |
803 | @param EAX Lower 32-bits of MSR value.\r | |
804 | @param EDX Upper 32-bits of MSR value.\r | |
805 | \r | |
806 | <b>Example usage</b>\r | |
807 | @code\r | |
808 | UINT64 Msr;\r | |
809 | \r | |
810 | Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS);\r | |
811 | AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr);\r | |
812 | @endcode\r | |
813 | @note MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r | |
814 | **/\r | |
815 | #define MSR_CORE2_LASTBRANCH_TOS 0x000001C9\r | |
816 | \r | |
817 | \r | |
818 | /**\r | |
819 | Unique. Last Exception Record From Linear IP (R) Contains a pointer to the\r | |
820 | last branch instruction that the processor executed prior to the last\r | |
821 | exception that was generated or the last interrupt that was handled.\r | |
822 | \r | |
823 | @param ECX MSR_CORE2_LER_FROM_LIP (0x000001DD)\r | |
824 | @param EAX Lower 32-bits of MSR value.\r | |
825 | @param EDX Upper 32-bits of MSR value.\r | |
826 | \r | |
827 | <b>Example usage</b>\r | |
828 | @code\r | |
829 | UINT64 Msr;\r | |
830 | \r | |
831 | Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP);\r | |
832 | @endcode\r | |
833 | @note MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r | |
834 | **/\r | |
835 | #define MSR_CORE2_LER_FROM_LIP 0x000001DD\r | |
836 | \r | |
837 | \r | |
838 | /**\r | |
839 | Unique. Last Exception Record To Linear IP (R) This area contains a pointer\r | |
840 | to the target of the last branch instruction that the processor executed\r | |
841 | prior to the last exception that was generated or the last interrupt that\r | |
842 | was handled.\r | |
843 | \r | |
844 | @param ECX MSR_CORE2_LER_TO_LIP (0x000001DE)\r | |
845 | @param EAX Lower 32-bits of MSR value.\r | |
846 | @param EDX Upper 32-bits of MSR value.\r | |
847 | \r | |
848 | <b>Example usage</b>\r | |
849 | @code\r | |
850 | UINT64 Msr;\r | |
851 | \r | |
852 | Msr = AsmReadMsr64 (MSR_CORE2_LER_TO_LIP);\r | |
853 | @endcode\r | |
854 | @note MSR_CORE2_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r | |
855 | **/\r | |
856 | #define MSR_CORE2_LER_TO_LIP 0x000001DE\r | |
857 | \r | |
858 | \r | |
859 | /**\r | |
860 | Unique. Fixed-Function Performance Counter Register n (R/W).\r | |
861 | \r | |
862 | @param ECX MSR_CORE2_PERF_FIXED_CTRn\r | |
863 | @param EAX Lower 32-bits of MSR value.\r | |
864 | @param EDX Upper 32-bits of MSR value.\r | |
865 | \r | |
866 | <b>Example usage</b>\r | |
867 | @code\r | |
868 | UINT64 Msr;\r | |
869 | \r | |
870 | Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR0);\r | |
871 | AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR0, Msr);\r | |
872 | @endcode\r | |
873 | @note MSR_CORE2_PERF_FIXED_CTR0 is defined as MSR_PERF_FIXED_CTR0 in SDM.\r | |
874 | MSR_CORE2_PERF_FIXED_CTR1 is defined as MSR_PERF_FIXED_CTR1 in SDM.\r | |
875 | MSR_CORE2_PERF_FIXED_CTR2 is defined as MSR_PERF_FIXED_CTR2 in SDM.\r | |
876 | @{\r | |
877 | **/\r | |
878 | #define MSR_CORE2_PERF_FIXED_CTR0 0x00000309\r | |
879 | #define MSR_CORE2_PERF_FIXED_CTR1 0x0000030A\r | |
880 | #define MSR_CORE2_PERF_FIXED_CTR2 0x0000030B\r | |
881 | /// @}\r | |
882 | \r | |
883 | \r | |
884 | /**\r | |
885 | Unique. RO. This applies to processors that do not support architectural\r | |
886 | perfmon version 2.\r | |
887 | \r | |
888 | @param ECX MSR_CORE2_PERF_CAPABILITIES (0x00000345)\r | |
889 | @param EAX Lower 32-bits of MSR value.\r | |
890 | Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.\r | |
891 | @param EDX Upper 32-bits of MSR value.\r | |
892 | Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.\r | |
893 | \r | |
894 | <b>Example usage</b>\r | |
895 | @code\r | |
896 | MSR_CORE2_PERF_CAPABILITIES_REGISTER Msr;\r | |
897 | \r | |
898 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_CAPABILITIES);\r | |
899 | AsmWriteMsr64 (MSR_CORE2_PERF_CAPABILITIES, Msr.Uint64);\r | |
900 | @endcode\r | |
901 | @note MSR_CORE2_PERF_CAPABILITIES is defined as MSR_PERF_CAPABILITIES in SDM.\r | |
902 | **/\r | |
903 | #define MSR_CORE2_PERF_CAPABILITIES 0x00000345\r | |
904 | \r | |
905 | /**\r | |
906 | MSR information returned for MSR index #MSR_CORE2_PERF_CAPABILITIES\r | |
907 | **/\r | |
908 | typedef union {\r | |
909 | ///\r | |
910 | /// Individual bit fields\r | |
911 | ///\r | |
912 | struct {\r | |
913 | ///\r | |
914 | /// [Bits 5:0] LBR Format. See Table 35-2.\r | |
915 | ///\r | |
916 | UINT32 LBR_FMT:6;\r | |
917 | ///\r | |
918 | /// [Bit 6] PEBS Record Format.\r | |
919 | ///\r | |
920 | UINT32 PEBS_FMT:1;\r | |
921 | ///\r | |
922 | /// [Bit 7] PEBSSaveArchRegs. See Table 35-2.\r | |
923 | ///\r | |
924 | UINT32 PEBS_ARCH_REG:1;\r | |
925 | UINT32 Reserved1:24;\r | |
926 | UINT32 Reserved2:32;\r | |
927 | } Bits;\r | |
928 | ///\r | |
929 | /// All bit fields as a 32-bit value\r | |
930 | ///\r | |
931 | UINT32 Uint32;\r | |
932 | ///\r | |
933 | /// All bit fields as a 64-bit value\r | |
934 | ///\r | |
935 | UINT64 Uint64;\r | |
936 | } MSR_CORE2_PERF_CAPABILITIES_REGISTER;\r | |
937 | \r | |
938 | \r | |
939 | /**\r | |
940 | Unique. Fixed-Function-Counter Control Register (R/W).\r | |
941 | \r | |
942 | @param ECX MSR_CORE2_PERF_FIXED_CTR_CTRL (0x0000038D)\r | |
943 | @param EAX Lower 32-bits of MSR value.\r | |
944 | @param EDX Upper 32-bits of MSR value.\r | |
945 | \r | |
946 | <b>Example usage</b>\r | |
947 | @code\r | |
948 | UINT64 Msr;\r | |
949 | \r | |
950 | Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL);\r | |
951 | AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL, Msr);\r | |
952 | @endcode\r | |
953 | @note MSR_CORE2_PERF_FIXED_CTR_CTRL is defined as MSR_PERF_FIXED_CTR_CTRL in SDM.\r | |
954 | **/\r | |
955 | #define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D\r | |
956 | \r | |
957 | \r | |
958 | /**\r | |
959 | Unique. See Section 18.4.2, "Global Counter Control Facilities.".\r | |
960 | \r | |
961 | @param ECX MSR_CORE2_PERF_GLOBAL_STATUS (0x0000038E)\r | |
962 | @param EAX Lower 32-bits of MSR value.\r | |
963 | @param EDX Upper 32-bits of MSR value.\r | |
964 | \r | |
965 | <b>Example usage</b>\r | |
966 | @code\r | |
967 | UINT64 Msr;\r | |
968 | \r | |
969 | Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS);\r | |
970 | AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS, Msr);\r | |
971 | @endcode\r | |
972 | @note MSR_CORE2_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.\r | |
973 | **/\r | |
974 | #define MSR_CORE2_PERF_GLOBAL_STATUS 0x0000038E\r | |
975 | \r | |
976 | \r | |
977 | /**\r | |
978 | Unique. See Section 18.4.2, "Global Counter Control Facilities.".\r | |
979 | \r | |
980 | @param ECX MSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F)\r | |
981 | @param EAX Lower 32-bits of MSR value.\r | |
982 | @param EDX Upper 32-bits of MSR value.\r | |
983 | \r | |
984 | <b>Example usage</b>\r | |
985 | @code\r | |
986 | UINT64 Msr;\r | |
987 | \r | |
988 | Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL);\r | |
989 | AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL, Msr);\r | |
990 | @endcode\r | |
991 | @note MSR_CORE2_PERF_GLOBAL_CTRL is defined as MSR_PERF_GLOBAL_CTRL in SDM.\r | |
992 | **/\r | |
993 | #define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F\r | |
994 | \r | |
995 | \r | |
996 | /**\r | |
997 | Unique. See Section 18.4.2, "Global Counter Control Facilities.".\r | |
998 | \r | |
999 | @param ECX MSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390)\r | |
1000 | @param EAX Lower 32-bits of MSR value.\r | |
1001 | @param EDX Upper 32-bits of MSR value.\r | |
1002 | \r | |
1003 | <b>Example usage</b>\r | |
1004 | @code\r | |
1005 | UINT64 Msr;\r | |
1006 | \r | |
1007 | Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL);\r | |
1008 | AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL, Msr);\r | |
1009 | @endcode\r | |
1010 | @note MSR_CORE2_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.\r | |
1011 | **/\r | |
1012 | #define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390\r | |
1013 | \r | |
1014 | \r | |
1015 | /**\r | |
1016 | Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling\r | |
1017 | (PEBS).".\r | |
1018 | \r | |
1019 | @param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1)\r | |
1020 | @param EAX Lower 32-bits of MSR value.\r | |
1021 | Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.\r | |
1022 | @param EDX Upper 32-bits of MSR value.\r | |
1023 | Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.\r | |
1024 | \r | |
1025 | <b>Example usage</b>\r | |
1026 | @code\r | |
1027 | MSR_CORE2_PEBS_ENABLE_REGISTER Msr;\r | |
1028 | \r | |
1029 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PEBS_ENABLE);\r | |
1030 | AsmWriteMsr64 (MSR_CORE2_PEBS_ENABLE, Msr.Uint64);\r | |
1031 | @endcode\r | |
1032 | @note MSR_CORE2_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r | |
1033 | **/\r | |
1034 | #define MSR_CORE2_PEBS_ENABLE 0x000003F1\r | |
1035 | \r | |
1036 | /**\r | |
1037 | MSR information returned for MSR index #MSR_CORE2_PEBS_ENABLE\r | |
1038 | **/\r | |
1039 | typedef union {\r | |
1040 | ///\r | |
1041 | /// Individual bit fields\r | |
1042 | ///\r | |
1043 | struct {\r | |
1044 | ///\r | |
1045 | /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r | |
1046 | ///\r | |
1047 | UINT32 Enable:1;\r | |
1048 | UINT32 Reserved1:31;\r | |
1049 | UINT32 Reserved2:32;\r | |
1050 | } Bits;\r | |
1051 | ///\r | |
1052 | /// All bit fields as a 32-bit value\r | |
1053 | ///\r | |
1054 | UINT32 Uint32;\r | |
1055 | ///\r | |
1056 | /// All bit fields as a 64-bit value\r | |
1057 | ///\r | |
1058 | UINT64 Uint64;\r | |
1059 | } MSR_CORE2_PEBS_ENABLE_REGISTER;\r | |
1060 | \r | |
1061 | \r | |
1062 | /**\r | |
1063 | Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon\r | |
1064 | processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.\r | |
1065 | \r | |
1066 | @param ECX MSR_CORE2_EMON_L3_CTR_CTLn\r | |
1067 | @param EAX Lower 32-bits of MSR value.\r | |
1068 | @param EDX Upper 32-bits of MSR value.\r | |
1069 | \r | |
1070 | <b>Example usage</b>\r | |
1071 | @code\r | |
1072 | UINT64 Msr;\r | |
1073 | \r | |
1074 | Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0);\r | |
1075 | AsmWriteMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0, Msr);\r | |
1076 | @endcode\r | |
1077 | @note MSR_CORE2_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.\r | |
1078 | MSR_CORE2_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.\r | |
1079 | MSR_CORE2_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.\r | |
1080 | MSR_CORE2_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.\r | |
1081 | MSR_CORE2_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.\r | |
1082 | MSR_CORE2_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.\r | |
1083 | MSR_CORE2_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.\r | |
1084 | MSR_CORE2_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.\r | |
1085 | @{\r | |
1086 | **/\r | |
1087 | #define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC\r | |
1088 | #define MSR_CORE2_EMON_L3_CTR_CTL1 0x000107CD\r | |
1089 | #define MSR_CORE2_EMON_L3_CTR_CTL2 0x000107CE\r | |
1090 | #define MSR_CORE2_EMON_L3_CTR_CTL3 0x000107CF\r | |
1091 | #define MSR_CORE2_EMON_L3_CTR_CTL4 0x000107D0\r | |
1092 | #define MSR_CORE2_EMON_L3_CTR_CTL5 0x000107D1\r | |
1093 | #define MSR_CORE2_EMON_L3_CTR_CTL6 0x000107D2\r | |
1094 | #define MSR_CORE2_EMON_L3_CTR_CTL7 0x000107D3\r | |
1095 | /// @}\r | |
1096 | \r | |
1097 | \r | |
1098 | /**\r | |
1099 | Unique. L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor\r | |
1100 | 7400 series (processor signature 06_1D) only. See Section 17.2.2.\r | |
1101 | \r | |
1102 | @param ECX MSR_CORE2_EMON_L3_GL_CTL (0x000107D8)\r | |
1103 | @param EAX Lower 32-bits of MSR value.\r | |
1104 | @param EDX Upper 32-bits of MSR value.\r | |
1105 | \r | |
1106 | <b>Example usage</b>\r | |
1107 | @code\r | |
1108 | UINT64 Msr;\r | |
1109 | \r | |
1110 | Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_GL_CTL);\r | |
1111 | AsmWriteMsr64 (MSR_CORE2_EMON_L3_GL_CTL, Msr);\r | |
1112 | @endcode\r | |
1113 | @note MSR_CORE2_EMON_L3_GL_CTL is defined as MSR_EMON_L3_GL_CTL in SDM.\r | |
1114 | **/\r | |
1115 | #define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8\r | |
1116 | \r | |
1117 | #endif\r |