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1 | /** @file\r | |
2 | SMM CPU misc functions for x64 arch specific.\r | |
3 | \r | |
4 | Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include "PiSmmCpuDxeSmm.h"\r | |
16 | \r | |
17 | /**\r | |
18 | Initialize Gdt for all processors.\r | |
19 | \r | |
20 | @param[in] Cr3 CR3 value.\r | |
21 | @param[out] GdtStepSize The step size for GDT table.\r | |
22 | \r | |
23 | @return GdtBase for processor 0.\r | |
24 | GdtBase for processor X is: GdtBase + (GdtStepSize * X)\r | |
25 | **/\r | |
26 | VOID *\r | |
27 | InitGdt (\r | |
28 | IN UINTN Cr3,\r | |
29 | OUT UINTN *GdtStepSize\r | |
30 | )\r | |
31 | {\r | |
32 | UINTN Index;\r | |
33 | IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;\r | |
34 | UINTN TssBase;\r | |
35 | UINTN GdtTssTableSize;\r | |
36 | UINT8 *GdtTssTables;\r | |
37 | UINTN GdtTableStepSize;\r | |
38 | \r | |
39 | //\r | |
40 | // For X64 SMM, we allocate separate GDT/TSS for each CPUs to avoid TSS load contention\r | |
41 | // on each SMI entry.\r | |
42 | //\r | |
43 | GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + 7) & ~7; // 8 bytes aligned\r | |
44 | GdtTssTables = (UINT8*)AllocatePages (EFI_SIZE_TO_PAGES (GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus));\r | |
45 | ASSERT (GdtTssTables != NULL);\r | |
46 | GdtTableStepSize = GdtTssTableSize;\r | |
47 | \r | |
48 | for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {\r | |
49 | CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE);\r | |
50 | \r | |
51 | //\r | |
52 | // Fixup TSS descriptors\r | |
53 | //\r | |
54 | TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);\r | |
55 | GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;\r | |
56 | GdtDescriptor->Bits.BaseLow = (UINT16)(UINTN)TssBase;\r | |
57 | GdtDescriptor->Bits.BaseMid = (UINT8)((UINTN)TssBase >> 16);\r | |
58 | GdtDescriptor->Bits.BaseHigh = (UINT8)((UINTN)TssBase >> 24);\r | |
59 | \r | |
60 | if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r | |
61 | //\r | |
62 | // Setup top of known good stack as IST1 for each processor.\r | |
63 | //\r | |
64 | *(UINTN *)(TssBase + TSS_X64_IST1_OFFSET) = (mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize);\r | |
65 | }\r | |
66 | }\r | |
67 | \r | |
68 | *GdtStepSize = GdtTableStepSize;\r | |
69 | return GdtTssTables;\r | |
70 | }\r |