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1 | /* | |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This header defines architecture specific interfaces, x86 version | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
7 | * the COPYING file in the top-level directory. | |
8 | * | |
9 | */ | |
10 | ||
11 | #ifndef _ASM_X86_KVM_HOST_H | |
12 | #define _ASM_X86_KVM_HOST_H | |
13 | ||
14 | #include <linux/types.h> | |
15 | #include <linux/mm.h> | |
16 | #include <linux/mmu_notifier.h> | |
17 | #include <linux/tracepoint.h> | |
18 | #include <linux/cpumask.h> | |
19 | #include <linux/irq_work.h> | |
20 | ||
21 | #include <linux/kvm.h> | |
22 | #include <linux/kvm_para.h> | |
23 | #include <linux/kvm_types.h> | |
24 | #include <linux/perf_event.h> | |
25 | #include <linux/pvclock_gtod.h> | |
26 | #include <linux/clocksource.h> | |
27 | #include <linux/irqbypass.h> | |
28 | #include <linux/hyperv.h> | |
29 | ||
30 | #include <asm/apic.h> | |
31 | #include <asm/pvclock-abi.h> | |
32 | #include <asm/desc.h> | |
33 | #include <asm/mtrr.h> | |
34 | #include <asm/msr-index.h> | |
35 | #include <asm/asm.h> | |
36 | #include <asm/kvm_page_track.h> | |
37 | ||
38 | #define KVM_MAX_VCPUS 288 | |
39 | #define KVM_SOFT_MAX_VCPUS 240 | |
40 | #define KVM_MAX_VCPU_ID 1023 | |
41 | #define KVM_USER_MEM_SLOTS 509 | |
42 | /* memory slots that are not exposed to userspace */ | |
43 | #define KVM_PRIVATE_MEM_SLOTS 3 | |
44 | #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) | |
45 | ||
46 | #define KVM_HALT_POLL_NS_DEFAULT 200000 | |
47 | ||
48 | #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS | |
49 | ||
50 | /* x86-specific vcpu->requests bit members */ | |
51 | #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0) | |
52 | #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1) | |
53 | #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2) | |
54 | #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3) | |
55 | #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4) | |
56 | #define KVM_REQ_EVENT KVM_ARCH_REQ(6) | |
57 | #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7) | |
58 | #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8) | |
59 | #define KVM_REQ_NMI KVM_ARCH_REQ(9) | |
60 | #define KVM_REQ_PMU KVM_ARCH_REQ(10) | |
61 | #define KVM_REQ_PMI KVM_ARCH_REQ(11) | |
62 | #define KVM_REQ_SMI KVM_ARCH_REQ(12) | |
63 | #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13) | |
64 | #define KVM_REQ_MCLOCK_INPROGRESS \ | |
65 | KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) | |
66 | #define KVM_REQ_SCAN_IOAPIC \ | |
67 | KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) | |
68 | #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16) | |
69 | #define KVM_REQ_APIC_PAGE_RELOAD \ | |
70 | KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) | |
71 | #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18) | |
72 | #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19) | |
73 | #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20) | |
74 | #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21) | |
75 | #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22) | |
76 | ||
77 | #define CR0_RESERVED_BITS \ | |
78 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
79 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
80 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
81 | ||
82 | #define CR3_L_MODE_RESERVED_BITS 0xFFFFFF0000000000ULL | |
83 | #define CR3_PCID_INVD BIT_64(63) | |
84 | #define CR4_RESERVED_BITS \ | |
85 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
86 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
87 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ | |
88 | | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ | |
89 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE | X86_CR4_SMAP \ | |
90 | | X86_CR4_PKE)) | |
91 | ||
92 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
93 | ||
94 | ||
95 | ||
96 | #define INVALID_PAGE (~(hpa_t)0) | |
97 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) | |
98 | ||
99 | #define UNMAPPED_GVA (~(gpa_t)0) | |
100 | ||
101 | /* KVM Hugepage definitions for x86 */ | |
102 | #define KVM_NR_PAGE_SIZES 3 | |
103 | #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) | |
104 | #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) | |
105 | #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) | |
106 | #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) | |
107 | #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) | |
108 | ||
109 | static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) | |
110 | { | |
111 | /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */ | |
112 | return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - | |
113 | (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
114 | } | |
115 | ||
116 | #define KVM_PERMILLE_MMU_PAGES 20 | |
117 | #define KVM_MIN_ALLOC_MMU_PAGES 64 | |
118 | #define KVM_MMU_HASH_SHIFT 12 | |
119 | #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) | |
120 | #define KVM_MIN_FREE_MMU_PAGES 5 | |
121 | #define KVM_REFILL_PAGES 25 | |
122 | #define KVM_MAX_CPUID_ENTRIES 80 | |
123 | #define KVM_NR_FIXED_MTRR_REGION 88 | |
124 | #define KVM_NR_VAR_MTRR 8 | |
125 | ||
126 | #define ASYNC_PF_PER_VCPU 64 | |
127 | ||
128 | enum kvm_reg { | |
129 | VCPU_REGS_RAX = 0, | |
130 | VCPU_REGS_RCX = 1, | |
131 | VCPU_REGS_RDX = 2, | |
132 | VCPU_REGS_RBX = 3, | |
133 | VCPU_REGS_RSP = 4, | |
134 | VCPU_REGS_RBP = 5, | |
135 | VCPU_REGS_RSI = 6, | |
136 | VCPU_REGS_RDI = 7, | |
137 | #ifdef CONFIG_X86_64 | |
138 | VCPU_REGS_R8 = 8, | |
139 | VCPU_REGS_R9 = 9, | |
140 | VCPU_REGS_R10 = 10, | |
141 | VCPU_REGS_R11 = 11, | |
142 | VCPU_REGS_R12 = 12, | |
143 | VCPU_REGS_R13 = 13, | |
144 | VCPU_REGS_R14 = 14, | |
145 | VCPU_REGS_R15 = 15, | |
146 | #endif | |
147 | VCPU_REGS_RIP, | |
148 | NR_VCPU_REGS | |
149 | }; | |
150 | ||
151 | enum kvm_reg_ex { | |
152 | VCPU_EXREG_PDPTR = NR_VCPU_REGS, | |
153 | VCPU_EXREG_CR3, | |
154 | VCPU_EXREG_RFLAGS, | |
155 | VCPU_EXREG_SEGMENTS, | |
156 | }; | |
157 | ||
158 | enum { | |
159 | VCPU_SREG_ES, | |
160 | VCPU_SREG_CS, | |
161 | VCPU_SREG_SS, | |
162 | VCPU_SREG_DS, | |
163 | VCPU_SREG_FS, | |
164 | VCPU_SREG_GS, | |
165 | VCPU_SREG_TR, | |
166 | VCPU_SREG_LDTR, | |
167 | }; | |
168 | ||
169 | #include <asm/kvm_emulate.h> | |
170 | ||
171 | #define KVM_NR_MEM_OBJS 40 | |
172 | ||
173 | #define KVM_NR_DB_REGS 4 | |
174 | ||
175 | #define DR6_BD (1 << 13) | |
176 | #define DR6_BS (1 << 14) | |
177 | #define DR6_RTM (1 << 16) | |
178 | #define DR6_FIXED_1 0xfffe0ff0 | |
179 | #define DR6_INIT 0xffff0ff0 | |
180 | #define DR6_VOLATILE 0x0001e00f | |
181 | ||
182 | #define DR7_BP_EN_MASK 0x000000ff | |
183 | #define DR7_GE (1 << 9) | |
184 | #define DR7_GD (1 << 13) | |
185 | #define DR7_FIXED_1 0x00000400 | |
186 | #define DR7_VOLATILE 0xffff2bff | |
187 | ||
188 | #define PFERR_PRESENT_BIT 0 | |
189 | #define PFERR_WRITE_BIT 1 | |
190 | #define PFERR_USER_BIT 2 | |
191 | #define PFERR_RSVD_BIT 3 | |
192 | #define PFERR_FETCH_BIT 4 | |
193 | #define PFERR_PK_BIT 5 | |
194 | #define PFERR_GUEST_FINAL_BIT 32 | |
195 | #define PFERR_GUEST_PAGE_BIT 33 | |
196 | ||
197 | #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) | |
198 | #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) | |
199 | #define PFERR_USER_MASK (1U << PFERR_USER_BIT) | |
200 | #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) | |
201 | #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) | |
202 | #define PFERR_PK_MASK (1U << PFERR_PK_BIT) | |
203 | #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT) | |
204 | #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT) | |
205 | ||
206 | #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ | |
207 | PFERR_USER_MASK | \ | |
208 | PFERR_WRITE_MASK | \ | |
209 | PFERR_PRESENT_MASK) | |
210 | ||
211 | /* | |
212 | * The mask used to denote special SPTEs, which can be either MMIO SPTEs or | |
213 | * Access Tracking SPTEs. We use bit 62 instead of bit 63 to avoid conflicting | |
214 | * with the SVE bit in EPT PTEs. | |
215 | */ | |
216 | #define SPTE_SPECIAL_MASK (1ULL << 62) | |
217 | ||
218 | /* apic attention bits */ | |
219 | #define KVM_APIC_CHECK_VAPIC 0 | |
220 | /* | |
221 | * The following bit is set with PV-EOI, unset on EOI. | |
222 | * We detect PV-EOI changes by guest by comparing | |
223 | * this bit with PV-EOI in guest memory. | |
224 | * See the implementation in apic_update_pv_eoi. | |
225 | */ | |
226 | #define KVM_APIC_PV_EOI_PENDING 1 | |
227 | ||
228 | struct kvm_kernel_irq_routing_entry; | |
229 | ||
230 | /* | |
231 | * We don't want allocation failures within the mmu code, so we preallocate | |
232 | * enough memory for a single page fault in a cache. | |
233 | */ | |
234 | struct kvm_mmu_memory_cache { | |
235 | int nobjs; | |
236 | void *objects[KVM_NR_MEM_OBJS]; | |
237 | }; | |
238 | ||
239 | /* | |
240 | * the pages used as guest page table on soft mmu are tracked by | |
241 | * kvm_memory_slot.arch.gfn_track which is 16 bits, so the role bits used | |
242 | * by indirect shadow page can not be more than 15 bits. | |
243 | * | |
244 | * Currently, we used 14 bits that are @level, @cr4_pae, @quadrant, @access, | |
245 | * @nxe, @cr0_wp, @smep_andnot_wp and @smap_andnot_wp. | |
246 | */ | |
247 | union kvm_mmu_page_role { | |
248 | unsigned word; | |
249 | struct { | |
250 | unsigned level:4; | |
251 | unsigned cr4_pae:1; | |
252 | unsigned quadrant:2; | |
253 | unsigned direct:1; | |
254 | unsigned access:3; | |
255 | unsigned invalid:1; | |
256 | unsigned nxe:1; | |
257 | unsigned cr0_wp:1; | |
258 | unsigned smep_andnot_wp:1; | |
259 | unsigned smap_andnot_wp:1; | |
260 | unsigned ad_disabled:1; | |
261 | unsigned :7; | |
262 | ||
263 | /* | |
264 | * This is left at the top of the word so that | |
265 | * kvm_memslots_for_spte_role can extract it with a | |
266 | * simple shift. While there is room, give it a whole | |
267 | * byte so it is also faster to load it from memory. | |
268 | */ | |
269 | unsigned smm:8; | |
270 | }; | |
271 | }; | |
272 | ||
273 | struct kvm_rmap_head { | |
274 | unsigned long val; | |
275 | }; | |
276 | ||
277 | struct kvm_mmu_page { | |
278 | struct list_head link; | |
279 | struct hlist_node hash_link; | |
280 | ||
281 | /* | |
282 | * The following two entries are used to key the shadow page in the | |
283 | * hash table. | |
284 | */ | |
285 | gfn_t gfn; | |
286 | union kvm_mmu_page_role role; | |
287 | ||
288 | u64 *spt; | |
289 | /* hold the gfn of each spte inside spt */ | |
290 | gfn_t *gfns; | |
291 | bool unsync; | |
292 | int root_count; /* Currently serving as active root */ | |
293 | unsigned int unsync_children; | |
294 | struct kvm_rmap_head parent_ptes; /* rmap pointers to parent sptes */ | |
295 | ||
296 | /* The page is obsolete if mmu_valid_gen != kvm->arch.mmu_valid_gen. */ | |
297 | unsigned long mmu_valid_gen; | |
298 | ||
299 | DECLARE_BITMAP(unsync_child_bitmap, 512); | |
300 | ||
301 | #ifdef CONFIG_X86_32 | |
302 | /* | |
303 | * Used out of the mmu-lock to avoid reading spte values while an | |
304 | * update is in progress; see the comments in __get_spte_lockless(). | |
305 | */ | |
306 | int clear_spte_count; | |
307 | #endif | |
308 | ||
309 | /* Number of writes since the last time traversal visited this page. */ | |
310 | atomic_t write_flooding_count; | |
311 | }; | |
312 | ||
313 | struct kvm_pio_request { | |
314 | unsigned long count; | |
315 | int in; | |
316 | int port; | |
317 | int size; | |
318 | }; | |
319 | ||
320 | struct rsvd_bits_validate { | |
321 | u64 rsvd_bits_mask[2][4]; | |
322 | u64 bad_mt_xwr; | |
323 | }; | |
324 | ||
325 | /* | |
326 | * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level | |
327 | * 32-bit). The kvm_mmu structure abstracts the details of the current mmu | |
328 | * mode. | |
329 | */ | |
330 | struct kvm_mmu { | |
331 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); | |
332 | unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); | |
333 | u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); | |
334 | int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, | |
335 | bool prefault); | |
336 | void (*inject_page_fault)(struct kvm_vcpu *vcpu, | |
337 | struct x86_exception *fault); | |
338 | gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, | |
339 | struct x86_exception *exception); | |
340 | gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, | |
341 | struct x86_exception *exception); | |
342 | int (*sync_page)(struct kvm_vcpu *vcpu, | |
343 | struct kvm_mmu_page *sp); | |
344 | void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva); | |
345 | void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
346 | u64 *spte, const void *pte); | |
347 | hpa_t root_hpa; | |
348 | union kvm_mmu_page_role base_role; | |
349 | u8 root_level; | |
350 | u8 shadow_root_level; | |
351 | u8 ept_ad; | |
352 | bool direct_map; | |
353 | ||
354 | /* | |
355 | * Bitmap; bit set = permission fault | |
356 | * Byte index: page fault error code [4:1] | |
357 | * Bit index: pte permissions in ACC_* format | |
358 | */ | |
359 | u8 permissions[16]; | |
360 | ||
361 | /* | |
362 | * The pkru_mask indicates if protection key checks are needed. It | |
363 | * consists of 16 domains indexed by page fault error code bits [4:1], | |
364 | * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables. | |
365 | * Each domain has 2 bits which are ANDed with AD and WD from PKRU. | |
366 | */ | |
367 | u32 pkru_mask; | |
368 | ||
369 | u64 *pae_root; | |
370 | u64 *lm_root; | |
371 | ||
372 | /* | |
373 | * check zero bits on shadow page table entries, these | |
374 | * bits include not only hardware reserved bits but also | |
375 | * the bits spte never used. | |
376 | */ | |
377 | struct rsvd_bits_validate shadow_zero_check; | |
378 | ||
379 | struct rsvd_bits_validate guest_rsvd_check; | |
380 | ||
381 | /* Can have large pages at levels 2..last_nonleaf_level-1. */ | |
382 | u8 last_nonleaf_level; | |
383 | ||
384 | bool nx; | |
385 | ||
386 | u64 pdptrs[4]; /* pae */ | |
387 | }; | |
388 | ||
389 | enum pmc_type { | |
390 | KVM_PMC_GP = 0, | |
391 | KVM_PMC_FIXED, | |
392 | }; | |
393 | ||
394 | struct kvm_pmc { | |
395 | enum pmc_type type; | |
396 | u8 idx; | |
397 | u64 counter; | |
398 | u64 eventsel; | |
399 | struct perf_event *perf_event; | |
400 | struct kvm_vcpu *vcpu; | |
401 | }; | |
402 | ||
403 | struct kvm_pmu { | |
404 | unsigned nr_arch_gp_counters; | |
405 | unsigned nr_arch_fixed_counters; | |
406 | unsigned available_event_types; | |
407 | u64 fixed_ctr_ctrl; | |
408 | u64 global_ctrl; | |
409 | u64 global_status; | |
410 | u64 global_ovf_ctrl; | |
411 | u64 counter_bitmask[2]; | |
412 | u64 global_ctrl_mask; | |
413 | u64 reserved_bits; | |
414 | u8 version; | |
415 | struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; | |
416 | struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; | |
417 | struct irq_work irq_work; | |
418 | u64 reprogram_pmi; | |
419 | }; | |
420 | ||
421 | struct kvm_pmu_ops; | |
422 | ||
423 | enum { | |
424 | KVM_DEBUGREG_BP_ENABLED = 1, | |
425 | KVM_DEBUGREG_WONT_EXIT = 2, | |
426 | KVM_DEBUGREG_RELOAD = 4, | |
427 | }; | |
428 | ||
429 | struct kvm_mtrr_range { | |
430 | u64 base; | |
431 | u64 mask; | |
432 | struct list_head node; | |
433 | }; | |
434 | ||
435 | struct kvm_mtrr { | |
436 | struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; | |
437 | mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; | |
438 | u64 deftype; | |
439 | ||
440 | struct list_head head; | |
441 | }; | |
442 | ||
443 | /* Hyper-V SynIC timer */ | |
444 | struct kvm_vcpu_hv_stimer { | |
445 | struct hrtimer timer; | |
446 | int index; | |
447 | u64 config; | |
448 | u64 count; | |
449 | u64 exp_time; | |
450 | struct hv_message msg; | |
451 | bool msg_pending; | |
452 | }; | |
453 | ||
454 | /* Hyper-V synthetic interrupt controller (SynIC)*/ | |
455 | struct kvm_vcpu_hv_synic { | |
456 | u64 version; | |
457 | u64 control; | |
458 | u64 msg_page; | |
459 | u64 evt_page; | |
460 | atomic64_t sint[HV_SYNIC_SINT_COUNT]; | |
461 | atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT]; | |
462 | DECLARE_BITMAP(auto_eoi_bitmap, 256); | |
463 | DECLARE_BITMAP(vec_bitmap, 256); | |
464 | bool active; | |
465 | bool dont_zero_synic_pages; | |
466 | }; | |
467 | ||
468 | /* Hyper-V per vcpu emulation context */ | |
469 | struct kvm_vcpu_hv { | |
470 | u64 hv_vapic; | |
471 | s64 runtime_offset; | |
472 | struct kvm_vcpu_hv_synic synic; | |
473 | struct kvm_hyperv_exit exit; | |
474 | struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT]; | |
475 | DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT); | |
476 | }; | |
477 | ||
478 | struct kvm_vcpu_arch { | |
479 | /* | |
480 | * rip and regs accesses must go through | |
481 | * kvm_{register,rip}_{read,write} functions. | |
482 | */ | |
483 | unsigned long regs[NR_VCPU_REGS]; | |
484 | u32 regs_avail; | |
485 | u32 regs_dirty; | |
486 | ||
487 | unsigned long cr0; | |
488 | unsigned long cr0_guest_owned_bits; | |
489 | unsigned long cr2; | |
490 | unsigned long cr3; | |
491 | unsigned long cr4; | |
492 | unsigned long cr4_guest_owned_bits; | |
493 | unsigned long cr8; | |
494 | u32 hflags; | |
495 | u64 efer; | |
496 | u64 apic_base; | |
497 | struct kvm_lapic *apic; /* kernel irqchip context */ | |
498 | bool apicv_active; | |
499 | DECLARE_BITMAP(ioapic_handled_vectors, 256); | |
500 | unsigned long apic_attention; | |
501 | int32_t apic_arb_prio; | |
502 | int mp_state; | |
503 | u64 ia32_misc_enable_msr; | |
504 | u64 smbase; | |
505 | bool tpr_access_reporting; | |
506 | u64 ia32_xss; | |
507 | ||
508 | /* | |
509 | * Paging state of the vcpu | |
510 | * | |
511 | * If the vcpu runs in guest mode with two level paging this still saves | |
512 | * the paging mode of the l1 guest. This context is always used to | |
513 | * handle faults. | |
514 | */ | |
515 | struct kvm_mmu mmu; | |
516 | ||
517 | /* | |
518 | * Paging state of an L2 guest (used for nested npt) | |
519 | * | |
520 | * This context will save all necessary information to walk page tables | |
521 | * of the an L2 guest. This context is only initialized for page table | |
522 | * walking and not for faulting since we never handle l2 page faults on | |
523 | * the host. | |
524 | */ | |
525 | struct kvm_mmu nested_mmu; | |
526 | ||
527 | /* | |
528 | * Pointer to the mmu context currently used for | |
529 | * gva_to_gpa translations. | |
530 | */ | |
531 | struct kvm_mmu *walk_mmu; | |
532 | ||
533 | struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; | |
534 | struct kvm_mmu_memory_cache mmu_page_cache; | |
535 | struct kvm_mmu_memory_cache mmu_page_header_cache; | |
536 | ||
537 | struct fpu guest_fpu; | |
538 | u64 xcr0; | |
539 | u64 guest_supported_xcr0; | |
540 | u32 guest_xstate_size; | |
541 | ||
542 | struct kvm_pio_request pio; | |
543 | void *pio_data; | |
544 | ||
545 | u8 event_exit_inst_len; | |
546 | ||
547 | struct kvm_queued_exception { | |
548 | bool pending; | |
549 | bool has_error_code; | |
550 | bool reinject; | |
551 | u8 nr; | |
552 | u32 error_code; | |
553 | } exception; | |
554 | ||
555 | struct kvm_queued_interrupt { | |
556 | bool pending; | |
557 | bool soft; | |
558 | u8 nr; | |
559 | } interrupt; | |
560 | ||
561 | int halt_request; /* real mode on Intel only */ | |
562 | ||
563 | int cpuid_nent; | |
564 | struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; | |
565 | ||
566 | int maxphyaddr; | |
567 | ||
568 | /* emulate context */ | |
569 | ||
570 | struct x86_emulate_ctxt emulate_ctxt; | |
571 | bool emulate_regs_need_sync_to_vcpu; | |
572 | bool emulate_regs_need_sync_from_vcpu; | |
573 | int (*complete_userspace_io)(struct kvm_vcpu *vcpu); | |
574 | ||
575 | gpa_t time; | |
576 | struct pvclock_vcpu_time_info hv_clock; | |
577 | unsigned int hw_tsc_khz; | |
578 | struct gfn_to_hva_cache pv_time; | |
579 | bool pv_time_enabled; | |
580 | /* set guest stopped flag in pvclock flags field */ | |
581 | bool pvclock_set_guest_stopped_request; | |
582 | ||
583 | struct { | |
584 | u64 msr_val; | |
585 | u64 last_steal; | |
586 | struct gfn_to_hva_cache stime; | |
587 | struct kvm_steal_time steal; | |
588 | } st; | |
589 | ||
590 | u64 tsc_offset; | |
591 | u64 last_guest_tsc; | |
592 | u64 last_host_tsc; | |
593 | u64 tsc_offset_adjustment; | |
594 | u64 this_tsc_nsec; | |
595 | u64 this_tsc_write; | |
596 | u64 this_tsc_generation; | |
597 | bool tsc_catchup; | |
598 | bool tsc_always_catchup; | |
599 | s8 virtual_tsc_shift; | |
600 | u32 virtual_tsc_mult; | |
601 | u32 virtual_tsc_khz; | |
602 | s64 ia32_tsc_adjust_msr; | |
603 | u64 tsc_scaling_ratio; | |
604 | ||
605 | atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ | |
606 | unsigned nmi_pending; /* NMI queued after currently running handler */ | |
607 | bool nmi_injected; /* Trying to inject an NMI this entry */ | |
608 | bool smi_pending; /* SMI queued after currently running handler */ | |
609 | ||
610 | struct kvm_mtrr mtrr_state; | |
611 | u64 pat; | |
612 | ||
613 | unsigned switch_db_regs; | |
614 | unsigned long db[KVM_NR_DB_REGS]; | |
615 | unsigned long dr6; | |
616 | unsigned long dr7; | |
617 | unsigned long eff_db[KVM_NR_DB_REGS]; | |
618 | unsigned long guest_debug_dr7; | |
619 | u64 msr_platform_info; | |
620 | u64 msr_misc_features_enables; | |
621 | ||
622 | u64 mcg_cap; | |
623 | u64 mcg_status; | |
624 | u64 mcg_ctl; | |
625 | u64 mcg_ext_ctl; | |
626 | u64 *mce_banks; | |
627 | ||
628 | /* Cache MMIO info */ | |
629 | u64 mmio_gva; | |
630 | unsigned access; | |
631 | gfn_t mmio_gfn; | |
632 | u64 mmio_gen; | |
633 | ||
634 | struct kvm_pmu pmu; | |
635 | ||
636 | /* used for guest single stepping over the given code position */ | |
637 | unsigned long singlestep_rip; | |
638 | ||
639 | struct kvm_vcpu_hv hyperv; | |
640 | ||
641 | cpumask_var_t wbinvd_dirty_mask; | |
642 | ||
643 | unsigned long last_retry_eip; | |
644 | unsigned long last_retry_addr; | |
645 | ||
646 | struct { | |
647 | bool halted; | |
648 | gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; | |
649 | struct gfn_to_hva_cache data; | |
650 | u64 msr_val; | |
651 | u32 id; | |
652 | bool send_user_only; | |
653 | } apf; | |
654 | ||
655 | /* OSVW MSRs (AMD only) */ | |
656 | struct { | |
657 | u64 length; | |
658 | u64 status; | |
659 | } osvw; | |
660 | ||
661 | struct { | |
662 | u64 msr_val; | |
663 | struct gfn_to_hva_cache data; | |
664 | } pv_eoi; | |
665 | ||
666 | /* | |
667 | * Indicate whether the access faults on its page table in guest | |
668 | * which is set when fix page fault and used to detect unhandeable | |
669 | * instruction. | |
670 | */ | |
671 | bool write_fault_to_shadow_pgtable; | |
672 | ||
673 | /* set at EPT violation at this point */ | |
674 | unsigned long exit_qualification; | |
675 | ||
676 | /* pv related host specific info */ | |
677 | struct { | |
678 | bool pv_unhalted; | |
679 | } pv; | |
680 | ||
681 | int pending_ioapic_eoi; | |
682 | int pending_external_vector; | |
683 | ||
684 | /* GPA available (AMD only) */ | |
685 | bool gpa_available; | |
686 | }; | |
687 | ||
688 | struct kvm_lpage_info { | |
689 | int disallow_lpage; | |
690 | }; | |
691 | ||
692 | struct kvm_arch_memory_slot { | |
693 | struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES]; | |
694 | struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; | |
695 | unsigned short *gfn_track[KVM_PAGE_TRACK_MAX]; | |
696 | }; | |
697 | ||
698 | /* | |
699 | * We use as the mode the number of bits allocated in the LDR for the | |
700 | * logical processor ID. It happens that these are all powers of two. | |
701 | * This makes it is very easy to detect cases where the APICs are | |
702 | * configured for multiple modes; in that case, we cannot use the map and | |
703 | * hence cannot use kvm_irq_delivery_to_apic_fast either. | |
704 | */ | |
705 | #define KVM_APIC_MODE_XAPIC_CLUSTER 4 | |
706 | #define KVM_APIC_MODE_XAPIC_FLAT 8 | |
707 | #define KVM_APIC_MODE_X2APIC 16 | |
708 | ||
709 | struct kvm_apic_map { | |
710 | struct rcu_head rcu; | |
711 | u8 mode; | |
712 | u32 max_apic_id; | |
713 | union { | |
714 | struct kvm_lapic *xapic_flat_map[8]; | |
715 | struct kvm_lapic *xapic_cluster_map[16][4]; | |
716 | }; | |
717 | struct kvm_lapic *phys_map[]; | |
718 | }; | |
719 | ||
720 | /* Hyper-V emulation context */ | |
721 | struct kvm_hv { | |
722 | struct mutex hv_lock; | |
723 | u64 hv_guest_os_id; | |
724 | u64 hv_hypercall; | |
725 | u64 hv_tsc_page; | |
726 | ||
727 | /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ | |
728 | u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; | |
729 | u64 hv_crash_ctl; | |
730 | ||
731 | HV_REFERENCE_TSC_PAGE tsc_ref; | |
732 | }; | |
733 | ||
734 | enum kvm_irqchip_mode { | |
735 | KVM_IRQCHIP_NONE, | |
736 | KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */ | |
737 | KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */ | |
738 | }; | |
739 | ||
740 | struct kvm_arch { | |
741 | unsigned int n_used_mmu_pages; | |
742 | unsigned int n_requested_mmu_pages; | |
743 | unsigned int n_max_mmu_pages; | |
744 | unsigned int indirect_shadow_pages; | |
745 | unsigned long mmu_valid_gen; | |
746 | struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; | |
747 | /* | |
748 | * Hash table of struct kvm_mmu_page. | |
749 | */ | |
750 | struct list_head active_mmu_pages; | |
751 | struct list_head zapped_obsolete_pages; | |
752 | struct kvm_page_track_notifier_node mmu_sp_tracker; | |
753 | struct kvm_page_track_notifier_head track_notifier_head; | |
754 | ||
755 | struct list_head assigned_dev_head; | |
756 | struct iommu_domain *iommu_domain; | |
757 | bool iommu_noncoherent; | |
758 | #define __KVM_HAVE_ARCH_NONCOHERENT_DMA | |
759 | atomic_t noncoherent_dma_count; | |
760 | #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE | |
761 | atomic_t assigned_device_count; | |
762 | struct kvm_pic *vpic; | |
763 | struct kvm_ioapic *vioapic; | |
764 | struct kvm_pit *vpit; | |
765 | atomic_t vapics_in_nmi_mode; | |
766 | struct mutex apic_map_lock; | |
767 | struct kvm_apic_map *apic_map; | |
768 | ||
769 | unsigned int tss_addr; | |
770 | bool apic_access_page_done; | |
771 | ||
772 | gpa_t wall_clock; | |
773 | ||
774 | bool ept_identity_pagetable_done; | |
775 | gpa_t ept_identity_map_addr; | |
776 | ||
777 | unsigned long irq_sources_bitmap; | |
778 | s64 kvmclock_offset; | |
779 | raw_spinlock_t tsc_write_lock; | |
780 | u64 last_tsc_nsec; | |
781 | u64 last_tsc_write; | |
782 | u32 last_tsc_khz; | |
783 | u64 cur_tsc_nsec; | |
784 | u64 cur_tsc_write; | |
785 | u64 cur_tsc_offset; | |
786 | u64 cur_tsc_generation; | |
787 | int nr_vcpus_matched_tsc; | |
788 | ||
789 | spinlock_t pvclock_gtod_sync_lock; | |
790 | bool use_master_clock; | |
791 | u64 master_kernel_ns; | |
792 | u64 master_cycle_now; | |
793 | struct delayed_work kvmclock_update_work; | |
794 | struct delayed_work kvmclock_sync_work; | |
795 | ||
796 | struct kvm_xen_hvm_config xen_hvm_config; | |
797 | ||
798 | /* reads protected by irq_srcu, writes by irq_lock */ | |
799 | struct hlist_head mask_notifier_list; | |
800 | ||
801 | struct kvm_hv hyperv; | |
802 | ||
803 | #ifdef CONFIG_KVM_MMU_AUDIT | |
804 | int audit_point; | |
805 | #endif | |
806 | ||
807 | bool backwards_tsc_observed; | |
808 | bool boot_vcpu_runs_old_kvmclock; | |
809 | u32 bsp_vcpu_id; | |
810 | ||
811 | u64 disabled_quirks; | |
812 | ||
813 | enum kvm_irqchip_mode irqchip_mode; | |
814 | u8 nr_reserved_ioapic_pins; | |
815 | ||
816 | bool disabled_lapic_found; | |
817 | ||
818 | /* Struct members for AVIC */ | |
819 | u32 avic_vm_id; | |
820 | u32 ldr_mode; | |
821 | struct page *avic_logical_id_table_page; | |
822 | struct page *avic_physical_id_table_page; | |
823 | struct hlist_node hnode; | |
824 | ||
825 | bool x2apic_format; | |
826 | bool x2apic_broadcast_quirk_disabled; | |
827 | }; | |
828 | ||
829 | struct kvm_vm_stat { | |
830 | ulong mmu_shadow_zapped; | |
831 | ulong mmu_pte_write; | |
832 | ulong mmu_pte_updated; | |
833 | ulong mmu_pde_zapped; | |
834 | ulong mmu_flooded; | |
835 | ulong mmu_recycled; | |
836 | ulong mmu_cache_miss; | |
837 | ulong mmu_unsync; | |
838 | ulong remote_tlb_flush; | |
839 | ulong lpages; | |
840 | ulong max_mmu_page_hash_collisions; | |
841 | }; | |
842 | ||
843 | struct kvm_vcpu_stat { | |
844 | u64 pf_fixed; | |
845 | u64 pf_guest; | |
846 | u64 tlb_flush; | |
847 | u64 invlpg; | |
848 | ||
849 | u64 exits; | |
850 | u64 io_exits; | |
851 | u64 mmio_exits; | |
852 | u64 signal_exits; | |
853 | u64 irq_window_exits; | |
854 | u64 nmi_window_exits; | |
855 | u64 halt_exits; | |
856 | u64 halt_successful_poll; | |
857 | u64 halt_attempted_poll; | |
858 | u64 halt_poll_invalid; | |
859 | u64 halt_wakeup; | |
860 | u64 request_irq_exits; | |
861 | u64 irq_exits; | |
862 | u64 host_state_reload; | |
863 | u64 efer_reload; | |
864 | u64 fpu_reload; | |
865 | u64 insn_emulation; | |
866 | u64 insn_emulation_fail; | |
867 | u64 hypercalls; | |
868 | u64 irq_injections; | |
869 | u64 nmi_injections; | |
870 | u64 req_event; | |
871 | }; | |
872 | ||
873 | struct x86_instruction_info; | |
874 | ||
875 | struct msr_data { | |
876 | bool host_initiated; | |
877 | u32 index; | |
878 | u64 data; | |
879 | }; | |
880 | ||
881 | struct kvm_lapic_irq { | |
882 | u32 vector; | |
883 | u16 delivery_mode; | |
884 | u16 dest_mode; | |
885 | bool level; | |
886 | u16 trig_mode; | |
887 | u32 shorthand; | |
888 | u32 dest_id; | |
889 | bool msi_redir_hint; | |
890 | }; | |
891 | ||
892 | struct kvm_x86_ops { | |
893 | int (*cpu_has_kvm_support)(void); /* __init */ | |
894 | int (*disabled_by_bios)(void); /* __init */ | |
895 | int (*hardware_enable)(void); | |
896 | void (*hardware_disable)(void); | |
897 | void (*check_processor_compatibility)(void *rtn); | |
898 | int (*hardware_setup)(void); /* __init */ | |
899 | void (*hardware_unsetup)(void); /* __exit */ | |
900 | bool (*cpu_has_accelerated_tpr)(void); | |
901 | bool (*cpu_has_high_real_mode_segbase)(void); | |
902 | void (*cpuid_update)(struct kvm_vcpu *vcpu); | |
903 | ||
904 | int (*vm_init)(struct kvm *kvm); | |
905 | void (*vm_destroy)(struct kvm *kvm); | |
906 | ||
907 | /* Create, but do not attach this VCPU */ | |
908 | struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); | |
909 | void (*vcpu_free)(struct kvm_vcpu *vcpu); | |
910 | void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); | |
911 | ||
912 | void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); | |
913 | void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); | |
914 | void (*vcpu_put)(struct kvm_vcpu *vcpu); | |
915 | ||
916 | void (*update_bp_intercept)(struct kvm_vcpu *vcpu); | |
917 | int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); | |
918 | int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); | |
919 | u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); | |
920 | void (*get_segment)(struct kvm_vcpu *vcpu, | |
921 | struct kvm_segment *var, int seg); | |
922 | int (*get_cpl)(struct kvm_vcpu *vcpu); | |
923 | void (*set_segment)(struct kvm_vcpu *vcpu, | |
924 | struct kvm_segment *var, int seg); | |
925 | void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); | |
926 | void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); | |
927 | void (*decache_cr3)(struct kvm_vcpu *vcpu); | |
928 | void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); | |
929 | void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); | |
930 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); | |
931 | int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); | |
932 | void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); | |
933 | void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
934 | void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
935 | void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
936 | void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
937 | u64 (*get_dr6)(struct kvm_vcpu *vcpu); | |
938 | void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value); | |
939 | void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); | |
940 | void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); | |
941 | void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); | |
942 | unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); | |
943 | void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); | |
944 | u32 (*get_pkru)(struct kvm_vcpu *vcpu); | |
945 | ||
946 | void (*tlb_flush)(struct kvm_vcpu *vcpu); | |
947 | ||
948 | void (*run)(struct kvm_vcpu *vcpu); | |
949 | int (*handle_exit)(struct kvm_vcpu *vcpu); | |
950 | void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); | |
951 | void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); | |
952 | u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); | |
953 | void (*patch_hypercall)(struct kvm_vcpu *vcpu, | |
954 | unsigned char *hypercall_addr); | |
955 | void (*set_irq)(struct kvm_vcpu *vcpu); | |
956 | void (*set_nmi)(struct kvm_vcpu *vcpu); | |
957 | void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr, | |
958 | bool has_error_code, u32 error_code, | |
959 | bool reinject); | |
960 | void (*cancel_injection)(struct kvm_vcpu *vcpu); | |
961 | int (*interrupt_allowed)(struct kvm_vcpu *vcpu); | |
962 | int (*nmi_allowed)(struct kvm_vcpu *vcpu); | |
963 | bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); | |
964 | void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); | |
965 | void (*enable_nmi_window)(struct kvm_vcpu *vcpu); | |
966 | void (*enable_irq_window)(struct kvm_vcpu *vcpu); | |
967 | void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); | |
968 | bool (*get_enable_apicv)(void); | |
969 | void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu); | |
970 | void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); | |
971 | void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr); | |
972 | void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); | |
973 | void (*set_virtual_x2apic_mode)(struct kvm_vcpu *vcpu, bool set); | |
974 | void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa); | |
975 | void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); | |
976 | int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); | |
977 | int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); | |
978 | int (*get_tdp_level)(void); | |
979 | u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); | |
980 | int (*get_lpage_level)(void); | |
981 | bool (*rdtscp_supported)(void); | |
982 | bool (*invpcid_supported)(void); | |
983 | ||
984 | void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); | |
985 | ||
986 | void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); | |
987 | ||
988 | bool (*has_wbinvd_exit)(void); | |
989 | ||
990 | void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); | |
991 | ||
992 | void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); | |
993 | ||
994 | int (*check_intercept)(struct kvm_vcpu *vcpu, | |
995 | struct x86_instruction_info *info, | |
996 | enum x86_intercept_stage stage); | |
997 | void (*handle_external_intr)(struct kvm_vcpu *vcpu); | |
998 | bool (*mpx_supported)(void); | |
999 | bool (*xsaves_supported)(void); | |
1000 | ||
1001 | int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr); | |
1002 | ||
1003 | void (*sched_in)(struct kvm_vcpu *kvm, int cpu); | |
1004 | ||
1005 | /* | |
1006 | * Arch-specific dirty logging hooks. These hooks are only supposed to | |
1007 | * be valid if the specific arch has hardware-accelerated dirty logging | |
1008 | * mechanism. Currently only for PML on VMX. | |
1009 | * | |
1010 | * - slot_enable_log_dirty: | |
1011 | * called when enabling log dirty mode for the slot. | |
1012 | * - slot_disable_log_dirty: | |
1013 | * called when disabling log dirty mode for the slot. | |
1014 | * also called when slot is created with log dirty disabled. | |
1015 | * - flush_log_dirty: | |
1016 | * called before reporting dirty_bitmap to userspace. | |
1017 | * - enable_log_dirty_pt_masked: | |
1018 | * called when reenabling log dirty for the GFNs in the mask after | |
1019 | * corresponding bits are cleared in slot->dirty_bitmap. | |
1020 | */ | |
1021 | void (*slot_enable_log_dirty)(struct kvm *kvm, | |
1022 | struct kvm_memory_slot *slot); | |
1023 | void (*slot_disable_log_dirty)(struct kvm *kvm, | |
1024 | struct kvm_memory_slot *slot); | |
1025 | void (*flush_log_dirty)(struct kvm *kvm); | |
1026 | void (*enable_log_dirty_pt_masked)(struct kvm *kvm, | |
1027 | struct kvm_memory_slot *slot, | |
1028 | gfn_t offset, unsigned long mask); | |
1029 | int (*write_log_dirty)(struct kvm_vcpu *vcpu); | |
1030 | ||
1031 | /* pmu operations of sub-arch */ | |
1032 | const struct kvm_pmu_ops *pmu_ops; | |
1033 | ||
1034 | /* | |
1035 | * Architecture specific hooks for vCPU blocking due to | |
1036 | * HLT instruction. | |
1037 | * Returns for .pre_block(): | |
1038 | * - 0 means continue to block the vCPU. | |
1039 | * - 1 means we cannot block the vCPU since some event | |
1040 | * happens during this period, such as, 'ON' bit in | |
1041 | * posted-interrupts descriptor is set. | |
1042 | */ | |
1043 | int (*pre_block)(struct kvm_vcpu *vcpu); | |
1044 | void (*post_block)(struct kvm_vcpu *vcpu); | |
1045 | ||
1046 | void (*vcpu_blocking)(struct kvm_vcpu *vcpu); | |
1047 | void (*vcpu_unblocking)(struct kvm_vcpu *vcpu); | |
1048 | ||
1049 | int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, | |
1050 | uint32_t guest_irq, bool set); | |
1051 | void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); | |
1052 | ||
1053 | int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc); | |
1054 | void (*cancel_hv_timer)(struct kvm_vcpu *vcpu); | |
1055 | ||
1056 | void (*setup_mce)(struct kvm_vcpu *vcpu); | |
1057 | }; | |
1058 | ||
1059 | struct kvm_arch_async_pf { | |
1060 | u32 token; | |
1061 | gfn_t gfn; | |
1062 | unsigned long cr3; | |
1063 | bool direct_map; | |
1064 | }; | |
1065 | ||
1066 | extern struct kvm_x86_ops *kvm_x86_ops; | |
1067 | ||
1068 | int kvm_mmu_module_init(void); | |
1069 | void kvm_mmu_module_exit(void); | |
1070 | ||
1071 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu); | |
1072 | int kvm_mmu_create(struct kvm_vcpu *vcpu); | |
1073 | void kvm_mmu_setup(struct kvm_vcpu *vcpu); | |
1074 | void kvm_mmu_init_vm(struct kvm *kvm); | |
1075 | void kvm_mmu_uninit_vm(struct kvm *kvm); | |
1076 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, | |
1077 | u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, | |
1078 | u64 acc_track_mask); | |
1079 | ||
1080 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); | |
1081 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, | |
1082 | struct kvm_memory_slot *memslot); | |
1083 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
1084 | const struct kvm_memory_slot *memslot); | |
1085 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, | |
1086 | struct kvm_memory_slot *memslot); | |
1087 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
1088 | struct kvm_memory_slot *memslot); | |
1089 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
1090 | struct kvm_memory_slot *memslot); | |
1091 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1092 | struct kvm_memory_slot *slot, | |
1093 | gfn_t gfn_offset, unsigned long mask); | |
1094 | void kvm_mmu_zap_all(struct kvm *kvm); | |
1095 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots); | |
1096 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm); | |
1097 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages); | |
1098 | ||
1099 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); | |
1100 | bool pdptrs_changed(struct kvm_vcpu *vcpu); | |
1101 | ||
1102 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, | |
1103 | const void *val, int bytes); | |
1104 | ||
1105 | struct kvm_irq_mask_notifier { | |
1106 | void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); | |
1107 | int irq; | |
1108 | struct hlist_node link; | |
1109 | }; | |
1110 | ||
1111 | void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, | |
1112 | struct kvm_irq_mask_notifier *kimn); | |
1113 | void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, | |
1114 | struct kvm_irq_mask_notifier *kimn); | |
1115 | void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, | |
1116 | bool mask); | |
1117 | ||
1118 | extern bool tdp_enabled; | |
1119 | ||
1120 | u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); | |
1121 | ||
1122 | /* control of guest tsc rate supported? */ | |
1123 | extern bool kvm_has_tsc_control; | |
1124 | /* maximum supported tsc_khz for guests */ | |
1125 | extern u32 kvm_max_guest_tsc_khz; | |
1126 | /* number of bits of the fractional part of the TSC scaling ratio */ | |
1127 | extern u8 kvm_tsc_scaling_ratio_frac_bits; | |
1128 | /* maximum allowed value of TSC scaling ratio */ | |
1129 | extern u64 kvm_max_tsc_scaling_ratio; | |
1130 | /* 1ull << kvm_tsc_scaling_ratio_frac_bits */ | |
1131 | extern u64 kvm_default_tsc_scaling_ratio; | |
1132 | ||
1133 | extern u64 kvm_mce_cap_supported; | |
1134 | ||
1135 | enum emulation_result { | |
1136 | EMULATE_DONE, /* no further processing */ | |
1137 | EMULATE_USER_EXIT, /* kvm_run ready for userspace exit */ | |
1138 | EMULATE_FAIL, /* can't emulate this instruction */ | |
1139 | }; | |
1140 | ||
1141 | #define EMULTYPE_NO_DECODE (1 << 0) | |
1142 | #define EMULTYPE_TRAP_UD (1 << 1) | |
1143 | #define EMULTYPE_SKIP (1 << 2) | |
1144 | #define EMULTYPE_RETRY (1 << 3) | |
1145 | #define EMULTYPE_NO_REEXECUTE (1 << 4) | |
1146 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2, | |
1147 | int emulation_type, void *insn, int insn_len); | |
1148 | ||
1149 | static inline int emulate_instruction(struct kvm_vcpu *vcpu, | |
1150 | int emulation_type) | |
1151 | { | |
1152 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
1153 | } | |
1154 | ||
1155 | void kvm_enable_efer_bits(u64); | |
1156 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); | |
1157 | int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); | |
1158 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); | |
1159 | ||
1160 | struct x86_emulate_ctxt; | |
1161 | ||
1162 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port); | |
1163 | int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port); | |
1164 | int kvm_emulate_cpuid(struct kvm_vcpu *vcpu); | |
1165 | int kvm_emulate_halt(struct kvm_vcpu *vcpu); | |
1166 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu); | |
1167 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); | |
1168 | ||
1169 | void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); | |
1170 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); | |
1171 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); | |
1172 | ||
1173 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, | |
1174 | int reason, bool has_error_code, u32 error_code); | |
1175 | ||
1176 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); | |
1177 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); | |
1178 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); | |
1179 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); | |
1180 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); | |
1181 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); | |
1182 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); | |
1183 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); | |
1184 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); | |
1185 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); | |
1186 | ||
1187 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); | |
1188 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); | |
1189 | ||
1190 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); | |
1191 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); | |
1192 | bool kvm_rdpmc(struct kvm_vcpu *vcpu); | |
1193 | ||
1194 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); | |
1195 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
1196 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); | |
1197 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
1198 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); | |
1199 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
1200 | gfn_t gfn, void *data, int offset, int len, | |
1201 | u32 access); | |
1202 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); | |
1203 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); | |
1204 | ||
1205 | static inline int __kvm_irq_line_state(unsigned long *irq_state, | |
1206 | int irq_source_id, int level) | |
1207 | { | |
1208 | /* Logical OR for level trig interrupt */ | |
1209 | if (level) | |
1210 | __set_bit(irq_source_id, irq_state); | |
1211 | else | |
1212 | __clear_bit(irq_source_id, irq_state); | |
1213 | ||
1214 | return !!(*irq_state); | |
1215 | } | |
1216 | ||
1217 | int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); | |
1218 | void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); | |
1219 | ||
1220 | void kvm_inject_nmi(struct kvm_vcpu *vcpu); | |
1221 | ||
1222 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); | |
1223 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); | |
1224 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); | |
1225 | int kvm_mmu_load(struct kvm_vcpu *vcpu); | |
1226 | void kvm_mmu_unload(struct kvm_vcpu *vcpu); | |
1227 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); | |
1228 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, | |
1229 | struct x86_exception *exception); | |
1230 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, | |
1231 | struct x86_exception *exception); | |
1232 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, | |
1233 | struct x86_exception *exception); | |
1234 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, | |
1235 | struct x86_exception *exception); | |
1236 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, | |
1237 | struct x86_exception *exception); | |
1238 | ||
1239 | void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu); | |
1240 | ||
1241 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); | |
1242 | ||
1243 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u64 error_code, | |
1244 | void *insn, int insn_len); | |
1245 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); | |
1246 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu); | |
1247 | ||
1248 | void kvm_enable_tdp(void); | |
1249 | void kvm_disable_tdp(void); | |
1250 | ||
1251 | static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, | |
1252 | struct x86_exception *exception) | |
1253 | { | |
1254 | return gpa; | |
1255 | } | |
1256 | ||
1257 | static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) | |
1258 | { | |
1259 | struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); | |
1260 | ||
1261 | return (struct kvm_mmu_page *)page_private(page); | |
1262 | } | |
1263 | ||
1264 | static inline u16 kvm_read_ldt(void) | |
1265 | { | |
1266 | u16 ldt; | |
1267 | asm("sldt %0" : "=g"(ldt)); | |
1268 | return ldt; | |
1269 | } | |
1270 | ||
1271 | static inline void kvm_load_ldt(u16 sel) | |
1272 | { | |
1273 | asm("lldt %0" : : "rm"(sel)); | |
1274 | } | |
1275 | ||
1276 | #ifdef CONFIG_X86_64 | |
1277 | static inline unsigned long read_msr(unsigned long msr) | |
1278 | { | |
1279 | u64 value; | |
1280 | ||
1281 | rdmsrl(msr, value); | |
1282 | return value; | |
1283 | } | |
1284 | #endif | |
1285 | ||
1286 | static inline u32 get_rdx_init_val(void) | |
1287 | { | |
1288 | return 0x600; /* P6 family */ | |
1289 | } | |
1290 | ||
1291 | static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) | |
1292 | { | |
1293 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
1294 | } | |
1295 | ||
1296 | static inline u64 get_canonical(u64 la) | |
1297 | { | |
1298 | return ((int64_t)la << 16) >> 16; | |
1299 | } | |
1300 | ||
1301 | static inline bool is_noncanonical_address(u64 la) | |
1302 | { | |
1303 | #ifdef CONFIG_X86_64 | |
1304 | return get_canonical(la) != la; | |
1305 | #else | |
1306 | return false; | |
1307 | #endif | |
1308 | } | |
1309 | ||
1310 | #define TSS_IOPB_BASE_OFFSET 0x66 | |
1311 | #define TSS_BASE_SIZE 0x68 | |
1312 | #define TSS_IOPB_SIZE (65536 / 8) | |
1313 | #define TSS_REDIRECTION_SIZE (256 / 8) | |
1314 | #define RMODE_TSS_SIZE \ | |
1315 | (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) | |
1316 | ||
1317 | enum { | |
1318 | TASK_SWITCH_CALL = 0, | |
1319 | TASK_SWITCH_IRET = 1, | |
1320 | TASK_SWITCH_JMP = 2, | |
1321 | TASK_SWITCH_GATE = 3, | |
1322 | }; | |
1323 | ||
1324 | #define HF_GIF_MASK (1 << 0) | |
1325 | #define HF_HIF_MASK (1 << 1) | |
1326 | #define HF_VINTR_MASK (1 << 2) | |
1327 | #define HF_NMI_MASK (1 << 3) | |
1328 | #define HF_IRET_MASK (1 << 4) | |
1329 | #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ | |
1330 | #define HF_SMM_MASK (1 << 6) | |
1331 | #define HF_SMM_INSIDE_NMI_MASK (1 << 7) | |
1332 | ||
1333 | #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE | |
1334 | #define KVM_ADDRESS_SPACE_NUM 2 | |
1335 | ||
1336 | #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) | |
1337 | #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) | |
1338 | ||
1339 | /* | |
1340 | * Hardware virtualization extension instructions may fault if a | |
1341 | * reboot turns off virtualization while processes are running. | |
1342 | * Trap the fault and ignore the instruction if that happens. | |
1343 | */ | |
1344 | asmlinkage void kvm_spurious_fault(void); | |
1345 | ||
1346 | #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ | |
1347 | "666: " insn "\n\t" \ | |
1348 | "668: \n\t" \ | |
1349 | ".pushsection .fixup, \"ax\" \n" \ | |
1350 | "667: \n\t" \ | |
1351 | cleanup_insn "\n\t" \ | |
1352 | "cmpb $0, kvm_rebooting \n\t" \ | |
1353 | "jne 668b \n\t" \ | |
1354 | __ASM_SIZE(push) " $666b \n\t" \ | |
1355 | "call kvm_spurious_fault \n\t" \ | |
1356 | ".popsection \n\t" \ | |
1357 | _ASM_EXTABLE(666b, 667b) | |
1358 | ||
1359 | #define __kvm_handle_fault_on_reboot(insn) \ | |
1360 | ____kvm_handle_fault_on_reboot(insn, "") | |
1361 | ||
1362 | #define KVM_ARCH_WANT_MMU_NOTIFIER | |
1363 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); | |
1364 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); | |
1365 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); | |
1366 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); | |
1367 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); | |
1368 | int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); | |
1369 | int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); | |
1370 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); | |
1371 | int kvm_cpu_get_interrupt(struct kvm_vcpu *v); | |
1372 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); | |
1373 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu); | |
1374 | void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, | |
1375 | unsigned long address); | |
1376 | ||
1377 | void kvm_define_shared_msr(unsigned index, u32 msr); | |
1378 | int kvm_set_shared_msr(unsigned index, u64 val, u64 mask); | |
1379 | ||
1380 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc); | |
1381 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); | |
1382 | ||
1383 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); | |
1384 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); | |
1385 | ||
1386 | void kvm_make_mclock_inprogress_request(struct kvm *kvm); | |
1387 | void kvm_make_scan_ioapic_request(struct kvm *kvm); | |
1388 | ||
1389 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, | |
1390 | struct kvm_async_pf *work); | |
1391 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
1392 | struct kvm_async_pf *work); | |
1393 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, | |
1394 | struct kvm_async_pf *work); | |
1395 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); | |
1396 | extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); | |
1397 | ||
1398 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu); | |
1399 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); | |
1400 | ||
1401 | int kvm_is_in_guest(void); | |
1402 | ||
1403 | int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); | |
1404 | int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); | |
1405 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); | |
1406 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); | |
1407 | ||
1408 | bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, | |
1409 | struct kvm_vcpu **dest_vcpu); | |
1410 | ||
1411 | void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, | |
1412 | struct kvm_lapic_irq *irq); | |
1413 | ||
1414 | static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) | |
1415 | { | |
1416 | if (kvm_x86_ops->vcpu_blocking) | |
1417 | kvm_x86_ops->vcpu_blocking(vcpu); | |
1418 | } | |
1419 | ||
1420 | static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) | |
1421 | { | |
1422 | if (kvm_x86_ops->vcpu_unblocking) | |
1423 | kvm_x86_ops->vcpu_unblocking(vcpu); | |
1424 | } | |
1425 | ||
1426 | static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} | |
1427 | ||
1428 | static inline int kvm_cpu_get_apicid(int mps_cpu) | |
1429 | { | |
1430 | #ifdef CONFIG_X86_LOCAL_APIC | |
1431 | return __default_cpu_present_to_apicid(mps_cpu); | |
1432 | #else | |
1433 | WARN_ON_ONCE(1); | |
1434 | return BAD_APICID; | |
1435 | #endif | |
1436 | } | |
1437 | ||
1438 | #endif /* _ASM_X86_KVM_HOST_H */ |