[qemu.git] / cpu-all.h

/*
 * defines common to all virtual CPUs
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#ifndef CPU_ALL_H
#define CPU_ALL_H

#include "qemu-common.h"
#include "qemu-tls.h"
#include "cpu-common.h"
#include "memory_mapping.h"
#include "dump.h"

/* some important defines:
 *
 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
 * memory accesses.
 *
 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
 * otherwise little endian.
 *
 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
 *
 * TARGET_WORDS_BIGENDIAN : same for target cpu
 */

#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
#define BSWAP_NEEDED
#endif

#ifdef BSWAP_NEEDED

static inline uint16_t tswap16(uint16_t s)
{
    return bswap16(s);
}

static inline uint32_t tswap32(uint32_t s)
{
    return bswap32(s);
}

static inline uint64_t tswap64(uint64_t s)
{
    return bswap64(s);
}

static inline void tswap16s(uint16_t *s)
{
    *s = bswap16(*s);
}

static inline void tswap32s(uint32_t *s)
{
    *s = bswap32(*s);
}

static inline void tswap64s(uint64_t *s)
{
    *s = bswap64(*s);
}

#else

static inline uint16_t tswap16(uint16_t s)
{
    return s;
}

static inline uint32_t tswap32(uint32_t s)
{
    return s;
}

static inline uint64_t tswap64(uint64_t s)
{
    return s;
}

static inline void tswap16s(uint16_t *s)
{
}

static inline void tswap32s(uint32_t *s)
{
}

static inline void tswap64s(uint64_t *s)
{
}

#endif

#if TARGET_LONG_SIZE == 4
#define tswapl(s) tswap32(s)
#define tswapls(s) tswap32s((uint32_t *)(s))
#define bswaptls(s) bswap32s(s)
#else
#define tswapl(s) tswap64(s)
#define tswapls(s) tswap64s((uint64_t *)(s))
#define bswaptls(s) bswap64s(s)
#endif

/* CPU memory access without any memory or io remapping */

/*
 * the generic syntax for the memory accesses is:
 *
 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
 *
 * store: st{type}{size}{endian}_{access_type}(ptr, val)
 *
 * type is:
 * (empty): integer access
 *   f    : float access
 *
 * sign is:
 * (empty): for floats or 32 bit size
 *   u    : unsigned
 *   s    : signed
 *
 * size is:
 *   b: 8 bits
 *   w: 16 bits
 *   l: 32 bits
 *   q: 64 bits
 *
 * endian is:
 * (empty): target cpu endianness or 8 bit access
 *   r    : reversed target cpu endianness (not implemented yet)
 *   be   : big endian (not implemented yet)
 *   le   : little endian (not implemented yet)
 *
 * access_type is:
 *   raw    : host memory access
 *   user   : user mode access using soft MMU
 *   kernel : kernel mode access using soft MMU
 */

/* target-endianness CPU memory access functions */
#if defined(TARGET_WORDS_BIGENDIAN)
#define lduw_p(p) lduw_be_p(p)
#define ldsw_p(p) ldsw_be_p(p)
#define ldl_p(p) ldl_be_p(p)
#define ldq_p(p) ldq_be_p(p)
#define ldfl_p(p) ldfl_be_p(p)
#define ldfq_p(p) ldfq_be_p(p)
#define stw_p(p, v) stw_be_p(p, v)
#define stl_p(p, v) stl_be_p(p, v)
#define stq_p(p, v) stq_be_p(p, v)
#define stfl_p(p, v) stfl_be_p(p, v)
#define stfq_p(p, v) stfq_be_p(p, v)
#else
#define lduw_p(p) lduw_le_p(p)
#define ldsw_p(p) ldsw_le_p(p)
#define ldl_p(p) ldl_le_p(p)
#define ldq_p(p) ldq_le_p(p)
#define ldfl_p(p) ldfl_le_p(p)
#define ldfq_p(p) ldfq_le_p(p)
#define stw_p(p, v) stw_le_p(p, v)
#define stl_p(p, v) stl_le_p(p, v)
#define stq_p(p, v) stq_le_p(p, v)
#define stfl_p(p, v) stfl_le_p(p, v)
#define stfq_p(p, v) stfq_le_p(p, v)
#endif

/* MMU memory access macros */

#if defined(CONFIG_USER_ONLY)
#include <assert.h>
#include "qemu-types.h"

/* On some host systems the guest address space is reserved on the host.
 * This allows the guest address space to be offset to a convenient location.
 */
#if defined(CONFIG_USE_GUEST_BASE)
extern unsigned long guest_base;
extern int have_guest_base;
extern unsigned long reserved_va;
#define GUEST_BASE guest_base
#define RESERVED_VA reserved_va
#else
#define GUEST_BASE 0ul
#define RESERVED_VA 0ul
#endif

/* All direct uses of g2h and h2g need to go away for usermode softmmu.  */
#define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE))

#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
#define h2g_valid(x) 1
#else
#define h2g_valid(x) ({ \
    unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
    (__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \
    (!RESERVED_VA || (__guest < RESERVED_VA)); \
})
#endif

#define h2g(x) ({ \
    unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
    /* Check if given address fits target address space */ \
    assert(h2g_valid(x)); \
    (abi_ulong)__ret; \
})

#define saddr(x) g2h(x)
#define laddr(x) g2h(x)

#else /* !CONFIG_USER_ONLY */
/* NOTE: we use double casts if pointers and target_ulong have
   different sizes */
#define saddr(x) (uint8_t *)(intptr_t)(x)
#define laddr(x) (uint8_t *)(intptr_t)(x)
#endif

#define ldub_raw(p) ldub_p(laddr((p)))
#define ldsb_raw(p) ldsb_p(laddr((p)))
#define lduw_raw(p) lduw_p(laddr((p)))
#define ldsw_raw(p) ldsw_p(laddr((p)))
#define ldl_raw(p) ldl_p(laddr((p)))
#define ldq_raw(p) ldq_p(laddr((p)))
#define ldfl_raw(p) ldfl_p(laddr((p)))
#define ldfq_raw(p) ldfq_p(laddr((p)))
#define stb_raw(p, v) stb_p(saddr((p)), v)
#define stw_raw(p, v) stw_p(saddr((p)), v)
#define stl_raw(p, v) stl_p(saddr((p)), v)
#define stq_raw(p, v) stq_p(saddr((p)), v)
#define stfl_raw(p, v) stfl_p(saddr((p)), v)
#define stfq_raw(p, v) stfq_p(saddr((p)), v)


#if defined(CONFIG_USER_ONLY)

/* if user mode, no other memory access functions */
#define ldub(p) ldub_raw(p)
#define ldsb(p) ldsb_raw(p)
#define lduw(p) lduw_raw(p)
#define ldsw(p) ldsw_raw(p)
#define ldl(p) ldl_raw(p)
#define ldq(p) ldq_raw(p)
#define ldfl(p) ldfl_raw(p)
#define ldfq(p) ldfq_raw(p)
#define stb(p, v) stb_raw(p, v)
#define stw(p, v) stw_raw(p, v)
#define stl(p, v) stl_raw(p, v)
#define stq(p, v) stq_raw(p, v)
#define stfl(p, v) stfl_raw(p, v)
#define stfq(p, v) stfq_raw(p, v)

#ifndef CONFIG_TCG_PASS_AREG0
#define ldub_code(p) ldub_raw(p)
#define ldsb_code(p) ldsb_raw(p)
#define lduw_code(p) lduw_raw(p)
#define ldsw_code(p) ldsw_raw(p)
#define ldl_code(p) ldl_raw(p)
#define ldq_code(p) ldq_raw(p)
#else
#define cpu_ldub_code(env1, p) ldub_raw(p)
#define cpu_ldsb_code(env1, p) ldsb_raw(p)
#define cpu_lduw_code(env1, p) lduw_raw(p)
#define cpu_ldsw_code(env1, p) ldsw_raw(p)
#define cpu_ldl_code(env1, p) ldl_raw(p)
#define cpu_ldq_code(env1, p) ldq_raw(p)
#endif

#define ldub_kernel(p) ldub_raw(p)
#define ldsb_kernel(p) ldsb_raw(p)
#define lduw_kernel(p) lduw_raw(p)
#define ldsw_kernel(p) ldsw_raw(p)
#define ldl_kernel(p) ldl_raw(p)
#define ldq_kernel(p) ldq_raw(p)
#define ldfl_kernel(p) ldfl_raw(p)
#define ldfq_kernel(p) ldfq_raw(p)
#define stb_kernel(p, v) stb_raw(p, v)
#define stw_kernel(p, v) stw_raw(p, v)
#define stl_kernel(p, v) stl_raw(p, v)
#define stq_kernel(p, v) stq_raw(p, v)
#define stfl_kernel(p, v) stfl_raw(p, v)
#define stfq_kernel(p, vt) stfq_raw(p, v)

#endif /* defined(CONFIG_USER_ONLY) */

/* page related stuff */

#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)

/* ??? These should be the larger of uintptr_t and target_ulong.  */
extern uintptr_t qemu_real_host_page_size;
extern uintptr_t qemu_host_page_size;
extern uintptr_t qemu_host_page_mask;

#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)

/* same as PROT_xxx */
#define PAGE_READ      0x0001
#define PAGE_WRITE     0x0002
#define PAGE_EXEC      0x0004
#define PAGE_BITS      (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
#define PAGE_VALID     0x0008
/* original state of the write flag (used when tracking self-modifying
   code */
#define PAGE_WRITE_ORG 0x0010
#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
/* FIXME: Code that sets/uses this is broken and needs to go away.  */
#define PAGE_RESERVED  0x0020
#endif

#if defined(CONFIG_USER_ONLY)
void page_dump(FILE *f);

typedef int (*walk_memory_regions_fn)(void *, abi_ulong,
                                      abi_ulong, unsigned long);
int walk_memory_regions(void *, walk_memory_regions_fn);

int page_get_flags(target_ulong address);
void page_set_flags(target_ulong start, target_ulong end, int flags);
int page_check_range(target_ulong start, target_ulong len, int flags);
#endif

CPUArchState *cpu_copy(CPUArchState *env);
CPUArchState *qemu_get_cpu(int cpu);

#define CPU_DUMP_CODE 0x00010000

void cpu_dump_state(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf,
                    int flags);
void cpu_dump_statistics(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf,
                         int flags);

void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...)
    GCC_FMT_ATTR(2, 3);
extern CPUArchState *first_cpu;
DECLARE_TLS(CPUArchState *,cpu_single_env);
#define cpu_single_env tls_var(cpu_single_env)

/* Flags for use in ENV->INTERRUPT_PENDING.

   The numbers assigned here are non-sequential in order to preserve
   binary compatibility with the vmstate dump.  Bit 0 (0x0001) was
   previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
   the vmstate dump.  */

/* External hardware interrupt pending.  This is typically used for
   interrupts from devices.  */
#define CPU_INTERRUPT_HARD        0x0002

/* Exit the current TB.  This is typically used when some system-level device
   makes some change to the memory mapping.  E.g. the a20 line change.  */
#define CPU_INTERRUPT_EXITTB      0x0004

/* Halt the CPU.  */
#define CPU_INTERRUPT_HALT        0x0020

/* Debug event pending.  */
#define CPU_INTERRUPT_DEBUG       0x0080

/* Several target-specific external hardware interrupts.  Each target/cpu.h
   should define proper names based on these defines.  */
#define CPU_INTERRUPT_TGT_EXT_0   0x0008
#define CPU_INTERRUPT_TGT_EXT_1   0x0010
#define CPU_INTERRUPT_TGT_EXT_2   0x0040
#define CPU_INTERRUPT_TGT_EXT_3   0x0200
#define CPU_INTERRUPT_TGT_EXT_4   0x1000

/* Several target-specific internal interrupts.  These differ from the
   preceding target-specific interrupts in that they are intended to
   originate from within the cpu itself, typically in response to some
   instruction being executed.  These, therefore, are not masked while
   single-stepping within the debugger.  */
#define CPU_INTERRUPT_TGT_INT_0   0x0100
#define CPU_INTERRUPT_TGT_INT_1   0x0400
#define CPU_INTERRUPT_TGT_INT_2   0x0800
#define CPU_INTERRUPT_TGT_INT_3   0x2000

/* First unused bit: 0x4000.  */

/* The set of all bits that should be masked when single-stepping.  */
#define CPU_INTERRUPT_SSTEP_MASK \
    (CPU_INTERRUPT_HARD          \
     | CPU_INTERRUPT_TGT_EXT_0   \
     | CPU_INTERRUPT_TGT_EXT_1   \
     | CPU_INTERRUPT_TGT_EXT_2   \
     | CPU_INTERRUPT_TGT_EXT_3   \
     | CPU_INTERRUPT_TGT_EXT_4)

#ifndef CONFIG_USER_ONLY
typedef void (*CPUInterruptHandler)(CPUArchState *, int);

extern CPUInterruptHandler cpu_interrupt_handler;

static inline void cpu_interrupt(CPUArchState *s, int mask)
{
    cpu_interrupt_handler(s, mask);
}
#else /* USER_ONLY */
void cpu_interrupt(CPUArchState *env, int mask);
#endif /* USER_ONLY */

void cpu_reset_interrupt(CPUArchState *env, int mask);

void cpu_exit(CPUArchState *s);

bool qemu_cpu_has_work(CPUArchState *env);

/* Breakpoint/watchpoint flags */
#define BP_MEM_READ           0x01
#define BP_MEM_WRITE          0x02
#define BP_MEM_ACCESS         (BP_MEM_READ | BP_MEM_WRITE)
#define BP_STOP_BEFORE_ACCESS 0x04
#define BP_WATCHPOINT_HIT     0x08
#define BP_GDB                0x10
#define BP_CPU                0x20

int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
                          CPUBreakpoint **breakpoint);
int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags);
void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint);
void cpu_breakpoint_remove_all(CPUArchState *env, int mask);
int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
                          int flags, CPUWatchpoint **watchpoint);
int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr,
                          target_ulong len, int flags);
void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint);
void cpu_watchpoint_remove_all(CPUArchState *env, int mask);

#define SSTEP_ENABLE  0x1  /* Enable simulated HW single stepping */
#define SSTEP_NOIRQ   0x2  /* Do not use IRQ while single stepping */
#define SSTEP_NOTIMER 0x4  /* Do not Timers while single stepping */

void cpu_single_step(CPUArchState *env, int enabled);
void cpu_state_reset(CPUArchState *s);
int cpu_is_stopped(CPUArchState *env);
void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data);

#define CPU_LOG_TB_OUT_ASM (1 << 0)
#define CPU_LOG_TB_IN_ASM  (1 << 1)
#define CPU_LOG_TB_OP      (1 << 2)
#define CPU_LOG_TB_OP_OPT  (1 << 3)
#define CPU_LOG_INT        (1 << 4)
#define CPU_LOG_EXEC       (1 << 5)
#define CPU_LOG_PCALL      (1 << 6)
#define CPU_LOG_IOPORT     (1 << 7)
#define CPU_LOG_TB_CPU     (1 << 8)
#define CPU_LOG_RESET      (1 << 9)

/* define log items */
typedef struct CPULogItem {
    int mask;
    const char *name;
    const char *help;
} CPULogItem;

extern const CPULogItem cpu_log_items[];

void cpu_set_log(int log_flags);
void cpu_set_log_filename(const char *filename);
int cpu_str_to_log_mask(const char *str);

#if !defined(CONFIG_USER_ONLY)

/* Return the physical page corresponding to a virtual one. Use it
   only for debugging because no protection checks are done. Return -1
   if no page found. */
target_phys_addr_t cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr);

/* memory API */

extern int phys_ram_fd;
extern ram_addr_t ram_size;

/* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
#define RAM_PREALLOC_MASK   (1 << 0)

typedef struct RAMBlock {
    struct MemoryRegion *mr;
    uint8_t *host;
    ram_addr_t offset;
    ram_addr_t length;
    uint32_t flags;
    char idstr[256];
    QLIST_ENTRY(RAMBlock) next;
#if defined(__linux__) && !defined(TARGET_S390X)
    int fd;
#endif
} RAMBlock;

typedef struct RAMList {
    uint8_t *phys_dirty;
    QLIST_HEAD(, RAMBlock) blocks;
} RAMList;
extern RAMList ram_list;

extern const char *mem_path;
extern int mem_prealloc;

/* Flags stored in the low bits of the TLB virtual address.  These are
   defined so that fast path ram access is all zeros.  */
/* Zero if TLB entry is valid.  */
#define TLB_INVALID_MASK   (1 << 3)
/* Set if TLB entry references a clean RAM page.  The iotlb entry will
   contain the page physical address.  */
#define TLB_NOTDIRTY    (1 << 4)
/* Set if TLB entry is an IO callback.  */
#define TLB_MMIO        (1 << 5)

void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);
#endif /* !CONFIG_USER_ONLY */

int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
                        uint8_t *buf, int len, int is_write);

#if defined(CONFIG_HAVE_GET_MEMORY_MAPPING)
int cpu_get_memory_mapping(MemoryMappingList *list, CPUArchState *env);
bool cpu_paging_enabled(CPUArchState *env);
#else
static inline int cpu_get_memory_mapping(MemoryMappingList *list,
                                         CPUArchState *env)
{
    return -1;
}

static inline bool cpu_paging_enabled(CPUArchState *env)
{
    return true;
}
#endif

typedef int (*write_core_dump_function)(void *buf, size_t size, void *opaque);
#if defined(CONFIG_HAVE_CORE_DUMP)
int cpu_write_elf64_note(write_core_dump_function f, CPUArchState *env,
                         int cpuid, void *opaque);
int cpu_write_elf32_note(write_core_dump_function f, CPUArchState *env,
                         int cpuid, void *opaque);
int cpu_write_elf64_qemunote(write_core_dump_function f, CPUArchState *env,
                             void *opaque);
int cpu_write_elf32_qemunote(write_core_dump_function f, CPUArchState *env,
                             void *opaque);
int cpu_get_dump_info(ArchDumpInfo *info);
#else
static inline int cpu_write_elf64_note(write_core_dump_function f,
                                       CPUArchState *env, int cpuid,
                                       void *opaque)
{
    return -1;
}

static inline int cpu_write_elf32_note(write_core_dump_function f,
                                       CPUArchState *env, int cpuid,
                                       void *opaque)
{
    return -1;
}

static inline int cpu_write_elf64_qemunote(write_core_dump_function f,
                                           CPUArchState *env,
                                           void *opaque)
{
    return -1;
}

static inline int cpu_write_elf32_qemunote(write_core_dump_function f,
                                           CPUArchState *env,
                                           void *opaque)
{
    return -1;
}

static inline int cpu_get_dump_info(ArchDumpInfo *info)
{
    return -1;
}
#endif

#endif /* CPU_ALL_H */
Commit	Line	Data
	1	/*
	2	* defines common to all virtual CPUs
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#ifndef CPU_ALL_H
	20	#define CPU_ALL_H
	21
	22	#include "qemu-common.h"
	23	#include "qemu-tls.h"
	24	#include "cpu-common.h"
	25	#include "memory_mapping.h"
	26	#include "dump.h"
	27
	28	/* some important defines:
	29	*
	30	* WORDS_ALIGNED : if defined, the host cpu can only make word aligned
	31	* memory accesses.
	32	*
	33	* HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
	34	* otherwise little endian.
	35	*
	36	* (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
	37	*
	38	* TARGET_WORDS_BIGENDIAN : same for target cpu
	39	*/
	40
	41	#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
	42	#define BSWAP_NEEDED
	43	#endif
	44
	45	#ifdef BSWAP_NEEDED
	46
	47	static inline uint16_t tswap16(uint16_t s)
	48	{
	49	return bswap16(s);
	50	}
	51
	52	static inline uint32_t tswap32(uint32_t s)
	53	{
	54	return bswap32(s);
	55	}
	56
	57	static inline uint64_t tswap64(uint64_t s)
	58	{
	59	return bswap64(s);
	60	}
	61
	62	static inline void tswap16s(uint16_t *s)
	63	{
	64	s = bswap16(s);
	65	}
	66
	67	static inline void tswap32s(uint32_t *s)
	68	{
	69	s = bswap32(s);
	70	}
	71
	72	static inline void tswap64s(uint64_t *s)
	73	{
	74	s = bswap64(s);
	75	}
	76
	77	#else
	78
	79	static inline uint16_t tswap16(uint16_t s)
	80	{
	81	return s;
	82	}
	83
	84	static inline uint32_t tswap32(uint32_t s)
	85	{
	86	return s;
	87	}
	88
	89	static inline uint64_t tswap64(uint64_t s)
	90	{
	91	return s;
	92	}
	93
	94	static inline void tswap16s(uint16_t *s)
	95	{
	96	}
	97
	98	static inline void tswap32s(uint32_t *s)
	99	{
	100	}
	101
	102	static inline void tswap64s(uint64_t *s)
	103	{
	104	}
	105
	106	#endif
	107
	108	#if TARGET_LONG_SIZE == 4
	109	#define tswapl(s) tswap32(s)
	110	#define tswapls(s) tswap32s((uint32_t *)(s))
	111	#define bswaptls(s) bswap32s(s)
	112	#else
	113	#define tswapl(s) tswap64(s)
	114	#define tswapls(s) tswap64s((uint64_t *)(s))
	115	#define bswaptls(s) bswap64s(s)
	116	#endif
	117
	118	/* CPU memory access without any memory or io remapping */
	119
	120	/*
	121	* the generic syntax for the memory accesses is:
	122	*
	123	* load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
	124	*
	125	* store: st{type}{size}{endian}_{access_type}(ptr, val)
	126	*
	127	* type is:
	128	* (empty): integer access
	129	* f : float access
	130	*
	131	* sign is:
	132	* (empty): for floats or 32 bit size
	133	* u : unsigned
	134	* s : signed
	135	*
	136	* size is:
	137	* b: 8 bits
	138	* w: 16 bits
	139	* l: 32 bits
	140	* q: 64 bits
	141	*
	142	* endian is:
	143	* (empty): target cpu endianness or 8 bit access
	144	* r : reversed target cpu endianness (not implemented yet)
	145	* be : big endian (not implemented yet)
	146	* le : little endian (not implemented yet)
	147	*
	148	* access_type is:
	149	* raw : host memory access
	150	* user : user mode access using soft MMU
	151	* kernel : kernel mode access using soft MMU
	152	*/
	153
	154	/* target-endianness CPU memory access functions */
	155	#if defined(TARGET_WORDS_BIGENDIAN)
	156	#define lduw_p(p) lduw_be_p(p)
	157	#define ldsw_p(p) ldsw_be_p(p)
	158	#define ldl_p(p) ldl_be_p(p)
	159	#define ldq_p(p) ldq_be_p(p)
	160	#define ldfl_p(p) ldfl_be_p(p)
	161	#define ldfq_p(p) ldfq_be_p(p)
	162	#define stw_p(p, v) stw_be_p(p, v)
	163	#define stl_p(p, v) stl_be_p(p, v)
	164	#define stq_p(p, v) stq_be_p(p, v)
	165	#define stfl_p(p, v) stfl_be_p(p, v)
	166	#define stfq_p(p, v) stfq_be_p(p, v)
	167	#else
	168	#define lduw_p(p) lduw_le_p(p)
	169	#define ldsw_p(p) ldsw_le_p(p)
	170	#define ldl_p(p) ldl_le_p(p)
	171	#define ldq_p(p) ldq_le_p(p)
	172	#define ldfl_p(p) ldfl_le_p(p)
	173	#define ldfq_p(p) ldfq_le_p(p)
	174	#define stw_p(p, v) stw_le_p(p, v)
	175	#define stl_p(p, v) stl_le_p(p, v)
	176	#define stq_p(p, v) stq_le_p(p, v)
	177	#define stfl_p(p, v) stfl_le_p(p, v)
	178	#define stfq_p(p, v) stfq_le_p(p, v)
	179	#endif
	180
	181	/* MMU memory access macros */
	182
	183	#if defined(CONFIG_USER_ONLY)
	184	#include <assert.h>
	185	#include "qemu-types.h"
	186
	187	/* On some host systems the guest address space is reserved on the host.
	188	* This allows the guest address space to be offset to a convenient location.
	189	*/
	190	#if defined(CONFIG_USE_GUEST_BASE)
	191	extern unsigned long guest_base;
	192	extern int have_guest_base;
	193	extern unsigned long reserved_va;
	194	#define GUEST_BASE guest_base
	195	#define RESERVED_VA reserved_va
	196	#else
	197	#define GUEST_BASE 0ul
	198	#define RESERVED_VA 0ul
	199	#endif
	200
	201	/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
	202	#define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE))
	203
	204	#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
	205	#define h2g_valid(x) 1
	206	#else
	207	#define h2g_valid(x) ({ \
	208	unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
	209	(__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \
	210	(!RESERVED_VA \|\| (__guest < RESERVED_VA)); \
	211	})
	212	#endif
	213
	214	#define h2g(x) ({ \
	215	unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
	216	/* Check if given address fits target address space */ \
	217	assert(h2g_valid(x)); \
	218	(abi_ulong)__ret; \
	219	})
	220
	221	#define saddr(x) g2h(x)
	222	#define laddr(x) g2h(x)
	223
	224	#else /* !CONFIG_USER_ONLY */
	225	/* NOTE: we use double casts if pointers and target_ulong have
	226	different sizes */
	227	#define saddr(x) (uint8_t *)(intptr_t)(x)
	228	#define laddr(x) (uint8_t *)(intptr_t)(x)
	229	#endif
	230
	231	#define ldub_raw(p) ldub_p(laddr((p)))
	232	#define ldsb_raw(p) ldsb_p(laddr((p)))
	233	#define lduw_raw(p) lduw_p(laddr((p)))
	234	#define ldsw_raw(p) ldsw_p(laddr((p)))
	235	#define ldl_raw(p) ldl_p(laddr((p)))
	236	#define ldq_raw(p) ldq_p(laddr((p)))
	237	#define ldfl_raw(p) ldfl_p(laddr((p)))
	238	#define ldfq_raw(p) ldfq_p(laddr((p)))
	239	#define stb_raw(p, v) stb_p(saddr((p)), v)
	240	#define stw_raw(p, v) stw_p(saddr((p)), v)
	241	#define stl_raw(p, v) stl_p(saddr((p)), v)
	242	#define stq_raw(p, v) stq_p(saddr((p)), v)
	243	#define stfl_raw(p, v) stfl_p(saddr((p)), v)
	244	#define stfq_raw(p, v) stfq_p(saddr((p)), v)
	245
	246
	247	#if defined(CONFIG_USER_ONLY)
	248
	249	/* if user mode, no other memory access functions */
	250	#define ldub(p) ldub_raw(p)
	251	#define ldsb(p) ldsb_raw(p)
	252	#define lduw(p) lduw_raw(p)
	253	#define ldsw(p) ldsw_raw(p)
	254	#define ldl(p) ldl_raw(p)
	255	#define ldq(p) ldq_raw(p)
	256	#define ldfl(p) ldfl_raw(p)
	257	#define ldfq(p) ldfq_raw(p)
	258	#define stb(p, v) stb_raw(p, v)
	259	#define stw(p, v) stw_raw(p, v)
	260	#define stl(p, v) stl_raw(p, v)
	261	#define stq(p, v) stq_raw(p, v)
	262	#define stfl(p, v) stfl_raw(p, v)
	263	#define stfq(p, v) stfq_raw(p, v)
	264
	265	#ifndef CONFIG_TCG_PASS_AREG0
	266	#define ldub_code(p) ldub_raw(p)
	267	#define ldsb_code(p) ldsb_raw(p)
	268	#define lduw_code(p) lduw_raw(p)
	269	#define ldsw_code(p) ldsw_raw(p)
	270	#define ldl_code(p) ldl_raw(p)
	271	#define ldq_code(p) ldq_raw(p)
	272	#else
	273	#define cpu_ldub_code(env1, p) ldub_raw(p)
	274	#define cpu_ldsb_code(env1, p) ldsb_raw(p)
	275	#define cpu_lduw_code(env1, p) lduw_raw(p)
	276	#define cpu_ldsw_code(env1, p) ldsw_raw(p)
	277	#define cpu_ldl_code(env1, p) ldl_raw(p)
	278	#define cpu_ldq_code(env1, p) ldq_raw(p)
	279	#endif
	280
	281	#define ldub_kernel(p) ldub_raw(p)
	282	#define ldsb_kernel(p) ldsb_raw(p)
	283	#define lduw_kernel(p) lduw_raw(p)
	284	#define ldsw_kernel(p) ldsw_raw(p)
	285	#define ldl_kernel(p) ldl_raw(p)
	286	#define ldq_kernel(p) ldq_raw(p)
	287	#define ldfl_kernel(p) ldfl_raw(p)
	288	#define ldfq_kernel(p) ldfq_raw(p)
	289	#define stb_kernel(p, v) stb_raw(p, v)
	290	#define stw_kernel(p, v) stw_raw(p, v)
	291	#define stl_kernel(p, v) stl_raw(p, v)
	292	#define stq_kernel(p, v) stq_raw(p, v)
	293	#define stfl_kernel(p, v) stfl_raw(p, v)
	294	#define stfq_kernel(p, vt) stfq_raw(p, v)
	295
	296	#endif /* defined(CONFIG_USER_ONLY) */
	297
	298	/* page related stuff */
	299
	300	#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
	301	#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
	302	#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
	303
	304	/* ??? These should be the larger of uintptr_t and target_ulong. */
	305	extern uintptr_t qemu_real_host_page_size;
	306	extern uintptr_t qemu_host_page_size;
	307	extern uintptr_t qemu_host_page_mask;
	308
	309	#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
	310
	311	/* same as PROT_xxx */
	312	#define PAGE_READ 0x0001
	313	#define PAGE_WRITE 0x0002
	314	#define PAGE_EXEC 0x0004
	315	#define PAGE_BITS (PAGE_READ \| PAGE_WRITE \| PAGE_EXEC)
	316	#define PAGE_VALID 0x0008
	317	/* original state of the write flag (used when tracking self-modifying
	318	code */
	319	#define PAGE_WRITE_ORG 0x0010
	320	#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
	321	/* FIXME: Code that sets/uses this is broken and needs to go away. */
	322	#define PAGE_RESERVED 0x0020
	323	#endif
	324
	325	#if defined(CONFIG_USER_ONLY)
	326	void page_dump(FILE *f);
	327
	328	typedef int (walk_memory_regions_fn)(void , abi_ulong,
	329	abi_ulong, unsigned long);
	330	int walk_memory_regions(void *, walk_memory_regions_fn);
	331
	332	int page_get_flags(target_ulong address);
	333	void page_set_flags(target_ulong start, target_ulong end, int flags);
	334	int page_check_range(target_ulong start, target_ulong len, int flags);
	335	#endif
	336
	337	CPUArchState cpu_copy(CPUArchState env);
	338	CPUArchState *qemu_get_cpu(int cpu);
	339
	340	#define CPU_DUMP_CODE 0x00010000
	341
	342	void cpu_dump_state(CPUArchState env, FILE f, fprintf_function cpu_fprintf,
	343	int flags);
	344	void cpu_dump_statistics(CPUArchState env, FILE f, fprintf_function cpu_fprintf,
	345	int flags);
	346
	347	void QEMU_NORETURN cpu_abort(CPUArchState env, const char fmt, ...)
	348	GCC_FMT_ATTR(2, 3);
	349	extern CPUArchState *first_cpu;
	350	DECLARE_TLS(CPUArchState *,cpu_single_env);
	351	#define cpu_single_env tls_var(cpu_single_env)
	352
	353	/* Flags for use in ENV->INTERRUPT_PENDING.
	354
	355	The numbers assigned here are non-sequential in order to preserve
	356	binary compatibility with the vmstate dump. Bit 0 (0x0001) was
	357	previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
	358	the vmstate dump. */
	359
	360	/* External hardware interrupt pending. This is typically used for
	361	interrupts from devices. */
	362	#define CPU_INTERRUPT_HARD 0x0002
	363
	364	/* Exit the current TB. This is typically used when some system-level device
	365	makes some change to the memory mapping. E.g. the a20 line change. */
	366	#define CPU_INTERRUPT_EXITTB 0x0004
	367
	368	/* Halt the CPU. */
	369	#define CPU_INTERRUPT_HALT 0x0020
	370
	371	/* Debug event pending. */
	372	#define CPU_INTERRUPT_DEBUG 0x0080
	373
	374	/* Several target-specific external hardware interrupts. Each target/cpu.h
	375	should define proper names based on these defines. */
	376	#define CPU_INTERRUPT_TGT_EXT_0 0x0008
	377	#define CPU_INTERRUPT_TGT_EXT_1 0x0010
	378	#define CPU_INTERRUPT_TGT_EXT_2 0x0040
	379	#define CPU_INTERRUPT_TGT_EXT_3 0x0200
	380	#define CPU_INTERRUPT_TGT_EXT_4 0x1000
	381
	382	/* Several target-specific internal interrupts. These differ from the
	383	preceding target-specific interrupts in that they are intended to
	384	originate from within the cpu itself, typically in response to some
	385	instruction being executed. These, therefore, are not masked while
	386	single-stepping within the debugger. */
	387	#define CPU_INTERRUPT_TGT_INT_0 0x0100
	388	#define CPU_INTERRUPT_TGT_INT_1 0x0400
	389	#define CPU_INTERRUPT_TGT_INT_2 0x0800
	390	#define CPU_INTERRUPT_TGT_INT_3 0x2000
	391
	392	/* First unused bit: 0x4000. */
	393
	394	/* The set of all bits that should be masked when single-stepping. */
	395	#define CPU_INTERRUPT_SSTEP_MASK \
	396	(CPU_INTERRUPT_HARD \
	397	\| CPU_INTERRUPT_TGT_EXT_0 \
	398	\| CPU_INTERRUPT_TGT_EXT_1 \
	399	\| CPU_INTERRUPT_TGT_EXT_2 \
	400	\| CPU_INTERRUPT_TGT_EXT_3 \
	401	\| CPU_INTERRUPT_TGT_EXT_4)
	402
	403	#ifndef CONFIG_USER_ONLY
	404	typedef void (CPUInterruptHandler)(CPUArchState , int);
	405
	406	extern CPUInterruptHandler cpu_interrupt_handler;
	407
	408	static inline void cpu_interrupt(CPUArchState *s, int mask)
	409	{
	410	cpu_interrupt_handler(s, mask);
	411	}
	412	#else /* USER_ONLY */
	413	void cpu_interrupt(CPUArchState *env, int mask);
	414	#endif /* USER_ONLY */
	415
	416	void cpu_reset_interrupt(CPUArchState *env, int mask);
	417
	418	void cpu_exit(CPUArchState *s);
	419
	420	bool qemu_cpu_has_work(CPUArchState *env);
	421
	422	/* Breakpoint/watchpoint flags */
	423	#define BP_MEM_READ 0x01
	424	#define BP_MEM_WRITE 0x02
	425	#define BP_MEM_ACCESS (BP_MEM_READ \| BP_MEM_WRITE)
	426	#define BP_STOP_BEFORE_ACCESS 0x04
	427	#define BP_WATCHPOINT_HIT 0x08
	428	#define BP_GDB 0x10
	429	#define BP_CPU 0x20
	430
	431	int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
	432	CPUBreakpoint **breakpoint);
	433	int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags);
	434	void cpu_breakpoint_remove_by_ref(CPUArchState env, CPUBreakpoint breakpoint);
	435	void cpu_breakpoint_remove_all(CPUArchState *env, int mask);
	436	int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
	437	int flags, CPUWatchpoint **watchpoint);
	438	int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr,
	439	target_ulong len, int flags);
	440	void cpu_watchpoint_remove_by_ref(CPUArchState env, CPUWatchpoint watchpoint);
	441	void cpu_watchpoint_remove_all(CPUArchState *env, int mask);
	442
	443	#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
	444	#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
	445	#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
	446
	447	void cpu_single_step(CPUArchState *env, int enabled);
	448	void cpu_state_reset(CPUArchState *s);
	449	int cpu_is_stopped(CPUArchState *env);
	450	void run_on_cpu(CPUArchState env, void (func)(void data), void data);
	451
	452	#define CPU_LOG_TB_OUT_ASM (1 << 0)
	453	#define CPU_LOG_TB_IN_ASM (1 << 1)
	454	#define CPU_LOG_TB_OP (1 << 2)
	455	#define CPU_LOG_TB_OP_OPT (1 << 3)
	456	#define CPU_LOG_INT (1 << 4)
	457	#define CPU_LOG_EXEC (1 << 5)
	458	#define CPU_LOG_PCALL (1 << 6)
	459	#define CPU_LOG_IOPORT (1 << 7)
	460	#define CPU_LOG_TB_CPU (1 << 8)
	461	#define CPU_LOG_RESET (1 << 9)
	462
	463	/* define log items */
	464	typedef struct CPULogItem {
	465	int mask;
	466	const char *name;
	467	const char *help;
	468	} CPULogItem;
	469
	470	extern const CPULogItem cpu_log_items[];
	471
	472	void cpu_set_log(int log_flags);
	473	void cpu_set_log_filename(const char *filename);
	474	int cpu_str_to_log_mask(const char *str);
	475
	476	#if !defined(CONFIG_USER_ONLY)
	477
	478	/* Return the physical page corresponding to a virtual one. Use it
	479	only for debugging because no protection checks are done. Return -1
	480	if no page found. */
	481	target_phys_addr_t cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr);
	482
	483	/* memory API */
	484
	485	extern int phys_ram_fd;
	486	extern ram_addr_t ram_size;
	487
	488	/* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
	489	#define RAM_PREALLOC_MASK (1 << 0)
	490
	491	typedef struct RAMBlock {
	492	struct MemoryRegion *mr;
	493	uint8_t *host;
	494	ram_addr_t offset;
	495	ram_addr_t length;
	496	uint32_t flags;
	497	char idstr[256];
	498	QLIST_ENTRY(RAMBlock) next;
	499	#if defined(__linux__) && !defined(TARGET_S390X)
	500	int fd;
	501	#endif
	502	} RAMBlock;
	503
	504	typedef struct RAMList {
	505	uint8_t *phys_dirty;
	506	QLIST_HEAD(, RAMBlock) blocks;
	507	} RAMList;
	508	extern RAMList ram_list;
	509
	510	extern const char *mem_path;
	511	extern int mem_prealloc;
	512
	513	/* Flags stored in the low bits of the TLB virtual address. These are
	514	defined so that fast path ram access is all zeros. */
	515	/* Zero if TLB entry is valid. */
	516	#define TLB_INVALID_MASK (1 << 3)
	517	/* Set if TLB entry references a clean RAM page. The iotlb entry will
	518	contain the page physical address. */
	519	#define TLB_NOTDIRTY (1 << 4)
	520	/* Set if TLB entry is an IO callback. */
	521	#define TLB_MMIO (1 << 5)
	522
	523	void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);
	524	#endif /* !CONFIG_USER_ONLY */
	525
	526	int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
	527	uint8_t *buf, int len, int is_write);
	528
	529	#if defined(CONFIG_HAVE_GET_MEMORY_MAPPING)
	530	int cpu_get_memory_mapping(MemoryMappingList list, CPUArchState env);
	531	bool cpu_paging_enabled(CPUArchState *env);
	532	#else
	533	static inline int cpu_get_memory_mapping(MemoryMappingList *list,
	534	CPUArchState *env)
	535	{
	536	return -1;
	537	}
	538
	539	static inline bool cpu_paging_enabled(CPUArchState *env)
	540	{
	541	return true;
	542	}
	543	#endif
	544
	545	typedef int (write_core_dump_function)(void buf, size_t size, void *opaque);
	546	#if defined(CONFIG_HAVE_CORE_DUMP)
	547	int cpu_write_elf64_note(write_core_dump_function f, CPUArchState *env,
	548	int cpuid, void *opaque);
	549	int cpu_write_elf32_note(write_core_dump_function f, CPUArchState *env,
	550	int cpuid, void *opaque);
	551	int cpu_write_elf64_qemunote(write_core_dump_function f, CPUArchState *env,
	552	void *opaque);
	553	int cpu_write_elf32_qemunote(write_core_dump_function f, CPUArchState *env,
	554	void *opaque);
	555	int cpu_get_dump_info(ArchDumpInfo *info);
	556	#else
	557	static inline int cpu_write_elf64_note(write_core_dump_function f,
	558	CPUArchState *env, int cpuid,
	559	void *opaque)
	560	{
	561	return -1;
	562	}
	563
	564	static inline int cpu_write_elf32_note(write_core_dump_function f,
	565	CPUArchState *env, int cpuid,
	566	void *opaque)
	567	{
	568	return -1;
	569	}
	570
	571	static inline int cpu_write_elf64_qemunote(write_core_dump_function f,
	572	CPUArchState *env,
	573	void *opaque)
	574	{
	575	return -1;
	576	}
	577
	578	static inline int cpu_write_elf32_qemunote(write_core_dump_function f,
	579	CPUArchState *env,
	580	void *opaque)
	581	{
	582	return -1;
	583	}
	584
	585	static inline int cpu_get_dump_info(ArchDumpInfo *info)
	586	{
	587	return -1;
	588	}
	589	#endif
	590
	591	#endif /* CPU_ALL_H */