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1 | /* | |
2 | * defines common to all virtual CPUs | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA | |
19 | */ | |
20 | #ifndef CPU_ALL_H | |
21 | #define CPU_ALL_H | |
22 | ||
23 | #include "qemu-common.h" | |
24 | ||
25 | #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) | |
26 | #define WORDS_ALIGNED | |
27 | #endif | |
28 | ||
29 | /* some important defines: | |
30 | * | |
31 | * WORDS_ALIGNED : if defined, the host cpu can only make word aligned | |
32 | * memory accesses. | |
33 | * | |
34 | * WORDS_BIGENDIAN : if defined, the host cpu is big endian and | |
35 | * otherwise little endian. | |
36 | * | |
37 | * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet)) | |
38 | * | |
39 | * TARGET_WORDS_BIGENDIAN : same for target cpu | |
40 | */ | |
41 | ||
42 | #include "bswap.h" | |
43 | #include "softfloat.h" | |
44 | ||
45 | #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) | |
46 | #define BSWAP_NEEDED | |
47 | #endif | |
48 | ||
49 | #ifdef BSWAP_NEEDED | |
50 | ||
51 | static inline uint16_t tswap16(uint16_t s) | |
52 | { | |
53 | return bswap16(s); | |
54 | } | |
55 | ||
56 | static inline uint32_t tswap32(uint32_t s) | |
57 | { | |
58 | return bswap32(s); | |
59 | } | |
60 | ||
61 | static inline uint64_t tswap64(uint64_t s) | |
62 | { | |
63 | return bswap64(s); | |
64 | } | |
65 | ||
66 | static inline void tswap16s(uint16_t *s) | |
67 | { | |
68 | *s = bswap16(*s); | |
69 | } | |
70 | ||
71 | static inline void tswap32s(uint32_t *s) | |
72 | { | |
73 | *s = bswap32(*s); | |
74 | } | |
75 | ||
76 | static inline void tswap64s(uint64_t *s) | |
77 | { | |
78 | *s = bswap64(*s); | |
79 | } | |
80 | ||
81 | #else | |
82 | ||
83 | static inline uint16_t tswap16(uint16_t s) | |
84 | { | |
85 | return s; | |
86 | } | |
87 | ||
88 | static inline uint32_t tswap32(uint32_t s) | |
89 | { | |
90 | return s; | |
91 | } | |
92 | ||
93 | static inline uint64_t tswap64(uint64_t s) | |
94 | { | |
95 | return s; | |
96 | } | |
97 | ||
98 | static inline void tswap16s(uint16_t *s) | |
99 | { | |
100 | } | |
101 | ||
102 | static inline void tswap32s(uint32_t *s) | |
103 | { | |
104 | } | |
105 | ||
106 | static inline void tswap64s(uint64_t *s) | |
107 | { | |
108 | } | |
109 | ||
110 | #endif | |
111 | ||
112 | #if TARGET_LONG_SIZE == 4 | |
113 | #define tswapl(s) tswap32(s) | |
114 | #define tswapls(s) tswap32s((uint32_t *)(s)) | |
115 | #define bswaptls(s) bswap32s(s) | |
116 | #else | |
117 | #define tswapl(s) tswap64(s) | |
118 | #define tswapls(s) tswap64s((uint64_t *)(s)) | |
119 | #define bswaptls(s) bswap64s(s) | |
120 | #endif | |
121 | ||
122 | typedef union { | |
123 | float32 f; | |
124 | uint32_t l; | |
125 | } CPU_FloatU; | |
126 | ||
127 | /* NOTE: arm FPA is horrible as double 32 bit words are stored in big | |
128 | endian ! */ | |
129 | typedef union { | |
130 | float64 d; | |
131 | #if defined(WORDS_BIGENDIAN) \ | |
132 | || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT)) | |
133 | struct { | |
134 | uint32_t upper; | |
135 | uint32_t lower; | |
136 | } l; | |
137 | #else | |
138 | struct { | |
139 | uint32_t lower; | |
140 | uint32_t upper; | |
141 | } l; | |
142 | #endif | |
143 | uint64_t ll; | |
144 | } CPU_DoubleU; | |
145 | ||
146 | #ifdef TARGET_SPARC | |
147 | typedef union { | |
148 | float128 q; | |
149 | #if defined(WORDS_BIGENDIAN) \ | |
150 | || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT)) | |
151 | struct { | |
152 | uint32_t upmost; | |
153 | uint32_t upper; | |
154 | uint32_t lower; | |
155 | uint32_t lowest; | |
156 | } l; | |
157 | struct { | |
158 | uint64_t upper; | |
159 | uint64_t lower; | |
160 | } ll; | |
161 | #else | |
162 | struct { | |
163 | uint32_t lowest; | |
164 | uint32_t lower; | |
165 | uint32_t upper; | |
166 | uint32_t upmost; | |
167 | } l; | |
168 | struct { | |
169 | uint64_t lower; | |
170 | uint64_t upper; | |
171 | } ll; | |
172 | #endif | |
173 | } CPU_QuadU; | |
174 | #endif | |
175 | ||
176 | /* CPU memory access without any memory or io remapping */ | |
177 | ||
178 | /* | |
179 | * the generic syntax for the memory accesses is: | |
180 | * | |
181 | * load: ld{type}{sign}{size}{endian}_{access_type}(ptr) | |
182 | * | |
183 | * store: st{type}{size}{endian}_{access_type}(ptr, val) | |
184 | * | |
185 | * type is: | |
186 | * (empty): integer access | |
187 | * f : float access | |
188 | * | |
189 | * sign is: | |
190 | * (empty): for floats or 32 bit size | |
191 | * u : unsigned | |
192 | * s : signed | |
193 | * | |
194 | * size is: | |
195 | * b: 8 bits | |
196 | * w: 16 bits | |
197 | * l: 32 bits | |
198 | * q: 64 bits | |
199 | * | |
200 | * endian is: | |
201 | * (empty): target cpu endianness or 8 bit access | |
202 | * r : reversed target cpu endianness (not implemented yet) | |
203 | * be : big endian (not implemented yet) | |
204 | * le : little endian (not implemented yet) | |
205 | * | |
206 | * access_type is: | |
207 | * raw : host memory access | |
208 | * user : user mode access using soft MMU | |
209 | * kernel : kernel mode access using soft MMU | |
210 | */ | |
211 | static inline int ldub_p(const void *ptr) | |
212 | { | |
213 | return *(uint8_t *)ptr; | |
214 | } | |
215 | ||
216 | static inline int ldsb_p(const void *ptr) | |
217 | { | |
218 | return *(int8_t *)ptr; | |
219 | } | |
220 | ||
221 | static inline void stb_p(void *ptr, int v) | |
222 | { | |
223 | *(uint8_t *)ptr = v; | |
224 | } | |
225 | ||
226 | /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the | |
227 | kernel handles unaligned load/stores may give better results, but | |
228 | it is a system wide setting : bad */ | |
229 | #if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED) | |
230 | ||
231 | /* conservative code for little endian unaligned accesses */ | |
232 | static inline int lduw_le_p(const void *ptr) | |
233 | { | |
234 | #ifdef _ARCH_PPC | |
235 | int val; | |
236 | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); | |
237 | return val; | |
238 | #else | |
239 | const uint8_t *p = ptr; | |
240 | return p[0] | (p[1] << 8); | |
241 | #endif | |
242 | } | |
243 | ||
244 | static inline int ldsw_le_p(const void *ptr) | |
245 | { | |
246 | #ifdef _ARCH_PPC | |
247 | int val; | |
248 | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); | |
249 | return (int16_t)val; | |
250 | #else | |
251 | const uint8_t *p = ptr; | |
252 | return (int16_t)(p[0] | (p[1] << 8)); | |
253 | #endif | |
254 | } | |
255 | ||
256 | static inline int ldl_le_p(const void *ptr) | |
257 | { | |
258 | #ifdef _ARCH_PPC | |
259 | int val; | |
260 | __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr)); | |
261 | return val; | |
262 | #else | |
263 | const uint8_t *p = ptr; | |
264 | return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); | |
265 | #endif | |
266 | } | |
267 | ||
268 | static inline uint64_t ldq_le_p(const void *ptr) | |
269 | { | |
270 | const uint8_t *p = ptr; | |
271 | uint32_t v1, v2; | |
272 | v1 = ldl_le_p(p); | |
273 | v2 = ldl_le_p(p + 4); | |
274 | return v1 | ((uint64_t)v2 << 32); | |
275 | } | |
276 | ||
277 | static inline void stw_le_p(void *ptr, int v) | |
278 | { | |
279 | #ifdef _ARCH_PPC | |
280 | __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr)); | |
281 | #else | |
282 | uint8_t *p = ptr; | |
283 | p[0] = v; | |
284 | p[1] = v >> 8; | |
285 | #endif | |
286 | } | |
287 | ||
288 | static inline void stl_le_p(void *ptr, int v) | |
289 | { | |
290 | #ifdef _ARCH_PPC | |
291 | __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr)); | |
292 | #else | |
293 | uint8_t *p = ptr; | |
294 | p[0] = v; | |
295 | p[1] = v >> 8; | |
296 | p[2] = v >> 16; | |
297 | p[3] = v >> 24; | |
298 | #endif | |
299 | } | |
300 | ||
301 | static inline void stq_le_p(void *ptr, uint64_t v) | |
302 | { | |
303 | uint8_t *p = ptr; | |
304 | stl_le_p(p, (uint32_t)v); | |
305 | stl_le_p(p + 4, v >> 32); | |
306 | } | |
307 | ||
308 | /* float access */ | |
309 | ||
310 | static inline float32 ldfl_le_p(const void *ptr) | |
311 | { | |
312 | union { | |
313 | float32 f; | |
314 | uint32_t i; | |
315 | } u; | |
316 | u.i = ldl_le_p(ptr); | |
317 | return u.f; | |
318 | } | |
319 | ||
320 | static inline void stfl_le_p(void *ptr, float32 v) | |
321 | { | |
322 | union { | |
323 | float32 f; | |
324 | uint32_t i; | |
325 | } u; | |
326 | u.f = v; | |
327 | stl_le_p(ptr, u.i); | |
328 | } | |
329 | ||
330 | static inline float64 ldfq_le_p(const void *ptr) | |
331 | { | |
332 | CPU_DoubleU u; | |
333 | u.l.lower = ldl_le_p(ptr); | |
334 | u.l.upper = ldl_le_p(ptr + 4); | |
335 | return u.d; | |
336 | } | |
337 | ||
338 | static inline void stfq_le_p(void *ptr, float64 v) | |
339 | { | |
340 | CPU_DoubleU u; | |
341 | u.d = v; | |
342 | stl_le_p(ptr, u.l.lower); | |
343 | stl_le_p(ptr + 4, u.l.upper); | |
344 | } | |
345 | ||
346 | #else | |
347 | ||
348 | static inline int lduw_le_p(const void *ptr) | |
349 | { | |
350 | return *(uint16_t *)ptr; | |
351 | } | |
352 | ||
353 | static inline int ldsw_le_p(const void *ptr) | |
354 | { | |
355 | return *(int16_t *)ptr; | |
356 | } | |
357 | ||
358 | static inline int ldl_le_p(const void *ptr) | |
359 | { | |
360 | return *(uint32_t *)ptr; | |
361 | } | |
362 | ||
363 | static inline uint64_t ldq_le_p(const void *ptr) | |
364 | { | |
365 | return *(uint64_t *)ptr; | |
366 | } | |
367 | ||
368 | static inline void stw_le_p(void *ptr, int v) | |
369 | { | |
370 | *(uint16_t *)ptr = v; | |
371 | } | |
372 | ||
373 | static inline void stl_le_p(void *ptr, int v) | |
374 | { | |
375 | *(uint32_t *)ptr = v; | |
376 | } | |
377 | ||
378 | static inline void stq_le_p(void *ptr, uint64_t v) | |
379 | { | |
380 | *(uint64_t *)ptr = v; | |
381 | } | |
382 | ||
383 | /* float access */ | |
384 | ||
385 | static inline float32 ldfl_le_p(const void *ptr) | |
386 | { | |
387 | return *(float32 *)ptr; | |
388 | } | |
389 | ||
390 | static inline float64 ldfq_le_p(const void *ptr) | |
391 | { | |
392 | return *(float64 *)ptr; | |
393 | } | |
394 | ||
395 | static inline void stfl_le_p(void *ptr, float32 v) | |
396 | { | |
397 | *(float32 *)ptr = v; | |
398 | } | |
399 | ||
400 | static inline void stfq_le_p(void *ptr, float64 v) | |
401 | { | |
402 | *(float64 *)ptr = v; | |
403 | } | |
404 | #endif | |
405 | ||
406 | #if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED) | |
407 | ||
408 | static inline int lduw_be_p(const void *ptr) | |
409 | { | |
410 | #if defined(__i386__) | |
411 | int val; | |
412 | asm volatile ("movzwl %1, %0\n" | |
413 | "xchgb %b0, %h0\n" | |
414 | : "=q" (val) | |
415 | : "m" (*(uint16_t *)ptr)); | |
416 | return val; | |
417 | #else | |
418 | const uint8_t *b = ptr; | |
419 | return ((b[0] << 8) | b[1]); | |
420 | #endif | |
421 | } | |
422 | ||
423 | static inline int ldsw_be_p(const void *ptr) | |
424 | { | |
425 | #if defined(__i386__) | |
426 | int val; | |
427 | asm volatile ("movzwl %1, %0\n" | |
428 | "xchgb %b0, %h0\n" | |
429 | : "=q" (val) | |
430 | : "m" (*(uint16_t *)ptr)); | |
431 | return (int16_t)val; | |
432 | #else | |
433 | const uint8_t *b = ptr; | |
434 | return (int16_t)((b[0] << 8) | b[1]); | |
435 | #endif | |
436 | } | |
437 | ||
438 | static inline int ldl_be_p(const void *ptr) | |
439 | { | |
440 | #if defined(__i386__) || defined(__x86_64__) | |
441 | int val; | |
442 | asm volatile ("movl %1, %0\n" | |
443 | "bswap %0\n" | |
444 | : "=r" (val) | |
445 | : "m" (*(uint32_t *)ptr)); | |
446 | return val; | |
447 | #else | |
448 | const uint8_t *b = ptr; | |
449 | return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3]; | |
450 | #endif | |
451 | } | |
452 | ||
453 | static inline uint64_t ldq_be_p(const void *ptr) | |
454 | { | |
455 | uint32_t a,b; | |
456 | a = ldl_be_p(ptr); | |
457 | b = ldl_be_p((uint8_t *)ptr + 4); | |
458 | return (((uint64_t)a<<32)|b); | |
459 | } | |
460 | ||
461 | static inline void stw_be_p(void *ptr, int v) | |
462 | { | |
463 | #if defined(__i386__) | |
464 | asm volatile ("xchgb %b0, %h0\n" | |
465 | "movw %w0, %1\n" | |
466 | : "=q" (v) | |
467 | : "m" (*(uint16_t *)ptr), "0" (v)); | |
468 | #else | |
469 | uint8_t *d = (uint8_t *) ptr; | |
470 | d[0] = v >> 8; | |
471 | d[1] = v; | |
472 | #endif | |
473 | } | |
474 | ||
475 | static inline void stl_be_p(void *ptr, int v) | |
476 | { | |
477 | #if defined(__i386__) || defined(__x86_64__) | |
478 | asm volatile ("bswap %0\n" | |
479 | "movl %0, %1\n" | |
480 | : "=r" (v) | |
481 | : "m" (*(uint32_t *)ptr), "0" (v)); | |
482 | #else | |
483 | uint8_t *d = (uint8_t *) ptr; | |
484 | d[0] = v >> 24; | |
485 | d[1] = v >> 16; | |
486 | d[2] = v >> 8; | |
487 | d[3] = v; | |
488 | #endif | |
489 | } | |
490 | ||
491 | static inline void stq_be_p(void *ptr, uint64_t v) | |
492 | { | |
493 | stl_be_p(ptr, v >> 32); | |
494 | stl_be_p((uint8_t *)ptr + 4, v); | |
495 | } | |
496 | ||
497 | /* float access */ | |
498 | ||
499 | static inline float32 ldfl_be_p(const void *ptr) | |
500 | { | |
501 | union { | |
502 | float32 f; | |
503 | uint32_t i; | |
504 | } u; | |
505 | u.i = ldl_be_p(ptr); | |
506 | return u.f; | |
507 | } | |
508 | ||
509 | static inline void stfl_be_p(void *ptr, float32 v) | |
510 | { | |
511 | union { | |
512 | float32 f; | |
513 | uint32_t i; | |
514 | } u; | |
515 | u.f = v; | |
516 | stl_be_p(ptr, u.i); | |
517 | } | |
518 | ||
519 | static inline float64 ldfq_be_p(const void *ptr) | |
520 | { | |
521 | CPU_DoubleU u; | |
522 | u.l.upper = ldl_be_p(ptr); | |
523 | u.l.lower = ldl_be_p((uint8_t *)ptr + 4); | |
524 | return u.d; | |
525 | } | |
526 | ||
527 | static inline void stfq_be_p(void *ptr, float64 v) | |
528 | { | |
529 | CPU_DoubleU u; | |
530 | u.d = v; | |
531 | stl_be_p(ptr, u.l.upper); | |
532 | stl_be_p((uint8_t *)ptr + 4, u.l.lower); | |
533 | } | |
534 | ||
535 | #else | |
536 | ||
537 | static inline int lduw_be_p(const void *ptr) | |
538 | { | |
539 | return *(uint16_t *)ptr; | |
540 | } | |
541 | ||
542 | static inline int ldsw_be_p(const void *ptr) | |
543 | { | |
544 | return *(int16_t *)ptr; | |
545 | } | |
546 | ||
547 | static inline int ldl_be_p(const void *ptr) | |
548 | { | |
549 | return *(uint32_t *)ptr; | |
550 | } | |
551 | ||
552 | static inline uint64_t ldq_be_p(const void *ptr) | |
553 | { | |
554 | return *(uint64_t *)ptr; | |
555 | } | |
556 | ||
557 | static inline void stw_be_p(void *ptr, int v) | |
558 | { | |
559 | *(uint16_t *)ptr = v; | |
560 | } | |
561 | ||
562 | static inline void stl_be_p(void *ptr, int v) | |
563 | { | |
564 | *(uint32_t *)ptr = v; | |
565 | } | |
566 | ||
567 | static inline void stq_be_p(void *ptr, uint64_t v) | |
568 | { | |
569 | *(uint64_t *)ptr = v; | |
570 | } | |
571 | ||
572 | /* float access */ | |
573 | ||
574 | static inline float32 ldfl_be_p(const void *ptr) | |
575 | { | |
576 | return *(float32 *)ptr; | |
577 | } | |
578 | ||
579 | static inline float64 ldfq_be_p(const void *ptr) | |
580 | { | |
581 | return *(float64 *)ptr; | |
582 | } | |
583 | ||
584 | static inline void stfl_be_p(void *ptr, float32 v) | |
585 | { | |
586 | *(float32 *)ptr = v; | |
587 | } | |
588 | ||
589 | static inline void stfq_be_p(void *ptr, float64 v) | |
590 | { | |
591 | *(float64 *)ptr = v; | |
592 | } | |
593 | ||
594 | #endif | |
595 | ||
596 | /* target CPU memory access functions */ | |
597 | #if defined(TARGET_WORDS_BIGENDIAN) | |
598 | #define lduw_p(p) lduw_be_p(p) | |
599 | #define ldsw_p(p) ldsw_be_p(p) | |
600 | #define ldl_p(p) ldl_be_p(p) | |
601 | #define ldq_p(p) ldq_be_p(p) | |
602 | #define ldfl_p(p) ldfl_be_p(p) | |
603 | #define ldfq_p(p) ldfq_be_p(p) | |
604 | #define stw_p(p, v) stw_be_p(p, v) | |
605 | #define stl_p(p, v) stl_be_p(p, v) | |
606 | #define stq_p(p, v) stq_be_p(p, v) | |
607 | #define stfl_p(p, v) stfl_be_p(p, v) | |
608 | #define stfq_p(p, v) stfq_be_p(p, v) | |
609 | #else | |
610 | #define lduw_p(p) lduw_le_p(p) | |
611 | #define ldsw_p(p) ldsw_le_p(p) | |
612 | #define ldl_p(p) ldl_le_p(p) | |
613 | #define ldq_p(p) ldq_le_p(p) | |
614 | #define ldfl_p(p) ldfl_le_p(p) | |
615 | #define ldfq_p(p) ldfq_le_p(p) | |
616 | #define stw_p(p, v) stw_le_p(p, v) | |
617 | #define stl_p(p, v) stl_le_p(p, v) | |
618 | #define stq_p(p, v) stq_le_p(p, v) | |
619 | #define stfl_p(p, v) stfl_le_p(p, v) | |
620 | #define stfq_p(p, v) stfq_le_p(p, v) | |
621 | #endif | |
622 | ||
623 | /* MMU memory access macros */ | |
624 | ||
625 | #if defined(CONFIG_USER_ONLY) | |
626 | #include <assert.h> | |
627 | #include "qemu-types.h" | |
628 | ||
629 | /* On some host systems the guest address space is reserved on the host. | |
630 | * This allows the guest address space to be offset to a convenient location. | |
631 | */ | |
632 | //#define GUEST_BASE 0x20000000 | |
633 | #define GUEST_BASE 0 | |
634 | ||
635 | /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ | |
636 | #define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE)) | |
637 | #define h2g(x) ({ \ | |
638 | unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \ | |
639 | /* Check if given address fits target address space */ \ | |
640 | assert(__ret == (abi_ulong)__ret); \ | |
641 | (abi_ulong)__ret; \ | |
642 | }) | |
643 | #define h2g_valid(x) ({ \ | |
644 | unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \ | |
645 | (__guest == (abi_ulong)__guest); \ | |
646 | }) | |
647 | ||
648 | #define saddr(x) g2h(x) | |
649 | #define laddr(x) g2h(x) | |
650 | ||
651 | #else /* !CONFIG_USER_ONLY */ | |
652 | /* NOTE: we use double casts if pointers and target_ulong have | |
653 | different sizes */ | |
654 | #define saddr(x) (uint8_t *)(long)(x) | |
655 | #define laddr(x) (uint8_t *)(long)(x) | |
656 | #endif | |
657 | ||
658 | #define ldub_raw(p) ldub_p(laddr((p))) | |
659 | #define ldsb_raw(p) ldsb_p(laddr((p))) | |
660 | #define lduw_raw(p) lduw_p(laddr((p))) | |
661 | #define ldsw_raw(p) ldsw_p(laddr((p))) | |
662 | #define ldl_raw(p) ldl_p(laddr((p))) | |
663 | #define ldq_raw(p) ldq_p(laddr((p))) | |
664 | #define ldfl_raw(p) ldfl_p(laddr((p))) | |
665 | #define ldfq_raw(p) ldfq_p(laddr((p))) | |
666 | #define stb_raw(p, v) stb_p(saddr((p)), v) | |
667 | #define stw_raw(p, v) stw_p(saddr((p)), v) | |
668 | #define stl_raw(p, v) stl_p(saddr((p)), v) | |
669 | #define stq_raw(p, v) stq_p(saddr((p)), v) | |
670 | #define stfl_raw(p, v) stfl_p(saddr((p)), v) | |
671 | #define stfq_raw(p, v) stfq_p(saddr((p)), v) | |
672 | ||
673 | ||
674 | #if defined(CONFIG_USER_ONLY) | |
675 | ||
676 | /* if user mode, no other memory access functions */ | |
677 | #define ldub(p) ldub_raw(p) | |
678 | #define ldsb(p) ldsb_raw(p) | |
679 | #define lduw(p) lduw_raw(p) | |
680 | #define ldsw(p) ldsw_raw(p) | |
681 | #define ldl(p) ldl_raw(p) | |
682 | #define ldq(p) ldq_raw(p) | |
683 | #define ldfl(p) ldfl_raw(p) | |
684 | #define ldfq(p) ldfq_raw(p) | |
685 | #define stb(p, v) stb_raw(p, v) | |
686 | #define stw(p, v) stw_raw(p, v) | |
687 | #define stl(p, v) stl_raw(p, v) | |
688 | #define stq(p, v) stq_raw(p, v) | |
689 | #define stfl(p, v) stfl_raw(p, v) | |
690 | #define stfq(p, v) stfq_raw(p, v) | |
691 | ||
692 | #define ldub_code(p) ldub_raw(p) | |
693 | #define ldsb_code(p) ldsb_raw(p) | |
694 | #define lduw_code(p) lduw_raw(p) | |
695 | #define ldsw_code(p) ldsw_raw(p) | |
696 | #define ldl_code(p) ldl_raw(p) | |
697 | #define ldq_code(p) ldq_raw(p) | |
698 | ||
699 | #define ldub_kernel(p) ldub_raw(p) | |
700 | #define ldsb_kernel(p) ldsb_raw(p) | |
701 | #define lduw_kernel(p) lduw_raw(p) | |
702 | #define ldsw_kernel(p) ldsw_raw(p) | |
703 | #define ldl_kernel(p) ldl_raw(p) | |
704 | #define ldq_kernel(p) ldq_raw(p) | |
705 | #define ldfl_kernel(p) ldfl_raw(p) | |
706 | #define ldfq_kernel(p) ldfq_raw(p) | |
707 | #define stb_kernel(p, v) stb_raw(p, v) | |
708 | #define stw_kernel(p, v) stw_raw(p, v) | |
709 | #define stl_kernel(p, v) stl_raw(p, v) | |
710 | #define stq_kernel(p, v) stq_raw(p, v) | |
711 | #define stfl_kernel(p, v) stfl_raw(p, v) | |
712 | #define stfq_kernel(p, vt) stfq_raw(p, v) | |
713 | ||
714 | #endif /* defined(CONFIG_USER_ONLY) */ | |
715 | ||
716 | /* page related stuff */ | |
717 | ||
718 | #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) | |
719 | #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) | |
720 | #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) | |
721 | ||
722 | /* ??? These should be the larger of unsigned long and target_ulong. */ | |
723 | extern unsigned long qemu_real_host_page_size; | |
724 | extern unsigned long qemu_host_page_bits; | |
725 | extern unsigned long qemu_host_page_size; | |
726 | extern unsigned long qemu_host_page_mask; | |
727 | ||
728 | #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) | |
729 | ||
730 | /* same as PROT_xxx */ | |
731 | #define PAGE_READ 0x0001 | |
732 | #define PAGE_WRITE 0x0002 | |
733 | #define PAGE_EXEC 0x0004 | |
734 | #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) | |
735 | #define PAGE_VALID 0x0008 | |
736 | /* original state of the write flag (used when tracking self-modifying | |
737 | code */ | |
738 | #define PAGE_WRITE_ORG 0x0010 | |
739 | #define PAGE_RESERVED 0x0020 | |
740 | ||
741 | void page_dump(FILE *f); | |
742 | int page_get_flags(target_ulong address); | |
743 | void page_set_flags(target_ulong start, target_ulong end, int flags); | |
744 | int page_check_range(target_ulong start, target_ulong len, int flags); | |
745 | ||
746 | void cpu_exec_init_all(unsigned long tb_size); | |
747 | CPUState *cpu_copy(CPUState *env); | |
748 | ||
749 | void cpu_dump_state(CPUState *env, FILE *f, | |
750 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), | |
751 | int flags); | |
752 | void cpu_dump_statistics (CPUState *env, FILE *f, | |
753 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), | |
754 | int flags); | |
755 | ||
756 | void noreturn cpu_abort(CPUState *env, const char *fmt, ...) | |
757 | __attribute__ ((__format__ (__printf__, 2, 3))); | |
758 | extern CPUState *first_cpu; | |
759 | extern CPUState *cpu_single_env; | |
760 | extern int64_t qemu_icount; | |
761 | extern int use_icount; | |
762 | ||
763 | #define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */ | |
764 | #define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */ | |
765 | #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */ | |
766 | #define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */ | |
767 | #define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */ | |
768 | #define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */ | |
769 | #define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */ | |
770 | #define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */ | |
771 | #define CPU_INTERRUPT_VIRQ 0x100 /* virtual interrupt pending. */ | |
772 | #define CPU_INTERRUPT_NMI 0x200 /* NMI pending. */ | |
773 | ||
774 | void cpu_interrupt(CPUState *s, int mask); | |
775 | void cpu_reset_interrupt(CPUState *env, int mask); | |
776 | ||
777 | /* Breakpoint/watchpoint flags */ | |
778 | #define BP_MEM_READ 0x01 | |
779 | #define BP_MEM_WRITE 0x02 | |
780 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) | |
781 | #define BP_STOP_BEFORE_ACCESS 0x04 | |
782 | #define BP_WATCHPOINT_HIT 0x08 | |
783 | #define BP_GDB 0x10 | |
784 | #define BP_CPU 0x20 | |
785 | ||
786 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, | |
787 | CPUBreakpoint **breakpoint); | |
788 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags); | |
789 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint); | |
790 | void cpu_breakpoint_remove_all(CPUState *env, int mask); | |
791 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, | |
792 | int flags, CPUWatchpoint **watchpoint); | |
793 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, | |
794 | target_ulong len, int flags); | |
795 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint); | |
796 | void cpu_watchpoint_remove_all(CPUState *env, int mask); | |
797 | ||
798 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ | |
799 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
800 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
801 | ||
802 | void cpu_single_step(CPUState *env, int enabled); | |
803 | void cpu_reset(CPUState *s); | |
804 | ||
805 | /* Return the physical page corresponding to a virtual one. Use it | |
806 | only for debugging because no protection checks are done. Return -1 | |
807 | if no page found. */ | |
808 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr); | |
809 | ||
810 | #define CPU_LOG_TB_OUT_ASM (1 << 0) | |
811 | #define CPU_LOG_TB_IN_ASM (1 << 1) | |
812 | #define CPU_LOG_TB_OP (1 << 2) | |
813 | #define CPU_LOG_TB_OP_OPT (1 << 3) | |
814 | #define CPU_LOG_INT (1 << 4) | |
815 | #define CPU_LOG_EXEC (1 << 5) | |
816 | #define CPU_LOG_PCALL (1 << 6) | |
817 | #define CPU_LOG_IOPORT (1 << 7) | |
818 | #define CPU_LOG_TB_CPU (1 << 8) | |
819 | ||
820 | /* define log items */ | |
821 | typedef struct CPULogItem { | |
822 | int mask; | |
823 | const char *name; | |
824 | const char *help; | |
825 | } CPULogItem; | |
826 | ||
827 | extern const CPULogItem cpu_log_items[]; | |
828 | ||
829 | void cpu_set_log(int log_flags); | |
830 | void cpu_set_log_filename(const char *filename); | |
831 | int cpu_str_to_log_mask(const char *str); | |
832 | ||
833 | /* IO ports API */ | |
834 | ||
835 | /* NOTE: as these functions may be even used when there is an isa | |
836 | brige on non x86 targets, we always defined them */ | |
837 | #ifndef NO_CPU_IO_DEFS | |
838 | void cpu_outb(CPUState *env, int addr, int val); | |
839 | void cpu_outw(CPUState *env, int addr, int val); | |
840 | void cpu_outl(CPUState *env, int addr, int val); | |
841 | int cpu_inb(CPUState *env, int addr); | |
842 | int cpu_inw(CPUState *env, int addr); | |
843 | int cpu_inl(CPUState *env, int addr); | |
844 | #endif | |
845 | ||
846 | /* address in the RAM (different from a physical address) */ | |
847 | #ifdef USE_KQEMU | |
848 | typedef uint32_t ram_addr_t; | |
849 | #else | |
850 | typedef unsigned long ram_addr_t; | |
851 | #endif | |
852 | ||
853 | /* memory API */ | |
854 | ||
855 | extern ram_addr_t phys_ram_size; | |
856 | extern int phys_ram_fd; | |
857 | extern uint8_t *phys_ram_base; | |
858 | extern uint8_t *phys_ram_dirty; | |
859 | extern ram_addr_t ram_size; | |
860 | ||
861 | /* physical memory access */ | |
862 | ||
863 | /* MMIO pages are identified by a combination of an IO device index and | |
864 | 3 flags. The ROMD code stores the page ram offset in iotlb entry, | |
865 | so only a limited number of ids are avaiable. */ | |
866 | ||
867 | #define IO_MEM_SHIFT 3 | |
868 | #define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT)) | |
869 | ||
870 | #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */ | |
871 | #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */ | |
872 | #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT) | |
873 | #define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT) | |
874 | ||
875 | /* Acts like a ROM when read and like a device when written. */ | |
876 | #define IO_MEM_ROMD (1) | |
877 | #define IO_MEM_SUBPAGE (2) | |
878 | #define IO_MEM_SUBWIDTH (4) | |
879 | ||
880 | /* Flags stored in the low bits of the TLB virtual address. These are | |
881 | defined so that fast path ram access is all zeros. */ | |
882 | /* Zero if TLB entry is valid. */ | |
883 | #define TLB_INVALID_MASK (1 << 3) | |
884 | /* Set if TLB entry references a clean RAM page. The iotlb entry will | |
885 | contain the page physical address. */ | |
886 | #define TLB_NOTDIRTY (1 << 4) | |
887 | /* Set if TLB entry is an IO callback. */ | |
888 | #define TLB_MMIO (1 << 5) | |
889 | ||
890 | typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value); | |
891 | typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr); | |
892 | ||
893 | void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, | |
894 | ram_addr_t size, | |
895 | ram_addr_t phys_offset, | |
896 | ram_addr_t region_offset); | |
897 | static inline void cpu_register_physical_memory(target_phys_addr_t start_addr, | |
898 | ram_addr_t size, | |
899 | ram_addr_t phys_offset) | |
900 | { | |
901 | cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0); | |
902 | } | |
903 | ||
904 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr); | |
905 | ram_addr_t qemu_ram_alloc(ram_addr_t); | |
906 | void qemu_ram_free(ram_addr_t addr); | |
907 | int cpu_register_io_memory(int io_index, | |
908 | CPUReadMemoryFunc **mem_read, | |
909 | CPUWriteMemoryFunc **mem_write, | |
910 | void *opaque); | |
911 | CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index); | |
912 | CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index); | |
913 | ||
914 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, | |
915 | int len, int is_write); | |
916 | static inline void cpu_physical_memory_read(target_phys_addr_t addr, | |
917 | uint8_t *buf, int len) | |
918 | { | |
919 | cpu_physical_memory_rw(addr, buf, len, 0); | |
920 | } | |
921 | static inline void cpu_physical_memory_write(target_phys_addr_t addr, | |
922 | const uint8_t *buf, int len) | |
923 | { | |
924 | cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1); | |
925 | } | |
926 | void *cpu_physical_memory_map(target_phys_addr_t addr, | |
927 | target_phys_addr_t *plen, | |
928 | int is_write); | |
929 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, | |
930 | int is_write, target_phys_addr_t access_len); | |
931 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)); | |
932 | void cpu_unregister_map_client(void *cookie); | |
933 | ||
934 | uint32_t ldub_phys(target_phys_addr_t addr); | |
935 | uint32_t lduw_phys(target_phys_addr_t addr); | |
936 | uint32_t ldl_phys(target_phys_addr_t addr); | |
937 | uint64_t ldq_phys(target_phys_addr_t addr); | |
938 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val); | |
939 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val); | |
940 | void stb_phys(target_phys_addr_t addr, uint32_t val); | |
941 | void stw_phys(target_phys_addr_t addr, uint32_t val); | |
942 | void stl_phys(target_phys_addr_t addr, uint32_t val); | |
943 | void stq_phys(target_phys_addr_t addr, uint64_t val); | |
944 | ||
945 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, | |
946 | const uint8_t *buf, int len); | |
947 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, | |
948 | uint8_t *buf, int len, int is_write); | |
949 | ||
950 | #define VGA_DIRTY_FLAG 0x01 | |
951 | #define CODE_DIRTY_FLAG 0x02 | |
952 | #define KQEMU_DIRTY_FLAG 0x04 | |
953 | #define MIGRATION_DIRTY_FLAG 0x08 | |
954 | ||
955 | /* read dirty bit (return 0 or 1) */ | |
956 | static inline int cpu_physical_memory_is_dirty(ram_addr_t addr) | |
957 | { | |
958 | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff; | |
959 | } | |
960 | ||
961 | static inline int cpu_physical_memory_get_dirty(ram_addr_t addr, | |
962 | int dirty_flags) | |
963 | { | |
964 | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags; | |
965 | } | |
966 | ||
967 | static inline void cpu_physical_memory_set_dirty(ram_addr_t addr) | |
968 | { | |
969 | phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff; | |
970 | } | |
971 | ||
972 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, | |
973 | int dirty_flags); | |
974 | void cpu_tlb_update_dirty(CPUState *env); | |
975 | ||
976 | int cpu_physical_memory_set_dirty_tracking(int enable); | |
977 | ||
978 | int cpu_physical_memory_get_dirty_tracking(void); | |
979 | ||
980 | void cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, target_phys_addr_t end_addr); | |
981 | ||
982 | void dump_exec_info(FILE *f, | |
983 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); | |
984 | ||
985 | /* Coalesced MMIO regions are areas where write operations can be reordered. | |
986 | * This usually implies that write operations are side-effect free. This allows | |
987 | * batching which can make a major impact on performance when using | |
988 | * virtualization. | |
989 | */ | |
990 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size); | |
991 | ||
992 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size); | |
993 | ||
994 | /*******************************************/ | |
995 | /* host CPU ticks (if available) */ | |
996 | ||
997 | #if defined(_ARCH_PPC) | |
998 | ||
999 | static inline int64_t cpu_get_real_ticks(void) | |
1000 | { | |
1001 | int64_t retval; | |
1002 | #ifdef _ARCH_PPC64 | |
1003 | /* This reads timebase in one 64bit go and includes Cell workaround from: | |
1004 | http://ozlabs.org/pipermail/linuxppc-dev/2006-October/027052.html | |
1005 | */ | |
1006 | __asm__ __volatile__ ( | |
1007 | "mftb %0\n\t" | |
1008 | "cmpwi %0,0\n\t" | |
1009 | "beq- $-8" | |
1010 | : "=r" (retval)); | |
1011 | #else | |
1012 | /* http://ozlabs.org/pipermail/linuxppc-dev/1999-October/003889.html */ | |
1013 | unsigned long junk; | |
1014 | __asm__ __volatile__ ( | |
1015 | "mftbu %1\n\t" | |
1016 | "mftb %L0\n\t" | |
1017 | "mftbu %0\n\t" | |
1018 | "cmpw %0,%1\n\t" | |
1019 | "bne $-16" | |
1020 | : "=r" (retval), "=r" (junk)); | |
1021 | #endif | |
1022 | return retval; | |
1023 | } | |
1024 | ||
1025 | #elif defined(__i386__) | |
1026 | ||
1027 | static inline int64_t cpu_get_real_ticks(void) | |
1028 | { | |
1029 | int64_t val; | |
1030 | asm volatile ("rdtsc" : "=A" (val)); | |
1031 | return val; | |
1032 | } | |
1033 | ||
1034 | #elif defined(__x86_64__) | |
1035 | ||
1036 | static inline int64_t cpu_get_real_ticks(void) | |
1037 | { | |
1038 | uint32_t low,high; | |
1039 | int64_t val; | |
1040 | asm volatile("rdtsc" : "=a" (low), "=d" (high)); | |
1041 | val = high; | |
1042 | val <<= 32; | |
1043 | val |= low; | |
1044 | return val; | |
1045 | } | |
1046 | ||
1047 | #elif defined(__hppa__) | |
1048 | ||
1049 | static inline int64_t cpu_get_real_ticks(void) | |
1050 | { | |
1051 | int val; | |
1052 | asm volatile ("mfctl %%cr16, %0" : "=r"(val)); | |
1053 | return val; | |
1054 | } | |
1055 | ||
1056 | #elif defined(__ia64) | |
1057 | ||
1058 | static inline int64_t cpu_get_real_ticks(void) | |
1059 | { | |
1060 | int64_t val; | |
1061 | asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory"); | |
1062 | return val; | |
1063 | } | |
1064 | ||
1065 | #elif defined(__s390__) | |
1066 | ||
1067 | static inline int64_t cpu_get_real_ticks(void) | |
1068 | { | |
1069 | int64_t val; | |
1070 | asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc"); | |
1071 | return val; | |
1072 | } | |
1073 | ||
1074 | #elif defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__) | |
1075 | ||
1076 | static inline int64_t cpu_get_real_ticks (void) | |
1077 | { | |
1078 | #if defined(_LP64) | |
1079 | uint64_t rval; | |
1080 | asm volatile("rd %%tick,%0" : "=r"(rval)); | |
1081 | return rval; | |
1082 | #else | |
1083 | union { | |
1084 | uint64_t i64; | |
1085 | struct { | |
1086 | uint32_t high; | |
1087 | uint32_t low; | |
1088 | } i32; | |
1089 | } rval; | |
1090 | asm volatile("rd %%tick,%1; srlx %1,32,%0" | |
1091 | : "=r"(rval.i32.high), "=r"(rval.i32.low)); | |
1092 | return rval.i64; | |
1093 | #endif | |
1094 | } | |
1095 | ||
1096 | #elif defined(__mips__) | |
1097 | ||
1098 | static inline int64_t cpu_get_real_ticks(void) | |
1099 | { | |
1100 | #if __mips_isa_rev >= 2 | |
1101 | uint32_t count; | |
1102 | static uint32_t cyc_per_count = 0; | |
1103 | ||
1104 | if (!cyc_per_count) | |
1105 | __asm__ __volatile__("rdhwr %0, $3" : "=r" (cyc_per_count)); | |
1106 | ||
1107 | __asm__ __volatile__("rdhwr %1, $2" : "=r" (count)); | |
1108 | return (int64_t)(count * cyc_per_count); | |
1109 | #else | |
1110 | /* FIXME */ | |
1111 | static int64_t ticks = 0; | |
1112 | return ticks++; | |
1113 | #endif | |
1114 | } | |
1115 | ||
1116 | #else | |
1117 | /* The host CPU doesn't have an easily accessible cycle counter. | |
1118 | Just return a monotonically increasing value. This will be | |
1119 | totally wrong, but hopefully better than nothing. */ | |
1120 | static inline int64_t cpu_get_real_ticks (void) | |
1121 | { | |
1122 | static int64_t ticks = 0; | |
1123 | return ticks++; | |
1124 | } | |
1125 | #endif | |
1126 | ||
1127 | /* profiling */ | |
1128 | #ifdef CONFIG_PROFILER | |
1129 | static inline int64_t profile_getclock(void) | |
1130 | { | |
1131 | return cpu_get_real_ticks(); | |
1132 | } | |
1133 | ||
1134 | extern int64_t kqemu_time, kqemu_time_start; | |
1135 | extern int64_t qemu_time, qemu_time_start; | |
1136 | extern int64_t tlb_flush_time; | |
1137 | extern int64_t kqemu_exec_count; | |
1138 | extern int64_t dev_time; | |
1139 | extern int64_t kqemu_ret_int_count; | |
1140 | extern int64_t kqemu_ret_excp_count; | |
1141 | extern int64_t kqemu_ret_intr_count; | |
1142 | #endif | |
1143 | ||
1144 | #endif /* CPU_ALL_H */ |