[qemu.git] / cpu-common.h

#ifndef CPU_COMMON_H
#define CPU_COMMON_H 1

/* CPU interfaces that are target indpendent.  */

#if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__)
#define WORDS_ALIGNED
#endif

#ifdef TARGET_PHYS_ADDR_BITS
#include "targphys.h"
#endif

#ifndef NEED_CPU_H
#include "poison.h"
#endif

#include "bswap.h"
#include "qemu-queue.h"

#if !defined(CONFIG_USER_ONLY)

enum device_endian {
    DEVICE_NATIVE_ENDIAN,
    DEVICE_BIG_ENDIAN,
    DEVICE_LITTLE_ENDIAN,
};

/* address in the RAM (different from a physical address) */
typedef unsigned long ram_addr_t;

/* memory API */

typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);

void cpu_register_physical_memory_log(target_phys_addr_t start_addr,
                                      ram_addr_t size,
                                      ram_addr_t phys_offset,
                                      ram_addr_t region_offset,
                                      bool log_dirty);

static inline void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
                                                       ram_addr_t size,
                                                       ram_addr_t phys_offset,
                                                       ram_addr_t region_offset)
{
    cpu_register_physical_memory_log(start_addr, size, phys_offset,
                                     region_offset, false);
}

static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
                                                ram_addr_t size,
                                                ram_addr_t phys_offset)
{
    cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
}

ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name,
                        ram_addr_t size, void *host);
ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size);
void qemu_ram_free(ram_addr_t addr);
void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
/* This should only be used for ram local to a device.  */
void *qemu_get_ram_ptr(ram_addr_t addr);
/* Same but slower, to use for migration, where the order of
 * RAMBlocks must not change. */
void *qemu_safe_ram_ptr(ram_addr_t addr);
void qemu_put_ram_ptr(void *addr);
/* This should not be used by devices.  */
int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);

int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
                           CPUWriteMemoryFunc * const *mem_write,
                           void *opaque, enum device_endian endian);
void cpu_unregister_io_memory(int table_address);

void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
                            int len, int is_write);
static inline void cpu_physical_memory_read(target_phys_addr_t addr,
                                            void *buf, int len)
{
    cpu_physical_memory_rw(addr, buf, len, 0);
}
static inline void cpu_physical_memory_write(target_phys_addr_t addr,
                                             const void *buf, int len)
{
    cpu_physical_memory_rw(addr, (void *)buf, len, 1);
}
void *cpu_physical_memory_map(target_phys_addr_t addr,
                              target_phys_addr_t *plen,
                              int is_write);
void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
                               int is_write, target_phys_addr_t access_len);
void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
void cpu_unregister_map_client(void *cookie);

struct CPUPhysMemoryClient;
typedef struct CPUPhysMemoryClient CPUPhysMemoryClient;
struct CPUPhysMemoryClient {
    void (*set_memory)(struct CPUPhysMemoryClient *client,
                       target_phys_addr_t start_addr,
                       ram_addr_t size,
                       ram_addr_t phys_offset,
                       bool log_dirty);
    int (*sync_dirty_bitmap)(struct CPUPhysMemoryClient *client,
                             target_phys_addr_t start_addr,
                             target_phys_addr_t end_addr);
    int (*migration_log)(struct CPUPhysMemoryClient *client,
                         int enable);
    int (*log_start)(struct CPUPhysMemoryClient *client,
                     target_phys_addr_t phys_addr, ram_addr_t size);
    int (*log_stop)(struct CPUPhysMemoryClient *client,
                    target_phys_addr_t phys_addr, ram_addr_t size);
    QLIST_ENTRY(CPUPhysMemoryClient) list;
};

void cpu_register_phys_memory_client(CPUPhysMemoryClient *);
void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *);

/* Coalesced MMIO regions are areas where write operations can be reordered.
 * This usually implies that write operations are side-effect free.  This allows
 * batching which can make a major impact on performance when using
 * virtualization.
 */
void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);

void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);

void qemu_flush_coalesced_mmio_buffer(void);

uint32_t ldub_phys(target_phys_addr_t addr);
uint32_t lduw_phys(target_phys_addr_t addr);
uint32_t ldl_phys(target_phys_addr_t addr);
uint64_t ldq_phys(target_phys_addr_t addr);
void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
void stb_phys(target_phys_addr_t addr, uint32_t val);
void stw_phys(target_phys_addr_t addr, uint32_t val);
void stl_phys(target_phys_addr_t addr, uint32_t val);
void stq_phys(target_phys_addr_t addr, uint64_t val);

void cpu_physical_memory_write_rom(target_phys_addr_t addr,
                                   const uint8_t *buf, int len);

#define IO_MEM_SHIFT       3

#define IO_MEM_RAM         (0 << IO_MEM_SHIFT) /* hardcoded offset */
#define IO_MEM_ROM         (1 << IO_MEM_SHIFT) /* hardcoded offset */
#define IO_MEM_UNASSIGNED  (2 << IO_MEM_SHIFT)
#define IO_MEM_NOTDIRTY    (3 << IO_MEM_SHIFT)

/* Acts like a ROM when read and like a device when written.  */
#define IO_MEM_ROMD        (1)
#define IO_MEM_SUBPAGE     (2)

#endif

#endif /* !CPU_COMMON_H */
Commit	Line	Data
	1	#ifndef CPU_COMMON_H
	2	#define CPU_COMMON_H 1
	3
	4	/* CPU interfaces that are target indpendent. */
	5
	6	#if defined(__arm__) \|\| defined(__sparc__) \|\| defined(__mips__) \|\| defined(__hppa__) \|\| defined(__ia64__)
	7	#define WORDS_ALIGNED
	8	#endif
	9
	10	#ifdef TARGET_PHYS_ADDR_BITS
	11	#include "targphys.h"
	12	#endif
	13
	14	#ifndef NEED_CPU_H
	15	#include "poison.h"
	16	#endif
	17
	18	#include "bswap.h"
	19	#include "qemu-queue.h"
	20
	21	#if !defined(CONFIG_USER_ONLY)
	22
	23	enum device_endian {
	24	DEVICE_NATIVE_ENDIAN,
	25	DEVICE_BIG_ENDIAN,
	26	DEVICE_LITTLE_ENDIAN,
	27	};
	28
	29	/* address in the RAM (different from a physical address) */
	30	typedef unsigned long ram_addr_t;
	31
	32	/* memory API */
	33
	34	typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
	35	typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
	36
	37	void cpu_register_physical_memory_log(target_phys_addr_t start_addr,
	38	ram_addr_t size,
	39	ram_addr_t phys_offset,
	40	ram_addr_t region_offset,
	41	bool log_dirty);
	42
	43	static inline void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
	44	ram_addr_t size,
	45	ram_addr_t phys_offset,
	46	ram_addr_t region_offset)
	47	{
	48	cpu_register_physical_memory_log(start_addr, size, phys_offset,
	49	region_offset, false);
	50	}
	51
	52	static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
	53	ram_addr_t size,
	54	ram_addr_t phys_offset)
	55	{
	56	cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
	57	}
	58
	59	ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
	60	ram_addr_t qemu_ram_alloc_from_ptr(DeviceState dev, const char name,
	61	ram_addr_t size, void *host);
	62	ram_addr_t qemu_ram_alloc(DeviceState dev, const char name, ram_addr_t size);
	63	void qemu_ram_free(ram_addr_t addr);
	64	void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
	65	/* This should only be used for ram local to a device. */
	66	void *qemu_get_ram_ptr(ram_addr_t addr);
	67	/* Same but slower, to use for migration, where the order of
	68	* RAMBlocks must not change. */
	69	void *qemu_safe_ram_ptr(ram_addr_t addr);
	70	void qemu_put_ram_ptr(void *addr);
	71	/* This should not be used by devices. */
	72	int qemu_ram_addr_from_host(void ptr, ram_addr_t ram_addr);
	73	ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
	74
	75	int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
	76	CPUWriteMemoryFunc * const *mem_write,
	77	void *opaque, enum device_endian endian);
	78	void cpu_unregister_io_memory(int table_address);
	79
	80	void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
	81	int len, int is_write);
	82	static inline void cpu_physical_memory_read(target_phys_addr_t addr,
	83	void *buf, int len)
	84	{
	85	cpu_physical_memory_rw(addr, buf, len, 0);
	86	}
	87	static inline void cpu_physical_memory_write(target_phys_addr_t addr,
	88	const void *buf, int len)
	89	{
	90	cpu_physical_memory_rw(addr, (void *)buf, len, 1);
	91	}
	92	void *cpu_physical_memory_map(target_phys_addr_t addr,
	93	target_phys_addr_t *plen,
	94	int is_write);
	95	void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
	96	int is_write, target_phys_addr_t access_len);
	97	void cpu_register_map_client(void opaque, void (callback)(void opaque));
	98	void cpu_unregister_map_client(void *cookie);
	99
	100	struct CPUPhysMemoryClient;
	101	typedef struct CPUPhysMemoryClient CPUPhysMemoryClient;
	102	struct CPUPhysMemoryClient {
	103	void (set_memory)(struct CPUPhysMemoryClient client,
	104	target_phys_addr_t start_addr,
	105	ram_addr_t size,
	106	ram_addr_t phys_offset,
	107	bool log_dirty);
	108	int (sync_dirty_bitmap)(struct CPUPhysMemoryClient client,
	109	target_phys_addr_t start_addr,
	110	target_phys_addr_t end_addr);
	111	int (migration_log)(struct CPUPhysMemoryClient client,
	112	int enable);
	113	int (log_start)(struct CPUPhysMemoryClient client,
	114	target_phys_addr_t phys_addr, ram_addr_t size);
	115	int (log_stop)(struct CPUPhysMemoryClient client,
	116	target_phys_addr_t phys_addr, ram_addr_t size);
	117	QLIST_ENTRY(CPUPhysMemoryClient) list;
	118	};
	119
	120	void cpu_register_phys_memory_client(CPUPhysMemoryClient *);
	121	void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *);
	122
	123	/* Coalesced MMIO regions are areas where write operations can be reordered.
	124	* This usually implies that write operations are side-effect free. This allows
	125	* batching which can make a major impact on performance when using
	126	* virtualization.
	127	*/
	128	void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
	129
	130	void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
	131
	132	void qemu_flush_coalesced_mmio_buffer(void);
	133
	134	uint32_t ldub_phys(target_phys_addr_t addr);
	135	uint32_t lduw_phys(target_phys_addr_t addr);
	136	uint32_t ldl_phys(target_phys_addr_t addr);
	137	uint64_t ldq_phys(target_phys_addr_t addr);
	138	void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
	139	void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
	140	void stb_phys(target_phys_addr_t addr, uint32_t val);
	141	void stw_phys(target_phys_addr_t addr, uint32_t val);
	142	void stl_phys(target_phys_addr_t addr, uint32_t val);
	143	void stq_phys(target_phys_addr_t addr, uint64_t val);
	144
	145	void cpu_physical_memory_write_rom(target_phys_addr_t addr,
	146	const uint8_t *buf, int len);
	147
	148	#define IO_MEM_SHIFT 3
	149
	150	#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
	151	#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
	152	#define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
	153	#define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT)
	154
	155	/* Acts like a ROM when read and like a device when written. */
	156	#define IO_MEM_ROMD (1)
	157	#define IO_MEM_SUBPAGE (2)
	158
	159	#endif
	160
	161	#endif /* !CPU_COMMON_H */