[qemu.git] / exec-all.h

/*
 * internal execution defines for qemu
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef _EXEC_ALL_H_
#define _EXEC_ALL_H_

#include "qemu-common.h"

/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS

/* Page tracking code uses ram addresses in system mode, and virtual
   addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
   type.  */
#if defined(CONFIG_USER_ONLY)
typedef abi_ulong tb_page_addr_t;
#else
typedef ram_addr_t tb_page_addr_t;
#endif

/* is_jmp field values */
#define DISAS_NEXT    0 /* next instruction can be analyzed */
#define DISAS_JUMP    1 /* only pc was modified dynamically */
#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */

struct TranslationBlock;
typedef struct TranslationBlock TranslationBlock;

/* XXX: make safe guess about sizes */
#define MAX_OP_PER_INSTR 208

#if HOST_LONG_BITS == 32
#define MAX_OPC_PARAM_PER_ARG 2
#else
#define MAX_OPC_PARAM_PER_ARG 1
#endif
#define MAX_OPC_PARAM_IARGS 4
#define MAX_OPC_PARAM_OARGS 1
#define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)

/* A Call op needs up to 4 + 2N parameters on 32-bit archs,
 * and up to 4 + N parameters on 64-bit archs
 * (N = number of input arguments + output arguments).  */
#define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
#define OPC_BUF_SIZE 640
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)

/* Maximum size a TCG op can expand to.  This is complicated because a
   single op may require several host instructions and register reloads.
   For now take a wild guess at 192 bytes, which should allow at least
   a couple of fixup instructions per argument.  */
#define TCG_MAX_OP_SIZE 192

#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)

extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
extern uint16_t gen_opc_icount[OPC_BUF_SIZE];

#include "qemu-log.h"

void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb);
void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
                          int pc_pos);

void cpu_gen_init(void);
int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
                 int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb,
                      CPUArchState *env, uintptr_t searched_pc);
void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc);
void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, uintptr_t retaddr);
TranslationBlock *tb_gen_code(CPUArchState *env, 
                              target_ulong pc, target_ulong cs_base, int flags,
                              int cflags);
void cpu_exec_init(CPUArchState *env);
void QEMU_NORETURN cpu_loop_exit(CPUArchState *env1);
int page_unprotect(target_ulong address, uintptr_t pc, void *puc);
void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
                                   int is_cpu_write_access);
void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
                              int is_cpu_write_access);
#if !defined(CONFIG_USER_ONLY)
/* cputlb.c */
void tlb_flush_page(CPUArchState *env, target_ulong addr);
void tlb_flush(CPUArchState *env, int flush_global);
void tlb_set_page(CPUArchState *env, target_ulong vaddr,
                  target_phys_addr_t paddr, int prot,
                  int mmu_idx, target_ulong size);
void tb_invalidate_phys_addr(target_phys_addr_t addr);
#else
static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
{
}

static inline void tlb_flush(CPUArchState *env, int flush_global)
{
}
#endif

#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */

#define CODE_GEN_PHYS_HASH_BITS     15
#define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)

#define MIN_CODE_GEN_BUFFER_SIZE     (1024 * 1024)

/* estimated block size for TB allocation */
/* XXX: use a per code average code fragment size and modulate it
   according to the host CPU */
#if defined(CONFIG_SOFTMMU)
#define CODE_GEN_AVG_BLOCK_SIZE 128
#else
#define CODE_GEN_AVG_BLOCK_SIZE 64
#endif

#if defined(__arm__) || defined(_ARCH_PPC) \
    || defined(__x86_64__) || defined(__i386__) \
    || defined(__sparc__) \
    || defined(CONFIG_TCG_INTERPRETER)
#define USE_DIRECT_JUMP
#endif

struct TranslationBlock {
    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
    target_ulong cs_base; /* CS base for this block */
    uint64_t flags; /* flags defining in which context the code was generated */
    uint16_t size;      /* size of target code for this block (1 <=
                           size <= TARGET_PAGE_SIZE) */
    uint16_t cflags;    /* compile flags */
#define CF_COUNT_MASK  0x7fff
#define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */

    uint8_t *tc_ptr;    /* pointer to the translated code */
    /* next matching tb for physical address. */
    struct TranslationBlock *phys_hash_next;
    /* first and second physical page containing code. The lower bit
       of the pointer tells the index in page_next[] */
    struct TranslationBlock *page_next[2];
    tb_page_addr_t page_addr[2];

    /* the following data are used to directly call another TB from
       the code of this one. */
    uint16_t tb_next_offset[2]; /* offset of original jump target */
#ifdef USE_DIRECT_JUMP
    uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
#else
    uintptr_t tb_next[2]; /* address of jump generated code */
#endif
    /* list of TBs jumping to this one. This is a circular list using
       the two least significant bits of the pointers to tell what is
       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
       jmp_first */
    struct TranslationBlock *jmp_next[2];
    struct TranslationBlock *jmp_first;
    uint32_t icount;
};

static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
{
    target_ulong tmp;
    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
    return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
}

static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
{
    target_ulong tmp;
    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
    return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
	    | (tmp & TB_JMP_ADDR_MASK));
}

static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
{
    return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
}

void tb_free(TranslationBlock *tb);
void tb_flush(CPUArchState *env);
void tb_link_page(TranslationBlock *tb,
                  tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);

extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];

#if defined(USE_DIRECT_JUMP)

#if defined(CONFIG_TCG_INTERPRETER)
static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
{
    /* patch the branch destination */
    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
    /* no need to flush icache explicitly */
}
#elif defined(_ARCH_PPC)
void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
#define tb_set_jmp_target1 ppc_tb_set_jmp_target
#elif defined(__i386__) || defined(__x86_64__)
static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
{
    /* patch the branch destination */
    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
    /* no need to flush icache explicitly */
}
#elif defined(__arm__)
static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
{
#if !QEMU_GNUC_PREREQ(4, 1)
    register unsigned long _beg __asm ("a1");
    register unsigned long _end __asm ("a2");
    register unsigned long _flg __asm ("a3");
#endif

    /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
    *(uint32_t *)jmp_addr =
        (*(uint32_t *)jmp_addr & ~0xffffff)
        | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);

#if QEMU_GNUC_PREREQ(4, 1)
    __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
#else
    /* flush icache */
    _beg = jmp_addr;
    _end = jmp_addr + 4;
    _flg = 0;
    __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
#endif
}
#elif defined(__sparc__)
void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
#else
#error tb_set_jmp_target1 is missing
#endif

static inline void tb_set_jmp_target(TranslationBlock *tb,
                                     int n, uintptr_t addr)
{
    uint16_t offset = tb->tb_jmp_offset[n];
    tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
}

#else

/* set the jump target */
static inline void tb_set_jmp_target(TranslationBlock *tb,
                                     int n, uintptr_t addr)
{
    tb->tb_next[n] = addr;
}

#endif

static inline void tb_add_jump(TranslationBlock *tb, int n,
                               TranslationBlock *tb_next)
{
    /* NOTE: this test is only needed for thread safety */
    if (!tb->jmp_next[n]) {
        /* patch the native jump address */
        tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);

        /* add in TB jmp circular list */
        tb->jmp_next[n] = tb_next->jmp_first;
        tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n));
    }
}

TranslationBlock *tb_find_pc(uintptr_t pc_ptr);

#include "qemu-lock.h"

extern spinlock_t tb_lock;

extern int tb_invalidated_flag;

/* The return address may point to the start of the next instruction.
   Subtracting one gets us the call instruction itself.  */
#if defined(CONFIG_TCG_INTERPRETER)
/* Alpha and SH4 user mode emulations and Softmmu call GETPC().
   For all others, GETPC remains undefined (which makes TCI a little faster. */
# if defined(CONFIG_SOFTMMU) || defined(TARGET_ALPHA) || defined(TARGET_SH4)
extern uintptr_t tci_tb_ptr;
#  define GETPC() tci_tb_ptr
# endif
#elif defined(__s390__) && !defined(__s390x__)
# define GETPC() \
    (((uintptr_t)__builtin_return_address(0) & 0x7fffffffUL) - 1)
#elif defined(__arm__)
/* Thumb return addresses have the low bit set, so we need to subtract two.
   This is still safe in ARM mode because instructions are 4 bytes.  */
# define GETPC() ((uintptr_t)__builtin_return_address(0) - 2)
#else
# define GETPC() ((uintptr_t)__builtin_return_address(0) - 1)
#endif

#if !defined(CONFIG_USER_ONLY)

struct MemoryRegion *iotlb_to_region(target_phys_addr_t index);
uint64_t io_mem_read(struct MemoryRegion *mr, target_phys_addr_t addr,
                     unsigned size);
void io_mem_write(struct MemoryRegion *mr, target_phys_addr_t addr,
                  uint64_t value, unsigned size);

void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
              uintptr_t retaddr);

#include "softmmu_defs.h"

#define ACCESS_TYPE (NB_MMU_MODES + 1)
#define MEMSUFFIX _code

#define DATA_SIZE 1
#include "softmmu_header.h"

#define DATA_SIZE 2
#include "softmmu_header.h"

#define DATA_SIZE 4
#include "softmmu_header.h"

#define DATA_SIZE 8
#include "softmmu_header.h"

#undef ACCESS_TYPE
#undef MEMSUFFIX

#endif

#if defined(CONFIG_USER_ONLY)
static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
{
    return addr;
}
#else
/* cputlb.c */
tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
#endif

typedef void (CPUDebugExcpHandler)(CPUArchState *env);

void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);

/* vl.c */
extern int singlestep;

/* cpu-exec.c */
extern volatile sig_atomic_t exit_request;

/* Deterministic execution requires that IO only be performed on the last
   instruction of a TB so that interrupts take effect immediately.  */
static inline int can_do_io(CPUArchState *env)
{
    if (!use_icount) {
        return 1;
    }
    /* If not executing code then assume we are ok.  */
    if (!env->current_tb) {
        return 1;
    }
    return env->can_do_io != 0;
}

#endif
Commit	Line	Data
	1	/*
	2	* internal execution defines for qemu
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#ifndef _EXEC_ALL_H_
	21	#define _EXEC_ALL_H_
	22
	23	#include "qemu-common.h"
	24
	25	/* allow to see translation results - the slowdown should be negligible, so we leave it */
	26	#define DEBUG_DISAS
	27
	28	/* Page tracking code uses ram addresses in system mode, and virtual
	29	addresses in userspace mode. Define tb_page_addr_t to be an appropriate
	30	type. */
	31	#if defined(CONFIG_USER_ONLY)
	32	typedef abi_ulong tb_page_addr_t;
	33	#else
	34	typedef ram_addr_t tb_page_addr_t;
	35	#endif
	36
	37	/* is_jmp field values */
	38	#define DISAS_NEXT 0 /* next instruction can be analyzed */
	39	#define DISAS_JUMP 1 /* only pc was modified dynamically */
	40	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
	41	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
	42
	43	struct TranslationBlock;
	44	typedef struct TranslationBlock TranslationBlock;
	45
	46	/* XXX: make safe guess about sizes */
	47	#define MAX_OP_PER_INSTR 208
	48
	49	#if HOST_LONG_BITS == 32
	50	#define MAX_OPC_PARAM_PER_ARG 2
	51	#else
	52	#define MAX_OPC_PARAM_PER_ARG 1
	53	#endif
	54	#define MAX_OPC_PARAM_IARGS 4
	55	#define MAX_OPC_PARAM_OARGS 1
	56	#define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
	57
	58	/* A Call op needs up to 4 + 2N parameters on 32-bit archs,
	59	* and up to 4 + N parameters on 64-bit archs
	60	* (N = number of input arguments + output arguments). */
	61	#define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
	62	#define OPC_BUF_SIZE 640
	63	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
	64
	65	/* Maximum size a TCG op can expand to. This is complicated because a
	66	single op may require several host instructions and register reloads.
	67	For now take a wild guess at 192 bytes, which should allow at least
	68	a couple of fixup instructions per argument. */
	69	#define TCG_MAX_OP_SIZE 192
	70
	71	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
	72
	73	extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
	74	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
	75	extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
	76
	77	#include "qemu-log.h"
	78
	79	void gen_intermediate_code(CPUArchState env, struct TranslationBlock tb);
	80	void gen_intermediate_code_pc(CPUArchState env, struct TranslationBlock tb);
	81	void restore_state_to_opc(CPUArchState env, struct TranslationBlock tb,
	82	int pc_pos);
	83
	84	void cpu_gen_init(void);
	85	int cpu_gen_code(CPUArchState env, struct TranslationBlock tb,
	86	int *gen_code_size_ptr);
	87	int cpu_restore_state(struct TranslationBlock *tb,
	88	CPUArchState *env, uintptr_t searched_pc);
	89	void QEMU_NORETURN cpu_resume_from_signal(CPUArchState env1, void puc);
	90	void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, uintptr_t retaddr);
	91	TranslationBlock tb_gen_code(CPUArchState env,
	92	target_ulong pc, target_ulong cs_base, int flags,
	93	int cflags);
	94	void cpu_exec_init(CPUArchState *env);
	95	void QEMU_NORETURN cpu_loop_exit(CPUArchState *env1);
	96	int page_unprotect(target_ulong address, uintptr_t pc, void *puc);
	97	void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
	98	int is_cpu_write_access);
	99	void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
	100	int is_cpu_write_access);
	101	#if !defined(CONFIG_USER_ONLY)
	102	/* cputlb.c */
	103	void tlb_flush_page(CPUArchState *env, target_ulong addr);
	104	void tlb_flush(CPUArchState *env, int flush_global);
	105	void tlb_set_page(CPUArchState *env, target_ulong vaddr,
	106	target_phys_addr_t paddr, int prot,
	107	int mmu_idx, target_ulong size);
	108	void tb_invalidate_phys_addr(target_phys_addr_t addr);
	109	#else
	110	static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
	111	{
	112	}
	113
	114	static inline void tlb_flush(CPUArchState *env, int flush_global)
	115	{
	116	}
	117	#endif
	118
	119	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
	120
	121	#define CODE_GEN_PHYS_HASH_BITS 15
	122	#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
	123
	124	#define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
	125
	126	/* estimated block size for TB allocation */
	127	/* XXX: use a per code average code fragment size and modulate it
	128	according to the host CPU */
	129	#if defined(CONFIG_SOFTMMU)
	130	#define CODE_GEN_AVG_BLOCK_SIZE 128
	131	#else
	132	#define CODE_GEN_AVG_BLOCK_SIZE 64
	133	#endif
	134
	135	#if defined(__arm__) \|\| defined(_ARCH_PPC) \
	136	\|\| defined(__x86_64__) \|\| defined(__i386__) \
	137	\|\| defined(__sparc__) \
	138	\|\| defined(CONFIG_TCG_INTERPRETER)
	139	#define USE_DIRECT_JUMP
	140	#endif
	141
	142	struct TranslationBlock {
	143	target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
	144	target_ulong cs_base; /* CS base for this block */
	145	uint64_t flags; /* flags defining in which context the code was generated */
	146	uint16_t size; /* size of target code for this block (1 <=
	147	size <= TARGET_PAGE_SIZE) */
	148	uint16_t cflags; /* compile flags */
	149	#define CF_COUNT_MASK 0x7fff
	150	#define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
	151
	152	uint8_t tc_ptr; / pointer to the translated code */
	153	/* next matching tb for physical address. */
	154	struct TranslationBlock *phys_hash_next;
	155	/* first and second physical page containing code. The lower bit
	156	of the pointer tells the index in page_next[] */
	157	struct TranslationBlock *page_next[2];
	158	tb_page_addr_t page_addr[2];
	159
	160	/* the following data are used to directly call another TB from
	161	the code of this one. */
	162	uint16_t tb_next_offset[2]; /* offset of original jump target */
	163	#ifdef USE_DIRECT_JUMP
	164	uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
	165	#else
	166	uintptr_t tb_next[2]; /* address of jump generated code */
	167	#endif
	168	/* list of TBs jumping to this one. This is a circular list using
	169	the two least significant bits of the pointers to tell what is
	170	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
	171	jmp_first */
	172	struct TranslationBlock *jmp_next[2];
	173	struct TranslationBlock *jmp_first;
	174	uint32_t icount;
	175	};
	176
	177	static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
	178	{
	179	target_ulong tmp;
	180	tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
	181	return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
	182	}
	183
	184	static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
	185	{
	186	target_ulong tmp;
	187	tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
	188	return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
	189	\| (tmp & TB_JMP_ADDR_MASK));
	190	}
	191
	192	static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
	193	{
	194	return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
	195	}
	196
	197	void tb_free(TranslationBlock *tb);
	198	void tb_flush(CPUArchState *env);
	199	void tb_link_page(TranslationBlock *tb,
	200	tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
	201	void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
	202
	203	extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
	204
	205	#if defined(USE_DIRECT_JUMP)
	206
	207	#if defined(CONFIG_TCG_INTERPRETER)
	208	static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
	209	{
	210	/* patch the branch destination */
	211	(uint32_t )jmp_addr = addr - (jmp_addr + 4);
	212	/* no need to flush icache explicitly */
	213	}
	214	#elif defined(_ARCH_PPC)
	215	void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
	216	#define tb_set_jmp_target1 ppc_tb_set_jmp_target
	217	#elif defined(__i386__) \|\| defined(__x86_64__)
	218	static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
	219	{
	220	/* patch the branch destination */
	221	(uint32_t )jmp_addr = addr - (jmp_addr + 4);
	222	/* no need to flush icache explicitly */
	223	}
	224	#elif defined(__arm__)
	225	static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
	226	{
	227	#if !QEMU_GNUC_PREREQ(4, 1)
	228	register unsigned long _beg __asm ("a1");
	229	register unsigned long _end __asm ("a2");
	230	register unsigned long _flg __asm ("a3");
	231	#endif
	232
	233	/* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
	234	(uint32_t )jmp_addr =
	235	((uint32_t )jmp_addr & ~0xffffff)
	236	\| (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
	237
	238	#if QEMU_GNUC_PREREQ(4, 1)
	239	__builtin___clear_cache((char ) jmp_addr, (char ) jmp_addr + 4);
	240	#else
	241	/* flush icache */
	242	_beg = jmp_addr;
	243	_end = jmp_addr + 4;
	244	_flg = 0;
	245	__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
	246	#endif
	247	}
	248	#elif defined(__sparc__)
	249	void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
	250	#else
	251	#error tb_set_jmp_target1 is missing
	252	#endif
	253
	254	static inline void tb_set_jmp_target(TranslationBlock *tb,
	255	int n, uintptr_t addr)
	256	{
	257	uint16_t offset = tb->tb_jmp_offset[n];
	258	tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
	259	}
	260
	261	#else
	262
	263	/* set the jump target */
	264	static inline void tb_set_jmp_target(TranslationBlock *tb,
	265	int n, uintptr_t addr)
	266	{
	267	tb->tb_next[n] = addr;
	268	}
	269
	270	#endif
	271
	272	static inline void tb_add_jump(TranslationBlock *tb, int n,
	273	TranslationBlock *tb_next)
	274	{
	275	/* NOTE: this test is only needed for thread safety */
	276	if (!tb->jmp_next[n]) {
	277	/* patch the native jump address */
	278	tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
	279
	280	/* add in TB jmp circular list */
	281	tb->jmp_next[n] = tb_next->jmp_first;
	282	tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) \| (n));
	283	}
	284	}
	285
	286	TranslationBlock *tb_find_pc(uintptr_t pc_ptr);
	287
	288	#include "qemu-lock.h"
	289
	290	extern spinlock_t tb_lock;
	291
	292	extern int tb_invalidated_flag;
	293
	294	/* The return address may point to the start of the next instruction.
	295	Subtracting one gets us the call instruction itself. */
	296	#if defined(CONFIG_TCG_INTERPRETER)
	297	/* Alpha and SH4 user mode emulations and Softmmu call GETPC().
	298	For all others, GETPC remains undefined (which makes TCI a little faster. */
	299	# if defined(CONFIG_SOFTMMU) \|\| defined(TARGET_ALPHA) \|\| defined(TARGET_SH4)
	300	extern uintptr_t tci_tb_ptr;
	301	# define GETPC() tci_tb_ptr
	302	# endif
	303	#elif defined(__s390__) && !defined(__s390x__)
	304	# define GETPC() \
	305	(((uintptr_t)__builtin_return_address(0) & 0x7fffffffUL) - 1)
	306	#elif defined(__arm__)
	307	/* Thumb return addresses have the low bit set, so we need to subtract two.
	308	This is still safe in ARM mode because instructions are 4 bytes. */
	309	# define GETPC() ((uintptr_t)__builtin_return_address(0) - 2)
	310	#else
	311	# define GETPC() ((uintptr_t)__builtin_return_address(0) - 1)
	312	#endif
	313
	314	#if !defined(CONFIG_USER_ONLY)
	315
	316	struct MemoryRegion *iotlb_to_region(target_phys_addr_t index);
	317	uint64_t io_mem_read(struct MemoryRegion *mr, target_phys_addr_t addr,
	318	unsigned size);
	319	void io_mem_write(struct MemoryRegion *mr, target_phys_addr_t addr,
	320	uint64_t value, unsigned size);
	321
	322	void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
	323	uintptr_t retaddr);
	324
	325	#include "softmmu_defs.h"
	326
	327	#define ACCESS_TYPE (NB_MMU_MODES + 1)
	328	#define MEMSUFFIX _code
	329
	330	#define DATA_SIZE 1
	331	#include "softmmu_header.h"
	332
	333	#define DATA_SIZE 2
	334	#include "softmmu_header.h"
	335
	336	#define DATA_SIZE 4
	337	#include "softmmu_header.h"
	338
	339	#define DATA_SIZE 8
	340	#include "softmmu_header.h"
	341
	342	#undef ACCESS_TYPE
	343	#undef MEMSUFFIX
	344
	345	#endif
	346
	347	#if defined(CONFIG_USER_ONLY)
	348	static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
	349	{
	350	return addr;
	351	}
	352	#else
	353	/* cputlb.c */
	354	tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
	355	#endif
	356
	357	typedef void (CPUDebugExcpHandler)(CPUArchState *env);
	358
	359	void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
	360
	361	/* vl.c */
	362	extern int singlestep;
	363
	364	/* cpu-exec.c */
	365	extern volatile sig_atomic_t exit_request;
	366
	367	/* Deterministic execution requires that IO only be performed on the last
	368	instruction of a TB so that interrupts take effect immediately. */
	369	static inline int can_do_io(CPUArchState *env)
	370	{
	371	if (!use_icount) {
	372	return 1;
	373	}
	374	/* If not executing code then assume we are ok. */
	375	if (!env->current_tb) {
	376	return 1;
	377	}
	378	return env->can_do_io != 0;
	379	}
	380
	381	#endif