[qemu.git] / exec-all.h

/*
 * internal execution defines for qemu
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef _EXEC_ALL_H_
#define _EXEC_ALL_H_

#include "qemu-common.h"

/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS

/* Page tracking code uses ram addresses in system mode, and virtual
   addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
   type.  */
#if defined(CONFIG_USER_ONLY)
typedef abi_ulong tb_page_addr_t;
#else
typedef ram_addr_t tb_page_addr_t;
#endif

/* is_jmp field values */
#define DISAS_NEXT    0 /* next instruction can be analyzed */
#define DISAS_JUMP    1 /* only pc was modified dynamically */
#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */

typedef struct TranslationBlock TranslationBlock;

/* XXX: make safe guess about sizes */
#if (HOST_LONG_BITS == 32) && (TARGET_LONG_BITS == 64)
#define MAX_OP_PER_INSTR 128
#else
#define MAX_OP_PER_INSTR 96
#endif

#if HOST_LONG_BITS == 32
#define MAX_OPC_PARAM_PER_ARG 2
#else
#define MAX_OPC_PARAM_PER_ARG 1
#endif
#define MAX_OPC_PARAM_IARGS 4
#define MAX_OPC_PARAM_OARGS 1
#define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)

/* A Call op needs up to 4 + 2N parameters on 32-bit archs,
 * and up to 4 + N parameters on 64-bit archs
 * (N = number of input arguments + output arguments).  */
#define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
#define OPC_BUF_SIZE 640
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)

/* Maximum size a TCG op can expand to.  This is complicated because a
   single op may require several host instructions and register reloads.
   For now take a wild guess at 192 bytes, which should allow at least
   a couple of fixup instructions per argument.  */
#define TCG_MAX_OP_SIZE 192

#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)

extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
extern uint16_t gen_opc_icount[OPC_BUF_SIZE];

#include "qemu-log.h"

void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
void restore_state_to_opc(CPUState *env, struct TranslationBlock *tb,
                          int pc_pos);

void cpu_gen_init(void);
int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
                 int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb,
                      CPUState *env, unsigned long searched_pc);
void cpu_resume_from_signal(CPUState *env1, void *puc);
void cpu_io_recompile(CPUState *env, void *retaddr);
TranslationBlock *tb_gen_code(CPUState *env, 
                              target_ulong pc, target_ulong cs_base, int flags,
                              int cflags);
void cpu_exec_init(CPUState *env);
void QEMU_NORETURN cpu_loop_exit(void);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
                                   int is_cpu_write_access);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
#if !defined(CONFIG_USER_ONLY)
void tlb_set_page(CPUState *env, target_ulong vaddr,
                  target_phys_addr_t paddr, int prot,
                  int mmu_idx, target_ulong size);
#endif

#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */

#define CODE_GEN_PHYS_HASH_BITS     15
#define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)

#define MIN_CODE_GEN_BUFFER_SIZE     (1024 * 1024)

/* estimated block size for TB allocation */
/* XXX: use a per code average code fragment size and modulate it
   according to the host CPU */
#if defined(CONFIG_SOFTMMU)
#define CODE_GEN_AVG_BLOCK_SIZE 128
#else
#define CODE_GEN_AVG_BLOCK_SIZE 64
#endif

#if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
#define USE_DIRECT_JUMP
#endif

struct TranslationBlock {
    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
    target_ulong cs_base; /* CS base for this block */
    uint64_t flags; /* flags defining in which context the code was generated */
    uint16_t size;      /* size of target code for this block (1 <=
                           size <= TARGET_PAGE_SIZE) */
    uint16_t cflags;    /* compile flags */
#define CF_COUNT_MASK  0x7fff
#define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */

    uint8_t *tc_ptr;    /* pointer to the translated code */
    /* next matching tb for physical address. */
    struct TranslationBlock *phys_hash_next;
    /* first and second physical page containing code. The lower bit
       of the pointer tells the index in page_next[] */
    struct TranslationBlock *page_next[2];
    tb_page_addr_t page_addr[2];

    /* the following data are used to directly call another TB from
       the code of this one. */
    uint16_t tb_next_offset[2]; /* offset of original jump target */
#ifdef USE_DIRECT_JUMP
    uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
#else
    unsigned long tb_next[2]; /* address of jump generated code */
#endif
    /* list of TBs jumping to this one. This is a circular list using
       the two least significant bits of the pointers to tell what is
       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
       jmp_first */
    struct TranslationBlock *jmp_next[2];
    struct TranslationBlock *jmp_first;
    uint32_t icount;
};

static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
{
    target_ulong tmp;
    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
    return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
}

static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
{
    target_ulong tmp;
    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
    return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
	    | (tmp & TB_JMP_ADDR_MASK));
}

static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
{
    return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
}

void tb_free(TranslationBlock *tb);
void tb_flush(CPUState *env);
void tb_link_page(TranslationBlock *tb,
                  tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);

extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];

#if defined(USE_DIRECT_JUMP)

#if defined(_ARCH_PPC)
void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
#define tb_set_jmp_target1 ppc_tb_set_jmp_target
#elif defined(__i386__) || defined(__x86_64__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    /* patch the branch destination */
    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
    /* no need to flush icache explicitly */
}
#elif defined(__arm__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
#if !QEMU_GNUC_PREREQ(4, 1)
    register unsigned long _beg __asm ("a1");
    register unsigned long _end __asm ("a2");
    register unsigned long _flg __asm ("a3");
#endif

    /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
    *(uint32_t *)jmp_addr =
        (*(uint32_t *)jmp_addr & ~0xffffff)
        | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);

#if QEMU_GNUC_PREREQ(4, 1)
    __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
#else
    /* flush icache */
    _beg = jmp_addr;
    _end = jmp_addr + 4;
    _flg = 0;
    __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
#endif
}
#endif

static inline void tb_set_jmp_target(TranslationBlock *tb,
                                     int n, unsigned long addr)
{
    unsigned long offset;

    offset = tb->tb_jmp_offset[n];
    tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
}

#else

/* set the jump target */
static inline void tb_set_jmp_target(TranslationBlock *tb,
                                     int n, unsigned long addr)
{
    tb->tb_next[n] = addr;
}

#endif

static inline void tb_add_jump(TranslationBlock *tb, int n,
                               TranslationBlock *tb_next)
{
    /* NOTE: this test is only needed for thread safety */
    if (!tb->jmp_next[n]) {
        /* patch the native jump address */
        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);

        /* add in TB jmp circular list */
        tb->jmp_next[n] = tb_next->jmp_first;
        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
    }
}

TranslationBlock *tb_find_pc(unsigned long pc_ptr);

#include "qemu-lock.h"

extern spinlock_t tb_lock;

extern int tb_invalidated_flag;

#if !defined(CONFIG_USER_ONLY)

extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];

void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
              void *retaddr);

#include "softmmu_defs.h"

#define ACCESS_TYPE (NB_MMU_MODES + 1)
#define MEMSUFFIX _code
#define env cpu_single_env

#define DATA_SIZE 1
#include "softmmu_header.h"

#define DATA_SIZE 2
#include "softmmu_header.h"

#define DATA_SIZE 4
#include "softmmu_header.h"

#define DATA_SIZE 8
#include "softmmu_header.h"

#undef ACCESS_TYPE
#undef MEMSUFFIX
#undef env

#endif

#if defined(CONFIG_USER_ONLY)
static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
{
    return addr;
}
#else
/* NOTE: this function can trigger an exception */
/* NOTE2: the returned address is not exactly the physical address: it
   is the offset relative to phys_ram_base */
static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
{
    int mmu_idx, page_index, pd;
    void *p;

    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    mmu_idx = cpu_mmu_index(env1);
    if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
                 (addr & TARGET_PAGE_MASK))) {
        ldub_code(addr);
    }
    pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
    if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
#if defined(TARGET_SPARC) || defined(TARGET_MIPS)
        do_unassigned_access(addr, 0, 1, 0, 4);
#else
        cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
#endif
    }
    p = (void *)(unsigned long)addr
        + env1->tlb_table[mmu_idx][page_index].addend;
    return qemu_ram_addr_from_host_nofail(p);
}
#endif

typedef void (CPUDebugExcpHandler)(CPUState *env);

CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);

/* vl.c */
extern int singlestep;

/* cpu-exec.c */
extern volatile sig_atomic_t exit_request;

#endif
Commit	Line	Data
	1	/*
	2	* internal execution defines for qemu
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#ifndef _EXEC_ALL_H_
	21	#define _EXEC_ALL_H_
	22
	23	#include "qemu-common.h"
	24
	25	/* allow to see translation results - the slowdown should be negligible, so we leave it */
	26	#define DEBUG_DISAS
	27
	28	/* Page tracking code uses ram addresses in system mode, and virtual
	29	addresses in userspace mode. Define tb_page_addr_t to be an appropriate
	30	type. */
	31	#if defined(CONFIG_USER_ONLY)
	32	typedef abi_ulong tb_page_addr_t;
	33	#else
	34	typedef ram_addr_t tb_page_addr_t;
	35	#endif
	36
	37	/* is_jmp field values */
	38	#define DISAS_NEXT 0 /* next instruction can be analyzed */
	39	#define DISAS_JUMP 1 /* only pc was modified dynamically */
	40	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
	41	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
	42
	43	typedef struct TranslationBlock TranslationBlock;
	44
	45	/* XXX: make safe guess about sizes */
	46	#if (HOST_LONG_BITS == 32) && (TARGET_LONG_BITS == 64)
	47	#define MAX_OP_PER_INSTR 128
	48	#else
	49	#define MAX_OP_PER_INSTR 96
	50	#endif
	51
	52	#if HOST_LONG_BITS == 32
	53	#define MAX_OPC_PARAM_PER_ARG 2
	54	#else
	55	#define MAX_OPC_PARAM_PER_ARG 1
	56	#endif
	57	#define MAX_OPC_PARAM_IARGS 4
	58	#define MAX_OPC_PARAM_OARGS 1
	59	#define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
	60
	61	/* A Call op needs up to 4 + 2N parameters on 32-bit archs,
	62	* and up to 4 + N parameters on 64-bit archs
	63	* (N = number of input arguments + output arguments). */
	64	#define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
	65	#define OPC_BUF_SIZE 640
	66	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
	67
	68	/* Maximum size a TCG op can expand to. This is complicated because a
	69	single op may require several host instructions and register reloads.
	70	For now take a wild guess at 192 bytes, which should allow at least
	71	a couple of fixup instructions per argument. */
	72	#define TCG_MAX_OP_SIZE 192
	73
	74	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
	75
	76	extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
	77	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
	78	extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
	79
	80	#include "qemu-log.h"
	81
	82	void gen_intermediate_code(CPUState env, struct TranslationBlock tb);
	83	void gen_intermediate_code_pc(CPUState env, struct TranslationBlock tb);
	84	void restore_state_to_opc(CPUState env, struct TranslationBlock tb,
	85	int pc_pos);
	86
	87	void cpu_gen_init(void);
	88	int cpu_gen_code(CPUState env, struct TranslationBlock tb,
	89	int *gen_code_size_ptr);
	90	int cpu_restore_state(struct TranslationBlock *tb,
	91	CPUState *env, unsigned long searched_pc);
	92	void cpu_resume_from_signal(CPUState env1, void puc);
	93	void cpu_io_recompile(CPUState env, void retaddr);
	94	TranslationBlock tb_gen_code(CPUState env,
	95	target_ulong pc, target_ulong cs_base, int flags,
	96	int cflags);
	97	void cpu_exec_init(CPUState *env);
	98	void QEMU_NORETURN cpu_loop_exit(void);
	99	int page_unprotect(target_ulong address, unsigned long pc, void *puc);
	100	void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
	101	int is_cpu_write_access);
	102	void tlb_flush_page(CPUState *env, target_ulong addr);
	103	void tlb_flush(CPUState *env, int flush_global);
	104	#if !defined(CONFIG_USER_ONLY)
	105	void tlb_set_page(CPUState *env, target_ulong vaddr,
	106	target_phys_addr_t paddr, int prot,
	107	int mmu_idx, target_ulong size);
	108	#endif
	109
	110	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
	111
	112	#define CODE_GEN_PHYS_HASH_BITS 15
	113	#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
	114
	115	#define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
	116
	117	/* estimated block size for TB allocation */
	118	/* XXX: use a per code average code fragment size and modulate it
	119	according to the host CPU */
	120	#if defined(CONFIG_SOFTMMU)
	121	#define CODE_GEN_AVG_BLOCK_SIZE 128
	122	#else
	123	#define CODE_GEN_AVG_BLOCK_SIZE 64
	124	#endif
	125
	126	#if defined(_ARCH_PPC) \|\| defined(__x86_64__) \|\| defined(__arm__) \|\| defined(__i386__)
	127	#define USE_DIRECT_JUMP
	128	#endif
	129
	130	struct TranslationBlock {
	131	target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
	132	target_ulong cs_base; /* CS base for this block */
	133	uint64_t flags; /* flags defining in which context the code was generated */
	134	uint16_t size; /* size of target code for this block (1 <=
	135	size <= TARGET_PAGE_SIZE) */
	136	uint16_t cflags; /* compile flags */
	137	#define CF_COUNT_MASK 0x7fff
	138	#define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
	139
	140	uint8_t tc_ptr; / pointer to the translated code */
	141	/* next matching tb for physical address. */
	142	struct TranslationBlock *phys_hash_next;
	143	/* first and second physical page containing code. The lower bit
	144	of the pointer tells the index in page_next[] */
	145	struct TranslationBlock *page_next[2];
	146	tb_page_addr_t page_addr[2];
	147
	148	/* the following data are used to directly call another TB from
	149	the code of this one. */
	150	uint16_t tb_next_offset[2]; /* offset of original jump target */
	151	#ifdef USE_DIRECT_JUMP
	152	uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
	153	#else
	154	unsigned long tb_next[2]; /* address of jump generated code */
	155	#endif
	156	/* list of TBs jumping to this one. This is a circular list using
	157	the two least significant bits of the pointers to tell what is
	158	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
	159	jmp_first */
	160	struct TranslationBlock *jmp_next[2];
	161	struct TranslationBlock *jmp_first;
	162	uint32_t icount;
	163	};
	164
	165	static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
	166	{
	167	target_ulong tmp;
	168	tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
	169	return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
	170	}
	171
	172	static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
	173	{
	174	target_ulong tmp;
	175	tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
	176	return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
	177	\| (tmp & TB_JMP_ADDR_MASK));
	178	}
	179
	180	static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
	181	{
	182	return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
	183	}
	184
	185	void tb_free(TranslationBlock *tb);
	186	void tb_flush(CPUState *env);
	187	void tb_link_page(TranslationBlock *tb,
	188	tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
	189	void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
	190
	191	extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
	192
	193	#if defined(USE_DIRECT_JUMP)
	194
	195	#if defined(_ARCH_PPC)
	196	void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
	197	#define tb_set_jmp_target1 ppc_tb_set_jmp_target
	198	#elif defined(__i386__) \|\| defined(__x86_64__)
	199	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
	200	{
	201	/* patch the branch destination */
	202	(uint32_t )jmp_addr = addr - (jmp_addr + 4);
	203	/* no need to flush icache explicitly */
	204	}
	205	#elif defined(__arm__)
	206	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
	207	{
	208	#if !QEMU_GNUC_PREREQ(4, 1)
	209	register unsigned long _beg __asm ("a1");
	210	register unsigned long _end __asm ("a2");
	211	register unsigned long _flg __asm ("a3");
	212	#endif
	213
	214	/* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
	215	(uint32_t )jmp_addr =
	216	((uint32_t )jmp_addr & ~0xffffff)
	217	\| (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
	218
	219	#if QEMU_GNUC_PREREQ(4, 1)
	220	__builtin___clear_cache((char ) jmp_addr, (char ) jmp_addr + 4);
	221	#else
	222	/* flush icache */
	223	_beg = jmp_addr;
	224	_end = jmp_addr + 4;
	225	_flg = 0;
	226	__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
	227	#endif
	228	}
	229	#endif
	230
	231	static inline void tb_set_jmp_target(TranslationBlock *tb,
	232	int n, unsigned long addr)
	233	{
	234	unsigned long offset;
	235
	236	offset = tb->tb_jmp_offset[n];
	237	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	238	}
	239
	240	#else
	241
	242	/* set the jump target */
	243	static inline void tb_set_jmp_target(TranslationBlock *tb,
	244	int n, unsigned long addr)
	245	{
	246	tb->tb_next[n] = addr;
	247	}
	248
	249	#endif
	250
	251	static inline void tb_add_jump(TranslationBlock *tb, int n,
	252	TranslationBlock *tb_next)
	253	{
	254	/* NOTE: this test is only needed for thread safety */
	255	if (!tb->jmp_next[n]) {
	256	/* patch the native jump address */
	257	tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
	258
	259	/* add in TB jmp circular list */
	260	tb->jmp_next[n] = tb_next->jmp_first;
	261	tb_next->jmp_first = (TranslationBlock *)((long)(tb) \| (n));
	262	}
	263	}
	264
	265	TranslationBlock *tb_find_pc(unsigned long pc_ptr);
	266
	267	#include "qemu-lock.h"
	268
	269	extern spinlock_t tb_lock;
	270
	271	extern int tb_invalidated_flag;
	272
	273	#if !defined(CONFIG_USER_ONLY)
	274
	275	extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
	276	extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
	277	extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
	278
	279	void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
	280	void *retaddr);
	281
	282	#include "softmmu_defs.h"
	283
	284	#define ACCESS_TYPE (NB_MMU_MODES + 1)
	285	#define MEMSUFFIX _code
	286	#define env cpu_single_env
	287
	288	#define DATA_SIZE 1
	289	#include "softmmu_header.h"
	290
	291	#define DATA_SIZE 2
	292	#include "softmmu_header.h"
	293
	294	#define DATA_SIZE 4
	295	#include "softmmu_header.h"
	296
	297	#define DATA_SIZE 8
	298	#include "softmmu_header.h"
	299
	300	#undef ACCESS_TYPE
	301	#undef MEMSUFFIX
	302	#undef env
	303
	304	#endif
	305
	306	#if defined(CONFIG_USER_ONLY)
	307	static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
	308	{
	309	return addr;
	310	}
	311	#else
	312	/* NOTE: this function can trigger an exception */
	313	/* NOTE2: the returned address is not exactly the physical address: it
	314	is the offset relative to phys_ram_base */
	315	static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
	316	{
	317	int mmu_idx, page_index, pd;
	318	void *p;
	319
	320	page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	321	mmu_idx = cpu_mmu_index(env1);
	322	if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
	323	(addr & TARGET_PAGE_MASK))) {
	324	ldub_code(addr);
	325	}
	326	pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
	327	if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
	328	#if defined(TARGET_SPARC) \|\| defined(TARGET_MIPS)
	329	do_unassigned_access(addr, 0, 1, 0, 4);
	330	#else
	331	cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
	332	#endif
	333	}
	334	p = (void *)(unsigned long)addr
	335	+ env1->tlb_table[mmu_idx][page_index].addend;
	336	return qemu_ram_addr_from_host_nofail(p);
	337	}
	338	#endif
	339
	340	typedef void (CPUDebugExcpHandler)(CPUState *env);
	341
	342	CPUDebugExcpHandler cpu_set_debug_excp_handler(CPUDebugExcpHandler handler);
	343
	344	/* vl.c */
	345	extern int singlestep;
	346
	347	/* cpu-exec.c */
	348	extern volatile sig_atomic_t exit_request;
	349
	350	#endif