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1 | /* | |
2 | * virtual page mapping and translated block handling | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #include "config.h" | |
20 | #ifdef _WIN32 | |
21 | #include <windows.h> | |
22 | #else | |
23 | #include <sys/types.h> | |
24 | #include <sys/mman.h> | |
25 | #endif | |
26 | ||
27 | #include "qemu-common.h" | |
28 | #include "cpu.h" | |
29 | #include "exec-all.h" | |
30 | #include "tcg.h" | |
31 | #include "hw/hw.h" | |
32 | #include "hw/qdev.h" | |
33 | #include "osdep.h" | |
34 | #include "kvm.h" | |
35 | #include "qemu-timer.h" | |
36 | #if defined(CONFIG_USER_ONLY) | |
37 | #include <qemu.h> | |
38 | #include <signal.h> | |
39 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) | |
40 | #include <sys/param.h> | |
41 | #if __FreeBSD_version >= 700104 | |
42 | #define HAVE_KINFO_GETVMMAP | |
43 | #define sigqueue sigqueue_freebsd /* avoid redefinition */ | |
44 | #include <sys/time.h> | |
45 | #include <sys/proc.h> | |
46 | #include <machine/profile.h> | |
47 | #define _KERNEL | |
48 | #include <sys/user.h> | |
49 | #undef _KERNEL | |
50 | #undef sigqueue | |
51 | #include <libutil.h> | |
52 | #endif | |
53 | #endif | |
54 | #endif | |
55 | ||
56 | //#define DEBUG_TB_INVALIDATE | |
57 | //#define DEBUG_FLUSH | |
58 | //#define DEBUG_TLB | |
59 | //#define DEBUG_UNASSIGNED | |
60 | ||
61 | /* make various TB consistency checks */ | |
62 | //#define DEBUG_TB_CHECK | |
63 | //#define DEBUG_TLB_CHECK | |
64 | ||
65 | //#define DEBUG_IOPORT | |
66 | //#define DEBUG_SUBPAGE | |
67 | ||
68 | #if !defined(CONFIG_USER_ONLY) | |
69 | /* TB consistency checks only implemented for usermode emulation. */ | |
70 | #undef DEBUG_TB_CHECK | |
71 | #endif | |
72 | ||
73 | #define SMC_BITMAP_USE_THRESHOLD 10 | |
74 | ||
75 | static TranslationBlock *tbs; | |
76 | static int code_gen_max_blocks; | |
77 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; | |
78 | static int nb_tbs; | |
79 | /* any access to the tbs or the page table must use this lock */ | |
80 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; | |
81 | ||
82 | #if defined(__arm__) || defined(__sparc_v9__) | |
83 | /* The prologue must be reachable with a direct jump. ARM and Sparc64 | |
84 | have limited branch ranges (possibly also PPC) so place it in a | |
85 | section close to code segment. */ | |
86 | #define code_gen_section \ | |
87 | __attribute__((__section__(".gen_code"))) \ | |
88 | __attribute__((aligned (32))) | |
89 | #elif defined(_WIN32) | |
90 | /* Maximum alignment for Win32 is 16. */ | |
91 | #define code_gen_section \ | |
92 | __attribute__((aligned (16))) | |
93 | #else | |
94 | #define code_gen_section \ | |
95 | __attribute__((aligned (32))) | |
96 | #endif | |
97 | ||
98 | uint8_t code_gen_prologue[1024] code_gen_section; | |
99 | static uint8_t *code_gen_buffer; | |
100 | static unsigned long code_gen_buffer_size; | |
101 | /* threshold to flush the translated code buffer */ | |
102 | static unsigned long code_gen_buffer_max_size; | |
103 | static uint8_t *code_gen_ptr; | |
104 | ||
105 | #if !defined(CONFIG_USER_ONLY) | |
106 | int phys_ram_fd; | |
107 | static int in_migration; | |
108 | ||
109 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list) }; | |
110 | #endif | |
111 | ||
112 | CPUState *first_cpu; | |
113 | /* current CPU in the current thread. It is only valid inside | |
114 | cpu_exec() */ | |
115 | CPUState *cpu_single_env; | |
116 | /* 0 = Do not count executed instructions. | |
117 | 1 = Precise instruction counting. | |
118 | 2 = Adaptive rate instruction counting. */ | |
119 | int use_icount = 0; | |
120 | /* Current instruction counter. While executing translated code this may | |
121 | include some instructions that have not yet been executed. */ | |
122 | int64_t qemu_icount; | |
123 | ||
124 | typedef struct PageDesc { | |
125 | /* list of TBs intersecting this ram page */ | |
126 | TranslationBlock *first_tb; | |
127 | /* in order to optimize self modifying code, we count the number | |
128 | of lookups we do to a given page to use a bitmap */ | |
129 | unsigned int code_write_count; | |
130 | uint8_t *code_bitmap; | |
131 | #if defined(CONFIG_USER_ONLY) | |
132 | unsigned long flags; | |
133 | #endif | |
134 | } PageDesc; | |
135 | ||
136 | /* In system mode we want L1_MAP to be based on ram offsets, | |
137 | while in user mode we want it to be based on virtual addresses. */ | |
138 | #if !defined(CONFIG_USER_ONLY) | |
139 | #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS | |
140 | # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS | |
141 | #else | |
142 | # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS | |
143 | #endif | |
144 | #else | |
145 | # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS | |
146 | #endif | |
147 | ||
148 | /* Size of the L2 (and L3, etc) page tables. */ | |
149 | #define L2_BITS 10 | |
150 | #define L2_SIZE (1 << L2_BITS) | |
151 | ||
152 | /* The bits remaining after N lower levels of page tables. */ | |
153 | #define P_L1_BITS_REM \ | |
154 | ((TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) | |
155 | #define V_L1_BITS_REM \ | |
156 | ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) | |
157 | ||
158 | /* Size of the L1 page table. Avoid silly small sizes. */ | |
159 | #if P_L1_BITS_REM < 4 | |
160 | #define P_L1_BITS (P_L1_BITS_REM + L2_BITS) | |
161 | #else | |
162 | #define P_L1_BITS P_L1_BITS_REM | |
163 | #endif | |
164 | ||
165 | #if V_L1_BITS_REM < 4 | |
166 | #define V_L1_BITS (V_L1_BITS_REM + L2_BITS) | |
167 | #else | |
168 | #define V_L1_BITS V_L1_BITS_REM | |
169 | #endif | |
170 | ||
171 | #define P_L1_SIZE ((target_phys_addr_t)1 << P_L1_BITS) | |
172 | #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS) | |
173 | ||
174 | #define P_L1_SHIFT (TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS - P_L1_BITS) | |
175 | #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS) | |
176 | ||
177 | unsigned long qemu_real_host_page_size; | |
178 | unsigned long qemu_host_page_bits; | |
179 | unsigned long qemu_host_page_size; | |
180 | unsigned long qemu_host_page_mask; | |
181 | ||
182 | /* This is a multi-level map on the virtual address space. | |
183 | The bottom level has pointers to PageDesc. */ | |
184 | static void *l1_map[V_L1_SIZE]; | |
185 | ||
186 | #if !defined(CONFIG_USER_ONLY) | |
187 | typedef struct PhysPageDesc { | |
188 | /* offset in host memory of the page + io_index in the low bits */ | |
189 | ram_addr_t phys_offset; | |
190 | ram_addr_t region_offset; | |
191 | } PhysPageDesc; | |
192 | ||
193 | /* This is a multi-level map on the physical address space. | |
194 | The bottom level has pointers to PhysPageDesc. */ | |
195 | static void *l1_phys_map[P_L1_SIZE]; | |
196 | ||
197 | static void io_mem_init(void); | |
198 | ||
199 | /* io memory support */ | |
200 | CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; | |
201 | CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; | |
202 | void *io_mem_opaque[IO_MEM_NB_ENTRIES]; | |
203 | static char io_mem_used[IO_MEM_NB_ENTRIES]; | |
204 | static int io_mem_watch; | |
205 | #endif | |
206 | ||
207 | /* log support */ | |
208 | #ifdef WIN32 | |
209 | static const char *logfilename = "qemu.log"; | |
210 | #else | |
211 | static const char *logfilename = "/tmp/qemu.log"; | |
212 | #endif | |
213 | FILE *logfile; | |
214 | int loglevel; | |
215 | static int log_append = 0; | |
216 | ||
217 | /* statistics */ | |
218 | #if !defined(CONFIG_USER_ONLY) | |
219 | static int tlb_flush_count; | |
220 | #endif | |
221 | static int tb_flush_count; | |
222 | static int tb_phys_invalidate_count; | |
223 | ||
224 | #ifdef _WIN32 | |
225 | static void map_exec(void *addr, long size) | |
226 | { | |
227 | DWORD old_protect; | |
228 | VirtualProtect(addr, size, | |
229 | PAGE_EXECUTE_READWRITE, &old_protect); | |
230 | ||
231 | } | |
232 | #else | |
233 | static void map_exec(void *addr, long size) | |
234 | { | |
235 | unsigned long start, end, page_size; | |
236 | ||
237 | page_size = getpagesize(); | |
238 | start = (unsigned long)addr; | |
239 | start &= ~(page_size - 1); | |
240 | ||
241 | end = (unsigned long)addr + size; | |
242 | end += page_size - 1; | |
243 | end &= ~(page_size - 1); | |
244 | ||
245 | mprotect((void *)start, end - start, | |
246 | PROT_READ | PROT_WRITE | PROT_EXEC); | |
247 | } | |
248 | #endif | |
249 | ||
250 | static void page_init(void) | |
251 | { | |
252 | /* NOTE: we can always suppose that qemu_host_page_size >= | |
253 | TARGET_PAGE_SIZE */ | |
254 | #ifdef _WIN32 | |
255 | { | |
256 | SYSTEM_INFO system_info; | |
257 | ||
258 | GetSystemInfo(&system_info); | |
259 | qemu_real_host_page_size = system_info.dwPageSize; | |
260 | } | |
261 | #else | |
262 | qemu_real_host_page_size = getpagesize(); | |
263 | #endif | |
264 | if (qemu_host_page_size == 0) | |
265 | qemu_host_page_size = qemu_real_host_page_size; | |
266 | if (qemu_host_page_size < TARGET_PAGE_SIZE) | |
267 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
268 | qemu_host_page_bits = 0; | |
269 | while ((1 << qemu_host_page_bits) < qemu_host_page_size) | |
270 | qemu_host_page_bits++; | |
271 | qemu_host_page_mask = ~(qemu_host_page_size - 1); | |
272 | ||
273 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) | |
274 | { | |
275 | #ifdef HAVE_KINFO_GETVMMAP | |
276 | struct kinfo_vmentry *freep; | |
277 | int i, cnt; | |
278 | ||
279 | freep = kinfo_getvmmap(getpid(), &cnt); | |
280 | if (freep) { | |
281 | mmap_lock(); | |
282 | for (i = 0; i < cnt; i++) { | |
283 | unsigned long startaddr, endaddr; | |
284 | ||
285 | startaddr = freep[i].kve_start; | |
286 | endaddr = freep[i].kve_end; | |
287 | if (h2g_valid(startaddr)) { | |
288 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
289 | ||
290 | if (h2g_valid(endaddr)) { | |
291 | endaddr = h2g(endaddr); | |
292 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
293 | } else { | |
294 | #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS | |
295 | endaddr = ~0ul; | |
296 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
297 | #endif | |
298 | } | |
299 | } | |
300 | } | |
301 | free(freep); | |
302 | mmap_unlock(); | |
303 | } | |
304 | #else | |
305 | FILE *f; | |
306 | ||
307 | last_brk = (unsigned long)sbrk(0); | |
308 | ||
309 | f = fopen("/compat/linux/proc/self/maps", "r"); | |
310 | if (f) { | |
311 | mmap_lock(); | |
312 | ||
313 | do { | |
314 | unsigned long startaddr, endaddr; | |
315 | int n; | |
316 | ||
317 | n = fscanf (f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr); | |
318 | ||
319 | if (n == 2 && h2g_valid(startaddr)) { | |
320 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
321 | ||
322 | if (h2g_valid(endaddr)) { | |
323 | endaddr = h2g(endaddr); | |
324 | } else { | |
325 | endaddr = ~0ul; | |
326 | } | |
327 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
328 | } | |
329 | } while (!feof(f)); | |
330 | ||
331 | fclose(f); | |
332 | mmap_unlock(); | |
333 | } | |
334 | #endif | |
335 | } | |
336 | #endif | |
337 | } | |
338 | ||
339 | static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) | |
340 | { | |
341 | PageDesc *pd; | |
342 | void **lp; | |
343 | int i; | |
344 | ||
345 | #if defined(CONFIG_USER_ONLY) | |
346 | /* We can't use qemu_malloc because it may recurse into a locked mutex. */ | |
347 | # define ALLOC(P, SIZE) \ | |
348 | do { \ | |
349 | P = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, \ | |
350 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); \ | |
351 | } while (0) | |
352 | #else | |
353 | # define ALLOC(P, SIZE) \ | |
354 | do { P = qemu_mallocz(SIZE); } while (0) | |
355 | #endif | |
356 | ||
357 | /* Level 1. Always allocated. */ | |
358 | lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1)); | |
359 | ||
360 | /* Level 2..N-1. */ | |
361 | for (i = V_L1_SHIFT / L2_BITS - 1; i > 0; i--) { | |
362 | void **p = *lp; | |
363 | ||
364 | if (p == NULL) { | |
365 | if (!alloc) { | |
366 | return NULL; | |
367 | } | |
368 | ALLOC(p, sizeof(void *) * L2_SIZE); | |
369 | *lp = p; | |
370 | } | |
371 | ||
372 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); | |
373 | } | |
374 | ||
375 | pd = *lp; | |
376 | if (pd == NULL) { | |
377 | if (!alloc) { | |
378 | return NULL; | |
379 | } | |
380 | ALLOC(pd, sizeof(PageDesc) * L2_SIZE); | |
381 | *lp = pd; | |
382 | } | |
383 | ||
384 | #undef ALLOC | |
385 | ||
386 | return pd + (index & (L2_SIZE - 1)); | |
387 | } | |
388 | ||
389 | static inline PageDesc *page_find(tb_page_addr_t index) | |
390 | { | |
391 | return page_find_alloc(index, 0); | |
392 | } | |
393 | ||
394 | #if !defined(CONFIG_USER_ONLY) | |
395 | static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc) | |
396 | { | |
397 | PhysPageDesc *pd; | |
398 | void **lp; | |
399 | int i; | |
400 | ||
401 | /* Level 1. Always allocated. */ | |
402 | lp = l1_phys_map + ((index >> P_L1_SHIFT) & (P_L1_SIZE - 1)); | |
403 | ||
404 | /* Level 2..N-1. */ | |
405 | for (i = P_L1_SHIFT / L2_BITS - 1; i > 0; i--) { | |
406 | void **p = *lp; | |
407 | if (p == NULL) { | |
408 | if (!alloc) { | |
409 | return NULL; | |
410 | } | |
411 | *lp = p = qemu_mallocz(sizeof(void *) * L2_SIZE); | |
412 | } | |
413 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); | |
414 | } | |
415 | ||
416 | pd = *lp; | |
417 | if (pd == NULL) { | |
418 | int i; | |
419 | ||
420 | if (!alloc) { | |
421 | return NULL; | |
422 | } | |
423 | ||
424 | *lp = pd = qemu_malloc(sizeof(PhysPageDesc) * L2_SIZE); | |
425 | ||
426 | for (i = 0; i < L2_SIZE; i++) { | |
427 | pd[i].phys_offset = IO_MEM_UNASSIGNED; | |
428 | pd[i].region_offset = (index + i) << TARGET_PAGE_BITS; | |
429 | } | |
430 | } | |
431 | ||
432 | return pd + (index & (L2_SIZE - 1)); | |
433 | } | |
434 | ||
435 | static inline PhysPageDesc *phys_page_find(target_phys_addr_t index) | |
436 | { | |
437 | return phys_page_find_alloc(index, 0); | |
438 | } | |
439 | ||
440 | static void tlb_protect_code(ram_addr_t ram_addr); | |
441 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, | |
442 | target_ulong vaddr); | |
443 | #define mmap_lock() do { } while(0) | |
444 | #define mmap_unlock() do { } while(0) | |
445 | #endif | |
446 | ||
447 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024) | |
448 | ||
449 | #if defined(CONFIG_USER_ONLY) | |
450 | /* Currently it is not recommended to allocate big chunks of data in | |
451 | user mode. It will change when a dedicated libc will be used */ | |
452 | #define USE_STATIC_CODE_GEN_BUFFER | |
453 | #endif | |
454 | ||
455 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
456 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] | |
457 | __attribute__((aligned (CODE_GEN_ALIGN))); | |
458 | #endif | |
459 | ||
460 | static void code_gen_alloc(unsigned long tb_size) | |
461 | { | |
462 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
463 | code_gen_buffer = static_code_gen_buffer; | |
464 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
465 | map_exec(code_gen_buffer, code_gen_buffer_size); | |
466 | #else | |
467 | code_gen_buffer_size = tb_size; | |
468 | if (code_gen_buffer_size == 0) { | |
469 | #if defined(CONFIG_USER_ONLY) | |
470 | /* in user mode, phys_ram_size is not meaningful */ | |
471 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
472 | #else | |
473 | /* XXX: needs adjustments */ | |
474 | code_gen_buffer_size = (unsigned long)(ram_size / 4); | |
475 | #endif | |
476 | } | |
477 | if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE) | |
478 | code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE; | |
479 | /* The code gen buffer location may have constraints depending on | |
480 | the host cpu and OS */ | |
481 | #if defined(__linux__) | |
482 | { | |
483 | int flags; | |
484 | void *start = NULL; | |
485 | ||
486 | flags = MAP_PRIVATE | MAP_ANONYMOUS; | |
487 | #if defined(__x86_64__) | |
488 | flags |= MAP_32BIT; | |
489 | /* Cannot map more than that */ | |
490 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
491 | code_gen_buffer_size = (800 * 1024 * 1024); | |
492 | #elif defined(__sparc_v9__) | |
493 | // Map the buffer below 2G, so we can use direct calls and branches | |
494 | flags |= MAP_FIXED; | |
495 | start = (void *) 0x60000000UL; | |
496 | if (code_gen_buffer_size > (512 * 1024 * 1024)) | |
497 | code_gen_buffer_size = (512 * 1024 * 1024); | |
498 | #elif defined(__arm__) | |
499 | /* Map the buffer below 32M, so we can use direct calls and branches */ | |
500 | flags |= MAP_FIXED; | |
501 | start = (void *) 0x01000000UL; | |
502 | if (code_gen_buffer_size > 16 * 1024 * 1024) | |
503 | code_gen_buffer_size = 16 * 1024 * 1024; | |
504 | #elif defined(__s390x__) | |
505 | /* Map the buffer so that we can use direct calls and branches. */ | |
506 | /* We have a +- 4GB range on the branches; leave some slop. */ | |
507 | if (code_gen_buffer_size > (3ul * 1024 * 1024 * 1024)) { | |
508 | code_gen_buffer_size = 3ul * 1024 * 1024 * 1024; | |
509 | } | |
510 | start = (void *)0x90000000UL; | |
511 | #endif | |
512 | code_gen_buffer = mmap(start, code_gen_buffer_size, | |
513 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
514 | flags, -1, 0); | |
515 | if (code_gen_buffer == MAP_FAILED) { | |
516 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
517 | exit(1); | |
518 | } | |
519 | } | |
520 | #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \ | |
521 | || defined(__DragonFly__) || defined(__OpenBSD__) | |
522 | { | |
523 | int flags; | |
524 | void *addr = NULL; | |
525 | flags = MAP_PRIVATE | MAP_ANONYMOUS; | |
526 | #if defined(__x86_64__) | |
527 | /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume | |
528 | * 0x40000000 is free */ | |
529 | flags |= MAP_FIXED; | |
530 | addr = (void *)0x40000000; | |
531 | /* Cannot map more than that */ | |
532 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
533 | code_gen_buffer_size = (800 * 1024 * 1024); | |
534 | #elif defined(__sparc_v9__) | |
535 | // Map the buffer below 2G, so we can use direct calls and branches | |
536 | flags |= MAP_FIXED; | |
537 | addr = (void *) 0x60000000UL; | |
538 | if (code_gen_buffer_size > (512 * 1024 * 1024)) { | |
539 | code_gen_buffer_size = (512 * 1024 * 1024); | |
540 | } | |
541 | #endif | |
542 | code_gen_buffer = mmap(addr, code_gen_buffer_size, | |
543 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
544 | flags, -1, 0); | |
545 | if (code_gen_buffer == MAP_FAILED) { | |
546 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
547 | exit(1); | |
548 | } | |
549 | } | |
550 | #else | |
551 | code_gen_buffer = qemu_malloc(code_gen_buffer_size); | |
552 | map_exec(code_gen_buffer, code_gen_buffer_size); | |
553 | #endif | |
554 | #endif /* !USE_STATIC_CODE_GEN_BUFFER */ | |
555 | map_exec(code_gen_prologue, sizeof(code_gen_prologue)); | |
556 | code_gen_buffer_max_size = code_gen_buffer_size - | |
557 | (TCG_MAX_OP_SIZE * OPC_MAX_SIZE); | |
558 | code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE; | |
559 | tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock)); | |
560 | } | |
561 | ||
562 | /* Must be called before using the QEMU cpus. 'tb_size' is the size | |
563 | (in bytes) allocated to the translation buffer. Zero means default | |
564 | size. */ | |
565 | void cpu_exec_init_all(unsigned long tb_size) | |
566 | { | |
567 | cpu_gen_init(); | |
568 | code_gen_alloc(tb_size); | |
569 | code_gen_ptr = code_gen_buffer; | |
570 | page_init(); | |
571 | #if !defined(CONFIG_USER_ONLY) | |
572 | io_mem_init(); | |
573 | #endif | |
574 | #if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE) | |
575 | /* There's no guest base to take into account, so go ahead and | |
576 | initialize the prologue now. */ | |
577 | tcg_prologue_init(&tcg_ctx); | |
578 | #endif | |
579 | } | |
580 | ||
581 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) | |
582 | ||
583 | static int cpu_common_post_load(void *opaque, int version_id) | |
584 | { | |
585 | CPUState *env = opaque; | |
586 | ||
587 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the | |
588 | version_id is increased. */ | |
589 | env->interrupt_request &= ~0x01; | |
590 | tlb_flush(env, 1); | |
591 | ||
592 | return 0; | |
593 | } | |
594 | ||
595 | static const VMStateDescription vmstate_cpu_common = { | |
596 | .name = "cpu_common", | |
597 | .version_id = 1, | |
598 | .minimum_version_id = 1, | |
599 | .minimum_version_id_old = 1, | |
600 | .post_load = cpu_common_post_load, | |
601 | .fields = (VMStateField []) { | |
602 | VMSTATE_UINT32(halted, CPUState), | |
603 | VMSTATE_UINT32(interrupt_request, CPUState), | |
604 | VMSTATE_END_OF_LIST() | |
605 | } | |
606 | }; | |
607 | #endif | |
608 | ||
609 | CPUState *qemu_get_cpu(int cpu) | |
610 | { | |
611 | CPUState *env = first_cpu; | |
612 | ||
613 | while (env) { | |
614 | if (env->cpu_index == cpu) | |
615 | break; | |
616 | env = env->next_cpu; | |
617 | } | |
618 | ||
619 | return env; | |
620 | } | |
621 | ||
622 | void cpu_exec_init(CPUState *env) | |
623 | { | |
624 | CPUState **penv; | |
625 | int cpu_index; | |
626 | ||
627 | #if defined(CONFIG_USER_ONLY) | |
628 | cpu_list_lock(); | |
629 | #endif | |
630 | env->next_cpu = NULL; | |
631 | penv = &first_cpu; | |
632 | cpu_index = 0; | |
633 | while (*penv != NULL) { | |
634 | penv = &(*penv)->next_cpu; | |
635 | cpu_index++; | |
636 | } | |
637 | env->cpu_index = cpu_index; | |
638 | env->numa_node = 0; | |
639 | QTAILQ_INIT(&env->breakpoints); | |
640 | QTAILQ_INIT(&env->watchpoints); | |
641 | #ifndef CONFIG_USER_ONLY | |
642 | env->thread_id = qemu_get_thread_id(); | |
643 | #endif | |
644 | *penv = env; | |
645 | #if defined(CONFIG_USER_ONLY) | |
646 | cpu_list_unlock(); | |
647 | #endif | |
648 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) | |
649 | vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env); | |
650 | register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION, | |
651 | cpu_save, cpu_load, env); | |
652 | #endif | |
653 | } | |
654 | ||
655 | /* Allocate a new translation block. Flush the translation buffer if | |
656 | too many translation blocks or too much generated code. */ | |
657 | static TranslationBlock *tb_alloc(target_ulong pc) | |
658 | { | |
659 | TranslationBlock *tb; | |
660 | ||
661 | if (nb_tbs >= code_gen_max_blocks || | |
662 | (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size) | |
663 | return NULL; | |
664 | tb = &tbs[nb_tbs++]; | |
665 | tb->pc = pc; | |
666 | tb->cflags = 0; | |
667 | return tb; | |
668 | } | |
669 | ||
670 | void tb_free(TranslationBlock *tb) | |
671 | { | |
672 | /* In practice this is mostly used for single use temporary TB | |
673 | Ignore the hard cases and just back up if this TB happens to | |
674 | be the last one generated. */ | |
675 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) { | |
676 | code_gen_ptr = tb->tc_ptr; | |
677 | nb_tbs--; | |
678 | } | |
679 | } | |
680 | ||
681 | static inline void invalidate_page_bitmap(PageDesc *p) | |
682 | { | |
683 | if (p->code_bitmap) { | |
684 | qemu_free(p->code_bitmap); | |
685 | p->code_bitmap = NULL; | |
686 | } | |
687 | p->code_write_count = 0; | |
688 | } | |
689 | ||
690 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */ | |
691 | ||
692 | static void page_flush_tb_1 (int level, void **lp) | |
693 | { | |
694 | int i; | |
695 | ||
696 | if (*lp == NULL) { | |
697 | return; | |
698 | } | |
699 | if (level == 0) { | |
700 | PageDesc *pd = *lp; | |
701 | for (i = 0; i < L2_SIZE; ++i) { | |
702 | pd[i].first_tb = NULL; | |
703 | invalidate_page_bitmap(pd + i); | |
704 | } | |
705 | } else { | |
706 | void **pp = *lp; | |
707 | for (i = 0; i < L2_SIZE; ++i) { | |
708 | page_flush_tb_1 (level - 1, pp + i); | |
709 | } | |
710 | } | |
711 | } | |
712 | ||
713 | static void page_flush_tb(void) | |
714 | { | |
715 | int i; | |
716 | for (i = 0; i < V_L1_SIZE; i++) { | |
717 | page_flush_tb_1(V_L1_SHIFT / L2_BITS - 1, l1_map + i); | |
718 | } | |
719 | } | |
720 | ||
721 | /* flush all the translation blocks */ | |
722 | /* XXX: tb_flush is currently not thread safe */ | |
723 | void tb_flush(CPUState *env1) | |
724 | { | |
725 | CPUState *env; | |
726 | #if defined(DEBUG_FLUSH) | |
727 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", | |
728 | (unsigned long)(code_gen_ptr - code_gen_buffer), | |
729 | nb_tbs, nb_tbs > 0 ? | |
730 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0); | |
731 | #endif | |
732 | if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size) | |
733 | cpu_abort(env1, "Internal error: code buffer overflow\n"); | |
734 | ||
735 | nb_tbs = 0; | |
736 | ||
737 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
738 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); | |
739 | } | |
740 | ||
741 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *)); | |
742 | page_flush_tb(); | |
743 | ||
744 | code_gen_ptr = code_gen_buffer; | |
745 | /* XXX: flush processor icache at this point if cache flush is | |
746 | expensive */ | |
747 | tb_flush_count++; | |
748 | } | |
749 | ||
750 | #ifdef DEBUG_TB_CHECK | |
751 | ||
752 | static void tb_invalidate_check(target_ulong address) | |
753 | { | |
754 | TranslationBlock *tb; | |
755 | int i; | |
756 | address &= TARGET_PAGE_MASK; | |
757 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { | |
758 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
759 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || | |
760 | address >= tb->pc + tb->size)) { | |
761 | printf("ERROR invalidate: address=" TARGET_FMT_lx | |
762 | " PC=%08lx size=%04x\n", | |
763 | address, (long)tb->pc, tb->size); | |
764 | } | |
765 | } | |
766 | } | |
767 | } | |
768 | ||
769 | /* verify that all the pages have correct rights for code */ | |
770 | static void tb_page_check(void) | |
771 | { | |
772 | TranslationBlock *tb; | |
773 | int i, flags1, flags2; | |
774 | ||
775 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { | |
776 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
777 | flags1 = page_get_flags(tb->pc); | |
778 | flags2 = page_get_flags(tb->pc + tb->size - 1); | |
779 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | |
780 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | |
781 | (long)tb->pc, tb->size, flags1, flags2); | |
782 | } | |
783 | } | |
784 | } | |
785 | } | |
786 | ||
787 | #endif | |
788 | ||
789 | /* invalidate one TB */ | |
790 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb, | |
791 | int next_offset) | |
792 | { | |
793 | TranslationBlock *tb1; | |
794 | for(;;) { | |
795 | tb1 = *ptb; | |
796 | if (tb1 == tb) { | |
797 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset); | |
798 | break; | |
799 | } | |
800 | ptb = (TranslationBlock **)((char *)tb1 + next_offset); | |
801 | } | |
802 | } | |
803 | ||
804 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) | |
805 | { | |
806 | TranslationBlock *tb1; | |
807 | unsigned int n1; | |
808 | ||
809 | for(;;) { | |
810 | tb1 = *ptb; | |
811 | n1 = (long)tb1 & 3; | |
812 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
813 | if (tb1 == tb) { | |
814 | *ptb = tb1->page_next[n1]; | |
815 | break; | |
816 | } | |
817 | ptb = &tb1->page_next[n1]; | |
818 | } | |
819 | } | |
820 | ||
821 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) | |
822 | { | |
823 | TranslationBlock *tb1, **ptb; | |
824 | unsigned int n1; | |
825 | ||
826 | ptb = &tb->jmp_next[n]; | |
827 | tb1 = *ptb; | |
828 | if (tb1) { | |
829 | /* find tb(n) in circular list */ | |
830 | for(;;) { | |
831 | tb1 = *ptb; | |
832 | n1 = (long)tb1 & 3; | |
833 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
834 | if (n1 == n && tb1 == tb) | |
835 | break; | |
836 | if (n1 == 2) { | |
837 | ptb = &tb1->jmp_first; | |
838 | } else { | |
839 | ptb = &tb1->jmp_next[n1]; | |
840 | } | |
841 | } | |
842 | /* now we can suppress tb(n) from the list */ | |
843 | *ptb = tb->jmp_next[n]; | |
844 | ||
845 | tb->jmp_next[n] = NULL; | |
846 | } | |
847 | } | |
848 | ||
849 | /* reset the jump entry 'n' of a TB so that it is not chained to | |
850 | another TB */ | |
851 | static inline void tb_reset_jump(TranslationBlock *tb, int n) | |
852 | { | |
853 | tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n])); | |
854 | } | |
855 | ||
856 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) | |
857 | { | |
858 | CPUState *env; | |
859 | PageDesc *p; | |
860 | unsigned int h, n1; | |
861 | tb_page_addr_t phys_pc; | |
862 | TranslationBlock *tb1, *tb2; | |
863 | ||
864 | /* remove the TB from the hash list */ | |
865 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
866 | h = tb_phys_hash_func(phys_pc); | |
867 | tb_remove(&tb_phys_hash[h], tb, | |
868 | offsetof(TranslationBlock, phys_hash_next)); | |
869 | ||
870 | /* remove the TB from the page list */ | |
871 | if (tb->page_addr[0] != page_addr) { | |
872 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | |
873 | tb_page_remove(&p->first_tb, tb); | |
874 | invalidate_page_bitmap(p); | |
875 | } | |
876 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { | |
877 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | |
878 | tb_page_remove(&p->first_tb, tb); | |
879 | invalidate_page_bitmap(p); | |
880 | } | |
881 | ||
882 | tb_invalidated_flag = 1; | |
883 | ||
884 | /* remove the TB from the hash list */ | |
885 | h = tb_jmp_cache_hash_func(tb->pc); | |
886 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
887 | if (env->tb_jmp_cache[h] == tb) | |
888 | env->tb_jmp_cache[h] = NULL; | |
889 | } | |
890 | ||
891 | /* suppress this TB from the two jump lists */ | |
892 | tb_jmp_remove(tb, 0); | |
893 | tb_jmp_remove(tb, 1); | |
894 | ||
895 | /* suppress any remaining jumps to this TB */ | |
896 | tb1 = tb->jmp_first; | |
897 | for(;;) { | |
898 | n1 = (long)tb1 & 3; | |
899 | if (n1 == 2) | |
900 | break; | |
901 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
902 | tb2 = tb1->jmp_next[n1]; | |
903 | tb_reset_jump(tb1, n1); | |
904 | tb1->jmp_next[n1] = NULL; | |
905 | tb1 = tb2; | |
906 | } | |
907 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */ | |
908 | ||
909 | tb_phys_invalidate_count++; | |
910 | } | |
911 | ||
912 | static inline void set_bits(uint8_t *tab, int start, int len) | |
913 | { | |
914 | int end, mask, end1; | |
915 | ||
916 | end = start + len; | |
917 | tab += start >> 3; | |
918 | mask = 0xff << (start & 7); | |
919 | if ((start & ~7) == (end & ~7)) { | |
920 | if (start < end) { | |
921 | mask &= ~(0xff << (end & 7)); | |
922 | *tab |= mask; | |
923 | } | |
924 | } else { | |
925 | *tab++ |= mask; | |
926 | start = (start + 8) & ~7; | |
927 | end1 = end & ~7; | |
928 | while (start < end1) { | |
929 | *tab++ = 0xff; | |
930 | start += 8; | |
931 | } | |
932 | if (start < end) { | |
933 | mask = ~(0xff << (end & 7)); | |
934 | *tab |= mask; | |
935 | } | |
936 | } | |
937 | } | |
938 | ||
939 | static void build_page_bitmap(PageDesc *p) | |
940 | { | |
941 | int n, tb_start, tb_end; | |
942 | TranslationBlock *tb; | |
943 | ||
944 | p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8); | |
945 | ||
946 | tb = p->first_tb; | |
947 | while (tb != NULL) { | |
948 | n = (long)tb & 3; | |
949 | tb = (TranslationBlock *)((long)tb & ~3); | |
950 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
951 | if (n == 0) { | |
952 | /* NOTE: tb_end may be after the end of the page, but | |
953 | it is not a problem */ | |
954 | tb_start = tb->pc & ~TARGET_PAGE_MASK; | |
955 | tb_end = tb_start + tb->size; | |
956 | if (tb_end > TARGET_PAGE_SIZE) | |
957 | tb_end = TARGET_PAGE_SIZE; | |
958 | } else { | |
959 | tb_start = 0; | |
960 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
961 | } | |
962 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); | |
963 | tb = tb->page_next[n]; | |
964 | } | |
965 | } | |
966 | ||
967 | TranslationBlock *tb_gen_code(CPUState *env, | |
968 | target_ulong pc, target_ulong cs_base, | |
969 | int flags, int cflags) | |
970 | { | |
971 | TranslationBlock *tb; | |
972 | uint8_t *tc_ptr; | |
973 | tb_page_addr_t phys_pc, phys_page2; | |
974 | target_ulong virt_page2; | |
975 | int code_gen_size; | |
976 | ||
977 | phys_pc = get_page_addr_code(env, pc); | |
978 | tb = tb_alloc(pc); | |
979 | if (!tb) { | |
980 | /* flush must be done */ | |
981 | tb_flush(env); | |
982 | /* cannot fail at this point */ | |
983 | tb = tb_alloc(pc); | |
984 | /* Don't forget to invalidate previous TB info. */ | |
985 | tb_invalidated_flag = 1; | |
986 | } | |
987 | tc_ptr = code_gen_ptr; | |
988 | tb->tc_ptr = tc_ptr; | |
989 | tb->cs_base = cs_base; | |
990 | tb->flags = flags; | |
991 | tb->cflags = cflags; | |
992 | cpu_gen_code(env, tb, &code_gen_size); | |
993 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); | |
994 | ||
995 | /* check next page if needed */ | |
996 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; | |
997 | phys_page2 = -1; | |
998 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { | |
999 | phys_page2 = get_page_addr_code(env, virt_page2); | |
1000 | } | |
1001 | tb_link_page(tb, phys_pc, phys_page2); | |
1002 | return tb; | |
1003 | } | |
1004 | ||
1005 | /* invalidate all TBs which intersect with the target physical page | |
1006 | starting in range [start;end[. NOTE: start and end must refer to | |
1007 | the same physical page. 'is_cpu_write_access' should be true if called | |
1008 | from a real cpu write access: the virtual CPU will exit the current | |
1009 | TB if code is modified inside this TB. */ | |
1010 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, | |
1011 | int is_cpu_write_access) | |
1012 | { | |
1013 | TranslationBlock *tb, *tb_next, *saved_tb; | |
1014 | CPUState *env = cpu_single_env; | |
1015 | tb_page_addr_t tb_start, tb_end; | |
1016 | PageDesc *p; | |
1017 | int n; | |
1018 | #ifdef TARGET_HAS_PRECISE_SMC | |
1019 | int current_tb_not_found = is_cpu_write_access; | |
1020 | TranslationBlock *current_tb = NULL; | |
1021 | int current_tb_modified = 0; | |
1022 | target_ulong current_pc = 0; | |
1023 | target_ulong current_cs_base = 0; | |
1024 | int current_flags = 0; | |
1025 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
1026 | ||
1027 | p = page_find(start >> TARGET_PAGE_BITS); | |
1028 | if (!p) | |
1029 | return; | |
1030 | if (!p->code_bitmap && | |
1031 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && | |
1032 | is_cpu_write_access) { | |
1033 | /* build code bitmap */ | |
1034 | build_page_bitmap(p); | |
1035 | } | |
1036 | ||
1037 | /* we remove all the TBs in the range [start, end[ */ | |
1038 | /* XXX: see if in some cases it could be faster to invalidate all the code */ | |
1039 | tb = p->first_tb; | |
1040 | while (tb != NULL) { | |
1041 | n = (long)tb & 3; | |
1042 | tb = (TranslationBlock *)((long)tb & ~3); | |
1043 | tb_next = tb->page_next[n]; | |
1044 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
1045 | if (n == 0) { | |
1046 | /* NOTE: tb_end may be after the end of the page, but | |
1047 | it is not a problem */ | |
1048 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
1049 | tb_end = tb_start + tb->size; | |
1050 | } else { | |
1051 | tb_start = tb->page_addr[1]; | |
1052 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
1053 | } | |
1054 | if (!(tb_end <= start || tb_start >= end)) { | |
1055 | #ifdef TARGET_HAS_PRECISE_SMC | |
1056 | if (current_tb_not_found) { | |
1057 | current_tb_not_found = 0; | |
1058 | current_tb = NULL; | |
1059 | if (env->mem_io_pc) { | |
1060 | /* now we have a real cpu fault */ | |
1061 | current_tb = tb_find_pc(env->mem_io_pc); | |
1062 | } | |
1063 | } | |
1064 | if (current_tb == tb && | |
1065 | (current_tb->cflags & CF_COUNT_MASK) != 1) { | |
1066 | /* If we are modifying the current TB, we must stop | |
1067 | its execution. We could be more precise by checking | |
1068 | that the modification is after the current PC, but it | |
1069 | would require a specialized function to partially | |
1070 | restore the CPU state */ | |
1071 | ||
1072 | current_tb_modified = 1; | |
1073 | cpu_restore_state(current_tb, env, env->mem_io_pc); | |
1074 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, | |
1075 | ¤t_flags); | |
1076 | } | |
1077 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
1078 | /* we need to do that to handle the case where a signal | |
1079 | occurs while doing tb_phys_invalidate() */ | |
1080 | saved_tb = NULL; | |
1081 | if (env) { | |
1082 | saved_tb = env->current_tb; | |
1083 | env->current_tb = NULL; | |
1084 | } | |
1085 | tb_phys_invalidate(tb, -1); | |
1086 | if (env) { | |
1087 | env->current_tb = saved_tb; | |
1088 | if (env->interrupt_request && env->current_tb) | |
1089 | cpu_interrupt(env, env->interrupt_request); | |
1090 | } | |
1091 | } | |
1092 | tb = tb_next; | |
1093 | } | |
1094 | #if !defined(CONFIG_USER_ONLY) | |
1095 | /* if no code remaining, no need to continue to use slow writes */ | |
1096 | if (!p->first_tb) { | |
1097 | invalidate_page_bitmap(p); | |
1098 | if (is_cpu_write_access) { | |
1099 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); | |
1100 | } | |
1101 | } | |
1102 | #endif | |
1103 | #ifdef TARGET_HAS_PRECISE_SMC | |
1104 | if (current_tb_modified) { | |
1105 | /* we generate a block containing just the instruction | |
1106 | modifying the memory. It will ensure that it cannot modify | |
1107 | itself */ | |
1108 | env->current_tb = NULL; | |
1109 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); | |
1110 | cpu_resume_from_signal(env, NULL); | |
1111 | } | |
1112 | #endif | |
1113 | } | |
1114 | ||
1115 | /* len must be <= 8 and start must be a multiple of len */ | |
1116 | static inline void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len) | |
1117 | { | |
1118 | PageDesc *p; | |
1119 | int offset, b; | |
1120 | #if 0 | |
1121 | if (1) { | |
1122 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", | |
1123 | cpu_single_env->mem_io_vaddr, len, | |
1124 | cpu_single_env->eip, | |
1125 | cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base); | |
1126 | } | |
1127 | #endif | |
1128 | p = page_find(start >> TARGET_PAGE_BITS); | |
1129 | if (!p) | |
1130 | return; | |
1131 | if (p->code_bitmap) { | |
1132 | offset = start & ~TARGET_PAGE_MASK; | |
1133 | b = p->code_bitmap[offset >> 3] >> (offset & 7); | |
1134 | if (b & ((1 << len) - 1)) | |
1135 | goto do_invalidate; | |
1136 | } else { | |
1137 | do_invalidate: | |
1138 | tb_invalidate_phys_page_range(start, start + len, 1); | |
1139 | } | |
1140 | } | |
1141 | ||
1142 | #if !defined(CONFIG_SOFTMMU) | |
1143 | static void tb_invalidate_phys_page(tb_page_addr_t addr, | |
1144 | unsigned long pc, void *puc) | |
1145 | { | |
1146 | TranslationBlock *tb; | |
1147 | PageDesc *p; | |
1148 | int n; | |
1149 | #ifdef TARGET_HAS_PRECISE_SMC | |
1150 | TranslationBlock *current_tb = NULL; | |
1151 | CPUState *env = cpu_single_env; | |
1152 | int current_tb_modified = 0; | |
1153 | target_ulong current_pc = 0; | |
1154 | target_ulong current_cs_base = 0; | |
1155 | int current_flags = 0; | |
1156 | #endif | |
1157 | ||
1158 | addr &= TARGET_PAGE_MASK; | |
1159 | p = page_find(addr >> TARGET_PAGE_BITS); | |
1160 | if (!p) | |
1161 | return; | |
1162 | tb = p->first_tb; | |
1163 | #ifdef TARGET_HAS_PRECISE_SMC | |
1164 | if (tb && pc != 0) { | |
1165 | current_tb = tb_find_pc(pc); | |
1166 | } | |
1167 | #endif | |
1168 | while (tb != NULL) { | |
1169 | n = (long)tb & 3; | |
1170 | tb = (TranslationBlock *)((long)tb & ~3); | |
1171 | #ifdef TARGET_HAS_PRECISE_SMC | |
1172 | if (current_tb == tb && | |
1173 | (current_tb->cflags & CF_COUNT_MASK) != 1) { | |
1174 | /* If we are modifying the current TB, we must stop | |
1175 | its execution. We could be more precise by checking | |
1176 | that the modification is after the current PC, but it | |
1177 | would require a specialized function to partially | |
1178 | restore the CPU state */ | |
1179 | ||
1180 | current_tb_modified = 1; | |
1181 | cpu_restore_state(current_tb, env, pc); | |
1182 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, | |
1183 | ¤t_flags); | |
1184 | } | |
1185 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
1186 | tb_phys_invalidate(tb, addr); | |
1187 | tb = tb->page_next[n]; | |
1188 | } | |
1189 | p->first_tb = NULL; | |
1190 | #ifdef TARGET_HAS_PRECISE_SMC | |
1191 | if (current_tb_modified) { | |
1192 | /* we generate a block containing just the instruction | |
1193 | modifying the memory. It will ensure that it cannot modify | |
1194 | itself */ | |
1195 | env->current_tb = NULL; | |
1196 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); | |
1197 | cpu_resume_from_signal(env, puc); | |
1198 | } | |
1199 | #endif | |
1200 | } | |
1201 | #endif | |
1202 | ||
1203 | /* add the tb in the target page and protect it if necessary */ | |
1204 | static inline void tb_alloc_page(TranslationBlock *tb, | |
1205 | unsigned int n, tb_page_addr_t page_addr) | |
1206 | { | |
1207 | PageDesc *p; | |
1208 | TranslationBlock *last_first_tb; | |
1209 | ||
1210 | tb->page_addr[n] = page_addr; | |
1211 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1); | |
1212 | tb->page_next[n] = p->first_tb; | |
1213 | last_first_tb = p->first_tb; | |
1214 | p->first_tb = (TranslationBlock *)((long)tb | n); | |
1215 | invalidate_page_bitmap(p); | |
1216 | ||
1217 | #if defined(TARGET_HAS_SMC) || 1 | |
1218 | ||
1219 | #if defined(CONFIG_USER_ONLY) | |
1220 | if (p->flags & PAGE_WRITE) { | |
1221 | target_ulong addr; | |
1222 | PageDesc *p2; | |
1223 | int prot; | |
1224 | ||
1225 | /* force the host page as non writable (writes will have a | |
1226 | page fault + mprotect overhead) */ | |
1227 | page_addr &= qemu_host_page_mask; | |
1228 | prot = 0; | |
1229 | for(addr = page_addr; addr < page_addr + qemu_host_page_size; | |
1230 | addr += TARGET_PAGE_SIZE) { | |
1231 | ||
1232 | p2 = page_find (addr >> TARGET_PAGE_BITS); | |
1233 | if (!p2) | |
1234 | continue; | |
1235 | prot |= p2->flags; | |
1236 | p2->flags &= ~PAGE_WRITE; | |
1237 | } | |
1238 | mprotect(g2h(page_addr), qemu_host_page_size, | |
1239 | (prot & PAGE_BITS) & ~PAGE_WRITE); | |
1240 | #ifdef DEBUG_TB_INVALIDATE | |
1241 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", | |
1242 | page_addr); | |
1243 | #endif | |
1244 | } | |
1245 | #else | |
1246 | /* if some code is already present, then the pages are already | |
1247 | protected. So we handle the case where only the first TB is | |
1248 | allocated in a physical page */ | |
1249 | if (!last_first_tb) { | |
1250 | tlb_protect_code(page_addr); | |
1251 | } | |
1252 | #endif | |
1253 | ||
1254 | #endif /* TARGET_HAS_SMC */ | |
1255 | } | |
1256 | ||
1257 | /* add a new TB and link it to the physical page tables. phys_page2 is | |
1258 | (-1) to indicate that only one page contains the TB. */ | |
1259 | void tb_link_page(TranslationBlock *tb, | |
1260 | tb_page_addr_t phys_pc, tb_page_addr_t phys_page2) | |
1261 | { | |
1262 | unsigned int h; | |
1263 | TranslationBlock **ptb; | |
1264 | ||
1265 | /* Grab the mmap lock to stop another thread invalidating this TB | |
1266 | before we are done. */ | |
1267 | mmap_lock(); | |
1268 | /* add in the physical hash table */ | |
1269 | h = tb_phys_hash_func(phys_pc); | |
1270 | ptb = &tb_phys_hash[h]; | |
1271 | tb->phys_hash_next = *ptb; | |
1272 | *ptb = tb; | |
1273 | ||
1274 | /* add in the page list */ | |
1275 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); | |
1276 | if (phys_page2 != -1) | |
1277 | tb_alloc_page(tb, 1, phys_page2); | |
1278 | else | |
1279 | tb->page_addr[1] = -1; | |
1280 | ||
1281 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); | |
1282 | tb->jmp_next[0] = NULL; | |
1283 | tb->jmp_next[1] = NULL; | |
1284 | ||
1285 | /* init original jump addresses */ | |
1286 | if (tb->tb_next_offset[0] != 0xffff) | |
1287 | tb_reset_jump(tb, 0); | |
1288 | if (tb->tb_next_offset[1] != 0xffff) | |
1289 | tb_reset_jump(tb, 1); | |
1290 | ||
1291 | #ifdef DEBUG_TB_CHECK | |
1292 | tb_page_check(); | |
1293 | #endif | |
1294 | mmap_unlock(); | |
1295 | } | |
1296 | ||
1297 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < | |
1298 | tb[1].tc_ptr. Return NULL if not found */ | |
1299 | TranslationBlock *tb_find_pc(unsigned long tc_ptr) | |
1300 | { | |
1301 | int m_min, m_max, m; | |
1302 | unsigned long v; | |
1303 | TranslationBlock *tb; | |
1304 | ||
1305 | if (nb_tbs <= 0) | |
1306 | return NULL; | |
1307 | if (tc_ptr < (unsigned long)code_gen_buffer || | |
1308 | tc_ptr >= (unsigned long)code_gen_ptr) | |
1309 | return NULL; | |
1310 | /* binary search (cf Knuth) */ | |
1311 | m_min = 0; | |
1312 | m_max = nb_tbs - 1; | |
1313 | while (m_min <= m_max) { | |
1314 | m = (m_min + m_max) >> 1; | |
1315 | tb = &tbs[m]; | |
1316 | v = (unsigned long)tb->tc_ptr; | |
1317 | if (v == tc_ptr) | |
1318 | return tb; | |
1319 | else if (tc_ptr < v) { | |
1320 | m_max = m - 1; | |
1321 | } else { | |
1322 | m_min = m + 1; | |
1323 | } | |
1324 | } | |
1325 | return &tbs[m_max]; | |
1326 | } | |
1327 | ||
1328 | static void tb_reset_jump_recursive(TranslationBlock *tb); | |
1329 | ||
1330 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) | |
1331 | { | |
1332 | TranslationBlock *tb1, *tb_next, **ptb; | |
1333 | unsigned int n1; | |
1334 | ||
1335 | tb1 = tb->jmp_next[n]; | |
1336 | if (tb1 != NULL) { | |
1337 | /* find head of list */ | |
1338 | for(;;) { | |
1339 | n1 = (long)tb1 & 3; | |
1340 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1341 | if (n1 == 2) | |
1342 | break; | |
1343 | tb1 = tb1->jmp_next[n1]; | |
1344 | } | |
1345 | /* we are now sure now that tb jumps to tb1 */ | |
1346 | tb_next = tb1; | |
1347 | ||
1348 | /* remove tb from the jmp_first list */ | |
1349 | ptb = &tb_next->jmp_first; | |
1350 | for(;;) { | |
1351 | tb1 = *ptb; | |
1352 | n1 = (long)tb1 & 3; | |
1353 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1354 | if (n1 == n && tb1 == tb) | |
1355 | break; | |
1356 | ptb = &tb1->jmp_next[n1]; | |
1357 | } | |
1358 | *ptb = tb->jmp_next[n]; | |
1359 | tb->jmp_next[n] = NULL; | |
1360 | ||
1361 | /* suppress the jump to next tb in generated code */ | |
1362 | tb_reset_jump(tb, n); | |
1363 | ||
1364 | /* suppress jumps in the tb on which we could have jumped */ | |
1365 | tb_reset_jump_recursive(tb_next); | |
1366 | } | |
1367 | } | |
1368 | ||
1369 | static void tb_reset_jump_recursive(TranslationBlock *tb) | |
1370 | { | |
1371 | tb_reset_jump_recursive2(tb, 0); | |
1372 | tb_reset_jump_recursive2(tb, 1); | |
1373 | } | |
1374 | ||
1375 | #if defined(TARGET_HAS_ICE) | |
1376 | #if defined(CONFIG_USER_ONLY) | |
1377 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) | |
1378 | { | |
1379 | tb_invalidate_phys_page_range(pc, pc + 1, 0); | |
1380 | } | |
1381 | #else | |
1382 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) | |
1383 | { | |
1384 | target_phys_addr_t addr; | |
1385 | target_ulong pd; | |
1386 | ram_addr_t ram_addr; | |
1387 | PhysPageDesc *p; | |
1388 | ||
1389 | addr = cpu_get_phys_page_debug(env, pc); | |
1390 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
1391 | if (!p) { | |
1392 | pd = IO_MEM_UNASSIGNED; | |
1393 | } else { | |
1394 | pd = p->phys_offset; | |
1395 | } | |
1396 | ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK); | |
1397 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); | |
1398 | } | |
1399 | #endif | |
1400 | #endif /* TARGET_HAS_ICE */ | |
1401 | ||
1402 | #if defined(CONFIG_USER_ONLY) | |
1403 | void cpu_watchpoint_remove_all(CPUState *env, int mask) | |
1404 | ||
1405 | { | |
1406 | } | |
1407 | ||
1408 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, | |
1409 | int flags, CPUWatchpoint **watchpoint) | |
1410 | { | |
1411 | return -ENOSYS; | |
1412 | } | |
1413 | #else | |
1414 | /* Add a watchpoint. */ | |
1415 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, | |
1416 | int flags, CPUWatchpoint **watchpoint) | |
1417 | { | |
1418 | target_ulong len_mask = ~(len - 1); | |
1419 | CPUWatchpoint *wp; | |
1420 | ||
1421 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ | |
1422 | if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) { | |
1423 | fprintf(stderr, "qemu: tried to set invalid watchpoint at " | |
1424 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); | |
1425 | return -EINVAL; | |
1426 | } | |
1427 | wp = qemu_malloc(sizeof(*wp)); | |
1428 | ||
1429 | wp->vaddr = addr; | |
1430 | wp->len_mask = len_mask; | |
1431 | wp->flags = flags; | |
1432 | ||
1433 | /* keep all GDB-injected watchpoints in front */ | |
1434 | if (flags & BP_GDB) | |
1435 | QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); | |
1436 | else | |
1437 | QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); | |
1438 | ||
1439 | tlb_flush_page(env, addr); | |
1440 | ||
1441 | if (watchpoint) | |
1442 | *watchpoint = wp; | |
1443 | return 0; | |
1444 | } | |
1445 | ||
1446 | /* Remove a specific watchpoint. */ | |
1447 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len, | |
1448 | int flags) | |
1449 | { | |
1450 | target_ulong len_mask = ~(len - 1); | |
1451 | CPUWatchpoint *wp; | |
1452 | ||
1453 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { | |
1454 | if (addr == wp->vaddr && len_mask == wp->len_mask | |
1455 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { | |
1456 | cpu_watchpoint_remove_by_ref(env, wp); | |
1457 | return 0; | |
1458 | } | |
1459 | } | |
1460 | return -ENOENT; | |
1461 | } | |
1462 | ||
1463 | /* Remove a specific watchpoint by reference. */ | |
1464 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint) | |
1465 | { | |
1466 | QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); | |
1467 | ||
1468 | tlb_flush_page(env, watchpoint->vaddr); | |
1469 | ||
1470 | qemu_free(watchpoint); | |
1471 | } | |
1472 | ||
1473 | /* Remove all matching watchpoints. */ | |
1474 | void cpu_watchpoint_remove_all(CPUState *env, int mask) | |
1475 | { | |
1476 | CPUWatchpoint *wp, *next; | |
1477 | ||
1478 | QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { | |
1479 | if (wp->flags & mask) | |
1480 | cpu_watchpoint_remove_by_ref(env, wp); | |
1481 | } | |
1482 | } | |
1483 | #endif | |
1484 | ||
1485 | /* Add a breakpoint. */ | |
1486 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, | |
1487 | CPUBreakpoint **breakpoint) | |
1488 | { | |
1489 | #if defined(TARGET_HAS_ICE) | |
1490 | CPUBreakpoint *bp; | |
1491 | ||
1492 | bp = qemu_malloc(sizeof(*bp)); | |
1493 | ||
1494 | bp->pc = pc; | |
1495 | bp->flags = flags; | |
1496 | ||
1497 | /* keep all GDB-injected breakpoints in front */ | |
1498 | if (flags & BP_GDB) | |
1499 | QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); | |
1500 | else | |
1501 | QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); | |
1502 | ||
1503 | breakpoint_invalidate(env, pc); | |
1504 | ||
1505 | if (breakpoint) | |
1506 | *breakpoint = bp; | |
1507 | return 0; | |
1508 | #else | |
1509 | return -ENOSYS; | |
1510 | #endif | |
1511 | } | |
1512 | ||
1513 | /* Remove a specific breakpoint. */ | |
1514 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags) | |
1515 | { | |
1516 | #if defined(TARGET_HAS_ICE) | |
1517 | CPUBreakpoint *bp; | |
1518 | ||
1519 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
1520 | if (bp->pc == pc && bp->flags == flags) { | |
1521 | cpu_breakpoint_remove_by_ref(env, bp); | |
1522 | return 0; | |
1523 | } | |
1524 | } | |
1525 | return -ENOENT; | |
1526 | #else | |
1527 | return -ENOSYS; | |
1528 | #endif | |
1529 | } | |
1530 | ||
1531 | /* Remove a specific breakpoint by reference. */ | |
1532 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint) | |
1533 | { | |
1534 | #if defined(TARGET_HAS_ICE) | |
1535 | QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); | |
1536 | ||
1537 | breakpoint_invalidate(env, breakpoint->pc); | |
1538 | ||
1539 | qemu_free(breakpoint); | |
1540 | #endif | |
1541 | } | |
1542 | ||
1543 | /* Remove all matching breakpoints. */ | |
1544 | void cpu_breakpoint_remove_all(CPUState *env, int mask) | |
1545 | { | |
1546 | #if defined(TARGET_HAS_ICE) | |
1547 | CPUBreakpoint *bp, *next; | |
1548 | ||
1549 | QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { | |
1550 | if (bp->flags & mask) | |
1551 | cpu_breakpoint_remove_by_ref(env, bp); | |
1552 | } | |
1553 | #endif | |
1554 | } | |
1555 | ||
1556 | /* enable or disable single step mode. EXCP_DEBUG is returned by the | |
1557 | CPU loop after each instruction */ | |
1558 | void cpu_single_step(CPUState *env, int enabled) | |
1559 | { | |
1560 | #if defined(TARGET_HAS_ICE) | |
1561 | if (env->singlestep_enabled != enabled) { | |
1562 | env->singlestep_enabled = enabled; | |
1563 | if (kvm_enabled()) | |
1564 | kvm_update_guest_debug(env, 0); | |
1565 | else { | |
1566 | /* must flush all the translated code to avoid inconsistencies */ | |
1567 | /* XXX: only flush what is necessary */ | |
1568 | tb_flush(env); | |
1569 | } | |
1570 | } | |
1571 | #endif | |
1572 | } | |
1573 | ||
1574 | /* enable or disable low levels log */ | |
1575 | void cpu_set_log(int log_flags) | |
1576 | { | |
1577 | loglevel = log_flags; | |
1578 | if (loglevel && !logfile) { | |
1579 | logfile = fopen(logfilename, log_append ? "a" : "w"); | |
1580 | if (!logfile) { | |
1581 | perror(logfilename); | |
1582 | _exit(1); | |
1583 | } | |
1584 | #if !defined(CONFIG_SOFTMMU) | |
1585 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ | |
1586 | { | |
1587 | static char logfile_buf[4096]; | |
1588 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); | |
1589 | } | |
1590 | #elif !defined(_WIN32) | |
1591 | /* Win32 doesn't support line-buffering and requires size >= 2 */ | |
1592 | setvbuf(logfile, NULL, _IOLBF, 0); | |
1593 | #endif | |
1594 | log_append = 1; | |
1595 | } | |
1596 | if (!loglevel && logfile) { | |
1597 | fclose(logfile); | |
1598 | logfile = NULL; | |
1599 | } | |
1600 | } | |
1601 | ||
1602 | void cpu_set_log_filename(const char *filename) | |
1603 | { | |
1604 | logfilename = strdup(filename); | |
1605 | if (logfile) { | |
1606 | fclose(logfile); | |
1607 | logfile = NULL; | |
1608 | } | |
1609 | cpu_set_log(loglevel); | |
1610 | } | |
1611 | ||
1612 | static void cpu_unlink_tb(CPUState *env) | |
1613 | { | |
1614 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the | |
1615 | problem and hope the cpu will stop of its own accord. For userspace | |
1616 | emulation this often isn't actually as bad as it sounds. Often | |
1617 | signals are used primarily to interrupt blocking syscalls. */ | |
1618 | TranslationBlock *tb; | |
1619 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; | |
1620 | ||
1621 | spin_lock(&interrupt_lock); | |
1622 | tb = env->current_tb; | |
1623 | /* if the cpu is currently executing code, we must unlink it and | |
1624 | all the potentially executing TB */ | |
1625 | if (tb) { | |
1626 | env->current_tb = NULL; | |
1627 | tb_reset_jump_recursive(tb); | |
1628 | } | |
1629 | spin_unlock(&interrupt_lock); | |
1630 | } | |
1631 | ||
1632 | #ifndef CONFIG_USER_ONLY | |
1633 | /* mask must never be zero, except for A20 change call */ | |
1634 | static void tcg_handle_interrupt(CPUState *env, int mask) | |
1635 | { | |
1636 | int old_mask; | |
1637 | ||
1638 | old_mask = env->interrupt_request; | |
1639 | env->interrupt_request |= mask; | |
1640 | ||
1641 | /* | |
1642 | * If called from iothread context, wake the target cpu in | |
1643 | * case its halted. | |
1644 | */ | |
1645 | if (!qemu_cpu_is_self(env)) { | |
1646 | qemu_cpu_kick(env); | |
1647 | return; | |
1648 | } | |
1649 | ||
1650 | if (use_icount) { | |
1651 | env->icount_decr.u16.high = 0xffff; | |
1652 | if (!can_do_io(env) | |
1653 | && (mask & ~old_mask) != 0) { | |
1654 | cpu_abort(env, "Raised interrupt while not in I/O function"); | |
1655 | } | |
1656 | } else { | |
1657 | cpu_unlink_tb(env); | |
1658 | } | |
1659 | } | |
1660 | ||
1661 | CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt; | |
1662 | ||
1663 | #else /* CONFIG_USER_ONLY */ | |
1664 | ||
1665 | void cpu_interrupt(CPUState *env, int mask) | |
1666 | { | |
1667 | env->interrupt_request |= mask; | |
1668 | cpu_unlink_tb(env); | |
1669 | } | |
1670 | #endif /* CONFIG_USER_ONLY */ | |
1671 | ||
1672 | void cpu_reset_interrupt(CPUState *env, int mask) | |
1673 | { | |
1674 | env->interrupt_request &= ~mask; | |
1675 | } | |
1676 | ||
1677 | void cpu_exit(CPUState *env) | |
1678 | { | |
1679 | env->exit_request = 1; | |
1680 | cpu_unlink_tb(env); | |
1681 | } | |
1682 | ||
1683 | const CPULogItem cpu_log_items[] = { | |
1684 | { CPU_LOG_TB_OUT_ASM, "out_asm", | |
1685 | "show generated host assembly code for each compiled TB" }, | |
1686 | { CPU_LOG_TB_IN_ASM, "in_asm", | |
1687 | "show target assembly code for each compiled TB" }, | |
1688 | { CPU_LOG_TB_OP, "op", | |
1689 | "show micro ops for each compiled TB" }, | |
1690 | { CPU_LOG_TB_OP_OPT, "op_opt", | |
1691 | "show micro ops " | |
1692 | #ifdef TARGET_I386 | |
1693 | "before eflags optimization and " | |
1694 | #endif | |
1695 | "after liveness analysis" }, | |
1696 | { CPU_LOG_INT, "int", | |
1697 | "show interrupts/exceptions in short format" }, | |
1698 | { CPU_LOG_EXEC, "exec", | |
1699 | "show trace before each executed TB (lots of logs)" }, | |
1700 | { CPU_LOG_TB_CPU, "cpu", | |
1701 | "show CPU state before block translation" }, | |
1702 | #ifdef TARGET_I386 | |
1703 | { CPU_LOG_PCALL, "pcall", | |
1704 | "show protected mode far calls/returns/exceptions" }, | |
1705 | { CPU_LOG_RESET, "cpu_reset", | |
1706 | "show CPU state before CPU resets" }, | |
1707 | #endif | |
1708 | #ifdef DEBUG_IOPORT | |
1709 | { CPU_LOG_IOPORT, "ioport", | |
1710 | "show all i/o ports accesses" }, | |
1711 | #endif | |
1712 | { 0, NULL, NULL }, | |
1713 | }; | |
1714 | ||
1715 | #ifndef CONFIG_USER_ONLY | |
1716 | static QLIST_HEAD(memory_client_list, CPUPhysMemoryClient) memory_client_list | |
1717 | = QLIST_HEAD_INITIALIZER(memory_client_list); | |
1718 | ||
1719 | static void cpu_notify_set_memory(target_phys_addr_t start_addr, | |
1720 | ram_addr_t size, | |
1721 | ram_addr_t phys_offset) | |
1722 | { | |
1723 | CPUPhysMemoryClient *client; | |
1724 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1725 | client->set_memory(client, start_addr, size, phys_offset); | |
1726 | } | |
1727 | } | |
1728 | ||
1729 | static int cpu_notify_sync_dirty_bitmap(target_phys_addr_t start, | |
1730 | target_phys_addr_t end) | |
1731 | { | |
1732 | CPUPhysMemoryClient *client; | |
1733 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1734 | int r = client->sync_dirty_bitmap(client, start, end); | |
1735 | if (r < 0) | |
1736 | return r; | |
1737 | } | |
1738 | return 0; | |
1739 | } | |
1740 | ||
1741 | static int cpu_notify_migration_log(int enable) | |
1742 | { | |
1743 | CPUPhysMemoryClient *client; | |
1744 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1745 | int r = client->migration_log(client, enable); | |
1746 | if (r < 0) | |
1747 | return r; | |
1748 | } | |
1749 | return 0; | |
1750 | } | |
1751 | ||
1752 | static void phys_page_for_each_1(CPUPhysMemoryClient *client, | |
1753 | int level, void **lp) | |
1754 | { | |
1755 | int i; | |
1756 | ||
1757 | if (*lp == NULL) { | |
1758 | return; | |
1759 | } | |
1760 | if (level == 0) { | |
1761 | PhysPageDesc *pd = *lp; | |
1762 | for (i = 0; i < L2_SIZE; ++i) { | |
1763 | if (pd[i].phys_offset != IO_MEM_UNASSIGNED) { | |
1764 | client->set_memory(client, pd[i].region_offset, | |
1765 | TARGET_PAGE_SIZE, pd[i].phys_offset); | |
1766 | } | |
1767 | } | |
1768 | } else { | |
1769 | void **pp = *lp; | |
1770 | for (i = 0; i < L2_SIZE; ++i) { | |
1771 | phys_page_for_each_1(client, level - 1, pp + i); | |
1772 | } | |
1773 | } | |
1774 | } | |
1775 | ||
1776 | static void phys_page_for_each(CPUPhysMemoryClient *client) | |
1777 | { | |
1778 | int i; | |
1779 | for (i = 0; i < P_L1_SIZE; ++i) { | |
1780 | phys_page_for_each_1(client, P_L1_SHIFT / L2_BITS - 1, | |
1781 | l1_phys_map + 1); | |
1782 | } | |
1783 | } | |
1784 | ||
1785 | void cpu_register_phys_memory_client(CPUPhysMemoryClient *client) | |
1786 | { | |
1787 | QLIST_INSERT_HEAD(&memory_client_list, client, list); | |
1788 | phys_page_for_each(client); | |
1789 | } | |
1790 | ||
1791 | void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *client) | |
1792 | { | |
1793 | QLIST_REMOVE(client, list); | |
1794 | } | |
1795 | #endif | |
1796 | ||
1797 | static int cmp1(const char *s1, int n, const char *s2) | |
1798 | { | |
1799 | if (strlen(s2) != n) | |
1800 | return 0; | |
1801 | return memcmp(s1, s2, n) == 0; | |
1802 | } | |
1803 | ||
1804 | /* takes a comma separated list of log masks. Return 0 if error. */ | |
1805 | int cpu_str_to_log_mask(const char *str) | |
1806 | { | |
1807 | const CPULogItem *item; | |
1808 | int mask; | |
1809 | const char *p, *p1; | |
1810 | ||
1811 | p = str; | |
1812 | mask = 0; | |
1813 | for(;;) { | |
1814 | p1 = strchr(p, ','); | |
1815 | if (!p1) | |
1816 | p1 = p + strlen(p); | |
1817 | if(cmp1(p,p1-p,"all")) { | |
1818 | for(item = cpu_log_items; item->mask != 0; item++) { | |
1819 | mask |= item->mask; | |
1820 | } | |
1821 | } else { | |
1822 | for(item = cpu_log_items; item->mask != 0; item++) { | |
1823 | if (cmp1(p, p1 - p, item->name)) | |
1824 | goto found; | |
1825 | } | |
1826 | return 0; | |
1827 | } | |
1828 | found: | |
1829 | mask |= item->mask; | |
1830 | if (*p1 != ',') | |
1831 | break; | |
1832 | p = p1 + 1; | |
1833 | } | |
1834 | return mask; | |
1835 | } | |
1836 | ||
1837 | void cpu_abort(CPUState *env, const char *fmt, ...) | |
1838 | { | |
1839 | va_list ap; | |
1840 | va_list ap2; | |
1841 | ||
1842 | va_start(ap, fmt); | |
1843 | va_copy(ap2, ap); | |
1844 | fprintf(stderr, "qemu: fatal: "); | |
1845 | vfprintf(stderr, fmt, ap); | |
1846 | fprintf(stderr, "\n"); | |
1847 | #ifdef TARGET_I386 | |
1848 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); | |
1849 | #else | |
1850 | cpu_dump_state(env, stderr, fprintf, 0); | |
1851 | #endif | |
1852 | if (qemu_log_enabled()) { | |
1853 | qemu_log("qemu: fatal: "); | |
1854 | qemu_log_vprintf(fmt, ap2); | |
1855 | qemu_log("\n"); | |
1856 | #ifdef TARGET_I386 | |
1857 | log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP); | |
1858 | #else | |
1859 | log_cpu_state(env, 0); | |
1860 | #endif | |
1861 | qemu_log_flush(); | |
1862 | qemu_log_close(); | |
1863 | } | |
1864 | va_end(ap2); | |
1865 | va_end(ap); | |
1866 | #if defined(CONFIG_USER_ONLY) | |
1867 | { | |
1868 | struct sigaction act; | |
1869 | sigfillset(&act.sa_mask); | |
1870 | act.sa_handler = SIG_DFL; | |
1871 | sigaction(SIGABRT, &act, NULL); | |
1872 | } | |
1873 | #endif | |
1874 | abort(); | |
1875 | } | |
1876 | ||
1877 | CPUState *cpu_copy(CPUState *env) | |
1878 | { | |
1879 | CPUState *new_env = cpu_init(env->cpu_model_str); | |
1880 | CPUState *next_cpu = new_env->next_cpu; | |
1881 | int cpu_index = new_env->cpu_index; | |
1882 | #if defined(TARGET_HAS_ICE) | |
1883 | CPUBreakpoint *bp; | |
1884 | CPUWatchpoint *wp; | |
1885 | #endif | |
1886 | ||
1887 | memcpy(new_env, env, sizeof(CPUState)); | |
1888 | ||
1889 | /* Preserve chaining and index. */ | |
1890 | new_env->next_cpu = next_cpu; | |
1891 | new_env->cpu_index = cpu_index; | |
1892 | ||
1893 | /* Clone all break/watchpoints. | |
1894 | Note: Once we support ptrace with hw-debug register access, make sure | |
1895 | BP_CPU break/watchpoints are handled correctly on clone. */ | |
1896 | QTAILQ_INIT(&env->breakpoints); | |
1897 | QTAILQ_INIT(&env->watchpoints); | |
1898 | #if defined(TARGET_HAS_ICE) | |
1899 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
1900 | cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); | |
1901 | } | |
1902 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { | |
1903 | cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, | |
1904 | wp->flags, NULL); | |
1905 | } | |
1906 | #endif | |
1907 | ||
1908 | return new_env; | |
1909 | } | |
1910 | ||
1911 | #if !defined(CONFIG_USER_ONLY) | |
1912 | ||
1913 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr) | |
1914 | { | |
1915 | unsigned int i; | |
1916 | ||
1917 | /* Discard jump cache entries for any tb which might potentially | |
1918 | overlap the flushed page. */ | |
1919 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); | |
1920 | memset (&env->tb_jmp_cache[i], 0, | |
1921 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1922 | ||
1923 | i = tb_jmp_cache_hash_page(addr); | |
1924 | memset (&env->tb_jmp_cache[i], 0, | |
1925 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1926 | } | |
1927 | ||
1928 | static CPUTLBEntry s_cputlb_empty_entry = { | |
1929 | .addr_read = -1, | |
1930 | .addr_write = -1, | |
1931 | .addr_code = -1, | |
1932 | .addend = -1, | |
1933 | }; | |
1934 | ||
1935 | /* NOTE: if flush_global is true, also flush global entries (not | |
1936 | implemented yet) */ | |
1937 | void tlb_flush(CPUState *env, int flush_global) | |
1938 | { | |
1939 | int i; | |
1940 | ||
1941 | #if defined(DEBUG_TLB) | |
1942 | printf("tlb_flush:\n"); | |
1943 | #endif | |
1944 | /* must reset current TB so that interrupts cannot modify the | |
1945 | links while we are modifying them */ | |
1946 | env->current_tb = NULL; | |
1947 | ||
1948 | for(i = 0; i < CPU_TLB_SIZE; i++) { | |
1949 | int mmu_idx; | |
1950 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
1951 | env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry; | |
1952 | } | |
1953 | } | |
1954 | ||
1955 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); | |
1956 | ||
1957 | env->tlb_flush_addr = -1; | |
1958 | env->tlb_flush_mask = 0; | |
1959 | tlb_flush_count++; | |
1960 | } | |
1961 | ||
1962 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) | |
1963 | { | |
1964 | if (addr == (tlb_entry->addr_read & | |
1965 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || | |
1966 | addr == (tlb_entry->addr_write & | |
1967 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || | |
1968 | addr == (tlb_entry->addr_code & | |
1969 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { | |
1970 | *tlb_entry = s_cputlb_empty_entry; | |
1971 | } | |
1972 | } | |
1973 | ||
1974 | void tlb_flush_page(CPUState *env, target_ulong addr) | |
1975 | { | |
1976 | int i; | |
1977 | int mmu_idx; | |
1978 | ||
1979 | #if defined(DEBUG_TLB) | |
1980 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); | |
1981 | #endif | |
1982 | /* Check if we need to flush due to large pages. */ | |
1983 | if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) { | |
1984 | #if defined(DEBUG_TLB) | |
1985 | printf("tlb_flush_page: forced full flush (" | |
1986 | TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", | |
1987 | env->tlb_flush_addr, env->tlb_flush_mask); | |
1988 | #endif | |
1989 | tlb_flush(env, 1); | |
1990 | return; | |
1991 | } | |
1992 | /* must reset current TB so that interrupts cannot modify the | |
1993 | links while we are modifying them */ | |
1994 | env->current_tb = NULL; | |
1995 | ||
1996 | addr &= TARGET_PAGE_MASK; | |
1997 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
1998 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) | |
1999 | tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); | |
2000 | ||
2001 | tlb_flush_jmp_cache(env, addr); | |
2002 | } | |
2003 | ||
2004 | /* update the TLBs so that writes to code in the virtual page 'addr' | |
2005 | can be detected */ | |
2006 | static void tlb_protect_code(ram_addr_t ram_addr) | |
2007 | { | |
2008 | cpu_physical_memory_reset_dirty(ram_addr, | |
2009 | ram_addr + TARGET_PAGE_SIZE, | |
2010 | CODE_DIRTY_FLAG); | |
2011 | } | |
2012 | ||
2013 | /* update the TLB so that writes in physical page 'phys_addr' are no longer | |
2014 | tested for self modifying code */ | |
2015 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, | |
2016 | target_ulong vaddr) | |
2017 | { | |
2018 | cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG); | |
2019 | } | |
2020 | ||
2021 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, | |
2022 | unsigned long start, unsigned long length) | |
2023 | { | |
2024 | unsigned long addr; | |
2025 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { | |
2026 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; | |
2027 | if ((addr - start) < length) { | |
2028 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY; | |
2029 | } | |
2030 | } | |
2031 | } | |
2032 | ||
2033 | /* Note: start and end must be within the same ram block. */ | |
2034 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, | |
2035 | int dirty_flags) | |
2036 | { | |
2037 | CPUState *env; | |
2038 | unsigned long length, start1; | |
2039 | int i; | |
2040 | ||
2041 | start &= TARGET_PAGE_MASK; | |
2042 | end = TARGET_PAGE_ALIGN(end); | |
2043 | ||
2044 | length = end - start; | |
2045 | if (length == 0) | |
2046 | return; | |
2047 | cpu_physical_memory_mask_dirty_range(start, length, dirty_flags); | |
2048 | ||
2049 | /* we modify the TLB cache so that the dirty bit will be set again | |
2050 | when accessing the range */ | |
2051 | start1 = (unsigned long)qemu_safe_ram_ptr(start); | |
2052 | /* Chek that we don't span multiple blocks - this breaks the | |
2053 | address comparisons below. */ | |
2054 | if ((unsigned long)qemu_safe_ram_ptr(end - 1) - start1 | |
2055 | != (end - 1) - start) { | |
2056 | abort(); | |
2057 | } | |
2058 | ||
2059 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
2060 | int mmu_idx; | |
2061 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
2062 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
2063 | tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], | |
2064 | start1, length); | |
2065 | } | |
2066 | } | |
2067 | } | |
2068 | ||
2069 | int cpu_physical_memory_set_dirty_tracking(int enable) | |
2070 | { | |
2071 | int ret = 0; | |
2072 | in_migration = enable; | |
2073 | ret = cpu_notify_migration_log(!!enable); | |
2074 | return ret; | |
2075 | } | |
2076 | ||
2077 | int cpu_physical_memory_get_dirty_tracking(void) | |
2078 | { | |
2079 | return in_migration; | |
2080 | } | |
2081 | ||
2082 | int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, | |
2083 | target_phys_addr_t end_addr) | |
2084 | { | |
2085 | int ret; | |
2086 | ||
2087 | ret = cpu_notify_sync_dirty_bitmap(start_addr, end_addr); | |
2088 | return ret; | |
2089 | } | |
2090 | ||
2091 | int cpu_physical_log_start(target_phys_addr_t start_addr, | |
2092 | ram_addr_t size) | |
2093 | { | |
2094 | CPUPhysMemoryClient *client; | |
2095 | QLIST_FOREACH(client, &memory_client_list, list) { | |
2096 | if (client->log_start) { | |
2097 | int r = client->log_start(client, start_addr, size); | |
2098 | if (r < 0) { | |
2099 | return r; | |
2100 | } | |
2101 | } | |
2102 | } | |
2103 | return 0; | |
2104 | } | |
2105 | ||
2106 | int cpu_physical_log_stop(target_phys_addr_t start_addr, | |
2107 | ram_addr_t size) | |
2108 | { | |
2109 | CPUPhysMemoryClient *client; | |
2110 | QLIST_FOREACH(client, &memory_client_list, list) { | |
2111 | if (client->log_stop) { | |
2112 | int r = client->log_stop(client, start_addr, size); | |
2113 | if (r < 0) { | |
2114 | return r; | |
2115 | } | |
2116 | } | |
2117 | } | |
2118 | return 0; | |
2119 | } | |
2120 | ||
2121 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) | |
2122 | { | |
2123 | ram_addr_t ram_addr; | |
2124 | void *p; | |
2125 | ||
2126 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { | |
2127 | p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK) | |
2128 | + tlb_entry->addend); | |
2129 | ram_addr = qemu_ram_addr_from_host_nofail(p); | |
2130 | if (!cpu_physical_memory_is_dirty(ram_addr)) { | |
2131 | tlb_entry->addr_write |= TLB_NOTDIRTY; | |
2132 | } | |
2133 | } | |
2134 | } | |
2135 | ||
2136 | /* update the TLB according to the current state of the dirty bits */ | |
2137 | void cpu_tlb_update_dirty(CPUState *env) | |
2138 | { | |
2139 | int i; | |
2140 | int mmu_idx; | |
2141 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
2142 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
2143 | tlb_update_dirty(&env->tlb_table[mmu_idx][i]); | |
2144 | } | |
2145 | } | |
2146 | ||
2147 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) | |
2148 | { | |
2149 | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) | |
2150 | tlb_entry->addr_write = vaddr; | |
2151 | } | |
2152 | ||
2153 | /* update the TLB corresponding to virtual page vaddr | |
2154 | so that it is no longer dirty */ | |
2155 | static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) | |
2156 | { | |
2157 | int i; | |
2158 | int mmu_idx; | |
2159 | ||
2160 | vaddr &= TARGET_PAGE_MASK; | |
2161 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
2162 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) | |
2163 | tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr); | |
2164 | } | |
2165 | ||
2166 | /* Our TLB does not support large pages, so remember the area covered by | |
2167 | large pages and trigger a full TLB flush if these are invalidated. */ | |
2168 | static void tlb_add_large_page(CPUState *env, target_ulong vaddr, | |
2169 | target_ulong size) | |
2170 | { | |
2171 | target_ulong mask = ~(size - 1); | |
2172 | ||
2173 | if (env->tlb_flush_addr == (target_ulong)-1) { | |
2174 | env->tlb_flush_addr = vaddr & mask; | |
2175 | env->tlb_flush_mask = mask; | |
2176 | return; | |
2177 | } | |
2178 | /* Extend the existing region to include the new page. | |
2179 | This is a compromise between unnecessary flushes and the cost | |
2180 | of maintaining a full variable size TLB. */ | |
2181 | mask &= env->tlb_flush_mask; | |
2182 | while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) { | |
2183 | mask <<= 1; | |
2184 | } | |
2185 | env->tlb_flush_addr &= mask; | |
2186 | env->tlb_flush_mask = mask; | |
2187 | } | |
2188 | ||
2189 | /* Add a new TLB entry. At most one entry for a given virtual address | |
2190 | is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the | |
2191 | supplied size is only used by tlb_flush_page. */ | |
2192 | void tlb_set_page(CPUState *env, target_ulong vaddr, | |
2193 | target_phys_addr_t paddr, int prot, | |
2194 | int mmu_idx, target_ulong size) | |
2195 | { | |
2196 | PhysPageDesc *p; | |
2197 | unsigned long pd; | |
2198 | unsigned int index; | |
2199 | target_ulong address; | |
2200 | target_ulong code_address; | |
2201 | unsigned long addend; | |
2202 | CPUTLBEntry *te; | |
2203 | CPUWatchpoint *wp; | |
2204 | target_phys_addr_t iotlb; | |
2205 | ||
2206 | assert(size >= TARGET_PAGE_SIZE); | |
2207 | if (size != TARGET_PAGE_SIZE) { | |
2208 | tlb_add_large_page(env, vaddr, size); | |
2209 | } | |
2210 | p = phys_page_find(paddr >> TARGET_PAGE_BITS); | |
2211 | if (!p) { | |
2212 | pd = IO_MEM_UNASSIGNED; | |
2213 | } else { | |
2214 | pd = p->phys_offset; | |
2215 | } | |
2216 | #if defined(DEBUG_TLB) | |
2217 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx | |
2218 | " prot=%x idx=%d pd=0x%08lx\n", | |
2219 | vaddr, paddr, prot, mmu_idx, pd); | |
2220 | #endif | |
2221 | ||
2222 | address = vaddr; | |
2223 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { | |
2224 | /* IO memory case (romd handled later) */ | |
2225 | address |= TLB_MMIO; | |
2226 | } | |
2227 | addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK); | |
2228 | if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { | |
2229 | /* Normal RAM. */ | |
2230 | iotlb = pd & TARGET_PAGE_MASK; | |
2231 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM) | |
2232 | iotlb |= IO_MEM_NOTDIRTY; | |
2233 | else | |
2234 | iotlb |= IO_MEM_ROM; | |
2235 | } else { | |
2236 | /* IO handlers are currently passed a physical address. | |
2237 | It would be nice to pass an offset from the base address | |
2238 | of that region. This would avoid having to special case RAM, | |
2239 | and avoid full address decoding in every device. | |
2240 | We can't use the high bits of pd for this because | |
2241 | IO_MEM_ROMD uses these as a ram address. */ | |
2242 | iotlb = (pd & ~TARGET_PAGE_MASK); | |
2243 | if (p) { | |
2244 | iotlb += p->region_offset; | |
2245 | } else { | |
2246 | iotlb += paddr; | |
2247 | } | |
2248 | } | |
2249 | ||
2250 | code_address = address; | |
2251 | /* Make accesses to pages with watchpoints go via the | |
2252 | watchpoint trap routines. */ | |
2253 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { | |
2254 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { | |
2255 | /* Avoid trapping reads of pages with a write breakpoint. */ | |
2256 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { | |
2257 | iotlb = io_mem_watch + paddr; | |
2258 | address |= TLB_MMIO; | |
2259 | break; | |
2260 | } | |
2261 | } | |
2262 | } | |
2263 | ||
2264 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
2265 | env->iotlb[mmu_idx][index] = iotlb - vaddr; | |
2266 | te = &env->tlb_table[mmu_idx][index]; | |
2267 | te->addend = addend - vaddr; | |
2268 | if (prot & PAGE_READ) { | |
2269 | te->addr_read = address; | |
2270 | } else { | |
2271 | te->addr_read = -1; | |
2272 | } | |
2273 | ||
2274 | if (prot & PAGE_EXEC) { | |
2275 | te->addr_code = code_address; | |
2276 | } else { | |
2277 | te->addr_code = -1; | |
2278 | } | |
2279 | if (prot & PAGE_WRITE) { | |
2280 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM || | |
2281 | (pd & IO_MEM_ROMD)) { | |
2282 | /* Write access calls the I/O callback. */ | |
2283 | te->addr_write = address | TLB_MMIO; | |
2284 | } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM && | |
2285 | !cpu_physical_memory_is_dirty(pd)) { | |
2286 | te->addr_write = address | TLB_NOTDIRTY; | |
2287 | } else { | |
2288 | te->addr_write = address; | |
2289 | } | |
2290 | } else { | |
2291 | te->addr_write = -1; | |
2292 | } | |
2293 | } | |
2294 | ||
2295 | #else | |
2296 | ||
2297 | void tlb_flush(CPUState *env, int flush_global) | |
2298 | { | |
2299 | } | |
2300 | ||
2301 | void tlb_flush_page(CPUState *env, target_ulong addr) | |
2302 | { | |
2303 | } | |
2304 | ||
2305 | /* | |
2306 | * Walks guest process memory "regions" one by one | |
2307 | * and calls callback function 'fn' for each region. | |
2308 | */ | |
2309 | ||
2310 | struct walk_memory_regions_data | |
2311 | { | |
2312 | walk_memory_regions_fn fn; | |
2313 | void *priv; | |
2314 | unsigned long start; | |
2315 | int prot; | |
2316 | }; | |
2317 | ||
2318 | static int walk_memory_regions_end(struct walk_memory_regions_data *data, | |
2319 | abi_ulong end, int new_prot) | |
2320 | { | |
2321 | if (data->start != -1ul) { | |
2322 | int rc = data->fn(data->priv, data->start, end, data->prot); | |
2323 | if (rc != 0) { | |
2324 | return rc; | |
2325 | } | |
2326 | } | |
2327 | ||
2328 | data->start = (new_prot ? end : -1ul); | |
2329 | data->prot = new_prot; | |
2330 | ||
2331 | return 0; | |
2332 | } | |
2333 | ||
2334 | static int walk_memory_regions_1(struct walk_memory_regions_data *data, | |
2335 | abi_ulong base, int level, void **lp) | |
2336 | { | |
2337 | abi_ulong pa; | |
2338 | int i, rc; | |
2339 | ||
2340 | if (*lp == NULL) { | |
2341 | return walk_memory_regions_end(data, base, 0); | |
2342 | } | |
2343 | ||
2344 | if (level == 0) { | |
2345 | PageDesc *pd = *lp; | |
2346 | for (i = 0; i < L2_SIZE; ++i) { | |
2347 | int prot = pd[i].flags; | |
2348 | ||
2349 | pa = base | (i << TARGET_PAGE_BITS); | |
2350 | if (prot != data->prot) { | |
2351 | rc = walk_memory_regions_end(data, pa, prot); | |
2352 | if (rc != 0) { | |
2353 | return rc; | |
2354 | } | |
2355 | } | |
2356 | } | |
2357 | } else { | |
2358 | void **pp = *lp; | |
2359 | for (i = 0; i < L2_SIZE; ++i) { | |
2360 | pa = base | ((abi_ulong)i << | |
2361 | (TARGET_PAGE_BITS + L2_BITS * level)); | |
2362 | rc = walk_memory_regions_1(data, pa, level - 1, pp + i); | |
2363 | if (rc != 0) { | |
2364 | return rc; | |
2365 | } | |
2366 | } | |
2367 | } | |
2368 | ||
2369 | return 0; | |
2370 | } | |
2371 | ||
2372 | int walk_memory_regions(void *priv, walk_memory_regions_fn fn) | |
2373 | { | |
2374 | struct walk_memory_regions_data data; | |
2375 | unsigned long i; | |
2376 | ||
2377 | data.fn = fn; | |
2378 | data.priv = priv; | |
2379 | data.start = -1ul; | |
2380 | data.prot = 0; | |
2381 | ||
2382 | for (i = 0; i < V_L1_SIZE; i++) { | |
2383 | int rc = walk_memory_regions_1(&data, (abi_ulong)i << V_L1_SHIFT, | |
2384 | V_L1_SHIFT / L2_BITS - 1, l1_map + i); | |
2385 | if (rc != 0) { | |
2386 | return rc; | |
2387 | } | |
2388 | } | |
2389 | ||
2390 | return walk_memory_regions_end(&data, 0, 0); | |
2391 | } | |
2392 | ||
2393 | static int dump_region(void *priv, abi_ulong start, | |
2394 | abi_ulong end, unsigned long prot) | |
2395 | { | |
2396 | FILE *f = (FILE *)priv; | |
2397 | ||
2398 | (void) fprintf(f, TARGET_ABI_FMT_lx"-"TARGET_ABI_FMT_lx | |
2399 | " "TARGET_ABI_FMT_lx" %c%c%c\n", | |
2400 | start, end, end - start, | |
2401 | ((prot & PAGE_READ) ? 'r' : '-'), | |
2402 | ((prot & PAGE_WRITE) ? 'w' : '-'), | |
2403 | ((prot & PAGE_EXEC) ? 'x' : '-')); | |
2404 | ||
2405 | return (0); | |
2406 | } | |
2407 | ||
2408 | /* dump memory mappings */ | |
2409 | void page_dump(FILE *f) | |
2410 | { | |
2411 | (void) fprintf(f, "%-8s %-8s %-8s %s\n", | |
2412 | "start", "end", "size", "prot"); | |
2413 | walk_memory_regions(f, dump_region); | |
2414 | } | |
2415 | ||
2416 | int page_get_flags(target_ulong address) | |
2417 | { | |
2418 | PageDesc *p; | |
2419 | ||
2420 | p = page_find(address >> TARGET_PAGE_BITS); | |
2421 | if (!p) | |
2422 | return 0; | |
2423 | return p->flags; | |
2424 | } | |
2425 | ||
2426 | /* Modify the flags of a page and invalidate the code if necessary. | |
2427 | The flag PAGE_WRITE_ORG is positioned automatically depending | |
2428 | on PAGE_WRITE. The mmap_lock should already be held. */ | |
2429 | void page_set_flags(target_ulong start, target_ulong end, int flags) | |
2430 | { | |
2431 | target_ulong addr, len; | |
2432 | ||
2433 | /* This function should never be called with addresses outside the | |
2434 | guest address space. If this assert fires, it probably indicates | |
2435 | a missing call to h2g_valid. */ | |
2436 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS | |
2437 | assert(end < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); | |
2438 | #endif | |
2439 | assert(start < end); | |
2440 | ||
2441 | start = start & TARGET_PAGE_MASK; | |
2442 | end = TARGET_PAGE_ALIGN(end); | |
2443 | ||
2444 | if (flags & PAGE_WRITE) { | |
2445 | flags |= PAGE_WRITE_ORG; | |
2446 | } | |
2447 | ||
2448 | for (addr = start, len = end - start; | |
2449 | len != 0; | |
2450 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
2451 | PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2452 | ||
2453 | /* If the write protection bit is set, then we invalidate | |
2454 | the code inside. */ | |
2455 | if (!(p->flags & PAGE_WRITE) && | |
2456 | (flags & PAGE_WRITE) && | |
2457 | p->first_tb) { | |
2458 | tb_invalidate_phys_page(addr, 0, NULL); | |
2459 | } | |
2460 | p->flags = flags; | |
2461 | } | |
2462 | } | |
2463 | ||
2464 | int page_check_range(target_ulong start, target_ulong len, int flags) | |
2465 | { | |
2466 | PageDesc *p; | |
2467 | target_ulong end; | |
2468 | target_ulong addr; | |
2469 | ||
2470 | /* This function should never be called with addresses outside the | |
2471 | guest address space. If this assert fires, it probably indicates | |
2472 | a missing call to h2g_valid. */ | |
2473 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS | |
2474 | assert(start < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); | |
2475 | #endif | |
2476 | ||
2477 | if (len == 0) { | |
2478 | return 0; | |
2479 | } | |
2480 | if (start + len - 1 < start) { | |
2481 | /* We've wrapped around. */ | |
2482 | return -1; | |
2483 | } | |
2484 | ||
2485 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */ | |
2486 | start = start & TARGET_PAGE_MASK; | |
2487 | ||
2488 | for (addr = start, len = end - start; | |
2489 | len != 0; | |
2490 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
2491 | p = page_find(addr >> TARGET_PAGE_BITS); | |
2492 | if( !p ) | |
2493 | return -1; | |
2494 | if( !(p->flags & PAGE_VALID) ) | |
2495 | return -1; | |
2496 | ||
2497 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) | |
2498 | return -1; | |
2499 | if (flags & PAGE_WRITE) { | |
2500 | if (!(p->flags & PAGE_WRITE_ORG)) | |
2501 | return -1; | |
2502 | /* unprotect the page if it was put read-only because it | |
2503 | contains translated code */ | |
2504 | if (!(p->flags & PAGE_WRITE)) { | |
2505 | if (!page_unprotect(addr, 0, NULL)) | |
2506 | return -1; | |
2507 | } | |
2508 | return 0; | |
2509 | } | |
2510 | } | |
2511 | return 0; | |
2512 | } | |
2513 | ||
2514 | /* called from signal handler: invalidate the code and unprotect the | |
2515 | page. Return TRUE if the fault was successfully handled. */ | |
2516 | int page_unprotect(target_ulong address, unsigned long pc, void *puc) | |
2517 | { | |
2518 | unsigned int prot; | |
2519 | PageDesc *p; | |
2520 | target_ulong host_start, host_end, addr; | |
2521 | ||
2522 | /* Technically this isn't safe inside a signal handler. However we | |
2523 | know this only ever happens in a synchronous SEGV handler, so in | |
2524 | practice it seems to be ok. */ | |
2525 | mmap_lock(); | |
2526 | ||
2527 | p = page_find(address >> TARGET_PAGE_BITS); | |
2528 | if (!p) { | |
2529 | mmap_unlock(); | |
2530 | return 0; | |
2531 | } | |
2532 | ||
2533 | /* if the page was really writable, then we change its | |
2534 | protection back to writable */ | |
2535 | if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) { | |
2536 | host_start = address & qemu_host_page_mask; | |
2537 | host_end = host_start + qemu_host_page_size; | |
2538 | ||
2539 | prot = 0; | |
2540 | for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) { | |
2541 | p = page_find(addr >> TARGET_PAGE_BITS); | |
2542 | p->flags |= PAGE_WRITE; | |
2543 | prot |= p->flags; | |
2544 | ||
2545 | /* and since the content will be modified, we must invalidate | |
2546 | the corresponding translated code. */ | |
2547 | tb_invalidate_phys_page(addr, pc, puc); | |
2548 | #ifdef DEBUG_TB_CHECK | |
2549 | tb_invalidate_check(addr); | |
2550 | #endif | |
2551 | } | |
2552 | mprotect((void *)g2h(host_start), qemu_host_page_size, | |
2553 | prot & PAGE_BITS); | |
2554 | ||
2555 | mmap_unlock(); | |
2556 | return 1; | |
2557 | } | |
2558 | mmap_unlock(); | |
2559 | return 0; | |
2560 | } | |
2561 | ||
2562 | static inline void tlb_set_dirty(CPUState *env, | |
2563 | unsigned long addr, target_ulong vaddr) | |
2564 | { | |
2565 | } | |
2566 | #endif /* defined(CONFIG_USER_ONLY) */ | |
2567 | ||
2568 | #if !defined(CONFIG_USER_ONLY) | |
2569 | ||
2570 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) | |
2571 | typedef struct subpage_t { | |
2572 | target_phys_addr_t base; | |
2573 | ram_addr_t sub_io_index[TARGET_PAGE_SIZE]; | |
2574 | ram_addr_t region_offset[TARGET_PAGE_SIZE]; | |
2575 | } subpage_t; | |
2576 | ||
2577 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, | |
2578 | ram_addr_t memory, ram_addr_t region_offset); | |
2579 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys, | |
2580 | ram_addr_t orig_memory, | |
2581 | ram_addr_t region_offset); | |
2582 | #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ | |
2583 | need_subpage) \ | |
2584 | do { \ | |
2585 | if (addr > start_addr) \ | |
2586 | start_addr2 = 0; \ | |
2587 | else { \ | |
2588 | start_addr2 = start_addr & ~TARGET_PAGE_MASK; \ | |
2589 | if (start_addr2 > 0) \ | |
2590 | need_subpage = 1; \ | |
2591 | } \ | |
2592 | \ | |
2593 | if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \ | |
2594 | end_addr2 = TARGET_PAGE_SIZE - 1; \ | |
2595 | else { \ | |
2596 | end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \ | |
2597 | if (end_addr2 < TARGET_PAGE_SIZE - 1) \ | |
2598 | need_subpage = 1; \ | |
2599 | } \ | |
2600 | } while (0) | |
2601 | ||
2602 | /* register physical memory. | |
2603 | For RAM, 'size' must be a multiple of the target page size. | |
2604 | If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an | |
2605 | io memory page. The address used when calling the IO function is | |
2606 | the offset from the start of the region, plus region_offset. Both | |
2607 | start_addr and region_offset are rounded down to a page boundary | |
2608 | before calculating this offset. This should not be a problem unless | |
2609 | the low bits of start_addr and region_offset differ. */ | |
2610 | void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, | |
2611 | ram_addr_t size, | |
2612 | ram_addr_t phys_offset, | |
2613 | ram_addr_t region_offset) | |
2614 | { | |
2615 | target_phys_addr_t addr, end_addr; | |
2616 | PhysPageDesc *p; | |
2617 | CPUState *env; | |
2618 | ram_addr_t orig_size = size; | |
2619 | subpage_t *subpage; | |
2620 | ||
2621 | assert(size); | |
2622 | cpu_notify_set_memory(start_addr, size, phys_offset); | |
2623 | ||
2624 | if (phys_offset == IO_MEM_UNASSIGNED) { | |
2625 | region_offset = start_addr; | |
2626 | } | |
2627 | region_offset &= TARGET_PAGE_MASK; | |
2628 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; | |
2629 | end_addr = start_addr + (target_phys_addr_t)size; | |
2630 | ||
2631 | addr = start_addr; | |
2632 | do { | |
2633 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2634 | if (p && p->phys_offset != IO_MEM_UNASSIGNED) { | |
2635 | ram_addr_t orig_memory = p->phys_offset; | |
2636 | target_phys_addr_t start_addr2, end_addr2; | |
2637 | int need_subpage = 0; | |
2638 | ||
2639 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, | |
2640 | need_subpage); | |
2641 | if (need_subpage) { | |
2642 | if (!(orig_memory & IO_MEM_SUBPAGE)) { | |
2643 | subpage = subpage_init((addr & TARGET_PAGE_MASK), | |
2644 | &p->phys_offset, orig_memory, | |
2645 | p->region_offset); | |
2646 | } else { | |
2647 | subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK) | |
2648 | >> IO_MEM_SHIFT]; | |
2649 | } | |
2650 | subpage_register(subpage, start_addr2, end_addr2, phys_offset, | |
2651 | region_offset); | |
2652 | p->region_offset = 0; | |
2653 | } else { | |
2654 | p->phys_offset = phys_offset; | |
2655 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || | |
2656 | (phys_offset & IO_MEM_ROMD)) | |
2657 | phys_offset += TARGET_PAGE_SIZE; | |
2658 | } | |
2659 | } else { | |
2660 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2661 | p->phys_offset = phys_offset; | |
2662 | p->region_offset = region_offset; | |
2663 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || | |
2664 | (phys_offset & IO_MEM_ROMD)) { | |
2665 | phys_offset += TARGET_PAGE_SIZE; | |
2666 | } else { | |
2667 | target_phys_addr_t start_addr2, end_addr2; | |
2668 | int need_subpage = 0; | |
2669 | ||
2670 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, | |
2671 | end_addr2, need_subpage); | |
2672 | ||
2673 | if (need_subpage) { | |
2674 | subpage = subpage_init((addr & TARGET_PAGE_MASK), | |
2675 | &p->phys_offset, IO_MEM_UNASSIGNED, | |
2676 | addr & TARGET_PAGE_MASK); | |
2677 | subpage_register(subpage, start_addr2, end_addr2, | |
2678 | phys_offset, region_offset); | |
2679 | p->region_offset = 0; | |
2680 | } | |
2681 | } | |
2682 | } | |
2683 | region_offset += TARGET_PAGE_SIZE; | |
2684 | addr += TARGET_PAGE_SIZE; | |
2685 | } while (addr != end_addr); | |
2686 | ||
2687 | /* since each CPU stores ram addresses in its TLB cache, we must | |
2688 | reset the modified entries */ | |
2689 | /* XXX: slow ! */ | |
2690 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
2691 | tlb_flush(env, 1); | |
2692 | } | |
2693 | } | |
2694 | ||
2695 | /* XXX: temporary until new memory mapping API */ | |
2696 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr) | |
2697 | { | |
2698 | PhysPageDesc *p; | |
2699 | ||
2700 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2701 | if (!p) | |
2702 | return IO_MEM_UNASSIGNED; | |
2703 | return p->phys_offset; | |
2704 | } | |
2705 | ||
2706 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) | |
2707 | { | |
2708 | if (kvm_enabled()) | |
2709 | kvm_coalesce_mmio_region(addr, size); | |
2710 | } | |
2711 | ||
2712 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) | |
2713 | { | |
2714 | if (kvm_enabled()) | |
2715 | kvm_uncoalesce_mmio_region(addr, size); | |
2716 | } | |
2717 | ||
2718 | void qemu_flush_coalesced_mmio_buffer(void) | |
2719 | { | |
2720 | if (kvm_enabled()) | |
2721 | kvm_flush_coalesced_mmio_buffer(); | |
2722 | } | |
2723 | ||
2724 | #if defined(__linux__) && !defined(TARGET_S390X) | |
2725 | ||
2726 | #include <sys/vfs.h> | |
2727 | ||
2728 | #define HUGETLBFS_MAGIC 0x958458f6 | |
2729 | ||
2730 | static long gethugepagesize(const char *path) | |
2731 | { | |
2732 | struct statfs fs; | |
2733 | int ret; | |
2734 | ||
2735 | do { | |
2736 | ret = statfs(path, &fs); | |
2737 | } while (ret != 0 && errno == EINTR); | |
2738 | ||
2739 | if (ret != 0) { | |
2740 | perror(path); | |
2741 | return 0; | |
2742 | } | |
2743 | ||
2744 | if (fs.f_type != HUGETLBFS_MAGIC) | |
2745 | fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path); | |
2746 | ||
2747 | return fs.f_bsize; | |
2748 | } | |
2749 | ||
2750 | static void *file_ram_alloc(RAMBlock *block, | |
2751 | ram_addr_t memory, | |
2752 | const char *path) | |
2753 | { | |
2754 | char *filename; | |
2755 | void *area; | |
2756 | int fd; | |
2757 | #ifdef MAP_POPULATE | |
2758 | int flags; | |
2759 | #endif | |
2760 | unsigned long hpagesize; | |
2761 | ||
2762 | hpagesize = gethugepagesize(path); | |
2763 | if (!hpagesize) { | |
2764 | return NULL; | |
2765 | } | |
2766 | ||
2767 | if (memory < hpagesize) { | |
2768 | return NULL; | |
2769 | } | |
2770 | ||
2771 | if (kvm_enabled() && !kvm_has_sync_mmu()) { | |
2772 | fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n"); | |
2773 | return NULL; | |
2774 | } | |
2775 | ||
2776 | if (asprintf(&filename, "%s/qemu_back_mem.XXXXXX", path) == -1) { | |
2777 | return NULL; | |
2778 | } | |
2779 | ||
2780 | fd = mkstemp(filename); | |
2781 | if (fd < 0) { | |
2782 | perror("unable to create backing store for hugepages"); | |
2783 | free(filename); | |
2784 | return NULL; | |
2785 | } | |
2786 | unlink(filename); | |
2787 | free(filename); | |
2788 | ||
2789 | memory = (memory+hpagesize-1) & ~(hpagesize-1); | |
2790 | ||
2791 | /* | |
2792 | * ftruncate is not supported by hugetlbfs in older | |
2793 | * hosts, so don't bother bailing out on errors. | |
2794 | * If anything goes wrong with it under other filesystems, | |
2795 | * mmap will fail. | |
2796 | */ | |
2797 | if (ftruncate(fd, memory)) | |
2798 | perror("ftruncate"); | |
2799 | ||
2800 | #ifdef MAP_POPULATE | |
2801 | /* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case | |
2802 | * MAP_PRIVATE is requested. For mem_prealloc we mmap as MAP_SHARED | |
2803 | * to sidestep this quirk. | |
2804 | */ | |
2805 | flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE; | |
2806 | area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0); | |
2807 | #else | |
2808 | area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); | |
2809 | #endif | |
2810 | if (area == MAP_FAILED) { | |
2811 | perror("file_ram_alloc: can't mmap RAM pages"); | |
2812 | close(fd); | |
2813 | return (NULL); | |
2814 | } | |
2815 | block->fd = fd; | |
2816 | return area; | |
2817 | } | |
2818 | #endif | |
2819 | ||
2820 | static ram_addr_t find_ram_offset(ram_addr_t size) | |
2821 | { | |
2822 | RAMBlock *block, *next_block; | |
2823 | ram_addr_t offset = 0, mingap = ULONG_MAX; | |
2824 | ||
2825 | if (QLIST_EMPTY(&ram_list.blocks)) | |
2826 | return 0; | |
2827 | ||
2828 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
2829 | ram_addr_t end, next = ULONG_MAX; | |
2830 | ||
2831 | end = block->offset + block->length; | |
2832 | ||
2833 | QLIST_FOREACH(next_block, &ram_list.blocks, next) { | |
2834 | if (next_block->offset >= end) { | |
2835 | next = MIN(next, next_block->offset); | |
2836 | } | |
2837 | } | |
2838 | if (next - end >= size && next - end < mingap) { | |
2839 | offset = end; | |
2840 | mingap = next - end; | |
2841 | } | |
2842 | } | |
2843 | return offset; | |
2844 | } | |
2845 | ||
2846 | static ram_addr_t last_ram_offset(void) | |
2847 | { | |
2848 | RAMBlock *block; | |
2849 | ram_addr_t last = 0; | |
2850 | ||
2851 | QLIST_FOREACH(block, &ram_list.blocks, next) | |
2852 | last = MAX(last, block->offset + block->length); | |
2853 | ||
2854 | return last; | |
2855 | } | |
2856 | ||
2857 | ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name, | |
2858 | ram_addr_t size, void *host) | |
2859 | { | |
2860 | RAMBlock *new_block, *block; | |
2861 | ||
2862 | size = TARGET_PAGE_ALIGN(size); | |
2863 | new_block = qemu_mallocz(sizeof(*new_block)); | |
2864 | ||
2865 | if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) { | |
2866 | char *id = dev->parent_bus->info->get_dev_path(dev); | |
2867 | if (id) { | |
2868 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); | |
2869 | qemu_free(id); | |
2870 | } | |
2871 | } | |
2872 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); | |
2873 | ||
2874 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
2875 | if (!strcmp(block->idstr, new_block->idstr)) { | |
2876 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", | |
2877 | new_block->idstr); | |
2878 | abort(); | |
2879 | } | |
2880 | } | |
2881 | ||
2882 | if (host) { | |
2883 | new_block->host = host; | |
2884 | new_block->flags |= RAM_PREALLOC_MASK; | |
2885 | } else { | |
2886 | if (mem_path) { | |
2887 | #if defined (__linux__) && !defined(TARGET_S390X) | |
2888 | new_block->host = file_ram_alloc(new_block, size, mem_path); | |
2889 | if (!new_block->host) { | |
2890 | new_block->host = qemu_vmalloc(size); | |
2891 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); | |
2892 | } | |
2893 | #else | |
2894 | fprintf(stderr, "-mem-path option unsupported\n"); | |
2895 | exit(1); | |
2896 | #endif | |
2897 | } else { | |
2898 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) | |
2899 | /* XXX S390 KVM requires the topmost vma of the RAM to be < 256GB */ | |
2900 | new_block->host = mmap((void*)0x1000000, size, | |
2901 | PROT_EXEC|PROT_READ|PROT_WRITE, | |
2902 | MAP_SHARED | MAP_ANONYMOUS, -1, 0); | |
2903 | #else | |
2904 | new_block->host = qemu_vmalloc(size); | |
2905 | #endif | |
2906 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); | |
2907 | } | |
2908 | } | |
2909 | ||
2910 | new_block->offset = find_ram_offset(size); | |
2911 | new_block->length = size; | |
2912 | ||
2913 | QLIST_INSERT_HEAD(&ram_list.blocks, new_block, next); | |
2914 | ||
2915 | ram_list.phys_dirty = qemu_realloc(ram_list.phys_dirty, | |
2916 | last_ram_offset() >> TARGET_PAGE_BITS); | |
2917 | memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS), | |
2918 | 0xff, size >> TARGET_PAGE_BITS); | |
2919 | ||
2920 | if (kvm_enabled()) | |
2921 | kvm_setup_guest_memory(new_block->host, size); | |
2922 | ||
2923 | return new_block->offset; | |
2924 | } | |
2925 | ||
2926 | ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size) | |
2927 | { | |
2928 | return qemu_ram_alloc_from_ptr(dev, name, size, NULL); | |
2929 | } | |
2930 | ||
2931 | void qemu_ram_free(ram_addr_t addr) | |
2932 | { | |
2933 | RAMBlock *block; | |
2934 | ||
2935 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
2936 | if (addr == block->offset) { | |
2937 | QLIST_REMOVE(block, next); | |
2938 | if (block->flags & RAM_PREALLOC_MASK) { | |
2939 | ; | |
2940 | } else if (mem_path) { | |
2941 | #if defined (__linux__) && !defined(TARGET_S390X) | |
2942 | if (block->fd) { | |
2943 | munmap(block->host, block->length); | |
2944 | close(block->fd); | |
2945 | } else { | |
2946 | qemu_vfree(block->host); | |
2947 | } | |
2948 | #else | |
2949 | abort(); | |
2950 | #endif | |
2951 | } else { | |
2952 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) | |
2953 | munmap(block->host, block->length); | |
2954 | #else | |
2955 | qemu_vfree(block->host); | |
2956 | #endif | |
2957 | } | |
2958 | qemu_free(block); | |
2959 | return; | |
2960 | } | |
2961 | } | |
2962 | ||
2963 | } | |
2964 | ||
2965 | #ifndef _WIN32 | |
2966 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) | |
2967 | { | |
2968 | RAMBlock *block; | |
2969 | ram_addr_t offset; | |
2970 | int flags; | |
2971 | void *area, *vaddr; | |
2972 | ||
2973 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
2974 | offset = addr - block->offset; | |
2975 | if (offset < block->length) { | |
2976 | vaddr = block->host + offset; | |
2977 | if (block->flags & RAM_PREALLOC_MASK) { | |
2978 | ; | |
2979 | } else { | |
2980 | flags = MAP_FIXED; | |
2981 | munmap(vaddr, length); | |
2982 | if (mem_path) { | |
2983 | #if defined(__linux__) && !defined(TARGET_S390X) | |
2984 | if (block->fd) { | |
2985 | #ifdef MAP_POPULATE | |
2986 | flags |= mem_prealloc ? MAP_POPULATE | MAP_SHARED : | |
2987 | MAP_PRIVATE; | |
2988 | #else | |
2989 | flags |= MAP_PRIVATE; | |
2990 | #endif | |
2991 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
2992 | flags, block->fd, offset); | |
2993 | } else { | |
2994 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; | |
2995 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
2996 | flags, -1, 0); | |
2997 | } | |
2998 | #else | |
2999 | abort(); | |
3000 | #endif | |
3001 | } else { | |
3002 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) | |
3003 | flags |= MAP_SHARED | MAP_ANONYMOUS; | |
3004 | area = mmap(vaddr, length, PROT_EXEC|PROT_READ|PROT_WRITE, | |
3005 | flags, -1, 0); | |
3006 | #else | |
3007 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; | |
3008 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
3009 | flags, -1, 0); | |
3010 | #endif | |
3011 | } | |
3012 | if (area != vaddr) { | |
3013 | fprintf(stderr, "Could not remap addr: %lx@%lx\n", | |
3014 | length, addr); | |
3015 | exit(1); | |
3016 | } | |
3017 | qemu_madvise(vaddr, length, QEMU_MADV_MERGEABLE); | |
3018 | } | |
3019 | return; | |
3020 | } | |
3021 | } | |
3022 | } | |
3023 | #endif /* !_WIN32 */ | |
3024 | ||
3025 | /* Return a host pointer to ram allocated with qemu_ram_alloc. | |
3026 | With the exception of the softmmu code in this file, this should | |
3027 | only be used for local memory (e.g. video ram) that the device owns, | |
3028 | and knows it isn't going to access beyond the end of the block. | |
3029 | ||
3030 | It should not be used for general purpose DMA. | |
3031 | Use cpu_physical_memory_map/cpu_physical_memory_rw instead. | |
3032 | */ | |
3033 | void *qemu_get_ram_ptr(ram_addr_t addr) | |
3034 | { | |
3035 | RAMBlock *block; | |
3036 | ||
3037 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
3038 | if (addr - block->offset < block->length) { | |
3039 | /* Move this entry to to start of the list. */ | |
3040 | if (block != QLIST_FIRST(&ram_list.blocks)) { | |
3041 | QLIST_REMOVE(block, next); | |
3042 | QLIST_INSERT_HEAD(&ram_list.blocks, block, next); | |
3043 | } | |
3044 | return block->host + (addr - block->offset); | |
3045 | } | |
3046 | } | |
3047 | ||
3048 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
3049 | abort(); | |
3050 | ||
3051 | return NULL; | |
3052 | } | |
3053 | ||
3054 | /* Return a host pointer to ram allocated with qemu_ram_alloc. | |
3055 | * Same as qemu_get_ram_ptr but avoid reordering ramblocks. | |
3056 | */ | |
3057 | void *qemu_safe_ram_ptr(ram_addr_t addr) | |
3058 | { | |
3059 | RAMBlock *block; | |
3060 | ||
3061 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
3062 | if (addr - block->offset < block->length) { | |
3063 | return block->host + (addr - block->offset); | |
3064 | } | |
3065 | } | |
3066 | ||
3067 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
3068 | abort(); | |
3069 | ||
3070 | return NULL; | |
3071 | } | |
3072 | ||
3073 | int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr) | |
3074 | { | |
3075 | RAMBlock *block; | |
3076 | uint8_t *host = ptr; | |
3077 | ||
3078 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
3079 | if (host - block->host < block->length) { | |
3080 | *ram_addr = block->offset + (host - block->host); | |
3081 | return 0; | |
3082 | } | |
3083 | } | |
3084 | return -1; | |
3085 | } | |
3086 | ||
3087 | /* Some of the softmmu routines need to translate from a host pointer | |
3088 | (typically a TLB entry) back to a ram offset. */ | |
3089 | ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) | |
3090 | { | |
3091 | ram_addr_t ram_addr; | |
3092 | ||
3093 | if (qemu_ram_addr_from_host(ptr, &ram_addr)) { | |
3094 | fprintf(stderr, "Bad ram pointer %p\n", ptr); | |
3095 | abort(); | |
3096 | } | |
3097 | return ram_addr; | |
3098 | } | |
3099 | ||
3100 | static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) | |
3101 | { | |
3102 | #ifdef DEBUG_UNASSIGNED | |
3103 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
3104 | #endif | |
3105 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) | |
3106 | do_unassigned_access(addr, 0, 0, 0, 1); | |
3107 | #endif | |
3108 | return 0; | |
3109 | } | |
3110 | ||
3111 | static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) | |
3112 | { | |
3113 | #ifdef DEBUG_UNASSIGNED | |
3114 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
3115 | #endif | |
3116 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) | |
3117 | do_unassigned_access(addr, 0, 0, 0, 2); | |
3118 | #endif | |
3119 | return 0; | |
3120 | } | |
3121 | ||
3122 | static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) | |
3123 | { | |
3124 | #ifdef DEBUG_UNASSIGNED | |
3125 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
3126 | #endif | |
3127 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) | |
3128 | do_unassigned_access(addr, 0, 0, 0, 4); | |
3129 | #endif | |
3130 | return 0; | |
3131 | } | |
3132 | ||
3133 | static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | |
3134 | { | |
3135 | #ifdef DEBUG_UNASSIGNED | |
3136 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
3137 | #endif | |
3138 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) | |
3139 | do_unassigned_access(addr, 1, 0, 0, 1); | |
3140 | #endif | |
3141 | } | |
3142 | ||
3143 | static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) | |
3144 | { | |
3145 | #ifdef DEBUG_UNASSIGNED | |
3146 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
3147 | #endif | |
3148 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) | |
3149 | do_unassigned_access(addr, 1, 0, 0, 2); | |
3150 | #endif | |
3151 | } | |
3152 | ||
3153 | static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) | |
3154 | { | |
3155 | #ifdef DEBUG_UNASSIGNED | |
3156 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
3157 | #endif | |
3158 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) | |
3159 | do_unassigned_access(addr, 1, 0, 0, 4); | |
3160 | #endif | |
3161 | } | |
3162 | ||
3163 | static CPUReadMemoryFunc * const unassigned_mem_read[3] = { | |
3164 | unassigned_mem_readb, | |
3165 | unassigned_mem_readw, | |
3166 | unassigned_mem_readl, | |
3167 | }; | |
3168 | ||
3169 | static CPUWriteMemoryFunc * const unassigned_mem_write[3] = { | |
3170 | unassigned_mem_writeb, | |
3171 | unassigned_mem_writew, | |
3172 | unassigned_mem_writel, | |
3173 | }; | |
3174 | ||
3175 | static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, | |
3176 | uint32_t val) | |
3177 | { | |
3178 | int dirty_flags; | |
3179 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); | |
3180 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
3181 | #if !defined(CONFIG_USER_ONLY) | |
3182 | tb_invalidate_phys_page_fast(ram_addr, 1); | |
3183 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); | |
3184 | #endif | |
3185 | } | |
3186 | stb_p(qemu_get_ram_ptr(ram_addr), val); | |
3187 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); | |
3188 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); | |
3189 | /* we remove the notdirty callback only if the code has been | |
3190 | flushed */ | |
3191 | if (dirty_flags == 0xff) | |
3192 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); | |
3193 | } | |
3194 | ||
3195 | static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr, | |
3196 | uint32_t val) | |
3197 | { | |
3198 | int dirty_flags; | |
3199 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); | |
3200 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
3201 | #if !defined(CONFIG_USER_ONLY) | |
3202 | tb_invalidate_phys_page_fast(ram_addr, 2); | |
3203 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); | |
3204 | #endif | |
3205 | } | |
3206 | stw_p(qemu_get_ram_ptr(ram_addr), val); | |
3207 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); | |
3208 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); | |
3209 | /* we remove the notdirty callback only if the code has been | |
3210 | flushed */ | |
3211 | if (dirty_flags == 0xff) | |
3212 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); | |
3213 | } | |
3214 | ||
3215 | static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr, | |
3216 | uint32_t val) | |
3217 | { | |
3218 | int dirty_flags; | |
3219 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); | |
3220 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
3221 | #if !defined(CONFIG_USER_ONLY) | |
3222 | tb_invalidate_phys_page_fast(ram_addr, 4); | |
3223 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); | |
3224 | #endif | |
3225 | } | |
3226 | stl_p(qemu_get_ram_ptr(ram_addr), val); | |
3227 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); | |
3228 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); | |
3229 | /* we remove the notdirty callback only if the code has been | |
3230 | flushed */ | |
3231 | if (dirty_flags == 0xff) | |
3232 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); | |
3233 | } | |
3234 | ||
3235 | static CPUReadMemoryFunc * const error_mem_read[3] = { | |
3236 | NULL, /* never used */ | |
3237 | NULL, /* never used */ | |
3238 | NULL, /* never used */ | |
3239 | }; | |
3240 | ||
3241 | static CPUWriteMemoryFunc * const notdirty_mem_write[3] = { | |
3242 | notdirty_mem_writeb, | |
3243 | notdirty_mem_writew, | |
3244 | notdirty_mem_writel, | |
3245 | }; | |
3246 | ||
3247 | /* Generate a debug exception if a watchpoint has been hit. */ | |
3248 | static void check_watchpoint(int offset, int len_mask, int flags) | |
3249 | { | |
3250 | CPUState *env = cpu_single_env; | |
3251 | target_ulong pc, cs_base; | |
3252 | TranslationBlock *tb; | |
3253 | target_ulong vaddr; | |
3254 | CPUWatchpoint *wp; | |
3255 | int cpu_flags; | |
3256 | ||
3257 | if (env->watchpoint_hit) { | |
3258 | /* We re-entered the check after replacing the TB. Now raise | |
3259 | * the debug interrupt so that is will trigger after the | |
3260 | * current instruction. */ | |
3261 | cpu_interrupt(env, CPU_INTERRUPT_DEBUG); | |
3262 | return; | |
3263 | } | |
3264 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; | |
3265 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { | |
3266 | if ((vaddr == (wp->vaddr & len_mask) || | |
3267 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { | |
3268 | wp->flags |= BP_WATCHPOINT_HIT; | |
3269 | if (!env->watchpoint_hit) { | |
3270 | env->watchpoint_hit = wp; | |
3271 | tb = tb_find_pc(env->mem_io_pc); | |
3272 | if (!tb) { | |
3273 | cpu_abort(env, "check_watchpoint: could not find TB for " | |
3274 | "pc=%p", (void *)env->mem_io_pc); | |
3275 | } | |
3276 | cpu_restore_state(tb, env, env->mem_io_pc); | |
3277 | tb_phys_invalidate(tb, -1); | |
3278 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { | |
3279 | env->exception_index = EXCP_DEBUG; | |
3280 | } else { | |
3281 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); | |
3282 | tb_gen_code(env, pc, cs_base, cpu_flags, 1); | |
3283 | } | |
3284 | cpu_resume_from_signal(env, NULL); | |
3285 | } | |
3286 | } else { | |
3287 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
3288 | } | |
3289 | } | |
3290 | } | |
3291 | ||
3292 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, | |
3293 | so these check for a hit then pass through to the normal out-of-line | |
3294 | phys routines. */ | |
3295 | static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr) | |
3296 | { | |
3297 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ); | |
3298 | return ldub_phys(addr); | |
3299 | } | |
3300 | ||
3301 | static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr) | |
3302 | { | |
3303 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ); | |
3304 | return lduw_phys(addr); | |
3305 | } | |
3306 | ||
3307 | static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr) | |
3308 | { | |
3309 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ); | |
3310 | return ldl_phys(addr); | |
3311 | } | |
3312 | ||
3313 | static void watch_mem_writeb(void *opaque, target_phys_addr_t addr, | |
3314 | uint32_t val) | |
3315 | { | |
3316 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE); | |
3317 | stb_phys(addr, val); | |
3318 | } | |
3319 | ||
3320 | static void watch_mem_writew(void *opaque, target_phys_addr_t addr, | |
3321 | uint32_t val) | |
3322 | { | |
3323 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE); | |
3324 | stw_phys(addr, val); | |
3325 | } | |
3326 | ||
3327 | static void watch_mem_writel(void *opaque, target_phys_addr_t addr, | |
3328 | uint32_t val) | |
3329 | { | |
3330 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE); | |
3331 | stl_phys(addr, val); | |
3332 | } | |
3333 | ||
3334 | static CPUReadMemoryFunc * const watch_mem_read[3] = { | |
3335 | watch_mem_readb, | |
3336 | watch_mem_readw, | |
3337 | watch_mem_readl, | |
3338 | }; | |
3339 | ||
3340 | static CPUWriteMemoryFunc * const watch_mem_write[3] = { | |
3341 | watch_mem_writeb, | |
3342 | watch_mem_writew, | |
3343 | watch_mem_writel, | |
3344 | }; | |
3345 | ||
3346 | static inline uint32_t subpage_readlen (subpage_t *mmio, | |
3347 | target_phys_addr_t addr, | |
3348 | unsigned int len) | |
3349 | { | |
3350 | unsigned int idx = SUBPAGE_IDX(addr); | |
3351 | #if defined(DEBUG_SUBPAGE) | |
3352 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__, | |
3353 | mmio, len, addr, idx); | |
3354 | #endif | |
3355 | ||
3356 | addr += mmio->region_offset[idx]; | |
3357 | idx = mmio->sub_io_index[idx]; | |
3358 | return io_mem_read[idx][len](io_mem_opaque[idx], addr); | |
3359 | } | |
3360 | ||
3361 | static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr, | |
3362 | uint32_t value, unsigned int len) | |
3363 | { | |
3364 | unsigned int idx = SUBPAGE_IDX(addr); | |
3365 | #if defined(DEBUG_SUBPAGE) | |
3366 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", | |
3367 | __func__, mmio, len, addr, idx, value); | |
3368 | #endif | |
3369 | ||
3370 | addr += mmio->region_offset[idx]; | |
3371 | idx = mmio->sub_io_index[idx]; | |
3372 | io_mem_write[idx][len](io_mem_opaque[idx], addr, value); | |
3373 | } | |
3374 | ||
3375 | static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) | |
3376 | { | |
3377 | return subpage_readlen(opaque, addr, 0); | |
3378 | } | |
3379 | ||
3380 | static void subpage_writeb (void *opaque, target_phys_addr_t addr, | |
3381 | uint32_t value) | |
3382 | { | |
3383 | subpage_writelen(opaque, addr, value, 0); | |
3384 | } | |
3385 | ||
3386 | static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr) | |
3387 | { | |
3388 | return subpage_readlen(opaque, addr, 1); | |
3389 | } | |
3390 | ||
3391 | static void subpage_writew (void *opaque, target_phys_addr_t addr, | |
3392 | uint32_t value) | |
3393 | { | |
3394 | subpage_writelen(opaque, addr, value, 1); | |
3395 | } | |
3396 | ||
3397 | static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr) | |
3398 | { | |
3399 | return subpage_readlen(opaque, addr, 2); | |
3400 | } | |
3401 | ||
3402 | static void subpage_writel (void *opaque, target_phys_addr_t addr, | |
3403 | uint32_t value) | |
3404 | { | |
3405 | subpage_writelen(opaque, addr, value, 2); | |
3406 | } | |
3407 | ||
3408 | static CPUReadMemoryFunc * const subpage_read[] = { | |
3409 | &subpage_readb, | |
3410 | &subpage_readw, | |
3411 | &subpage_readl, | |
3412 | }; | |
3413 | ||
3414 | static CPUWriteMemoryFunc * const subpage_write[] = { | |
3415 | &subpage_writeb, | |
3416 | &subpage_writew, | |
3417 | &subpage_writel, | |
3418 | }; | |
3419 | ||
3420 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, | |
3421 | ram_addr_t memory, ram_addr_t region_offset) | |
3422 | { | |
3423 | int idx, eidx; | |
3424 | ||
3425 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
3426 | return -1; | |
3427 | idx = SUBPAGE_IDX(start); | |
3428 | eidx = SUBPAGE_IDX(end); | |
3429 | #if defined(DEBUG_SUBPAGE) | |
3430 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__, | |
3431 | mmio, start, end, idx, eidx, memory); | |
3432 | #endif | |
3433 | if ((memory & ~TARGET_PAGE_MASK) == IO_MEM_RAM) | |
3434 | memory = IO_MEM_UNASSIGNED; | |
3435 | memory = (memory >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
3436 | for (; idx <= eidx; idx++) { | |
3437 | mmio->sub_io_index[idx] = memory; | |
3438 | mmio->region_offset[idx] = region_offset; | |
3439 | } | |
3440 | ||
3441 | return 0; | |
3442 | } | |
3443 | ||
3444 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys, | |
3445 | ram_addr_t orig_memory, | |
3446 | ram_addr_t region_offset) | |
3447 | { | |
3448 | subpage_t *mmio; | |
3449 | int subpage_memory; | |
3450 | ||
3451 | mmio = qemu_mallocz(sizeof(subpage_t)); | |
3452 | ||
3453 | mmio->base = base; | |
3454 | subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio, | |
3455 | DEVICE_NATIVE_ENDIAN); | |
3456 | #if defined(DEBUG_SUBPAGE) | |
3457 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, | |
3458 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); | |
3459 | #endif | |
3460 | *phys = subpage_memory | IO_MEM_SUBPAGE; | |
3461 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, orig_memory, region_offset); | |
3462 | ||
3463 | return mmio; | |
3464 | } | |
3465 | ||
3466 | static int get_free_io_mem_idx(void) | |
3467 | { | |
3468 | int i; | |
3469 | ||
3470 | for (i = 0; i<IO_MEM_NB_ENTRIES; i++) | |
3471 | if (!io_mem_used[i]) { | |
3472 | io_mem_used[i] = 1; | |
3473 | return i; | |
3474 | } | |
3475 | fprintf(stderr, "RAN out out io_mem_idx, max %d !\n", IO_MEM_NB_ENTRIES); | |
3476 | return -1; | |
3477 | } | |
3478 | ||
3479 | /* | |
3480 | * Usually, devices operate in little endian mode. There are devices out | |
3481 | * there that operate in big endian too. Each device gets byte swapped | |
3482 | * mmio if plugged onto a CPU that does the other endianness. | |
3483 | * | |
3484 | * CPU Device swap? | |
3485 | * | |
3486 | * little little no | |
3487 | * little big yes | |
3488 | * big little yes | |
3489 | * big big no | |
3490 | */ | |
3491 | ||
3492 | typedef struct SwapEndianContainer { | |
3493 | CPUReadMemoryFunc *read[3]; | |
3494 | CPUWriteMemoryFunc *write[3]; | |
3495 | void *opaque; | |
3496 | } SwapEndianContainer; | |
3497 | ||
3498 | static uint32_t swapendian_mem_readb (void *opaque, target_phys_addr_t addr) | |
3499 | { | |
3500 | uint32_t val; | |
3501 | SwapEndianContainer *c = opaque; | |
3502 | val = c->read[0](c->opaque, addr); | |
3503 | return val; | |
3504 | } | |
3505 | ||
3506 | static uint32_t swapendian_mem_readw(void *opaque, target_phys_addr_t addr) | |
3507 | { | |
3508 | uint32_t val; | |
3509 | SwapEndianContainer *c = opaque; | |
3510 | val = bswap16(c->read[1](c->opaque, addr)); | |
3511 | return val; | |
3512 | } | |
3513 | ||
3514 | static uint32_t swapendian_mem_readl(void *opaque, target_phys_addr_t addr) | |
3515 | { | |
3516 | uint32_t val; | |
3517 | SwapEndianContainer *c = opaque; | |
3518 | val = bswap32(c->read[2](c->opaque, addr)); | |
3519 | return val; | |
3520 | } | |
3521 | ||
3522 | static CPUReadMemoryFunc * const swapendian_readfn[3]={ | |
3523 | swapendian_mem_readb, | |
3524 | swapendian_mem_readw, | |
3525 | swapendian_mem_readl | |
3526 | }; | |
3527 | ||
3528 | static void swapendian_mem_writeb(void *opaque, target_phys_addr_t addr, | |
3529 | uint32_t val) | |
3530 | { | |
3531 | SwapEndianContainer *c = opaque; | |
3532 | c->write[0](c->opaque, addr, val); | |
3533 | } | |
3534 | ||
3535 | static void swapendian_mem_writew(void *opaque, target_phys_addr_t addr, | |
3536 | uint32_t val) | |
3537 | { | |
3538 | SwapEndianContainer *c = opaque; | |
3539 | c->write[1](c->opaque, addr, bswap16(val)); | |
3540 | } | |
3541 | ||
3542 | static void swapendian_mem_writel(void *opaque, target_phys_addr_t addr, | |
3543 | uint32_t val) | |
3544 | { | |
3545 | SwapEndianContainer *c = opaque; | |
3546 | c->write[2](c->opaque, addr, bswap32(val)); | |
3547 | } | |
3548 | ||
3549 | static CPUWriteMemoryFunc * const swapendian_writefn[3]={ | |
3550 | swapendian_mem_writeb, | |
3551 | swapendian_mem_writew, | |
3552 | swapendian_mem_writel | |
3553 | }; | |
3554 | ||
3555 | static void swapendian_init(int io_index) | |
3556 | { | |
3557 | SwapEndianContainer *c = qemu_malloc(sizeof(SwapEndianContainer)); | |
3558 | int i; | |
3559 | ||
3560 | /* Swap mmio for big endian targets */ | |
3561 | c->opaque = io_mem_opaque[io_index]; | |
3562 | for (i = 0; i < 3; i++) { | |
3563 | c->read[i] = io_mem_read[io_index][i]; | |
3564 | c->write[i] = io_mem_write[io_index][i]; | |
3565 | ||
3566 | io_mem_read[io_index][i] = swapendian_readfn[i]; | |
3567 | io_mem_write[io_index][i] = swapendian_writefn[i]; | |
3568 | } | |
3569 | io_mem_opaque[io_index] = c; | |
3570 | } | |
3571 | ||
3572 | static void swapendian_del(int io_index) | |
3573 | { | |
3574 | if (io_mem_read[io_index][0] == swapendian_readfn[0]) { | |
3575 | qemu_free(io_mem_opaque[io_index]); | |
3576 | } | |
3577 | } | |
3578 | ||
3579 | /* mem_read and mem_write are arrays of functions containing the | |
3580 | function to access byte (index 0), word (index 1) and dword (index | |
3581 | 2). Functions can be omitted with a NULL function pointer. | |
3582 | If io_index is non zero, the corresponding io zone is | |
3583 | modified. If it is zero, a new io zone is allocated. The return | |
3584 | value can be used with cpu_register_physical_memory(). (-1) is | |
3585 | returned if error. */ | |
3586 | static int cpu_register_io_memory_fixed(int io_index, | |
3587 | CPUReadMemoryFunc * const *mem_read, | |
3588 | CPUWriteMemoryFunc * const *mem_write, | |
3589 | void *opaque, enum device_endian endian) | |
3590 | { | |
3591 | int i; | |
3592 | ||
3593 | if (io_index <= 0) { | |
3594 | io_index = get_free_io_mem_idx(); | |
3595 | if (io_index == -1) | |
3596 | return io_index; | |
3597 | } else { | |
3598 | io_index >>= IO_MEM_SHIFT; | |
3599 | if (io_index >= IO_MEM_NB_ENTRIES) | |
3600 | return -1; | |
3601 | } | |
3602 | ||
3603 | for (i = 0; i < 3; ++i) { | |
3604 | io_mem_read[io_index][i] | |
3605 | = (mem_read[i] ? mem_read[i] : unassigned_mem_read[i]); | |
3606 | } | |
3607 | for (i = 0; i < 3; ++i) { | |
3608 | io_mem_write[io_index][i] | |
3609 | = (mem_write[i] ? mem_write[i] : unassigned_mem_write[i]); | |
3610 | } | |
3611 | io_mem_opaque[io_index] = opaque; | |
3612 | ||
3613 | switch (endian) { | |
3614 | case DEVICE_BIG_ENDIAN: | |
3615 | #ifndef TARGET_WORDS_BIGENDIAN | |
3616 | swapendian_init(io_index); | |
3617 | #endif | |
3618 | break; | |
3619 | case DEVICE_LITTLE_ENDIAN: | |
3620 | #ifdef TARGET_WORDS_BIGENDIAN | |
3621 | swapendian_init(io_index); | |
3622 | #endif | |
3623 | break; | |
3624 | case DEVICE_NATIVE_ENDIAN: | |
3625 | default: | |
3626 | break; | |
3627 | } | |
3628 | ||
3629 | return (io_index << IO_MEM_SHIFT); | |
3630 | } | |
3631 | ||
3632 | int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, | |
3633 | CPUWriteMemoryFunc * const *mem_write, | |
3634 | void *opaque, enum device_endian endian) | |
3635 | { | |
3636 | return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque, endian); | |
3637 | } | |
3638 | ||
3639 | void cpu_unregister_io_memory(int io_table_address) | |
3640 | { | |
3641 | int i; | |
3642 | int io_index = io_table_address >> IO_MEM_SHIFT; | |
3643 | ||
3644 | swapendian_del(io_index); | |
3645 | ||
3646 | for (i=0;i < 3; i++) { | |
3647 | io_mem_read[io_index][i] = unassigned_mem_read[i]; | |
3648 | io_mem_write[io_index][i] = unassigned_mem_write[i]; | |
3649 | } | |
3650 | io_mem_opaque[io_index] = NULL; | |
3651 | io_mem_used[io_index] = 0; | |
3652 | } | |
3653 | ||
3654 | static void io_mem_init(void) | |
3655 | { | |
3656 | int i; | |
3657 | ||
3658 | cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, | |
3659 | unassigned_mem_write, NULL, | |
3660 | DEVICE_NATIVE_ENDIAN); | |
3661 | cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, | |
3662 | unassigned_mem_write, NULL, | |
3663 | DEVICE_NATIVE_ENDIAN); | |
3664 | cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, | |
3665 | notdirty_mem_write, NULL, | |
3666 | DEVICE_NATIVE_ENDIAN); | |
3667 | for (i=0; i<5; i++) | |
3668 | io_mem_used[i] = 1; | |
3669 | ||
3670 | io_mem_watch = cpu_register_io_memory(watch_mem_read, | |
3671 | watch_mem_write, NULL, | |
3672 | DEVICE_NATIVE_ENDIAN); | |
3673 | } | |
3674 | ||
3675 | #endif /* !defined(CONFIG_USER_ONLY) */ | |
3676 | ||
3677 | /* physical memory access (slow version, mainly for debug) */ | |
3678 | #if defined(CONFIG_USER_ONLY) | |
3679 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, | |
3680 | uint8_t *buf, int len, int is_write) | |
3681 | { | |
3682 | int l, flags; | |
3683 | target_ulong page; | |
3684 | void * p; | |
3685 | ||
3686 | while (len > 0) { | |
3687 | page = addr & TARGET_PAGE_MASK; | |
3688 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3689 | if (l > len) | |
3690 | l = len; | |
3691 | flags = page_get_flags(page); | |
3692 | if (!(flags & PAGE_VALID)) | |
3693 | return -1; | |
3694 | if (is_write) { | |
3695 | if (!(flags & PAGE_WRITE)) | |
3696 | return -1; | |
3697 | /* XXX: this code should not depend on lock_user */ | |
3698 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) | |
3699 | return -1; | |
3700 | memcpy(p, buf, l); | |
3701 | unlock_user(p, addr, l); | |
3702 | } else { | |
3703 | if (!(flags & PAGE_READ)) | |
3704 | return -1; | |
3705 | /* XXX: this code should not depend on lock_user */ | |
3706 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) | |
3707 | return -1; | |
3708 | memcpy(buf, p, l); | |
3709 | unlock_user(p, addr, 0); | |
3710 | } | |
3711 | len -= l; | |
3712 | buf += l; | |
3713 | addr += l; | |
3714 | } | |
3715 | return 0; | |
3716 | } | |
3717 | ||
3718 | #else | |
3719 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, | |
3720 | int len, int is_write) | |
3721 | { | |
3722 | int l, io_index; | |
3723 | uint8_t *ptr; | |
3724 | uint32_t val; | |
3725 | target_phys_addr_t page; | |
3726 | unsigned long pd; | |
3727 | PhysPageDesc *p; | |
3728 | ||
3729 | while (len > 0) { | |
3730 | page = addr & TARGET_PAGE_MASK; | |
3731 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3732 | if (l > len) | |
3733 | l = len; | |
3734 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3735 | if (!p) { | |
3736 | pd = IO_MEM_UNASSIGNED; | |
3737 | } else { | |
3738 | pd = p->phys_offset; | |
3739 | } | |
3740 | ||
3741 | if (is_write) { | |
3742 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
3743 | target_phys_addr_t addr1 = addr; | |
3744 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
3745 | if (p) | |
3746 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
3747 | /* XXX: could force cpu_single_env to NULL to avoid | |
3748 | potential bugs */ | |
3749 | if (l >= 4 && ((addr1 & 3) == 0)) { | |
3750 | /* 32 bit write access */ | |
3751 | val = ldl_p(buf); | |
3752 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val); | |
3753 | l = 4; | |
3754 | } else if (l >= 2 && ((addr1 & 1) == 0)) { | |
3755 | /* 16 bit write access */ | |
3756 | val = lduw_p(buf); | |
3757 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val); | |
3758 | l = 2; | |
3759 | } else { | |
3760 | /* 8 bit write access */ | |
3761 | val = ldub_p(buf); | |
3762 | io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val); | |
3763 | l = 1; | |
3764 | } | |
3765 | } else { | |
3766 | unsigned long addr1; | |
3767 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3768 | /* RAM case */ | |
3769 | ptr = qemu_get_ram_ptr(addr1); | |
3770 | memcpy(ptr, buf, l); | |
3771 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
3772 | /* invalidate code */ | |
3773 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
3774 | /* set dirty bit */ | |
3775 | cpu_physical_memory_set_dirty_flags( | |
3776 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
3777 | } | |
3778 | } | |
3779 | } else { | |
3780 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && | |
3781 | !(pd & IO_MEM_ROMD)) { | |
3782 | target_phys_addr_t addr1 = addr; | |
3783 | /* I/O case */ | |
3784 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
3785 | if (p) | |
3786 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
3787 | if (l >= 4 && ((addr1 & 3) == 0)) { | |
3788 | /* 32 bit read access */ | |
3789 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1); | |
3790 | stl_p(buf, val); | |
3791 | l = 4; | |
3792 | } else if (l >= 2 && ((addr1 & 1) == 0)) { | |
3793 | /* 16 bit read access */ | |
3794 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1); | |
3795 | stw_p(buf, val); | |
3796 | l = 2; | |
3797 | } else { | |
3798 | /* 8 bit read access */ | |
3799 | val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1); | |
3800 | stb_p(buf, val); | |
3801 | l = 1; | |
3802 | } | |
3803 | } else { | |
3804 | /* RAM case */ | |
3805 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + | |
3806 | (addr & ~TARGET_PAGE_MASK); | |
3807 | memcpy(buf, ptr, l); | |
3808 | } | |
3809 | } | |
3810 | len -= l; | |
3811 | buf += l; | |
3812 | addr += l; | |
3813 | } | |
3814 | } | |
3815 | ||
3816 | /* used for ROM loading : can write in RAM and ROM */ | |
3817 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, | |
3818 | const uint8_t *buf, int len) | |
3819 | { | |
3820 | int l; | |
3821 | uint8_t *ptr; | |
3822 | target_phys_addr_t page; | |
3823 | unsigned long pd; | |
3824 | PhysPageDesc *p; | |
3825 | ||
3826 | while (len > 0) { | |
3827 | page = addr & TARGET_PAGE_MASK; | |
3828 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3829 | if (l > len) | |
3830 | l = len; | |
3831 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3832 | if (!p) { | |
3833 | pd = IO_MEM_UNASSIGNED; | |
3834 | } else { | |
3835 | pd = p->phys_offset; | |
3836 | } | |
3837 | ||
3838 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM && | |
3839 | (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM && | |
3840 | !(pd & IO_MEM_ROMD)) { | |
3841 | /* do nothing */ | |
3842 | } else { | |
3843 | unsigned long addr1; | |
3844 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3845 | /* ROM/RAM case */ | |
3846 | ptr = qemu_get_ram_ptr(addr1); | |
3847 | memcpy(ptr, buf, l); | |
3848 | } | |
3849 | len -= l; | |
3850 | buf += l; | |
3851 | addr += l; | |
3852 | } | |
3853 | } | |
3854 | ||
3855 | typedef struct { | |
3856 | void *buffer; | |
3857 | target_phys_addr_t addr; | |
3858 | target_phys_addr_t len; | |
3859 | } BounceBuffer; | |
3860 | ||
3861 | static BounceBuffer bounce; | |
3862 | ||
3863 | typedef struct MapClient { | |
3864 | void *opaque; | |
3865 | void (*callback)(void *opaque); | |
3866 | QLIST_ENTRY(MapClient) link; | |
3867 | } MapClient; | |
3868 | ||
3869 | static QLIST_HEAD(map_client_list, MapClient) map_client_list | |
3870 | = QLIST_HEAD_INITIALIZER(map_client_list); | |
3871 | ||
3872 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) | |
3873 | { | |
3874 | MapClient *client = qemu_malloc(sizeof(*client)); | |
3875 | ||
3876 | client->opaque = opaque; | |
3877 | client->callback = callback; | |
3878 | QLIST_INSERT_HEAD(&map_client_list, client, link); | |
3879 | return client; | |
3880 | } | |
3881 | ||
3882 | void cpu_unregister_map_client(void *_client) | |
3883 | { | |
3884 | MapClient *client = (MapClient *)_client; | |
3885 | ||
3886 | QLIST_REMOVE(client, link); | |
3887 | qemu_free(client); | |
3888 | } | |
3889 | ||
3890 | static void cpu_notify_map_clients(void) | |
3891 | { | |
3892 | MapClient *client; | |
3893 | ||
3894 | while (!QLIST_EMPTY(&map_client_list)) { | |
3895 | client = QLIST_FIRST(&map_client_list); | |
3896 | client->callback(client->opaque); | |
3897 | cpu_unregister_map_client(client); | |
3898 | } | |
3899 | } | |
3900 | ||
3901 | /* Map a physical memory region into a host virtual address. | |
3902 | * May map a subset of the requested range, given by and returned in *plen. | |
3903 | * May return NULL if resources needed to perform the mapping are exhausted. | |
3904 | * Use only for reads OR writes - not for read-modify-write operations. | |
3905 | * Use cpu_register_map_client() to know when retrying the map operation is | |
3906 | * likely to succeed. | |
3907 | */ | |
3908 | void *cpu_physical_memory_map(target_phys_addr_t addr, | |
3909 | target_phys_addr_t *plen, | |
3910 | int is_write) | |
3911 | { | |
3912 | target_phys_addr_t len = *plen; | |
3913 | target_phys_addr_t done = 0; | |
3914 | int l; | |
3915 | uint8_t *ret = NULL; | |
3916 | uint8_t *ptr; | |
3917 | target_phys_addr_t page; | |
3918 | unsigned long pd; | |
3919 | PhysPageDesc *p; | |
3920 | unsigned long addr1; | |
3921 | ||
3922 | while (len > 0) { | |
3923 | page = addr & TARGET_PAGE_MASK; | |
3924 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3925 | if (l > len) | |
3926 | l = len; | |
3927 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3928 | if (!p) { | |
3929 | pd = IO_MEM_UNASSIGNED; | |
3930 | } else { | |
3931 | pd = p->phys_offset; | |
3932 | } | |
3933 | ||
3934 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
3935 | if (done || bounce.buffer) { | |
3936 | break; | |
3937 | } | |
3938 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE); | |
3939 | bounce.addr = addr; | |
3940 | bounce.len = l; | |
3941 | if (!is_write) { | |
3942 | cpu_physical_memory_read(addr, bounce.buffer, l); | |
3943 | } | |
3944 | ptr = bounce.buffer; | |
3945 | } else { | |
3946 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3947 | ptr = qemu_get_ram_ptr(addr1); | |
3948 | } | |
3949 | if (!done) { | |
3950 | ret = ptr; | |
3951 | } else if (ret + done != ptr) { | |
3952 | break; | |
3953 | } | |
3954 | ||
3955 | len -= l; | |
3956 | addr += l; | |
3957 | done += l; | |
3958 | } | |
3959 | *plen = done; | |
3960 | return ret; | |
3961 | } | |
3962 | ||
3963 | /* Unmaps a memory region previously mapped by cpu_physical_memory_map(). | |
3964 | * Will also mark the memory as dirty if is_write == 1. access_len gives | |
3965 | * the amount of memory that was actually read or written by the caller. | |
3966 | */ | |
3967 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, | |
3968 | int is_write, target_phys_addr_t access_len) | |
3969 | { | |
3970 | if (buffer != bounce.buffer) { | |
3971 | if (is_write) { | |
3972 | ram_addr_t addr1 = qemu_ram_addr_from_host_nofail(buffer); | |
3973 | while (access_len) { | |
3974 | unsigned l; | |
3975 | l = TARGET_PAGE_SIZE; | |
3976 | if (l > access_len) | |
3977 | l = access_len; | |
3978 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
3979 | /* invalidate code */ | |
3980 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
3981 | /* set dirty bit */ | |
3982 | cpu_physical_memory_set_dirty_flags( | |
3983 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
3984 | } | |
3985 | addr1 += l; | |
3986 | access_len -= l; | |
3987 | } | |
3988 | } | |
3989 | return; | |
3990 | } | |
3991 | if (is_write) { | |
3992 | cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len); | |
3993 | } | |
3994 | qemu_vfree(bounce.buffer); | |
3995 | bounce.buffer = NULL; | |
3996 | cpu_notify_map_clients(); | |
3997 | } | |
3998 | ||
3999 | /* warning: addr must be aligned */ | |
4000 | uint32_t ldl_phys(target_phys_addr_t addr) | |
4001 | { | |
4002 | int io_index; | |
4003 | uint8_t *ptr; | |
4004 | uint32_t val; | |
4005 | unsigned long pd; | |
4006 | PhysPageDesc *p; | |
4007 | ||
4008 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4009 | if (!p) { | |
4010 | pd = IO_MEM_UNASSIGNED; | |
4011 | } else { | |
4012 | pd = p->phys_offset; | |
4013 | } | |
4014 | ||
4015 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && | |
4016 | !(pd & IO_MEM_ROMD)) { | |
4017 | /* I/O case */ | |
4018 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
4019 | if (p) | |
4020 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
4021 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); | |
4022 | } else { | |
4023 | /* RAM case */ | |
4024 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + | |
4025 | (addr & ~TARGET_PAGE_MASK); | |
4026 | val = ldl_p(ptr); | |
4027 | } | |
4028 | return val; | |
4029 | } | |
4030 | ||
4031 | /* warning: addr must be aligned */ | |
4032 | uint64_t ldq_phys(target_phys_addr_t addr) | |
4033 | { | |
4034 | int io_index; | |
4035 | uint8_t *ptr; | |
4036 | uint64_t val; | |
4037 | unsigned long pd; | |
4038 | PhysPageDesc *p; | |
4039 | ||
4040 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4041 | if (!p) { | |
4042 | pd = IO_MEM_UNASSIGNED; | |
4043 | } else { | |
4044 | pd = p->phys_offset; | |
4045 | } | |
4046 | ||
4047 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && | |
4048 | !(pd & IO_MEM_ROMD)) { | |
4049 | /* I/O case */ | |
4050 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
4051 | if (p) | |
4052 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
4053 | #ifdef TARGET_WORDS_BIGENDIAN | |
4054 | val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32; | |
4055 | val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4); | |
4056 | #else | |
4057 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); | |
4058 | val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32; | |
4059 | #endif | |
4060 | } else { | |
4061 | /* RAM case */ | |
4062 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + | |
4063 | (addr & ~TARGET_PAGE_MASK); | |
4064 | val = ldq_p(ptr); | |
4065 | } | |
4066 | return val; | |
4067 | } | |
4068 | ||
4069 | /* XXX: optimize */ | |
4070 | uint32_t ldub_phys(target_phys_addr_t addr) | |
4071 | { | |
4072 | uint8_t val; | |
4073 | cpu_physical_memory_read(addr, &val, 1); | |
4074 | return val; | |
4075 | } | |
4076 | ||
4077 | /* warning: addr must be aligned */ | |
4078 | uint32_t lduw_phys(target_phys_addr_t addr) | |
4079 | { | |
4080 | int io_index; | |
4081 | uint8_t *ptr; | |
4082 | uint64_t val; | |
4083 | unsigned long pd; | |
4084 | PhysPageDesc *p; | |
4085 | ||
4086 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4087 | if (!p) { | |
4088 | pd = IO_MEM_UNASSIGNED; | |
4089 | } else { | |
4090 | pd = p->phys_offset; | |
4091 | } | |
4092 | ||
4093 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && | |
4094 | !(pd & IO_MEM_ROMD)) { | |
4095 | /* I/O case */ | |
4096 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
4097 | if (p) | |
4098 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
4099 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr); | |
4100 | } else { | |
4101 | /* RAM case */ | |
4102 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + | |
4103 | (addr & ~TARGET_PAGE_MASK); | |
4104 | val = lduw_p(ptr); | |
4105 | } | |
4106 | return val; | |
4107 | } | |
4108 | ||
4109 | /* warning: addr must be aligned. The ram page is not masked as dirty | |
4110 | and the code inside is not invalidated. It is useful if the dirty | |
4111 | bits are used to track modified PTEs */ | |
4112 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) | |
4113 | { | |
4114 | int io_index; | |
4115 | uint8_t *ptr; | |
4116 | unsigned long pd; | |
4117 | PhysPageDesc *p; | |
4118 | ||
4119 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4120 | if (!p) { | |
4121 | pd = IO_MEM_UNASSIGNED; | |
4122 | } else { | |
4123 | pd = p->phys_offset; | |
4124 | } | |
4125 | ||
4126 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
4127 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
4128 | if (p) | |
4129 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
4130 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); | |
4131 | } else { | |
4132 | unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
4133 | ptr = qemu_get_ram_ptr(addr1); | |
4134 | stl_p(ptr, val); | |
4135 | ||
4136 | if (unlikely(in_migration)) { | |
4137 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
4138 | /* invalidate code */ | |
4139 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
4140 | /* set dirty bit */ | |
4141 | cpu_physical_memory_set_dirty_flags( | |
4142 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
4143 | } | |
4144 | } | |
4145 | } | |
4146 | } | |
4147 | ||
4148 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) | |
4149 | { | |
4150 | int io_index; | |
4151 | uint8_t *ptr; | |
4152 | unsigned long pd; | |
4153 | PhysPageDesc *p; | |
4154 | ||
4155 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4156 | if (!p) { | |
4157 | pd = IO_MEM_UNASSIGNED; | |
4158 | } else { | |
4159 | pd = p->phys_offset; | |
4160 | } | |
4161 | ||
4162 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
4163 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
4164 | if (p) | |
4165 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
4166 | #ifdef TARGET_WORDS_BIGENDIAN | |
4167 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32); | |
4168 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val); | |
4169 | #else | |
4170 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); | |
4171 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32); | |
4172 | #endif | |
4173 | } else { | |
4174 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + | |
4175 | (addr & ~TARGET_PAGE_MASK); | |
4176 | stq_p(ptr, val); | |
4177 | } | |
4178 | } | |
4179 | ||
4180 | /* warning: addr must be aligned */ | |
4181 | void stl_phys(target_phys_addr_t addr, uint32_t val) | |
4182 | { | |
4183 | int io_index; | |
4184 | uint8_t *ptr; | |
4185 | unsigned long pd; | |
4186 | PhysPageDesc *p; | |
4187 | ||
4188 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4189 | if (!p) { | |
4190 | pd = IO_MEM_UNASSIGNED; | |
4191 | } else { | |
4192 | pd = p->phys_offset; | |
4193 | } | |
4194 | ||
4195 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
4196 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
4197 | if (p) | |
4198 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
4199 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); | |
4200 | } else { | |
4201 | unsigned long addr1; | |
4202 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
4203 | /* RAM case */ | |
4204 | ptr = qemu_get_ram_ptr(addr1); | |
4205 | stl_p(ptr, val); | |
4206 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
4207 | /* invalidate code */ | |
4208 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
4209 | /* set dirty bit */ | |
4210 | cpu_physical_memory_set_dirty_flags(addr1, | |
4211 | (0xff & ~CODE_DIRTY_FLAG)); | |
4212 | } | |
4213 | } | |
4214 | } | |
4215 | ||
4216 | /* XXX: optimize */ | |
4217 | void stb_phys(target_phys_addr_t addr, uint32_t val) | |
4218 | { | |
4219 | uint8_t v = val; | |
4220 | cpu_physical_memory_write(addr, &v, 1); | |
4221 | } | |
4222 | ||
4223 | /* warning: addr must be aligned */ | |
4224 | void stw_phys(target_phys_addr_t addr, uint32_t val) | |
4225 | { | |
4226 | int io_index; | |
4227 | uint8_t *ptr; | |
4228 | unsigned long pd; | |
4229 | PhysPageDesc *p; | |
4230 | ||
4231 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4232 | if (!p) { | |
4233 | pd = IO_MEM_UNASSIGNED; | |
4234 | } else { | |
4235 | pd = p->phys_offset; | |
4236 | } | |
4237 | ||
4238 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
4239 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
4240 | if (p) | |
4241 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
4242 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val); | |
4243 | } else { | |
4244 | unsigned long addr1; | |
4245 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
4246 | /* RAM case */ | |
4247 | ptr = qemu_get_ram_ptr(addr1); | |
4248 | stw_p(ptr, val); | |
4249 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
4250 | /* invalidate code */ | |
4251 | tb_invalidate_phys_page_range(addr1, addr1 + 2, 0); | |
4252 | /* set dirty bit */ | |
4253 | cpu_physical_memory_set_dirty_flags(addr1, | |
4254 | (0xff & ~CODE_DIRTY_FLAG)); | |
4255 | } | |
4256 | } | |
4257 | } | |
4258 | ||
4259 | /* XXX: optimize */ | |
4260 | void stq_phys(target_phys_addr_t addr, uint64_t val) | |
4261 | { | |
4262 | val = tswap64(val); | |
4263 | cpu_physical_memory_write(addr, &val, 8); | |
4264 | } | |
4265 | ||
4266 | /* virtual memory access for debug (includes writing to ROM) */ | |
4267 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, | |
4268 | uint8_t *buf, int len, int is_write) | |
4269 | { | |
4270 | int l; | |
4271 | target_phys_addr_t phys_addr; | |
4272 | target_ulong page; | |
4273 | ||
4274 | while (len > 0) { | |
4275 | page = addr & TARGET_PAGE_MASK; | |
4276 | phys_addr = cpu_get_phys_page_debug(env, page); | |
4277 | /* if no physical page mapped, return an error */ | |
4278 | if (phys_addr == -1) | |
4279 | return -1; | |
4280 | l = (page + TARGET_PAGE_SIZE) - addr; | |
4281 | if (l > len) | |
4282 | l = len; | |
4283 | phys_addr += (addr & ~TARGET_PAGE_MASK); | |
4284 | if (is_write) | |
4285 | cpu_physical_memory_write_rom(phys_addr, buf, l); | |
4286 | else | |
4287 | cpu_physical_memory_rw(phys_addr, buf, l, is_write); | |
4288 | len -= l; | |
4289 | buf += l; | |
4290 | addr += l; | |
4291 | } | |
4292 | return 0; | |
4293 | } | |
4294 | #endif | |
4295 | ||
4296 | /* in deterministic execution mode, instructions doing device I/Os | |
4297 | must be at the end of the TB */ | |
4298 | void cpu_io_recompile(CPUState *env, void *retaddr) | |
4299 | { | |
4300 | TranslationBlock *tb; | |
4301 | uint32_t n, cflags; | |
4302 | target_ulong pc, cs_base; | |
4303 | uint64_t flags; | |
4304 | ||
4305 | tb = tb_find_pc((unsigned long)retaddr); | |
4306 | if (!tb) { | |
4307 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", | |
4308 | retaddr); | |
4309 | } | |
4310 | n = env->icount_decr.u16.low + tb->icount; | |
4311 | cpu_restore_state(tb, env, (unsigned long)retaddr); | |
4312 | /* Calculate how many instructions had been executed before the fault | |
4313 | occurred. */ | |
4314 | n = n - env->icount_decr.u16.low; | |
4315 | /* Generate a new TB ending on the I/O insn. */ | |
4316 | n++; | |
4317 | /* On MIPS and SH, delay slot instructions can only be restarted if | |
4318 | they were already the first instruction in the TB. If this is not | |
4319 | the first instruction in a TB then re-execute the preceding | |
4320 | branch. */ | |
4321 | #if defined(TARGET_MIPS) | |
4322 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { | |
4323 | env->active_tc.PC -= 4; | |
4324 | env->icount_decr.u16.low++; | |
4325 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
4326 | } | |
4327 | #elif defined(TARGET_SH4) | |
4328 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 | |
4329 | && n > 1) { | |
4330 | env->pc -= 2; | |
4331 | env->icount_decr.u16.low++; | |
4332 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); | |
4333 | } | |
4334 | #endif | |
4335 | /* This should never happen. */ | |
4336 | if (n > CF_COUNT_MASK) | |
4337 | cpu_abort(env, "TB too big during recompile"); | |
4338 | ||
4339 | cflags = n | CF_LAST_IO; | |
4340 | pc = tb->pc; | |
4341 | cs_base = tb->cs_base; | |
4342 | flags = tb->flags; | |
4343 | tb_phys_invalidate(tb, -1); | |
4344 | /* FIXME: In theory this could raise an exception. In practice | |
4345 | we have already translated the block once so it's probably ok. */ | |
4346 | tb_gen_code(env, pc, cs_base, flags, cflags); | |
4347 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not | |
4348 | the first in the TB) then we end up generating a whole new TB and | |
4349 | repeating the fault, which is horribly inefficient. | |
4350 | Better would be to execute just this insn uncached, or generate a | |
4351 | second new TB. */ | |
4352 | cpu_resume_from_signal(env, NULL); | |
4353 | } | |
4354 | ||
4355 | #if !defined(CONFIG_USER_ONLY) | |
4356 | ||
4357 | void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) | |
4358 | { | |
4359 | int i, target_code_size, max_target_code_size; | |
4360 | int direct_jmp_count, direct_jmp2_count, cross_page; | |
4361 | TranslationBlock *tb; | |
4362 | ||
4363 | target_code_size = 0; | |
4364 | max_target_code_size = 0; | |
4365 | cross_page = 0; | |
4366 | direct_jmp_count = 0; | |
4367 | direct_jmp2_count = 0; | |
4368 | for(i = 0; i < nb_tbs; i++) { | |
4369 | tb = &tbs[i]; | |
4370 | target_code_size += tb->size; | |
4371 | if (tb->size > max_target_code_size) | |
4372 | max_target_code_size = tb->size; | |
4373 | if (tb->page_addr[1] != -1) | |
4374 | cross_page++; | |
4375 | if (tb->tb_next_offset[0] != 0xffff) { | |
4376 | direct_jmp_count++; | |
4377 | if (tb->tb_next_offset[1] != 0xffff) { | |
4378 | direct_jmp2_count++; | |
4379 | } | |
4380 | } | |
4381 | } | |
4382 | /* XXX: avoid using doubles ? */ | |
4383 | cpu_fprintf(f, "Translation buffer state:\n"); | |
4384 | cpu_fprintf(f, "gen code size %td/%ld\n", | |
4385 | code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size); | |
4386 | cpu_fprintf(f, "TB count %d/%d\n", | |
4387 | nb_tbs, code_gen_max_blocks); | |
4388 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", | |
4389 | nb_tbs ? target_code_size / nb_tbs : 0, | |
4390 | max_target_code_size); | |
4391 | cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)\n", | |
4392 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0, | |
4393 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0); | |
4394 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", | |
4395 | cross_page, | |
4396 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); | |
4397 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", | |
4398 | direct_jmp_count, | |
4399 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, | |
4400 | direct_jmp2_count, | |
4401 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); | |
4402 | cpu_fprintf(f, "\nStatistics:\n"); | |
4403 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); | |
4404 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); | |
4405 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); | |
4406 | tcg_dump_info(f, cpu_fprintf); | |
4407 | } | |
4408 | ||
4409 | #define MMUSUFFIX _cmmu | |
4410 | #define GETPC() NULL | |
4411 | #define env cpu_single_env | |
4412 | #define SOFTMMU_CODE_ACCESS | |
4413 | ||
4414 | #define SHIFT 0 | |
4415 | #include "softmmu_template.h" | |
4416 | ||
4417 | #define SHIFT 1 | |
4418 | #include "softmmu_template.h" | |
4419 | ||
4420 | #define SHIFT 2 | |
4421 | #include "softmmu_template.h" | |
4422 | ||
4423 | #define SHIFT 3 | |
4424 | #include "softmmu_template.h" | |
4425 | ||
4426 | #undef env | |
4427 | ||
4428 | #endif |