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1 | /* | |
2 | * QEMU Sparc Sun4m ECC memory controller emulation | |
3 | * | |
4 | * Copyright (c) 2007 Robert Reif | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "sysbus.h" | |
26 | #include "trace.h" | |
27 | ||
28 | /* There are 3 versions of this chip used in SMP sun4m systems: | |
29 | * MCC (version 0, implementation 0) SS-600MP | |
30 | * EMC (version 0, implementation 1) SS-10 | |
31 | * SMC (version 0, implementation 2) SS-10SX and SS-20 | |
32 | * | |
33 | * Chipset docs: | |
34 | * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01, | |
35 | * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf | |
36 | */ | |
37 | ||
38 | #define ECC_MCC 0x00000000 | |
39 | #define ECC_EMC 0x10000000 | |
40 | #define ECC_SMC 0x20000000 | |
41 | ||
42 | /* Register indexes */ | |
43 | #define ECC_MER 0 /* Memory Enable Register */ | |
44 | #define ECC_MDR 1 /* Memory Delay Register */ | |
45 | #define ECC_MFSR 2 /* Memory Fault Status Register */ | |
46 | #define ECC_VCR 3 /* Video Configuration Register */ | |
47 | #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */ | |
48 | #define ECC_MFAR1 5 /* Memory Fault Address Register 1 */ | |
49 | #define ECC_DR 6 /* Diagnostic Register */ | |
50 | #define ECC_ECR0 7 /* Event Count Register 0 */ | |
51 | #define ECC_ECR1 8 /* Event Count Register 1 */ | |
52 | ||
53 | /* ECC fault control register */ | |
54 | #define ECC_MER_EE 0x00000001 /* Enable ECC checking */ | |
55 | #define ECC_MER_EI 0x00000002 /* Enable Interrupts on | |
56 | correctable errors */ | |
57 | #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */ | |
58 | #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */ | |
59 | #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */ | |
60 | #define ECC_MER_MRR3 0x00000020 /* SIMM 3 */ | |
61 | #define ECC_MER_MRR4 0x00000040 /* SIMM 4 */ | |
62 | #define ECC_MER_MRR5 0x00000080 /* SIMM 5 */ | |
63 | #define ECC_MER_MRR6 0x00000100 /* SIMM 6 */ | |
64 | #define ECC_MER_MRR7 0x00000200 /* SIMM 7 */ | |
65 | #define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */ | |
66 | #define ECC_MER_MRR 0x000003fc /* MRR mask */ | |
67 | #define ECC_MER_A 0x00000400 /* Memory controller addr map select */ | |
68 | #define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */ | |
69 | #define ECC_MER_VER 0x0f000000 /* Version */ | |
70 | #define ECC_MER_IMPL 0xf0000000 /* Implementation */ | |
71 | #define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */ | |
72 | #define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */ | |
73 | #define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */ | |
74 | ||
75 | /* ECC memory delay register */ | |
76 | #define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */ | |
77 | #define ECC_MDR_MI 0x00001c00 /* MIH Delay */ | |
78 | #define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */ | |
79 | #define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */ | |
80 | #define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */ | |
81 | #define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */ | |
82 | #define ECC_MDR_RSC 0x80000000 /* Refresh load control */ | |
83 | #define ECC_MDR_MASK 0x7fffffff | |
84 | ||
85 | /* ECC fault status register */ | |
86 | #define ECC_MFSR_CE 0x00000001 /* Correctable error */ | |
87 | #define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */ | |
88 | #define ECC_MFSR_TO 0x00000004 /* Timeout on write */ | |
89 | #define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */ | |
90 | #define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */ | |
91 | #define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */ | |
92 | #define ECC_MFSR_ME 0x00010000 /* Multiple errors */ | |
93 | #define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */ | |
94 | ||
95 | /* ECC fault address register 0 */ | |
96 | #define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */ | |
97 | #define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */ | |
98 | #define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */ | |
99 | #define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */ | |
100 | #define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */ | |
101 | #define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */ | |
102 | #define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */ | |
103 | #define ECC_MFAR0_S 0x08000000 /* Supervisor mode */ | |
104 | #define ECC_MFARO_MID 0xf0000000 /* Module ID */ | |
105 | ||
106 | /* ECC diagnostic register */ | |
107 | #define ECC_DR_CBX 0x00000001 | |
108 | #define ECC_DR_CB0 0x00000002 | |
109 | #define ECC_DR_CB1 0x00000004 | |
110 | #define ECC_DR_CB2 0x00000008 | |
111 | #define ECC_DR_CB4 0x00000010 | |
112 | #define ECC_DR_CB8 0x00000020 | |
113 | #define ECC_DR_CB16 0x00000040 | |
114 | #define ECC_DR_CB32 0x00000080 | |
115 | #define ECC_DR_DMODE 0x00000c00 | |
116 | ||
117 | #define ECC_NREGS 9 | |
118 | #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t)) | |
119 | ||
120 | #define ECC_DIAG_SIZE 4 | |
121 | #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1) | |
122 | ||
123 | typedef struct ECCState { | |
124 | SysBusDevice busdev; | |
125 | qemu_irq irq; | |
126 | uint32_t regs[ECC_NREGS]; | |
127 | uint8_t diag[ECC_DIAG_SIZE]; | |
128 | uint32_t version; | |
129 | } ECCState; | |
130 | ||
131 | static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) | |
132 | { | |
133 | ECCState *s = opaque; | |
134 | ||
135 | switch (addr >> 2) { | |
136 | case ECC_MER: | |
137 | if (s->version == ECC_MCC) | |
138 | s->regs[ECC_MER] = (val & ECC_MER_MASK_0); | |
139 | else if (s->version == ECC_EMC) | |
140 | s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1); | |
141 | else if (s->version == ECC_SMC) | |
142 | s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2); | |
143 | trace_ecc_mem_writel_mer(val); | |
144 | break; | |
145 | case ECC_MDR: | |
146 | s->regs[ECC_MDR] = val & ECC_MDR_MASK; | |
147 | trace_ecc_mem_writel_mdr(val); | |
148 | break; | |
149 | case ECC_MFSR: | |
150 | s->regs[ECC_MFSR] = val; | |
151 | qemu_irq_lower(s->irq); | |
152 | trace_ecc_mem_writel_mfsr(val); | |
153 | break; | |
154 | case ECC_VCR: | |
155 | s->regs[ECC_VCR] = val; | |
156 | trace_ecc_mem_writel_vcr(val); | |
157 | break; | |
158 | case ECC_DR: | |
159 | s->regs[ECC_DR] = val; | |
160 | trace_ecc_mem_writel_dr(val); | |
161 | break; | |
162 | case ECC_ECR0: | |
163 | s->regs[ECC_ECR0] = val; | |
164 | trace_ecc_mem_writel_ecr0(val); | |
165 | break; | |
166 | case ECC_ECR1: | |
167 | s->regs[ECC_ECR0] = val; | |
168 | trace_ecc_mem_writel_ecr1(val); | |
169 | break; | |
170 | } | |
171 | } | |
172 | ||
173 | static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr) | |
174 | { | |
175 | ECCState *s = opaque; | |
176 | uint32_t ret = 0; | |
177 | ||
178 | switch (addr >> 2) { | |
179 | case ECC_MER: | |
180 | ret = s->regs[ECC_MER]; | |
181 | trace_ecc_mem_readl_mer(ret); | |
182 | break; | |
183 | case ECC_MDR: | |
184 | ret = s->regs[ECC_MDR]; | |
185 | trace_ecc_mem_readl_mdr(ret); | |
186 | break; | |
187 | case ECC_MFSR: | |
188 | ret = s->regs[ECC_MFSR]; | |
189 | trace_ecc_mem_readl_mfsr(ret); | |
190 | break; | |
191 | case ECC_VCR: | |
192 | ret = s->regs[ECC_VCR]; | |
193 | trace_ecc_mem_readl_vcr(ret); | |
194 | break; | |
195 | case ECC_MFAR0: | |
196 | ret = s->regs[ECC_MFAR0]; | |
197 | trace_ecc_mem_readl_mfar0(ret); | |
198 | break; | |
199 | case ECC_MFAR1: | |
200 | ret = s->regs[ECC_MFAR1]; | |
201 | trace_ecc_mem_readl_mfar1(ret); | |
202 | break; | |
203 | case ECC_DR: | |
204 | ret = s->regs[ECC_DR]; | |
205 | trace_ecc_mem_readl_dr(ret); | |
206 | break; | |
207 | case ECC_ECR0: | |
208 | ret = s->regs[ECC_ECR0]; | |
209 | trace_ecc_mem_readl_ecr0(ret); | |
210 | break; | |
211 | case ECC_ECR1: | |
212 | ret = s->regs[ECC_ECR0]; | |
213 | trace_ecc_mem_readl_ecr1(ret); | |
214 | break; | |
215 | } | |
216 | return ret; | |
217 | } | |
218 | ||
219 | static CPUReadMemoryFunc * const ecc_mem_read[3] = { | |
220 | NULL, | |
221 | NULL, | |
222 | ecc_mem_readl, | |
223 | }; | |
224 | ||
225 | static CPUWriteMemoryFunc * const ecc_mem_write[3] = { | |
226 | NULL, | |
227 | NULL, | |
228 | ecc_mem_writel, | |
229 | }; | |
230 | ||
231 | static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr, | |
232 | uint32_t val) | |
233 | { | |
234 | ECCState *s = opaque; | |
235 | ||
236 | trace_ecc_diag_mem_writeb(addr, val); | |
237 | s->diag[addr & ECC_DIAG_MASK] = val; | |
238 | } | |
239 | ||
240 | static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr) | |
241 | { | |
242 | ECCState *s = opaque; | |
243 | uint32_t ret = s->diag[(int)addr]; | |
244 | ||
245 | trace_ecc_diag_mem_readb(addr, ret); | |
246 | return ret; | |
247 | } | |
248 | ||
249 | static CPUReadMemoryFunc * const ecc_diag_mem_read[3] = { | |
250 | ecc_diag_mem_readb, | |
251 | NULL, | |
252 | NULL, | |
253 | }; | |
254 | ||
255 | static CPUWriteMemoryFunc * const ecc_diag_mem_write[3] = { | |
256 | ecc_diag_mem_writeb, | |
257 | NULL, | |
258 | NULL, | |
259 | }; | |
260 | ||
261 | static const VMStateDescription vmstate_ecc = { | |
262 | .name ="ECC", | |
263 | .version_id = 3, | |
264 | .minimum_version_id = 3, | |
265 | .minimum_version_id_old = 3, | |
266 | .fields = (VMStateField []) { | |
267 | VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS), | |
268 | VMSTATE_BUFFER(diag, ECCState), | |
269 | VMSTATE_UINT32(version, ECCState), | |
270 | VMSTATE_END_OF_LIST() | |
271 | } | |
272 | }; | |
273 | ||
274 | static void ecc_reset(DeviceState *d) | |
275 | { | |
276 | ECCState *s = container_of(d, ECCState, busdev.qdev); | |
277 | ||
278 | if (s->version == ECC_MCC) | |
279 | s->regs[ECC_MER] &= ECC_MER_REU; | |
280 | else | |
281 | s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR | | |
282 | ECC_MER_DCI); | |
283 | s->regs[ECC_MDR] = 0x20; | |
284 | s->regs[ECC_MFSR] = 0; | |
285 | s->regs[ECC_VCR] = 0; | |
286 | s->regs[ECC_MFAR0] = 0x07c00000; | |
287 | s->regs[ECC_MFAR1] = 0; | |
288 | s->regs[ECC_DR] = 0; | |
289 | s->regs[ECC_ECR0] = 0; | |
290 | s->regs[ECC_ECR1] = 0; | |
291 | } | |
292 | ||
293 | static int ecc_init1(SysBusDevice *dev) | |
294 | { | |
295 | int ecc_io_memory; | |
296 | ECCState *s = FROM_SYSBUS(ECCState, dev); | |
297 | ||
298 | sysbus_init_irq(dev, &s->irq); | |
299 | s->regs[0] = s->version; | |
300 | ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s, | |
301 | DEVICE_NATIVE_ENDIAN); | |
302 | sysbus_init_mmio(dev, ECC_SIZE, ecc_io_memory); | |
303 | ||
304 | if (s->version == ECC_MCC) { // SS-600MP only | |
305 | ecc_io_memory = cpu_register_io_memory(ecc_diag_mem_read, | |
306 | ecc_diag_mem_write, s, | |
307 | DEVICE_NATIVE_ENDIAN); | |
308 | sysbus_init_mmio(dev, ECC_DIAG_SIZE, ecc_io_memory); | |
309 | } | |
310 | ||
311 | return 0; | |
312 | } | |
313 | ||
314 | static SysBusDeviceInfo ecc_info = { | |
315 | .init = ecc_init1, | |
316 | .qdev.name = "eccmemctl", | |
317 | .qdev.size = sizeof(ECCState), | |
318 | .qdev.vmsd = &vmstate_ecc, | |
319 | .qdev.reset = ecc_reset, | |
320 | .qdev.props = (Property[]) { | |
321 | DEFINE_PROP_HEX32("version", ECCState, version, -1), | |
322 | DEFINE_PROP_END_OF_LIST(), | |
323 | } | |
324 | }; | |
325 | ||
326 | ||
327 | static void ecc_register_devices(void) | |
328 | { | |
329 | sysbus_register_withprop(&ecc_info); | |
330 | } | |
331 | ||
332 | device_init(ecc_register_devices) |