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1 | /* | |
2 | * QEMU GT64120 PCI host | |
3 | * | |
4 | * Copyright (c) 2006,2007 Aurelien Jarno | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "hw.h" | |
26 | #include "mips.h" | |
27 | #include "pci/pci.h" | |
28 | #include "pci/pci_host.h" | |
29 | #include "pc.h" | |
30 | #include "exec-memory.h" | |
31 | ||
32 | //#define DEBUG | |
33 | ||
34 | #ifdef DEBUG | |
35 | #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) | |
36 | #else | |
37 | #define DPRINTF(fmt, ...) | |
38 | #endif | |
39 | ||
40 | #define GT_REGS (0x1000 >> 2) | |
41 | ||
42 | /* CPU Configuration */ | |
43 | #define GT_CPU (0x000 >> 2) | |
44 | #define GT_MULTI (0x120 >> 2) | |
45 | ||
46 | /* CPU Address Decode */ | |
47 | #define GT_SCS10LD (0x008 >> 2) | |
48 | #define GT_SCS10HD (0x010 >> 2) | |
49 | #define GT_SCS32LD (0x018 >> 2) | |
50 | #define GT_SCS32HD (0x020 >> 2) | |
51 | #define GT_CS20LD (0x028 >> 2) | |
52 | #define GT_CS20HD (0x030 >> 2) | |
53 | #define GT_CS3BOOTLD (0x038 >> 2) | |
54 | #define GT_CS3BOOTHD (0x040 >> 2) | |
55 | #define GT_PCI0IOLD (0x048 >> 2) | |
56 | #define GT_PCI0IOHD (0x050 >> 2) | |
57 | #define GT_PCI0M0LD (0x058 >> 2) | |
58 | #define GT_PCI0M0HD (0x060 >> 2) | |
59 | #define GT_PCI0M1LD (0x080 >> 2) | |
60 | #define GT_PCI0M1HD (0x088 >> 2) | |
61 | #define GT_PCI1IOLD (0x090 >> 2) | |
62 | #define GT_PCI1IOHD (0x098 >> 2) | |
63 | #define GT_PCI1M0LD (0x0a0 >> 2) | |
64 | #define GT_PCI1M0HD (0x0a8 >> 2) | |
65 | #define GT_PCI1M1LD (0x0b0 >> 2) | |
66 | #define GT_PCI1M1HD (0x0b8 >> 2) | |
67 | #define GT_ISD (0x068 >> 2) | |
68 | ||
69 | #define GT_SCS10AR (0x0d0 >> 2) | |
70 | #define GT_SCS32AR (0x0d8 >> 2) | |
71 | #define GT_CS20R (0x0e0 >> 2) | |
72 | #define GT_CS3BOOTR (0x0e8 >> 2) | |
73 | ||
74 | #define GT_PCI0IOREMAP (0x0f0 >> 2) | |
75 | #define GT_PCI0M0REMAP (0x0f8 >> 2) | |
76 | #define GT_PCI0M1REMAP (0x100 >> 2) | |
77 | #define GT_PCI1IOREMAP (0x108 >> 2) | |
78 | #define GT_PCI1M0REMAP (0x110 >> 2) | |
79 | #define GT_PCI1M1REMAP (0x118 >> 2) | |
80 | ||
81 | /* CPU Error Report */ | |
82 | #define GT_CPUERR_ADDRLO (0x070 >> 2) | |
83 | #define GT_CPUERR_ADDRHI (0x078 >> 2) | |
84 | #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */ | |
85 | #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */ | |
86 | #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */ | |
87 | ||
88 | /* CPU Sync Barrier */ | |
89 | #define GT_PCI0SYNC (0x0c0 >> 2) | |
90 | #define GT_PCI1SYNC (0x0c8 >> 2) | |
91 | ||
92 | /* SDRAM and Device Address Decode */ | |
93 | #define GT_SCS0LD (0x400 >> 2) | |
94 | #define GT_SCS0HD (0x404 >> 2) | |
95 | #define GT_SCS1LD (0x408 >> 2) | |
96 | #define GT_SCS1HD (0x40c >> 2) | |
97 | #define GT_SCS2LD (0x410 >> 2) | |
98 | #define GT_SCS2HD (0x414 >> 2) | |
99 | #define GT_SCS3LD (0x418 >> 2) | |
100 | #define GT_SCS3HD (0x41c >> 2) | |
101 | #define GT_CS0LD (0x420 >> 2) | |
102 | #define GT_CS0HD (0x424 >> 2) | |
103 | #define GT_CS1LD (0x428 >> 2) | |
104 | #define GT_CS1HD (0x42c >> 2) | |
105 | #define GT_CS2LD (0x430 >> 2) | |
106 | #define GT_CS2HD (0x434 >> 2) | |
107 | #define GT_CS3LD (0x438 >> 2) | |
108 | #define GT_CS3HD (0x43c >> 2) | |
109 | #define GT_BOOTLD (0x440 >> 2) | |
110 | #define GT_BOOTHD (0x444 >> 2) | |
111 | #define GT_ADERR (0x470 >> 2) | |
112 | ||
113 | /* SDRAM Configuration */ | |
114 | #define GT_SDRAM_CFG (0x448 >> 2) | |
115 | #define GT_SDRAM_OPMODE (0x474 >> 2) | |
116 | #define GT_SDRAM_BM (0x478 >> 2) | |
117 | #define GT_SDRAM_ADDRDECODE (0x47c >> 2) | |
118 | ||
119 | /* SDRAM Parameters */ | |
120 | #define GT_SDRAM_B0 (0x44c >> 2) | |
121 | #define GT_SDRAM_B1 (0x450 >> 2) | |
122 | #define GT_SDRAM_B2 (0x454 >> 2) | |
123 | #define GT_SDRAM_B3 (0x458 >> 2) | |
124 | ||
125 | /* Device Parameters */ | |
126 | #define GT_DEV_B0 (0x45c >> 2) | |
127 | #define GT_DEV_B1 (0x460 >> 2) | |
128 | #define GT_DEV_B2 (0x464 >> 2) | |
129 | #define GT_DEV_B3 (0x468 >> 2) | |
130 | #define GT_DEV_BOOT (0x46c >> 2) | |
131 | ||
132 | /* ECC */ | |
133 | #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */ | |
134 | #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */ | |
135 | #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */ | |
136 | #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */ | |
137 | #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */ | |
138 | ||
139 | /* DMA Record */ | |
140 | #define GT_DMA0_CNT (0x800 >> 2) | |
141 | #define GT_DMA1_CNT (0x804 >> 2) | |
142 | #define GT_DMA2_CNT (0x808 >> 2) | |
143 | #define GT_DMA3_CNT (0x80c >> 2) | |
144 | #define GT_DMA0_SA (0x810 >> 2) | |
145 | #define GT_DMA1_SA (0x814 >> 2) | |
146 | #define GT_DMA2_SA (0x818 >> 2) | |
147 | #define GT_DMA3_SA (0x81c >> 2) | |
148 | #define GT_DMA0_DA (0x820 >> 2) | |
149 | #define GT_DMA1_DA (0x824 >> 2) | |
150 | #define GT_DMA2_DA (0x828 >> 2) | |
151 | #define GT_DMA3_DA (0x82c >> 2) | |
152 | #define GT_DMA0_NEXT (0x830 >> 2) | |
153 | #define GT_DMA1_NEXT (0x834 >> 2) | |
154 | #define GT_DMA2_NEXT (0x838 >> 2) | |
155 | #define GT_DMA3_NEXT (0x83c >> 2) | |
156 | #define GT_DMA0_CUR (0x870 >> 2) | |
157 | #define GT_DMA1_CUR (0x874 >> 2) | |
158 | #define GT_DMA2_CUR (0x878 >> 2) | |
159 | #define GT_DMA3_CUR (0x87c >> 2) | |
160 | ||
161 | /* DMA Channel Control */ | |
162 | #define GT_DMA0_CTRL (0x840 >> 2) | |
163 | #define GT_DMA1_CTRL (0x844 >> 2) | |
164 | #define GT_DMA2_CTRL (0x848 >> 2) | |
165 | #define GT_DMA3_CTRL (0x84c >> 2) | |
166 | ||
167 | /* DMA Arbiter */ | |
168 | #define GT_DMA_ARB (0x860 >> 2) | |
169 | ||
170 | /* Timer/Counter */ | |
171 | #define GT_TC0 (0x850 >> 2) | |
172 | #define GT_TC1 (0x854 >> 2) | |
173 | #define GT_TC2 (0x858 >> 2) | |
174 | #define GT_TC3 (0x85c >> 2) | |
175 | #define GT_TC_CONTROL (0x864 >> 2) | |
176 | ||
177 | /* PCI Internal */ | |
178 | #define GT_PCI0_CMD (0xc00 >> 2) | |
179 | #define GT_PCI0_TOR (0xc04 >> 2) | |
180 | #define GT_PCI0_BS_SCS10 (0xc08 >> 2) | |
181 | #define GT_PCI0_BS_SCS32 (0xc0c >> 2) | |
182 | #define GT_PCI0_BS_CS20 (0xc10 >> 2) | |
183 | #define GT_PCI0_BS_CS3BT (0xc14 >> 2) | |
184 | #define GT_PCI1_IACK (0xc30 >> 2) | |
185 | #define GT_PCI0_IACK (0xc34 >> 2) | |
186 | #define GT_PCI0_BARE (0xc3c >> 2) | |
187 | #define GT_PCI0_PREFMBR (0xc40 >> 2) | |
188 | #define GT_PCI0_SCS10_BAR (0xc48 >> 2) | |
189 | #define GT_PCI0_SCS32_BAR (0xc4c >> 2) | |
190 | #define GT_PCI0_CS20_BAR (0xc50 >> 2) | |
191 | #define GT_PCI0_CS3BT_BAR (0xc54 >> 2) | |
192 | #define GT_PCI0_SSCS10_BAR (0xc58 >> 2) | |
193 | #define GT_PCI0_SSCS32_BAR (0xc5c >> 2) | |
194 | #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2) | |
195 | #define GT_PCI1_CMD (0xc80 >> 2) | |
196 | #define GT_PCI1_TOR (0xc84 >> 2) | |
197 | #define GT_PCI1_BS_SCS10 (0xc88 >> 2) | |
198 | #define GT_PCI1_BS_SCS32 (0xc8c >> 2) | |
199 | #define GT_PCI1_BS_CS20 (0xc90 >> 2) | |
200 | #define GT_PCI1_BS_CS3BT (0xc94 >> 2) | |
201 | #define GT_PCI1_BARE (0xcbc >> 2) | |
202 | #define GT_PCI1_PREFMBR (0xcc0 >> 2) | |
203 | #define GT_PCI1_SCS10_BAR (0xcc8 >> 2) | |
204 | #define GT_PCI1_SCS32_BAR (0xccc >> 2) | |
205 | #define GT_PCI1_CS20_BAR (0xcd0 >> 2) | |
206 | #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2) | |
207 | #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2) | |
208 | #define GT_PCI1_SSCS32_BAR (0xcdc >> 2) | |
209 | #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2) | |
210 | #define GT_PCI1_CFGADDR (0xcf0 >> 2) | |
211 | #define GT_PCI1_CFGDATA (0xcf4 >> 2) | |
212 | #define GT_PCI0_CFGADDR (0xcf8 >> 2) | |
213 | #define GT_PCI0_CFGDATA (0xcfc >> 2) | |
214 | ||
215 | /* Interrupts */ | |
216 | #define GT_INTRCAUSE (0xc18 >> 2) | |
217 | #define GT_INTRMASK (0xc1c >> 2) | |
218 | #define GT_PCI0_ICMASK (0xc24 >> 2) | |
219 | #define GT_PCI0_SERR0MASK (0xc28 >> 2) | |
220 | #define GT_CPU_INTSEL (0xc70 >> 2) | |
221 | #define GT_PCI0_INTSEL (0xc74 >> 2) | |
222 | #define GT_HINTRCAUSE (0xc98 >> 2) | |
223 | #define GT_HINTRMASK (0xc9c >> 2) | |
224 | #define GT_PCI0_HICMASK (0xca4 >> 2) | |
225 | #define GT_PCI1_SERR1MASK (0xca8 >> 2) | |
226 | ||
227 | #define PCI_MAPPING_ENTRY(regname) \ | |
228 | hwaddr regname ##_start; \ | |
229 | hwaddr regname ##_length; \ | |
230 | MemoryRegion regname ##_mem | |
231 | ||
232 | #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120" | |
233 | ||
234 | #define GT64120_PCI_HOST_BRIDGE(obj) \ | |
235 | OBJECT_CHECK(GT64120State, (obj), TYPE_GT64120_PCI_HOST_BRIDGE) | |
236 | ||
237 | typedef struct GT64120State { | |
238 | PCIHostState parent_obj; | |
239 | ||
240 | uint32_t regs[GT_REGS]; | |
241 | PCI_MAPPING_ENTRY(PCI0IO); | |
242 | PCI_MAPPING_ENTRY(ISD); | |
243 | } GT64120State; | |
244 | ||
245 | /* Adjust range to avoid touching space which isn't mappable via PCI */ | |
246 | /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000 | |
247 | 0x1fc00000 - 0x1fd00000 */ | |
248 | static void check_reserved_space (hwaddr *start, | |
249 | hwaddr *length) | |
250 | { | |
251 | hwaddr begin = *start; | |
252 | hwaddr end = *start + *length; | |
253 | ||
254 | if (end >= 0x1e000000LL && end < 0x1f100000LL) | |
255 | end = 0x1e000000LL; | |
256 | if (begin >= 0x1e000000LL && begin < 0x1f100000LL) | |
257 | begin = 0x1f100000LL; | |
258 | if (end >= 0x1fc00000LL && end < 0x1fd00000LL) | |
259 | end = 0x1fc00000LL; | |
260 | if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) | |
261 | begin = 0x1fd00000LL; | |
262 | /* XXX: This is broken when a reserved range splits the requested range */ | |
263 | if (end >= 0x1f100000LL && begin < 0x1e000000LL) | |
264 | end = 0x1e000000LL; | |
265 | if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) | |
266 | end = 0x1fc00000LL; | |
267 | ||
268 | *start = begin; | |
269 | *length = end - begin; | |
270 | } | |
271 | ||
272 | static void gt64120_isd_mapping(GT64120State *s) | |
273 | { | |
274 | hwaddr start = s->regs[GT_ISD] << 21; | |
275 | hwaddr length = 0x1000; | |
276 | ||
277 | if (s->ISD_length) { | |
278 | memory_region_del_subregion(get_system_memory(), &s->ISD_mem); | |
279 | } | |
280 | check_reserved_space(&start, &length); | |
281 | length = 0x1000; | |
282 | /* Map new address */ | |
283 | DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx | |
284 | " -> "TARGET_FMT_plx"@"TARGET_FMT_plx"\n", | |
285 | s->ISD_length, s->ISD_start, length, start); | |
286 | s->ISD_start = start; | |
287 | s->ISD_length = length; | |
288 | memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem); | |
289 | } | |
290 | ||
291 | static void gt64120_pci_mapping(GT64120State *s) | |
292 | { | |
293 | /* Update IO mapping */ | |
294 | if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) | |
295 | { | |
296 | /* Unmap old IO address */ | |
297 | if (s->PCI0IO_length) | |
298 | { | |
299 | memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem); | |
300 | memory_region_destroy(&s->PCI0IO_mem); | |
301 | } | |
302 | /* Map new IO address */ | |
303 | s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21; | |
304 | s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; | |
305 | isa_mem_base = s->PCI0IO_start; | |
306 | if (s->PCI0IO_length) { | |
307 | isa_mmio_setup(&s->PCI0IO_mem, s->PCI0IO_length); | |
308 | memory_region_add_subregion(get_system_memory(), s->PCI0IO_start, | |
309 | &s->PCI0IO_mem); | |
310 | } | |
311 | } | |
312 | } | |
313 | ||
314 | static void gt64120_writel (void *opaque, hwaddr addr, | |
315 | uint64_t val, unsigned size) | |
316 | { | |
317 | GT64120State *s = opaque; | |
318 | PCIHostState *phb = PCI_HOST_BRIDGE(s); | |
319 | uint32_t saddr; | |
320 | ||
321 | if (!(s->regs[GT_CPU] & 0x00001000)) | |
322 | val = bswap32(val); | |
323 | ||
324 | saddr = (addr & 0xfff) >> 2; | |
325 | switch (saddr) { | |
326 | ||
327 | /* CPU Configuration */ | |
328 | case GT_CPU: | |
329 | s->regs[GT_CPU] = val; | |
330 | break; | |
331 | case GT_MULTI: | |
332 | /* Read-only register as only one GT64xxx is present on the CPU bus */ | |
333 | break; | |
334 | ||
335 | /* CPU Address Decode */ | |
336 | case GT_PCI0IOLD: | |
337 | s->regs[GT_PCI0IOLD] = val & 0x00007fff; | |
338 | s->regs[GT_PCI0IOREMAP] = val & 0x000007ff; | |
339 | gt64120_pci_mapping(s); | |
340 | break; | |
341 | case GT_PCI0M0LD: | |
342 | s->regs[GT_PCI0M0LD] = val & 0x00007fff; | |
343 | s->regs[GT_PCI0M0REMAP] = val & 0x000007ff; | |
344 | break; | |
345 | case GT_PCI0M1LD: | |
346 | s->regs[GT_PCI0M1LD] = val & 0x00007fff; | |
347 | s->regs[GT_PCI0M1REMAP] = val & 0x000007ff; | |
348 | break; | |
349 | case GT_PCI1IOLD: | |
350 | s->regs[GT_PCI1IOLD] = val & 0x00007fff; | |
351 | s->regs[GT_PCI1IOREMAP] = val & 0x000007ff; | |
352 | break; | |
353 | case GT_PCI1M0LD: | |
354 | s->regs[GT_PCI1M0LD] = val & 0x00007fff; | |
355 | s->regs[GT_PCI1M0REMAP] = val & 0x000007ff; | |
356 | break; | |
357 | case GT_PCI1M1LD: | |
358 | s->regs[GT_PCI1M1LD] = val & 0x00007fff; | |
359 | s->regs[GT_PCI1M1REMAP] = val & 0x000007ff; | |
360 | break; | |
361 | case GT_PCI0IOHD: | |
362 | s->regs[saddr] = val & 0x0000007f; | |
363 | gt64120_pci_mapping(s); | |
364 | break; | |
365 | case GT_PCI0M0HD: | |
366 | case GT_PCI0M1HD: | |
367 | case GT_PCI1IOHD: | |
368 | case GT_PCI1M0HD: | |
369 | case GT_PCI1M1HD: | |
370 | s->regs[saddr] = val & 0x0000007f; | |
371 | break; | |
372 | case GT_ISD: | |
373 | s->regs[saddr] = val & 0x00007fff; | |
374 | gt64120_isd_mapping(s); | |
375 | break; | |
376 | ||
377 | case GT_PCI0IOREMAP: | |
378 | case GT_PCI0M0REMAP: | |
379 | case GT_PCI0M1REMAP: | |
380 | case GT_PCI1IOREMAP: | |
381 | case GT_PCI1M0REMAP: | |
382 | case GT_PCI1M1REMAP: | |
383 | s->regs[saddr] = val & 0x000007ff; | |
384 | break; | |
385 | ||
386 | /* CPU Error Report */ | |
387 | case GT_CPUERR_ADDRLO: | |
388 | case GT_CPUERR_ADDRHI: | |
389 | case GT_CPUERR_DATALO: | |
390 | case GT_CPUERR_DATAHI: | |
391 | case GT_CPUERR_PARITY: | |
392 | /* Read-only registers, do nothing */ | |
393 | break; | |
394 | ||
395 | /* CPU Sync Barrier */ | |
396 | case GT_PCI0SYNC: | |
397 | case GT_PCI1SYNC: | |
398 | /* Read-only registers, do nothing */ | |
399 | break; | |
400 | ||
401 | /* SDRAM and Device Address Decode */ | |
402 | case GT_SCS0LD: | |
403 | case GT_SCS0HD: | |
404 | case GT_SCS1LD: | |
405 | case GT_SCS1HD: | |
406 | case GT_SCS2LD: | |
407 | case GT_SCS2HD: | |
408 | case GT_SCS3LD: | |
409 | case GT_SCS3HD: | |
410 | case GT_CS0LD: | |
411 | case GT_CS0HD: | |
412 | case GT_CS1LD: | |
413 | case GT_CS1HD: | |
414 | case GT_CS2LD: | |
415 | case GT_CS2HD: | |
416 | case GT_CS3LD: | |
417 | case GT_CS3HD: | |
418 | case GT_BOOTLD: | |
419 | case GT_BOOTHD: | |
420 | case GT_ADERR: | |
421 | /* SDRAM Configuration */ | |
422 | case GT_SDRAM_CFG: | |
423 | case GT_SDRAM_OPMODE: | |
424 | case GT_SDRAM_BM: | |
425 | case GT_SDRAM_ADDRDECODE: | |
426 | /* Accept and ignore SDRAM interleave configuration */ | |
427 | s->regs[saddr] = val; | |
428 | break; | |
429 | ||
430 | /* Device Parameters */ | |
431 | case GT_DEV_B0: | |
432 | case GT_DEV_B1: | |
433 | case GT_DEV_B2: | |
434 | case GT_DEV_B3: | |
435 | case GT_DEV_BOOT: | |
436 | /* Not implemented */ | |
437 | DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2); | |
438 | break; | |
439 | ||
440 | /* ECC */ | |
441 | case GT_ECC_ERRDATALO: | |
442 | case GT_ECC_ERRDATAHI: | |
443 | case GT_ECC_MEM: | |
444 | case GT_ECC_CALC: | |
445 | case GT_ECC_ERRADDR: | |
446 | /* Read-only registers, do nothing */ | |
447 | break; | |
448 | ||
449 | /* DMA Record */ | |
450 | case GT_DMA0_CNT: | |
451 | case GT_DMA1_CNT: | |
452 | case GT_DMA2_CNT: | |
453 | case GT_DMA3_CNT: | |
454 | case GT_DMA0_SA: | |
455 | case GT_DMA1_SA: | |
456 | case GT_DMA2_SA: | |
457 | case GT_DMA3_SA: | |
458 | case GT_DMA0_DA: | |
459 | case GT_DMA1_DA: | |
460 | case GT_DMA2_DA: | |
461 | case GT_DMA3_DA: | |
462 | case GT_DMA0_NEXT: | |
463 | case GT_DMA1_NEXT: | |
464 | case GT_DMA2_NEXT: | |
465 | case GT_DMA3_NEXT: | |
466 | case GT_DMA0_CUR: | |
467 | case GT_DMA1_CUR: | |
468 | case GT_DMA2_CUR: | |
469 | case GT_DMA3_CUR: | |
470 | /* Not implemented */ | |
471 | DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); | |
472 | break; | |
473 | ||
474 | /* DMA Channel Control */ | |
475 | case GT_DMA0_CTRL: | |
476 | case GT_DMA1_CTRL: | |
477 | case GT_DMA2_CTRL: | |
478 | case GT_DMA3_CTRL: | |
479 | /* Not implemented */ | |
480 | DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); | |
481 | break; | |
482 | ||
483 | /* DMA Arbiter */ | |
484 | case GT_DMA_ARB: | |
485 | /* Not implemented */ | |
486 | DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); | |
487 | break; | |
488 | ||
489 | /* Timer/Counter */ | |
490 | case GT_TC0: | |
491 | case GT_TC1: | |
492 | case GT_TC2: | |
493 | case GT_TC3: | |
494 | case GT_TC_CONTROL: | |
495 | /* Not implemented */ | |
496 | DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2); | |
497 | break; | |
498 | ||
499 | /* PCI Internal */ | |
500 | case GT_PCI0_CMD: | |
501 | case GT_PCI1_CMD: | |
502 | s->regs[saddr] = val & 0x0401fc0f; | |
503 | break; | |
504 | case GT_PCI0_TOR: | |
505 | case GT_PCI0_BS_SCS10: | |
506 | case GT_PCI0_BS_SCS32: | |
507 | case GT_PCI0_BS_CS20: | |
508 | case GT_PCI0_BS_CS3BT: | |
509 | case GT_PCI1_IACK: | |
510 | case GT_PCI0_IACK: | |
511 | case GT_PCI0_BARE: | |
512 | case GT_PCI0_PREFMBR: | |
513 | case GT_PCI0_SCS10_BAR: | |
514 | case GT_PCI0_SCS32_BAR: | |
515 | case GT_PCI0_CS20_BAR: | |
516 | case GT_PCI0_CS3BT_BAR: | |
517 | case GT_PCI0_SSCS10_BAR: | |
518 | case GT_PCI0_SSCS32_BAR: | |
519 | case GT_PCI0_SCS3BT_BAR: | |
520 | case GT_PCI1_TOR: | |
521 | case GT_PCI1_BS_SCS10: | |
522 | case GT_PCI1_BS_SCS32: | |
523 | case GT_PCI1_BS_CS20: | |
524 | case GT_PCI1_BS_CS3BT: | |
525 | case GT_PCI1_BARE: | |
526 | case GT_PCI1_PREFMBR: | |
527 | case GT_PCI1_SCS10_BAR: | |
528 | case GT_PCI1_SCS32_BAR: | |
529 | case GT_PCI1_CS20_BAR: | |
530 | case GT_PCI1_CS3BT_BAR: | |
531 | case GT_PCI1_SSCS10_BAR: | |
532 | case GT_PCI1_SSCS32_BAR: | |
533 | case GT_PCI1_SCS3BT_BAR: | |
534 | case GT_PCI1_CFGADDR: | |
535 | case GT_PCI1_CFGDATA: | |
536 | /* not implemented */ | |
537 | break; | |
538 | case GT_PCI0_CFGADDR: | |
539 | phb->config_reg = val & 0x80fffffc; | |
540 | break; | |
541 | case GT_PCI0_CFGDATA: | |
542 | if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) { | |
543 | val = bswap32(val); | |
544 | } | |
545 | if (phb->config_reg & (1u << 31)) { | |
546 | pci_data_write(phb->bus, phb->config_reg, val, 4); | |
547 | } | |
548 | break; | |
549 | ||
550 | /* Interrupts */ | |
551 | case GT_INTRCAUSE: | |
552 | /* not really implemented */ | |
553 | s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); | |
554 | s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe); | |
555 | DPRINTF("INTRCAUSE %" PRIx64 "\n", val); | |
556 | break; | |
557 | case GT_INTRMASK: | |
558 | s->regs[saddr] = val & 0x3c3ffffe; | |
559 | DPRINTF("INTRMASK %" PRIx64 "\n", val); | |
560 | break; | |
561 | case GT_PCI0_ICMASK: | |
562 | s->regs[saddr] = val & 0x03fffffe; | |
563 | DPRINTF("ICMASK %" PRIx64 "\n", val); | |
564 | break; | |
565 | case GT_PCI0_SERR0MASK: | |
566 | s->regs[saddr] = val & 0x0000003f; | |
567 | DPRINTF("SERR0MASK %" PRIx64 "\n", val); | |
568 | break; | |
569 | ||
570 | /* Reserved when only PCI_0 is configured. */ | |
571 | case GT_HINTRCAUSE: | |
572 | case GT_CPU_INTSEL: | |
573 | case GT_PCI0_INTSEL: | |
574 | case GT_HINTRMASK: | |
575 | case GT_PCI0_HICMASK: | |
576 | case GT_PCI1_SERR1MASK: | |
577 | /* not implemented */ | |
578 | break; | |
579 | ||
580 | /* SDRAM Parameters */ | |
581 | case GT_SDRAM_B0: | |
582 | case GT_SDRAM_B1: | |
583 | case GT_SDRAM_B2: | |
584 | case GT_SDRAM_B3: | |
585 | /* We don't simulate electrical parameters of the SDRAM. | |
586 | Accept, but ignore the values. */ | |
587 | s->regs[saddr] = val; | |
588 | break; | |
589 | ||
590 | default: | |
591 | DPRINTF ("Bad register offset 0x%x\n", (int)addr); | |
592 | break; | |
593 | } | |
594 | } | |
595 | ||
596 | static uint64_t gt64120_readl (void *opaque, | |
597 | hwaddr addr, unsigned size) | |
598 | { | |
599 | GT64120State *s = opaque; | |
600 | PCIHostState *phb = PCI_HOST_BRIDGE(s); | |
601 | uint32_t val; | |
602 | uint32_t saddr; | |
603 | ||
604 | saddr = (addr & 0xfff) >> 2; | |
605 | switch (saddr) { | |
606 | ||
607 | /* CPU Configuration */ | |
608 | case GT_MULTI: | |
609 | /* Only one GT64xxx is present on the CPU bus, return | |
610 | the initial value */ | |
611 | val = s->regs[saddr]; | |
612 | break; | |
613 | ||
614 | /* CPU Error Report */ | |
615 | case GT_CPUERR_ADDRLO: | |
616 | case GT_CPUERR_ADDRHI: | |
617 | case GT_CPUERR_DATALO: | |
618 | case GT_CPUERR_DATAHI: | |
619 | case GT_CPUERR_PARITY: | |
620 | /* Emulated memory has no error, always return the initial | |
621 | values */ | |
622 | val = s->regs[saddr]; | |
623 | break; | |
624 | ||
625 | /* CPU Sync Barrier */ | |
626 | case GT_PCI0SYNC: | |
627 | case GT_PCI1SYNC: | |
628 | /* Reading those register should empty all FIFO on the PCI | |
629 | bus, which are not emulated. The return value should be | |
630 | a random value that should be ignored. */ | |
631 | val = 0xc000ffee; | |
632 | break; | |
633 | ||
634 | /* ECC */ | |
635 | case GT_ECC_ERRDATALO: | |
636 | case GT_ECC_ERRDATAHI: | |
637 | case GT_ECC_MEM: | |
638 | case GT_ECC_CALC: | |
639 | case GT_ECC_ERRADDR: | |
640 | /* Emulated memory has no error, always return the initial | |
641 | values */ | |
642 | val = s->regs[saddr]; | |
643 | break; | |
644 | ||
645 | case GT_CPU: | |
646 | case GT_SCS10LD: | |
647 | case GT_SCS10HD: | |
648 | case GT_SCS32LD: | |
649 | case GT_SCS32HD: | |
650 | case GT_CS20LD: | |
651 | case GT_CS20HD: | |
652 | case GT_CS3BOOTLD: | |
653 | case GT_CS3BOOTHD: | |
654 | case GT_SCS10AR: | |
655 | case GT_SCS32AR: | |
656 | case GT_CS20R: | |
657 | case GT_CS3BOOTR: | |
658 | case GT_PCI0IOLD: | |
659 | case GT_PCI0M0LD: | |
660 | case GT_PCI0M1LD: | |
661 | case GT_PCI1IOLD: | |
662 | case GT_PCI1M0LD: | |
663 | case GT_PCI1M1LD: | |
664 | case GT_PCI0IOHD: | |
665 | case GT_PCI0M0HD: | |
666 | case GT_PCI0M1HD: | |
667 | case GT_PCI1IOHD: | |
668 | case GT_PCI1M0HD: | |
669 | case GT_PCI1M1HD: | |
670 | case GT_PCI0IOREMAP: | |
671 | case GT_PCI0M0REMAP: | |
672 | case GT_PCI0M1REMAP: | |
673 | case GT_PCI1IOREMAP: | |
674 | case GT_PCI1M0REMAP: | |
675 | case GT_PCI1M1REMAP: | |
676 | case GT_ISD: | |
677 | val = s->regs[saddr]; | |
678 | break; | |
679 | case GT_PCI0_IACK: | |
680 | /* Read the IRQ number */ | |
681 | val = pic_read_irq(isa_pic); | |
682 | break; | |
683 | ||
684 | /* SDRAM and Device Address Decode */ | |
685 | case GT_SCS0LD: | |
686 | case GT_SCS0HD: | |
687 | case GT_SCS1LD: | |
688 | case GT_SCS1HD: | |
689 | case GT_SCS2LD: | |
690 | case GT_SCS2HD: | |
691 | case GT_SCS3LD: | |
692 | case GT_SCS3HD: | |
693 | case GT_CS0LD: | |
694 | case GT_CS0HD: | |
695 | case GT_CS1LD: | |
696 | case GT_CS1HD: | |
697 | case GT_CS2LD: | |
698 | case GT_CS2HD: | |
699 | case GT_CS3LD: | |
700 | case GT_CS3HD: | |
701 | case GT_BOOTLD: | |
702 | case GT_BOOTHD: | |
703 | case GT_ADERR: | |
704 | val = s->regs[saddr]; | |
705 | break; | |
706 | ||
707 | /* SDRAM Configuration */ | |
708 | case GT_SDRAM_CFG: | |
709 | case GT_SDRAM_OPMODE: | |
710 | case GT_SDRAM_BM: | |
711 | case GT_SDRAM_ADDRDECODE: | |
712 | val = s->regs[saddr]; | |
713 | break; | |
714 | ||
715 | /* SDRAM Parameters */ | |
716 | case GT_SDRAM_B0: | |
717 | case GT_SDRAM_B1: | |
718 | case GT_SDRAM_B2: | |
719 | case GT_SDRAM_B3: | |
720 | /* We don't simulate electrical parameters of the SDRAM. | |
721 | Just return the last written value. */ | |
722 | val = s->regs[saddr]; | |
723 | break; | |
724 | ||
725 | /* Device Parameters */ | |
726 | case GT_DEV_B0: | |
727 | case GT_DEV_B1: | |
728 | case GT_DEV_B2: | |
729 | case GT_DEV_B3: | |
730 | case GT_DEV_BOOT: | |
731 | val = s->regs[saddr]; | |
732 | break; | |
733 | ||
734 | /* DMA Record */ | |
735 | case GT_DMA0_CNT: | |
736 | case GT_DMA1_CNT: | |
737 | case GT_DMA2_CNT: | |
738 | case GT_DMA3_CNT: | |
739 | case GT_DMA0_SA: | |
740 | case GT_DMA1_SA: | |
741 | case GT_DMA2_SA: | |
742 | case GT_DMA3_SA: | |
743 | case GT_DMA0_DA: | |
744 | case GT_DMA1_DA: | |
745 | case GT_DMA2_DA: | |
746 | case GT_DMA3_DA: | |
747 | case GT_DMA0_NEXT: | |
748 | case GT_DMA1_NEXT: | |
749 | case GT_DMA2_NEXT: | |
750 | case GT_DMA3_NEXT: | |
751 | case GT_DMA0_CUR: | |
752 | case GT_DMA1_CUR: | |
753 | case GT_DMA2_CUR: | |
754 | case GT_DMA3_CUR: | |
755 | val = s->regs[saddr]; | |
756 | break; | |
757 | ||
758 | /* DMA Channel Control */ | |
759 | case GT_DMA0_CTRL: | |
760 | case GT_DMA1_CTRL: | |
761 | case GT_DMA2_CTRL: | |
762 | case GT_DMA3_CTRL: | |
763 | val = s->regs[saddr]; | |
764 | break; | |
765 | ||
766 | /* DMA Arbiter */ | |
767 | case GT_DMA_ARB: | |
768 | val = s->regs[saddr]; | |
769 | break; | |
770 | ||
771 | /* Timer/Counter */ | |
772 | case GT_TC0: | |
773 | case GT_TC1: | |
774 | case GT_TC2: | |
775 | case GT_TC3: | |
776 | case GT_TC_CONTROL: | |
777 | val = s->regs[saddr]; | |
778 | break; | |
779 | ||
780 | /* PCI Internal */ | |
781 | case GT_PCI0_CFGADDR: | |
782 | val = phb->config_reg; | |
783 | break; | |
784 | case GT_PCI0_CFGDATA: | |
785 | if (!(phb->config_reg & (1 << 31))) { | |
786 | val = 0xffffffff; | |
787 | } else { | |
788 | val = pci_data_read(phb->bus, phb->config_reg, 4); | |
789 | } | |
790 | if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) { | |
791 | val = bswap32(val); | |
792 | } | |
793 | break; | |
794 | ||
795 | case GT_PCI0_CMD: | |
796 | case GT_PCI0_TOR: | |
797 | case GT_PCI0_BS_SCS10: | |
798 | case GT_PCI0_BS_SCS32: | |
799 | case GT_PCI0_BS_CS20: | |
800 | case GT_PCI0_BS_CS3BT: | |
801 | case GT_PCI1_IACK: | |
802 | case GT_PCI0_BARE: | |
803 | case GT_PCI0_PREFMBR: | |
804 | case GT_PCI0_SCS10_BAR: | |
805 | case GT_PCI0_SCS32_BAR: | |
806 | case GT_PCI0_CS20_BAR: | |
807 | case GT_PCI0_CS3BT_BAR: | |
808 | case GT_PCI0_SSCS10_BAR: | |
809 | case GT_PCI0_SSCS32_BAR: | |
810 | case GT_PCI0_SCS3BT_BAR: | |
811 | case GT_PCI1_CMD: | |
812 | case GT_PCI1_TOR: | |
813 | case GT_PCI1_BS_SCS10: | |
814 | case GT_PCI1_BS_SCS32: | |
815 | case GT_PCI1_BS_CS20: | |
816 | case GT_PCI1_BS_CS3BT: | |
817 | case GT_PCI1_BARE: | |
818 | case GT_PCI1_PREFMBR: | |
819 | case GT_PCI1_SCS10_BAR: | |
820 | case GT_PCI1_SCS32_BAR: | |
821 | case GT_PCI1_CS20_BAR: | |
822 | case GT_PCI1_CS3BT_BAR: | |
823 | case GT_PCI1_SSCS10_BAR: | |
824 | case GT_PCI1_SSCS32_BAR: | |
825 | case GT_PCI1_SCS3BT_BAR: | |
826 | case GT_PCI1_CFGADDR: | |
827 | case GT_PCI1_CFGDATA: | |
828 | val = s->regs[saddr]; | |
829 | break; | |
830 | ||
831 | /* Interrupts */ | |
832 | case GT_INTRCAUSE: | |
833 | val = s->regs[saddr]; | |
834 | DPRINTF("INTRCAUSE %x\n", val); | |
835 | break; | |
836 | case GT_INTRMASK: | |
837 | val = s->regs[saddr]; | |
838 | DPRINTF("INTRMASK %x\n", val); | |
839 | break; | |
840 | case GT_PCI0_ICMASK: | |
841 | val = s->regs[saddr]; | |
842 | DPRINTF("ICMASK %x\n", val); | |
843 | break; | |
844 | case GT_PCI0_SERR0MASK: | |
845 | val = s->regs[saddr]; | |
846 | DPRINTF("SERR0MASK %x\n", val); | |
847 | break; | |
848 | ||
849 | /* Reserved when only PCI_0 is configured. */ | |
850 | case GT_HINTRCAUSE: | |
851 | case GT_CPU_INTSEL: | |
852 | case GT_PCI0_INTSEL: | |
853 | case GT_HINTRMASK: | |
854 | case GT_PCI0_HICMASK: | |
855 | case GT_PCI1_SERR1MASK: | |
856 | val = s->regs[saddr]; | |
857 | break; | |
858 | ||
859 | default: | |
860 | val = s->regs[saddr]; | |
861 | DPRINTF ("Bad register offset 0x%x\n", (int)addr); | |
862 | break; | |
863 | } | |
864 | ||
865 | if (!(s->regs[GT_CPU] & 0x00001000)) | |
866 | val = bswap32(val); | |
867 | ||
868 | return val; | |
869 | } | |
870 | ||
871 | static const MemoryRegionOps isd_mem_ops = { | |
872 | .read = gt64120_readl, | |
873 | .write = gt64120_writel, | |
874 | .endianness = DEVICE_NATIVE_ENDIAN, | |
875 | }; | |
876 | ||
877 | static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) | |
878 | { | |
879 | int slot; | |
880 | ||
881 | slot = (pci_dev->devfn >> 3); | |
882 | ||
883 | switch (slot) { | |
884 | /* PIIX4 USB */ | |
885 | case 10: | |
886 | return 3; | |
887 | /* AMD 79C973 Ethernet */ | |
888 | case 11: | |
889 | return 1; | |
890 | /* Crystal 4281 Sound */ | |
891 | case 12: | |
892 | return 2; | |
893 | /* PCI slot 1 to 4 */ | |
894 | case 18 ... 21: | |
895 | return ((slot - 18) + irq_num) & 0x03; | |
896 | /* Unknown device, don't do any translation */ | |
897 | default: | |
898 | return irq_num; | |
899 | } | |
900 | } | |
901 | ||
902 | static int pci_irq_levels[4]; | |
903 | ||
904 | static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) | |
905 | { | |
906 | int i, pic_irq, pic_level; | |
907 | qemu_irq *pic = opaque; | |
908 | ||
909 | pci_irq_levels[irq_num] = level; | |
910 | ||
911 | /* now we change the pic irq level according to the piix irq mappings */ | |
912 | /* XXX: optimize */ | |
913 | pic_irq = piix4_dev->config[0x60 + irq_num]; | |
914 | if (pic_irq < 16) { | |
915 | /* The pic level is the logical OR of all the PCI irqs mapped | |
916 | to it */ | |
917 | pic_level = 0; | |
918 | for (i = 0; i < 4; i++) { | |
919 | if (pic_irq == piix4_dev->config[0x60 + i]) | |
920 | pic_level |= pci_irq_levels[i]; | |
921 | } | |
922 | qemu_set_irq(pic[pic_irq], pic_level); | |
923 | } | |
924 | } | |
925 | ||
926 | ||
927 | static void gt64120_reset(void *opaque) | |
928 | { | |
929 | GT64120State *s = opaque; | |
930 | ||
931 | /* FIXME: Malta specific hw assumptions ahead */ | |
932 | ||
933 | /* CPU Configuration */ | |
934 | #ifdef TARGET_WORDS_BIGENDIAN | |
935 | s->regs[GT_CPU] = 0x00000000; | |
936 | #else | |
937 | s->regs[GT_CPU] = 0x00001000; | |
938 | #endif | |
939 | s->regs[GT_MULTI] = 0x00000003; | |
940 | ||
941 | /* CPU Address decode */ | |
942 | s->regs[GT_SCS10LD] = 0x00000000; | |
943 | s->regs[GT_SCS10HD] = 0x00000007; | |
944 | s->regs[GT_SCS32LD] = 0x00000008; | |
945 | s->regs[GT_SCS32HD] = 0x0000000f; | |
946 | s->regs[GT_CS20LD] = 0x000000e0; | |
947 | s->regs[GT_CS20HD] = 0x00000070; | |
948 | s->regs[GT_CS3BOOTLD] = 0x000000f8; | |
949 | s->regs[GT_CS3BOOTHD] = 0x0000007f; | |
950 | ||
951 | s->regs[GT_PCI0IOLD] = 0x00000080; | |
952 | s->regs[GT_PCI0IOHD] = 0x0000000f; | |
953 | s->regs[GT_PCI0M0LD] = 0x00000090; | |
954 | s->regs[GT_PCI0M0HD] = 0x0000001f; | |
955 | s->regs[GT_ISD] = 0x000000a0; | |
956 | s->regs[GT_PCI0M1LD] = 0x00000790; | |
957 | s->regs[GT_PCI0M1HD] = 0x0000001f; | |
958 | s->regs[GT_PCI1IOLD] = 0x00000100; | |
959 | s->regs[GT_PCI1IOHD] = 0x0000000f; | |
960 | s->regs[GT_PCI1M0LD] = 0x00000110; | |
961 | s->regs[GT_PCI1M0HD] = 0x0000001f; | |
962 | s->regs[GT_PCI1M1LD] = 0x00000120; | |
963 | s->regs[GT_PCI1M1HD] = 0x0000002f; | |
964 | ||
965 | s->regs[GT_SCS10AR] = 0x00000000; | |
966 | s->regs[GT_SCS32AR] = 0x00000008; | |
967 | s->regs[GT_CS20R] = 0x000000e0; | |
968 | s->regs[GT_CS3BOOTR] = 0x000000f8; | |
969 | ||
970 | s->regs[GT_PCI0IOREMAP] = 0x00000080; | |
971 | s->regs[GT_PCI0M0REMAP] = 0x00000090; | |
972 | s->regs[GT_PCI0M1REMAP] = 0x00000790; | |
973 | s->regs[GT_PCI1IOREMAP] = 0x00000100; | |
974 | s->regs[GT_PCI1M0REMAP] = 0x00000110; | |
975 | s->regs[GT_PCI1M1REMAP] = 0x00000120; | |
976 | ||
977 | /* CPU Error Report */ | |
978 | s->regs[GT_CPUERR_ADDRLO] = 0x00000000; | |
979 | s->regs[GT_CPUERR_ADDRHI] = 0x00000000; | |
980 | s->regs[GT_CPUERR_DATALO] = 0xffffffff; | |
981 | s->regs[GT_CPUERR_DATAHI] = 0xffffffff; | |
982 | s->regs[GT_CPUERR_PARITY] = 0x000000ff; | |
983 | ||
984 | /* CPU Sync Barrier */ | |
985 | s->regs[GT_PCI0SYNC] = 0x00000000; | |
986 | s->regs[GT_PCI1SYNC] = 0x00000000; | |
987 | ||
988 | /* SDRAM and Device Address Decode */ | |
989 | s->regs[GT_SCS0LD] = 0x00000000; | |
990 | s->regs[GT_SCS0HD] = 0x00000007; | |
991 | s->regs[GT_SCS1LD] = 0x00000008; | |
992 | s->regs[GT_SCS1HD] = 0x0000000f; | |
993 | s->regs[GT_SCS2LD] = 0x00000010; | |
994 | s->regs[GT_SCS2HD] = 0x00000017; | |
995 | s->regs[GT_SCS3LD] = 0x00000018; | |
996 | s->regs[GT_SCS3HD] = 0x0000001f; | |
997 | s->regs[GT_CS0LD] = 0x000000c0; | |
998 | s->regs[GT_CS0HD] = 0x000000c7; | |
999 | s->regs[GT_CS1LD] = 0x000000c8; | |
1000 | s->regs[GT_CS1HD] = 0x000000cf; | |
1001 | s->regs[GT_CS2LD] = 0x000000d0; | |
1002 | s->regs[GT_CS2HD] = 0x000000df; | |
1003 | s->regs[GT_CS3LD] = 0x000000f0; | |
1004 | s->regs[GT_CS3HD] = 0x000000fb; | |
1005 | s->regs[GT_BOOTLD] = 0x000000fc; | |
1006 | s->regs[GT_BOOTHD] = 0x000000ff; | |
1007 | s->regs[GT_ADERR] = 0xffffffff; | |
1008 | ||
1009 | /* SDRAM Configuration */ | |
1010 | s->regs[GT_SDRAM_CFG] = 0x00000200; | |
1011 | s->regs[GT_SDRAM_OPMODE] = 0x00000000; | |
1012 | s->regs[GT_SDRAM_BM] = 0x00000007; | |
1013 | s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002; | |
1014 | ||
1015 | /* SDRAM Parameters */ | |
1016 | s->regs[GT_SDRAM_B0] = 0x00000005; | |
1017 | s->regs[GT_SDRAM_B1] = 0x00000005; | |
1018 | s->regs[GT_SDRAM_B2] = 0x00000005; | |
1019 | s->regs[GT_SDRAM_B3] = 0x00000005; | |
1020 | ||
1021 | /* ECC */ | |
1022 | s->regs[GT_ECC_ERRDATALO] = 0x00000000; | |
1023 | s->regs[GT_ECC_ERRDATAHI] = 0x00000000; | |
1024 | s->regs[GT_ECC_MEM] = 0x00000000; | |
1025 | s->regs[GT_ECC_CALC] = 0x00000000; | |
1026 | s->regs[GT_ECC_ERRADDR] = 0x00000000; | |
1027 | ||
1028 | /* Device Parameters */ | |
1029 | s->regs[GT_DEV_B0] = 0x386fffff; | |
1030 | s->regs[GT_DEV_B1] = 0x386fffff; | |
1031 | s->regs[GT_DEV_B2] = 0x386fffff; | |
1032 | s->regs[GT_DEV_B3] = 0x386fffff; | |
1033 | s->regs[GT_DEV_BOOT] = 0x146fffff; | |
1034 | ||
1035 | /* DMA registers are all zeroed at reset */ | |
1036 | ||
1037 | /* Timer/Counter */ | |
1038 | s->regs[GT_TC0] = 0xffffffff; | |
1039 | s->regs[GT_TC1] = 0x00ffffff; | |
1040 | s->regs[GT_TC2] = 0x00ffffff; | |
1041 | s->regs[GT_TC3] = 0x00ffffff; | |
1042 | s->regs[GT_TC_CONTROL] = 0x00000000; | |
1043 | ||
1044 | /* PCI Internal */ | |
1045 | #ifdef TARGET_WORDS_BIGENDIAN | |
1046 | s->regs[GT_PCI0_CMD] = 0x00000000; | |
1047 | #else | |
1048 | s->regs[GT_PCI0_CMD] = 0x00010001; | |
1049 | #endif | |
1050 | s->regs[GT_PCI0_TOR] = 0x0000070f; | |
1051 | s->regs[GT_PCI0_BS_SCS10] = 0x00fff000; | |
1052 | s->regs[GT_PCI0_BS_SCS32] = 0x00fff000; | |
1053 | s->regs[GT_PCI0_BS_CS20] = 0x01fff000; | |
1054 | s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000; | |
1055 | s->regs[GT_PCI1_IACK] = 0x00000000; | |
1056 | s->regs[GT_PCI0_IACK] = 0x00000000; | |
1057 | s->regs[GT_PCI0_BARE] = 0x0000000f; | |
1058 | s->regs[GT_PCI0_PREFMBR] = 0x00000040; | |
1059 | s->regs[GT_PCI0_SCS10_BAR] = 0x00000000; | |
1060 | s->regs[GT_PCI0_SCS32_BAR] = 0x01000000; | |
1061 | s->regs[GT_PCI0_CS20_BAR] = 0x1c000000; | |
1062 | s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000; | |
1063 | s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000; | |
1064 | s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000; | |
1065 | s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000; | |
1066 | #ifdef TARGET_WORDS_BIGENDIAN | |
1067 | s->regs[GT_PCI1_CMD] = 0x00000000; | |
1068 | #else | |
1069 | s->regs[GT_PCI1_CMD] = 0x00010001; | |
1070 | #endif | |
1071 | s->regs[GT_PCI1_TOR] = 0x0000070f; | |
1072 | s->regs[GT_PCI1_BS_SCS10] = 0x00fff000; | |
1073 | s->regs[GT_PCI1_BS_SCS32] = 0x00fff000; | |
1074 | s->regs[GT_PCI1_BS_CS20] = 0x01fff000; | |
1075 | s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000; | |
1076 | s->regs[GT_PCI1_BARE] = 0x0000000f; | |
1077 | s->regs[GT_PCI1_PREFMBR] = 0x00000040; | |
1078 | s->regs[GT_PCI1_SCS10_BAR] = 0x00000000; | |
1079 | s->regs[GT_PCI1_SCS32_BAR] = 0x01000000; | |
1080 | s->regs[GT_PCI1_CS20_BAR] = 0x1c000000; | |
1081 | s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000; | |
1082 | s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000; | |
1083 | s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000; | |
1084 | s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000; | |
1085 | s->regs[GT_PCI1_CFGADDR] = 0x00000000; | |
1086 | s->regs[GT_PCI1_CFGDATA] = 0x00000000; | |
1087 | s->regs[GT_PCI0_CFGADDR] = 0x00000000; | |
1088 | ||
1089 | /* Interrupt registers are all zeroed at reset */ | |
1090 | ||
1091 | gt64120_isd_mapping(s); | |
1092 | gt64120_pci_mapping(s); | |
1093 | } | |
1094 | ||
1095 | PCIBus *gt64120_register(qemu_irq *pic) | |
1096 | { | |
1097 | GT64120State *d; | |
1098 | PCIHostState *phb; | |
1099 | DeviceState *dev; | |
1100 | ||
1101 | dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE); | |
1102 | qdev_init_nofail(dev); | |
1103 | d = GT64120_PCI_HOST_BRIDGE(dev); | |
1104 | phb = PCI_HOST_BRIDGE(dev); | |
1105 | phb->bus = pci_register_bus(dev, "pci", | |
1106 | gt64120_pci_set_irq, gt64120_pci_map_irq, | |
1107 | pic, | |
1108 | get_system_memory(), | |
1109 | get_system_io(), | |
1110 | PCI_DEVFN(18, 0), 4); | |
1111 | memory_region_init_io(&d->ISD_mem, &isd_mem_ops, d, "isd-mem", 0x1000); | |
1112 | ||
1113 | pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci"); | |
1114 | return phb->bus; | |
1115 | } | |
1116 | ||
1117 | static int gt64120_init(SysBusDevice *dev) | |
1118 | { | |
1119 | GT64120State *s; | |
1120 | ||
1121 | s = GT64120_PCI_HOST_BRIDGE(dev); | |
1122 | ||
1123 | /* FIXME: This value is computed from registers during reset, but some | |
1124 | devices (e.g. VGA card) need to know it when they are registered. | |
1125 | This also mean that changing the register to change the mapping | |
1126 | does not fully work. */ | |
1127 | isa_mem_base = 0x10000000; | |
1128 | qemu_register_reset(gt64120_reset, s); | |
1129 | return 0; | |
1130 | } | |
1131 | ||
1132 | static int gt64120_pci_init(PCIDevice *d) | |
1133 | { | |
1134 | /* FIXME: Malta specific hw assumptions ahead */ | |
1135 | pci_set_word(d->config + PCI_COMMAND, 0); | |
1136 | pci_set_word(d->config + PCI_STATUS, | |
1137 | PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); | |
1138 | pci_config_set_prog_interface(d->config, 0); | |
1139 | pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); | |
1140 | pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); | |
1141 | pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); | |
1142 | pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000); | |
1143 | pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000); | |
1144 | pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001); | |
1145 | pci_set_byte(d->config + 0x3d, 0x01); | |
1146 | ||
1147 | return 0; | |
1148 | } | |
1149 | ||
1150 | static void gt64120_pci_class_init(ObjectClass *klass, void *data) | |
1151 | { | |
1152 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
1153 | ||
1154 | k->init = gt64120_pci_init; | |
1155 | k->vendor_id = PCI_VENDOR_ID_MARVELL; | |
1156 | k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X; | |
1157 | k->revision = 0x10; | |
1158 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
1159 | } | |
1160 | ||
1161 | static const TypeInfo gt64120_pci_info = { | |
1162 | .name = "gt64120_pci", | |
1163 | .parent = TYPE_PCI_DEVICE, | |
1164 | .instance_size = sizeof(PCIDevice), | |
1165 | .class_init = gt64120_pci_class_init, | |
1166 | }; | |
1167 | ||
1168 | static void gt64120_class_init(ObjectClass *klass, void *data) | |
1169 | { | |
1170 | SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); | |
1171 | ||
1172 | sdc->init = gt64120_init; | |
1173 | } | |
1174 | ||
1175 | static const TypeInfo gt64120_info = { | |
1176 | .name = TYPE_GT64120_PCI_HOST_BRIDGE, | |
1177 | .parent = TYPE_PCI_HOST_BRIDGE, | |
1178 | .instance_size = sizeof(GT64120State), | |
1179 | .class_init = gt64120_class_init, | |
1180 | }; | |
1181 | ||
1182 | static void gt64120_pci_register_types(void) | |
1183 | { | |
1184 | type_register_static(>64120_info); | |
1185 | type_register_static(>64120_pci_info); | |
1186 | } | |
1187 | ||
1188 | type_init(gt64120_pci_register_types) |