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ide: Update command code definitions as per ACS-2 Table B.2
[qemu.git] / hw / ide / core.c
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1/*
2 * QEMU IDE disk and CD/DVD-ROM Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25#include <hw/hw.h>
26#include <hw/pc.h>
27#include <hw/pci.h>
28#include "qemu-error.h"
29#include "qemu-timer.h"
30#include "sysemu.h"
31#include "dma.h"
32#include "blockdev.h"
33
34#include <hw/ide/internal.h>
35
36/* These values were based on a Seagate ST3500418AS but have been modified
37 to make more sense in QEMU */
38static const int smart_attributes[][12] = {
39 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
40 /* raw read error rate*/
41 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
42 /* spin up */
43 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
44 /* start stop count */
45 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
46 /* remapped sectors */
47 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
48 /* power on hours */
49 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
50 /* power cycle count */
51 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* airflow-temperature-celsius */
53 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
54 /* end of list */
55 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
56};
57
58static int ide_handle_rw_error(IDEState *s, int error, int op);
59static void ide_dummy_transfer_stop(IDEState *s);
60
61static void padstr(char *str, const char *src, int len)
62{
63 int i, v;
64 for(i = 0; i < len; i++) {
65 if (*src)
66 v = *src++;
67 else
68 v = ' ';
69 str[i^1] = v;
70 }
71}
72
73static void put_le16(uint16_t *p, unsigned int v)
74{
75 *p = cpu_to_le16(v);
76}
77
78static void ide_identify(IDEState *s)
79{
80 uint16_t *p;
81 unsigned int oldsize;
82 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
83
84 if (s->identify_set) {
85 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
86 return;
87 }
88
89 memset(s->io_buffer, 0, 512);
90 p = (uint16_t *)s->io_buffer;
91 put_le16(p + 0, 0x0040);
92 put_le16(p + 1, s->cylinders);
93 put_le16(p + 3, s->heads);
94 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
95 put_le16(p + 5, 512); /* XXX: retired, remove ? */
96 put_le16(p + 6, s->sectors);
97 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
98 put_le16(p + 20, 3); /* XXX: retired, remove ? */
99 put_le16(p + 21, 512); /* cache size in sectors */
100 put_le16(p + 22, 4); /* ecc bytes */
101 padstr((char *)(p + 23), s->version, 8); /* firmware version */
102 padstr((char *)(p + 27), "QEMU HARDDISK", 40); /* model */
103#if MAX_MULT_SECTORS > 1
104 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
105#endif
106 put_le16(p + 48, 1); /* dword I/O */
107 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
108 put_le16(p + 51, 0x200); /* PIO transfer cycle */
109 put_le16(p + 52, 0x200); /* DMA transfer cycle */
110 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
111 put_le16(p + 54, s->cylinders);
112 put_le16(p + 55, s->heads);
113 put_le16(p + 56, s->sectors);
114 oldsize = s->cylinders * s->heads * s->sectors;
115 put_le16(p + 57, oldsize);
116 put_le16(p + 58, oldsize >> 16);
117 if (s->mult_sectors)
118 put_le16(p + 59, 0x100 | s->mult_sectors);
119 put_le16(p + 60, s->nb_sectors);
120 put_le16(p + 61, s->nb_sectors >> 16);
121 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
122 put_le16(p + 63, 0x07); /* mdma0-2 supported */
123 put_le16(p + 64, 0x03); /* pio3-4 supported */
124 put_le16(p + 65, 120);
125 put_le16(p + 66, 120);
126 put_le16(p + 67, 120);
127 put_le16(p + 68, 120);
128 if (dev && dev->conf.discard_granularity) {
129 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
130 }
131
132 if (s->ncq_queues) {
133 put_le16(p + 75, s->ncq_queues - 1);
134 /* NCQ supported */
135 put_le16(p + 76, (1 << 8));
136 }
137
138 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
139 put_le16(p + 81, 0x16); /* conforms to ata5 */
140 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
141 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
142 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
143 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
144 /* 14=set to 1, 1=SMART self test, 0=SMART error logging */
145 put_le16(p + 84, (1 << 14) | 0);
146 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
147 if (bdrv_enable_write_cache(s->bs))
148 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
149 else
150 put_le16(p + 85, (1 << 14) | 1);
151 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
152 put_le16(p + 86, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
153 /* 14=set to 1, 1=smart self test, 0=smart error logging */
154 put_le16(p + 87, (1 << 14) | 0);
155 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
156 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
157 put_le16(p + 100, s->nb_sectors);
158 put_le16(p + 101, s->nb_sectors >> 16);
159 put_le16(p + 102, s->nb_sectors >> 32);
160 put_le16(p + 103, s->nb_sectors >> 48);
161
162 if (dev && dev->conf.physical_block_size)
163 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
164 if (dev && dev->conf.discard_granularity) {
165 put_le16(p + 169, 1); /* TRIM support */
166 }
167
168 memcpy(s->identify_data, p, sizeof(s->identify_data));
169 s->identify_set = 1;
170}
171
172static void ide_atapi_identify(IDEState *s)
173{
174 uint16_t *p;
175
176 if (s->identify_set) {
177 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
178 return;
179 }
180
181 memset(s->io_buffer, 0, 512);
182 p = (uint16_t *)s->io_buffer;
183 /* Removable CDROM, 50us response, 12 byte packets */
184 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
185 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
186 put_le16(p + 20, 3); /* buffer type */
187 put_le16(p + 21, 512); /* cache size in sectors */
188 put_le16(p + 22, 4); /* ecc bytes */
189 padstr((char *)(p + 23), s->version, 8); /* firmware version */
190 padstr((char *)(p + 27), "QEMU DVD-ROM", 40); /* model */
191 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
192#ifdef USE_DMA_CDROM
193 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
194 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
195 put_le16(p + 62, 7); /* single word dma0-2 supported */
196 put_le16(p + 63, 7); /* mdma0-2 supported */
197#else
198 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
199 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
200 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
201#endif
202 put_le16(p + 64, 3); /* pio3-4 supported */
203 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
204 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
205 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
206 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
207
208 put_le16(p + 71, 30); /* in ns */
209 put_le16(p + 72, 30); /* in ns */
210
211 if (s->ncq_queues) {
212 put_le16(p + 75, s->ncq_queues - 1);
213 /* NCQ supported */
214 put_le16(p + 76, (1 << 8));
215 }
216
217 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
218#ifdef USE_DMA_CDROM
219 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
220#endif
221 memcpy(s->identify_data, p, sizeof(s->identify_data));
222 s->identify_set = 1;
223}
224
225static void ide_cfata_identify(IDEState *s)
226{
227 uint16_t *p;
228 uint32_t cur_sec;
229
230 p = (uint16_t *) s->identify_data;
231 if (s->identify_set)
232 goto fill_buffer;
233
234 memset(p, 0, sizeof(s->identify_data));
235
236 cur_sec = s->cylinders * s->heads * s->sectors;
237
238 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
239 put_le16(p + 1, s->cylinders); /* Default cylinders */
240 put_le16(p + 3, s->heads); /* Default heads */
241 put_le16(p + 6, s->sectors); /* Default sectors per track */
242 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
243 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
244 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
245 put_le16(p + 22, 0x0004); /* ECC bytes */
246 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
247 padstr((char *) (p + 27), "QEMU MICRODRIVE", 40);/* Model number */
248#if MAX_MULT_SECTORS > 1
249 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
250#else
251 put_le16(p + 47, 0x0000);
252#endif
253 put_le16(p + 49, 0x0f00); /* Capabilities */
254 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
255 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
256 put_le16(p + 53, 0x0003); /* Translation params valid */
257 put_le16(p + 54, s->cylinders); /* Current cylinders */
258 put_le16(p + 55, s->heads); /* Current heads */
259 put_le16(p + 56, s->sectors); /* Current sectors */
260 put_le16(p + 57, cur_sec); /* Current capacity */
261 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
262 if (s->mult_sectors) /* Multiple sector setting */
263 put_le16(p + 59, 0x100 | s->mult_sectors);
264 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
265 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
266 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
267 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
268 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
269 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
270 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
271 put_le16(p + 82, 0x400c); /* Command Set supported */
272 put_le16(p + 83, 0x7068); /* Command Set supported */
273 put_le16(p + 84, 0x4000); /* Features supported */
274 put_le16(p + 85, 0x000c); /* Command Set enabled */
275 put_le16(p + 86, 0x7044); /* Command Set enabled */
276 put_le16(p + 87, 0x4000); /* Features enabled */
277 put_le16(p + 91, 0x4060); /* Current APM level */
278 put_le16(p + 129, 0x0002); /* Current features option */
279 put_le16(p + 130, 0x0005); /* Reassigned sectors */
280 put_le16(p + 131, 0x0001); /* Initial power mode */
281 put_le16(p + 132, 0x0000); /* User signature */
282 put_le16(p + 160, 0x8100); /* Power requirement */
283 put_le16(p + 161, 0x8001); /* CF command set */
284
285 s->identify_set = 1;
286
287fill_buffer:
288 memcpy(s->io_buffer, p, sizeof(s->identify_data));
289}
290
291static void ide_set_signature(IDEState *s)
292{
293 s->select &= 0xf0; /* clear head */
294 /* put signature */
295 s->nsector = 1;
296 s->sector = 1;
297 if (s->drive_kind == IDE_CD) {
298 s->lcyl = 0x14;
299 s->hcyl = 0xeb;
300 } else if (s->bs) {
301 s->lcyl = 0;
302 s->hcyl = 0;
303 } else {
304 s->lcyl = 0xff;
305 s->hcyl = 0xff;
306 }
307}
308
309typedef struct TrimAIOCB {
310 BlockDriverAIOCB common;
311 QEMUBH *bh;
312 int ret;
313} TrimAIOCB;
314
315static void trim_aio_cancel(BlockDriverAIOCB *acb)
316{
317 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
318
319 qemu_bh_delete(iocb->bh);
320 iocb->bh = NULL;
321 qemu_aio_release(iocb);
322}
323
324static AIOPool trim_aio_pool = {
325 .aiocb_size = sizeof(TrimAIOCB),
326 .cancel = trim_aio_cancel,
327};
328
329static void ide_trim_bh_cb(void *opaque)
330{
331 TrimAIOCB *iocb = opaque;
332
333 iocb->common.cb(iocb->common.opaque, iocb->ret);
334
335 qemu_bh_delete(iocb->bh);
336 iocb->bh = NULL;
337
338 qemu_aio_release(iocb);
339}
340
341BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs,
342 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
343 BlockDriverCompletionFunc *cb, void *opaque)
344{
345 TrimAIOCB *iocb;
346 int i, j, ret;
347
348 iocb = qemu_aio_get(&trim_aio_pool, bs, cb, opaque);
349 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
350 iocb->ret = 0;
351
352 for (j = 0; j < qiov->niov; j++) {
353 uint64_t *buffer = qiov->iov[j].iov_base;
354
355 for (i = 0; i < qiov->iov[j].iov_len / 8; i++) {
356 /* 6-byte LBA + 2-byte range per entry */
357 uint64_t entry = le64_to_cpu(buffer[i]);
358 uint64_t sector = entry & 0x0000ffffffffffffULL;
359 uint16_t count = entry >> 48;
360
361 if (count == 0) {
362 break;
363 }
364
365 ret = bdrv_discard(bs, sector, count);
366 if (!iocb->ret) {
367 iocb->ret = ret;
368 }
369 }
370 }
371
372 qemu_bh_schedule(iocb->bh);
373
374 return &iocb->common;
375}
376
377static inline void ide_abort_command(IDEState *s)
378{
379 s->status = READY_STAT | ERR_STAT;
380 s->error = ABRT_ERR;
381}
382
383/* prepare data transfer and tell what to do after */
384void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
385 EndTransferFunc *end_transfer_func)
386{
387 s->end_transfer_func = end_transfer_func;
388 s->data_ptr = buf;
389 s->data_end = buf + size;
390 if (!(s->status & ERR_STAT)) {
391 s->status |= DRQ_STAT;
392 }
393 s->bus->dma->ops->start_transfer(s->bus->dma);
394}
395
396void ide_transfer_stop(IDEState *s)
397{
398 s->end_transfer_func = ide_transfer_stop;
399 s->data_ptr = s->io_buffer;
400 s->data_end = s->io_buffer;
401 s->status &= ~DRQ_STAT;
402}
403
404int64_t ide_get_sector(IDEState *s)
405{
406 int64_t sector_num;
407 if (s->select & 0x40) {
408 /* lba */
409 if (!s->lba48) {
410 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
411 (s->lcyl << 8) | s->sector;
412 } else {
413 sector_num = ((int64_t)s->hob_hcyl << 40) |
414 ((int64_t) s->hob_lcyl << 32) |
415 ((int64_t) s->hob_sector << 24) |
416 ((int64_t) s->hcyl << 16) |
417 ((int64_t) s->lcyl << 8) | s->sector;
418 }
419 } else {
420 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
421 (s->select & 0x0f) * s->sectors + (s->sector - 1);
422 }
423 return sector_num;
424}
425
426void ide_set_sector(IDEState *s, int64_t sector_num)
427{
428 unsigned int cyl, r;
429 if (s->select & 0x40) {
430 if (!s->lba48) {
431 s->select = (s->select & 0xf0) | (sector_num >> 24);
432 s->hcyl = (sector_num >> 16);
433 s->lcyl = (sector_num >> 8);
434 s->sector = (sector_num);
435 } else {
436 s->sector = sector_num;
437 s->lcyl = sector_num >> 8;
438 s->hcyl = sector_num >> 16;
439 s->hob_sector = sector_num >> 24;
440 s->hob_lcyl = sector_num >> 32;
441 s->hob_hcyl = sector_num >> 40;
442 }
443 } else {
444 cyl = sector_num / (s->heads * s->sectors);
445 r = sector_num % (s->heads * s->sectors);
446 s->hcyl = cyl >> 8;
447 s->lcyl = cyl;
448 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
449 s->sector = (r % s->sectors) + 1;
450 }
451}
452
453static void ide_rw_error(IDEState *s) {
454 ide_abort_command(s);
455 ide_set_irq(s->bus);
456}
457
458void ide_sector_read(IDEState *s)
459{
460 int64_t sector_num;
461 int ret, n;
462
463 s->status = READY_STAT | SEEK_STAT;
464 s->error = 0; /* not needed by IDE spec, but needed by Windows */
465 sector_num = ide_get_sector(s);
466 n = s->nsector;
467 if (n == 0) {
468 /* no more sector to read from disk */
469 ide_transfer_stop(s);
470 } else {
471#if defined(DEBUG_IDE)
472 printf("read sector=%" PRId64 "\n", sector_num);
473#endif
474 if (n > s->req_nb_sectors)
475 n = s->req_nb_sectors;
476
477 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
478 ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
479 bdrv_acct_done(s->bs, &s->acct);
480 if (ret != 0) {
481 if (ide_handle_rw_error(s, -ret,
482 BM_STATUS_PIO_RETRY | BM_STATUS_RETRY_READ))
483 {
484 return;
485 }
486 }
487 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read);
488 ide_set_irq(s->bus);
489 ide_set_sector(s, sector_num + n);
490 s->nsector -= n;
491 }
492}
493
494static void dma_buf_commit(IDEState *s, int is_write)
495{
496 qemu_sglist_destroy(&s->sg);
497}
498
499void ide_set_inactive(IDEState *s)
500{
501 s->bus->dma->aiocb = NULL;
502 s->bus->dma->ops->set_inactive(s->bus->dma);
503}
504
505void ide_dma_error(IDEState *s)
506{
507 ide_transfer_stop(s);
508 s->error = ABRT_ERR;
509 s->status = READY_STAT | ERR_STAT;
510 ide_set_inactive(s);
511 ide_set_irq(s->bus);
512}
513
514static int ide_handle_rw_error(IDEState *s, int error, int op)
515{
516 int is_read = (op & BM_STATUS_RETRY_READ);
517 BlockErrorAction action = bdrv_get_on_error(s->bs, is_read);
518
519 if (action == BLOCK_ERR_IGNORE) {
520 bdrv_mon_event(s->bs, BDRV_ACTION_IGNORE, is_read);
521 return 0;
522 }
523
524 if ((error == ENOSPC && action == BLOCK_ERR_STOP_ENOSPC)
525 || action == BLOCK_ERR_STOP_ANY) {
526 s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
527 s->bus->error_status = op;
528 bdrv_mon_event(s->bs, BDRV_ACTION_STOP, is_read);
529 vm_stop(VMSTOP_DISKFULL);
530 } else {
531 if (op & BM_STATUS_DMA_RETRY) {
532 dma_buf_commit(s, 0);
533 ide_dma_error(s);
534 } else {
535 ide_rw_error(s);
536 }
537 bdrv_mon_event(s->bs, BDRV_ACTION_REPORT, is_read);
538 }
539
540 return 1;
541}
542
543void ide_dma_cb(void *opaque, int ret)
544{
545 IDEState *s = opaque;
546 int n;
547 int64_t sector_num;
548
549handle_rw_error:
550 if (ret < 0) {
551 int op = BM_STATUS_DMA_RETRY;
552
553 if (s->dma_cmd == IDE_DMA_READ)
554 op |= BM_STATUS_RETRY_READ;
555 else if (s->dma_cmd == IDE_DMA_TRIM)
556 op |= BM_STATUS_RETRY_TRIM;
557
558 if (ide_handle_rw_error(s, -ret, op)) {
559 return;
560 }
561 }
562
563 n = s->io_buffer_size >> 9;
564 sector_num = ide_get_sector(s);
565 if (n > 0) {
566 dma_buf_commit(s, ide_cmd_is_read(s));
567 sector_num += n;
568 ide_set_sector(s, sector_num);
569 s->nsector -= n;
570 }
571
572 /* end of transfer ? */
573 if (s->nsector == 0) {
574 s->status = READY_STAT | SEEK_STAT;
575 ide_set_irq(s->bus);
576 goto eot;
577 }
578
579 /* launch next transfer */
580 n = s->nsector;
581 s->io_buffer_index = 0;
582 s->io_buffer_size = n * 512;
583 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
584 /* The PRDs were too short. Reset the Active bit, but don't raise an
585 * interrupt. */
586 goto eot;
587 }
588
589#ifdef DEBUG_AIO
590 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
591 sector_num, n, s->dma_cmd);
592#endif
593
594 switch (s->dma_cmd) {
595 case IDE_DMA_READ:
596 s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
597 ide_dma_cb, s);
598 break;
599 case IDE_DMA_WRITE:
600 s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
601 ide_dma_cb, s);
602 break;
603 case IDE_DMA_TRIM:
604 s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
605 ide_issue_trim, ide_dma_cb, s, 1);
606 break;
607 }
608
609 if (!s->bus->dma->aiocb) {
610 ret = -1;
611 goto handle_rw_error;
612 }
613 return;
614
615eot:
616 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
617 bdrv_acct_done(s->bs, &s->acct);
618 }
619 ide_set_inactive(s);
620}
621
622static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
623{
624 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
625 s->io_buffer_index = 0;
626 s->io_buffer_size = 0;
627 s->dma_cmd = dma_cmd;
628
629 switch (dma_cmd) {
630 case IDE_DMA_READ:
631 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
632 BDRV_ACCT_READ);
633 break;
634 case IDE_DMA_WRITE:
635 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
636 BDRV_ACCT_WRITE);
637 break;
638 default:
639 break;
640 }
641
642 s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb);
643}
644
645static void ide_sector_write_timer_cb(void *opaque)
646{
647 IDEState *s = opaque;
648 ide_set_irq(s->bus);
649}
650
651void ide_sector_write(IDEState *s)
652{
653 int64_t sector_num;
654 int ret, n, n1;
655
656 s->status = READY_STAT | SEEK_STAT;
657 sector_num = ide_get_sector(s);
658#if defined(DEBUG_IDE)
659 printf("write sector=%" PRId64 "\n", sector_num);
660#endif
661 n = s->nsector;
662 if (n > s->req_nb_sectors)
663 n = s->req_nb_sectors;
664
665 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
666 ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
667 bdrv_acct_done(s->bs, &s->acct);
668
669 if (ret != 0) {
670 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY))
671 return;
672 }
673
674 s->nsector -= n;
675 if (s->nsector == 0) {
676 /* no more sectors to write */
677 ide_transfer_stop(s);
678 } else {
679 n1 = s->nsector;
680 if (n1 > s->req_nb_sectors)
681 n1 = s->req_nb_sectors;
682 ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);
683 }
684 ide_set_sector(s, sector_num + n);
685
686 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
687 /* It seems there is a bug in the Windows 2000 installer HDD
688 IDE driver which fills the disk with empty logs when the
689 IDE write IRQ comes too early. This hack tries to correct
690 that at the expense of slower write performances. Use this
691 option _only_ to install Windows 2000. You must disable it
692 for normal use. */
693 qemu_mod_timer(s->sector_write_timer,
694 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000));
695 } else {
696 ide_set_irq(s->bus);
697 }
698}
699
700static void ide_flush_cb(void *opaque, int ret)
701{
702 IDEState *s = opaque;
703
704 if (ret < 0) {
705 /* XXX: What sector number to set here? */
706 if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) {
707 return;
708 }
709 }
710
711 bdrv_acct_done(s->bs, &s->acct);
712 s->status = READY_STAT | SEEK_STAT;
713 ide_set_irq(s->bus);
714}
715
716void ide_flush_cache(IDEState *s)
717{
718 BlockDriverAIOCB *acb;
719
720 if (s->bs == NULL) {
721 ide_flush_cb(s, 0);
722 return;
723 }
724
725 bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH);
726 acb = bdrv_aio_flush(s->bs, ide_flush_cb, s);
727 if (acb == NULL) {
728 ide_flush_cb(s, -EIO);
729 }
730}
731
732static void ide_cfata_metadata_inquiry(IDEState *s)
733{
734 uint16_t *p;
735 uint32_t spd;
736
737 p = (uint16_t *) s->io_buffer;
738 memset(p, 0, 0x200);
739 spd = ((s->mdata_size - 1) >> 9) + 1;
740
741 put_le16(p + 0, 0x0001); /* Data format revision */
742 put_le16(p + 1, 0x0000); /* Media property: silicon */
743 put_le16(p + 2, s->media_changed); /* Media status */
744 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
745 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
746 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
747 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
748}
749
750static void ide_cfata_metadata_read(IDEState *s)
751{
752 uint16_t *p;
753
754 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
755 s->status = ERR_STAT;
756 s->error = ABRT_ERR;
757 return;
758 }
759
760 p = (uint16_t *) s->io_buffer;
761 memset(p, 0, 0x200);
762
763 put_le16(p + 0, s->media_changed); /* Media status */
764 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
765 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
766 s->nsector << 9), 0x200 - 2));
767}
768
769static void ide_cfata_metadata_write(IDEState *s)
770{
771 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
772 s->status = ERR_STAT;
773 s->error = ABRT_ERR;
774 return;
775 }
776
777 s->media_changed = 0;
778
779 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
780 s->io_buffer + 2,
781 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
782 s->nsector << 9), 0x200 - 2));
783}
784
785/* called when the inserted state of the media has changed */
786static void ide_cd_change_cb(void *opaque)
787{
788 IDEState *s = opaque;
789 uint64_t nb_sectors;
790
791 bdrv_get_geometry(s->bs, &nb_sectors);
792 s->nb_sectors = nb_sectors;
793
794 /*
795 * First indicate to the guest that a CD has been removed. That's
796 * done on the next command the guest sends us.
797 *
798 * Then we set SENSE_UNIT_ATTENTION, by which the guest will
799 * detect a new CD in the drive. See ide_atapi_cmd() for details.
800 */
801 s->cdrom_changed = 1;
802 s->events.new_media = true;
803 ide_set_irq(s->bus);
804}
805
806static void ide_cmd_lba48_transform(IDEState *s, int lba48)
807{
808 s->lba48 = lba48;
809
810 /* handle the 'magic' 0 nsector count conversion here. to avoid
811 * fiddling with the rest of the read logic, we just store the
812 * full sector count in ->nsector and ignore ->hob_nsector from now
813 */
814 if (!s->lba48) {
815 if (!s->nsector)
816 s->nsector = 256;
817 } else {
818 if (!s->nsector && !s->hob_nsector)
819 s->nsector = 65536;
820 else {
821 int lo = s->nsector;
822 int hi = s->hob_nsector;
823
824 s->nsector = (hi << 8) | lo;
825 }
826 }
827}
828
829static void ide_clear_hob(IDEBus *bus)
830{
831 /* any write clears HOB high bit of device control register */
832 bus->ifs[0].select &= ~(1 << 7);
833 bus->ifs[1].select &= ~(1 << 7);
834}
835
836void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
837{
838 IDEBus *bus = opaque;
839
840#ifdef DEBUG_IDE
841 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
842#endif
843
844 addr &= 7;
845
846 /* ignore writes to command block while busy with previous command */
847 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
848 return;
849
850 switch(addr) {
851 case 0:
852 break;
853 case 1:
854 ide_clear_hob(bus);
855 /* NOTE: data is written to the two drives */
856 bus->ifs[0].hob_feature = bus->ifs[0].feature;
857 bus->ifs[1].hob_feature = bus->ifs[1].feature;
858 bus->ifs[0].feature = val;
859 bus->ifs[1].feature = val;
860 break;
861 case 2:
862 ide_clear_hob(bus);
863 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
864 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
865 bus->ifs[0].nsector = val;
866 bus->ifs[1].nsector = val;
867 break;
868 case 3:
869 ide_clear_hob(bus);
870 bus->ifs[0].hob_sector = bus->ifs[0].sector;
871 bus->ifs[1].hob_sector = bus->ifs[1].sector;
872 bus->ifs[0].sector = val;
873 bus->ifs[1].sector = val;
874 break;
875 case 4:
876 ide_clear_hob(bus);
877 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
878 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
879 bus->ifs[0].lcyl = val;
880 bus->ifs[1].lcyl = val;
881 break;
882 case 5:
883 ide_clear_hob(bus);
884 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
885 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
886 bus->ifs[0].hcyl = val;
887 bus->ifs[1].hcyl = val;
888 break;
889 case 6:
890 /* FIXME: HOB readback uses bit 7 */
891 bus->ifs[0].select = (val & ~0x10) | 0xa0;
892 bus->ifs[1].select = (val | 0x10) | 0xa0;
893 /* select drive */
894 bus->unit = (val >> 4) & 1;
895 break;
896 default:
897 case 7:
898 /* command */
899 ide_exec_cmd(bus, val);
900 break;
901 }
902}
903
904
905void ide_exec_cmd(IDEBus *bus, uint32_t val)
906{
907 IDEState *s;
908 int n;
909 int lba48 = 0;
910
911#if defined(DEBUG_IDE)
912 printf("ide: CMD=%02x\n", val);
913#endif
914 s = idebus_active_if(bus);
915 /* ignore commands to non existant slave */
916 if (s != bus->ifs && !s->bs)
917 return;
918
919 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
920 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
921 return;
922
923 switch(val) {
924 case WIN_DSM:
925 switch (s->feature) {
926 case DSM_TRIM:
927 if (!s->bs) {
928 goto abort_cmd;
929 }
930 ide_sector_start_dma(s, IDE_DMA_TRIM);
931 break;
932 default:
933 goto abort_cmd;
934 }
935 break;
936 case WIN_IDENTIFY:
937 if (s->bs && s->drive_kind != IDE_CD) {
938 if (s->drive_kind != IDE_CFATA)
939 ide_identify(s);
940 else
941 ide_cfata_identify(s);
942 s->status = READY_STAT | SEEK_STAT;
943 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
944 } else {
945 if (s->drive_kind == IDE_CD) {
946 ide_set_signature(s);
947 }
948 ide_abort_command(s);
949 }
950 ide_set_irq(s->bus);
951 break;
952 case WIN_SPECIFY:
953 case WIN_RECAL:
954 s->error = 0;
955 s->status = READY_STAT | SEEK_STAT;
956 ide_set_irq(s->bus);
957 break;
958 case WIN_SETMULT:
959 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
960 /* Disable Read and Write Multiple */
961 s->mult_sectors = 0;
962 s->status = READY_STAT | SEEK_STAT;
963 } else if ((s->nsector & 0xff) != 0 &&
964 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
965 (s->nsector & (s->nsector - 1)) != 0)) {
966 ide_abort_command(s);
967 } else {
968 s->mult_sectors = s->nsector & 0xff;
969 s->status = READY_STAT | SEEK_STAT;
970 }
971 ide_set_irq(s->bus);
972 break;
973 case WIN_VERIFY_EXT:
974 lba48 = 1;
975 case WIN_VERIFY:
976 case WIN_VERIFY_ONCE:
977 /* do sector number check ? */
978 ide_cmd_lba48_transform(s, lba48);
979 s->status = READY_STAT | SEEK_STAT;
980 ide_set_irq(s->bus);
981 break;
982 case WIN_READ_EXT:
983 lba48 = 1;
984 case WIN_READ:
985 case WIN_READ_ONCE:
986 if (!s->bs)
987 goto abort_cmd;
988 ide_cmd_lba48_transform(s, lba48);
989 s->req_nb_sectors = 1;
990 ide_sector_read(s);
991 break;
992 case WIN_WRITE_EXT:
993 lba48 = 1;
994 case WIN_WRITE:
995 case WIN_WRITE_ONCE:
996 case CFA_WRITE_SECT_WO_ERASE:
997 case WIN_WRITE_VERIFY:
998 ide_cmd_lba48_transform(s, lba48);
999 s->error = 0;
1000 s->status = SEEK_STAT | READY_STAT;
1001 s->req_nb_sectors = 1;
1002 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1003 s->media_changed = 1;
1004 break;
1005 case WIN_MULTREAD_EXT:
1006 lba48 = 1;
1007 case WIN_MULTREAD:
1008 if (!s->mult_sectors)
1009 goto abort_cmd;
1010 ide_cmd_lba48_transform(s, lba48);
1011 s->req_nb_sectors = s->mult_sectors;
1012 ide_sector_read(s);
1013 break;
1014 case WIN_MULTWRITE_EXT:
1015 lba48 = 1;
1016 case WIN_MULTWRITE:
1017 case CFA_WRITE_MULTI_WO_ERASE:
1018 if (!s->mult_sectors)
1019 goto abort_cmd;
1020 ide_cmd_lba48_transform(s, lba48);
1021 s->error = 0;
1022 s->status = SEEK_STAT | READY_STAT;
1023 s->req_nb_sectors = s->mult_sectors;
1024 n = s->nsector;
1025 if (n > s->req_nb_sectors)
1026 n = s->req_nb_sectors;
1027 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1028 s->media_changed = 1;
1029 break;
1030 case WIN_READDMA_EXT:
1031 lba48 = 1;
1032 case WIN_READDMA:
1033 case WIN_READDMA_ONCE:
1034 if (!s->bs)
1035 goto abort_cmd;
1036 ide_cmd_lba48_transform(s, lba48);
1037 ide_sector_start_dma(s, IDE_DMA_READ);
1038 break;
1039 case WIN_WRITEDMA_EXT:
1040 lba48 = 1;
1041 case WIN_WRITEDMA:
1042 case WIN_WRITEDMA_ONCE:
1043 if (!s->bs)
1044 goto abort_cmd;
1045 ide_cmd_lba48_transform(s, lba48);
1046 ide_sector_start_dma(s, IDE_DMA_WRITE);
1047 s->media_changed = 1;
1048 break;
1049 case WIN_READ_NATIVE_MAX_EXT:
1050 lba48 = 1;
1051 case WIN_READ_NATIVE_MAX:
1052 ide_cmd_lba48_transform(s, lba48);
1053 ide_set_sector(s, s->nb_sectors - 1);
1054 s->status = READY_STAT | SEEK_STAT;
1055 ide_set_irq(s->bus);
1056 break;
1057 case WIN_CHECKPOWERMODE1:
1058 case WIN_CHECKPOWERMODE2:
1059 s->error = 0;
1060 s->nsector = 0xff; /* device active or idle */
1061 s->status = READY_STAT | SEEK_STAT;
1062 ide_set_irq(s->bus);
1063 break;
1064 case WIN_SETFEATURES:
1065 if (!s->bs)
1066 goto abort_cmd;
1067 /* XXX: valid for CDROM ? */
1068 switch(s->feature) {
1069 case 0xcc: /* reverting to power-on defaults enable */
1070 case 0x66: /* reverting to power-on defaults disable */
1071 case 0x02: /* write cache enable */
1072 case 0x82: /* write cache disable */
1073 case 0xaa: /* read look-ahead enable */
1074 case 0x55: /* read look-ahead disable */
1075 case 0x05: /* set advanced power management mode */
1076 case 0x85: /* disable advanced power management mode */
1077 case 0x69: /* NOP */
1078 case 0x67: /* NOP */
1079 case 0x96: /* NOP */
1080 case 0x9a: /* NOP */
1081 case 0x42: /* enable Automatic Acoustic Mode */
1082 case 0xc2: /* disable Automatic Acoustic Mode */
1083 s->status = READY_STAT | SEEK_STAT;
1084 ide_set_irq(s->bus);
1085 break;
1086 case 0x03: { /* set transfer mode */
1087 uint8_t val = s->nsector & 0x07;
1088 uint16_t *identify_data = (uint16_t *)s->identify_data;
1089
1090 switch (s->nsector >> 3) {
1091 case 0x00: /* pio default */
1092 case 0x01: /* pio mode */
1093 put_le16(identify_data + 62,0x07);
1094 put_le16(identify_data + 63,0x07);
1095 put_le16(identify_data + 88,0x3f);
1096 break;
1097 case 0x02: /* sigle word dma mode*/
1098 put_le16(identify_data + 62,0x07 | (1 << (val + 8)));
1099 put_le16(identify_data + 63,0x07);
1100 put_le16(identify_data + 88,0x3f);
1101 break;
1102 case 0x04: /* mdma mode */
1103 put_le16(identify_data + 62,0x07);
1104 put_le16(identify_data + 63,0x07 | (1 << (val + 8)));
1105 put_le16(identify_data + 88,0x3f);
1106 break;
1107 case 0x08: /* udma mode */
1108 put_le16(identify_data + 62,0x07);
1109 put_le16(identify_data + 63,0x07);
1110 put_le16(identify_data + 88,0x3f | (1 << (val + 8)));
1111 break;
1112 default:
1113 goto abort_cmd;
1114 }
1115 s->status = READY_STAT | SEEK_STAT;
1116 ide_set_irq(s->bus);
1117 break;
1118 }
1119 default:
1120 goto abort_cmd;
1121 }
1122 break;
1123 case WIN_FLUSH_CACHE:
1124 case WIN_FLUSH_CACHE_EXT:
1125 ide_flush_cache(s);
1126 break;
1127 case WIN_STANDBY:
1128 case WIN_STANDBY2:
1129 case WIN_STANDBYNOW1:
1130 case WIN_STANDBYNOW2:
1131 case WIN_IDLEIMMEDIATE:
1132 case WIN_IDLEIMMEDIATE2:
1133 case WIN_SETIDLE1:
1134 case WIN_SETIDLE2:
1135 case WIN_SLEEPNOW1:
1136 case WIN_SLEEPNOW2:
1137 s->status = READY_STAT;
1138 ide_set_irq(s->bus);
1139 break;
1140 case WIN_SEEK:
1141 if(s->drive_kind == IDE_CD)
1142 goto abort_cmd;
1143 /* XXX: Check that seek is within bounds */
1144 s->status = READY_STAT | SEEK_STAT;
1145 ide_set_irq(s->bus);
1146 break;
1147 /* ATAPI commands */
1148 case WIN_PIDENTIFY:
1149 if (s->drive_kind == IDE_CD) {
1150 ide_atapi_identify(s);
1151 s->status = READY_STAT | SEEK_STAT;
1152 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1153 } else {
1154 ide_abort_command(s);
1155 }
1156 ide_set_irq(s->bus);
1157 break;
1158 case WIN_DIAGNOSE:
1159 ide_set_signature(s);
1160 if (s->drive_kind == IDE_CD)
1161 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1162 * devices to return a clear status register
1163 * with READY_STAT *not* set. */
1164 else
1165 s->status = READY_STAT | SEEK_STAT;
1166 s->error = 0x01; /* Device 0 passed, Device 1 passed or not
1167 * present.
1168 */
1169 ide_set_irq(s->bus);
1170 break;
1171 case WIN_DEVICE_RESET:
1172 if (s->drive_kind != IDE_CD)
1173 goto abort_cmd;
1174 ide_set_signature(s);
1175 s->status = 0x00; /* NOTE: READY is _not_ set */
1176 s->error = 0x01;
1177 break;
1178 case WIN_PACKETCMD:
1179 if (s->drive_kind != IDE_CD)
1180 goto abort_cmd;
1181 /* overlapping commands not supported */
1182 if (s->feature & 0x02)
1183 goto abort_cmd;
1184 s->status = READY_STAT | SEEK_STAT;
1185 s->atapi_dma = s->feature & 1;
1186 s->nsector = 1;
1187 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1188 ide_atapi_cmd);
1189 break;
1190 /* CF-ATA commands */
1191 case CFA_REQ_EXT_ERROR_CODE:
1192 if (s->drive_kind != IDE_CFATA)
1193 goto abort_cmd;
1194 s->error = 0x09; /* miscellaneous error */
1195 s->status = READY_STAT | SEEK_STAT;
1196 ide_set_irq(s->bus);
1197 break;
1198 case CFA_ERASE_SECTORS:
1199 case CFA_WEAR_LEVEL:
1200 if (s->drive_kind != IDE_CFATA)
1201 goto abort_cmd;
1202 if (val == CFA_WEAR_LEVEL)
1203 s->nsector = 0;
1204 if (val == CFA_ERASE_SECTORS)
1205 s->media_changed = 1;
1206 s->error = 0x00;
1207 s->status = READY_STAT | SEEK_STAT;
1208 ide_set_irq(s->bus);
1209 break;
1210 case CFA_TRANSLATE_SECTOR:
1211 if (s->drive_kind != IDE_CFATA)
1212 goto abort_cmd;
1213 s->error = 0x00;
1214 s->status = READY_STAT | SEEK_STAT;
1215 memset(s->io_buffer, 0, 0x200);
1216 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1217 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1218 s->io_buffer[0x02] = s->select; /* Head */
1219 s->io_buffer[0x03] = s->sector; /* Sector */
1220 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1221 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1222 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1223 s->io_buffer[0x13] = 0x00; /* Erase flag */
1224 s->io_buffer[0x18] = 0x00; /* Hot count */
1225 s->io_buffer[0x19] = 0x00; /* Hot count */
1226 s->io_buffer[0x1a] = 0x01; /* Hot count */
1227 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1228 ide_set_irq(s->bus);
1229 break;
1230 case CFA_ACCESS_METADATA_STORAGE:
1231 if (s->drive_kind != IDE_CFATA)
1232 goto abort_cmd;
1233 switch (s->feature) {
1234 case 0x02: /* Inquiry Metadata Storage */
1235 ide_cfata_metadata_inquiry(s);
1236 break;
1237 case 0x03: /* Read Metadata Storage */
1238 ide_cfata_metadata_read(s);
1239 break;
1240 case 0x04: /* Write Metadata Storage */
1241 ide_cfata_metadata_write(s);
1242 break;
1243 default:
1244 goto abort_cmd;
1245 }
1246 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1247 s->status = 0x00; /* NOTE: READY is _not_ set */
1248 ide_set_irq(s->bus);
1249 break;
1250 case IBM_SENSE_CONDITION:
1251 if (s->drive_kind != IDE_CFATA)
1252 goto abort_cmd;
1253 switch (s->feature) {
1254 case 0x01: /* sense temperature in device */
1255 s->nsector = 0x50; /* +20 C */
1256 break;
1257 default:
1258 goto abort_cmd;
1259 }
1260 s->status = READY_STAT | SEEK_STAT;
1261 ide_set_irq(s->bus);
1262 break;
1263
1264 case WIN_SMART:
1265 if (s->drive_kind == IDE_CD)
1266 goto abort_cmd;
1267 if (s->hcyl != 0xc2 || s->lcyl != 0x4f)
1268 goto abort_cmd;
1269 if (!s->smart_enabled && s->feature != SMART_ENABLE)
1270 goto abort_cmd;
1271 switch (s->feature) {
1272 case SMART_DISABLE:
1273 s->smart_enabled = 0;
1274 s->status = READY_STAT | SEEK_STAT;
1275 ide_set_irq(s->bus);
1276 break;
1277 case SMART_ENABLE:
1278 s->smart_enabled = 1;
1279 s->status = READY_STAT | SEEK_STAT;
1280 ide_set_irq(s->bus);
1281 break;
1282 case SMART_ATTR_AUTOSAVE:
1283 switch (s->sector) {
1284 case 0x00:
1285 s->smart_autosave = 0;
1286 break;
1287 case 0xf1:
1288 s->smart_autosave = 1;
1289 break;
1290 default:
1291 goto abort_cmd;
1292 }
1293 s->status = READY_STAT | SEEK_STAT;
1294 ide_set_irq(s->bus);
1295 break;
1296 case SMART_STATUS:
1297 if (!s->smart_errors) {
1298 s->hcyl = 0xc2;
1299 s->lcyl = 0x4f;
1300 } else {
1301 s->hcyl = 0x2c;
1302 s->lcyl = 0xf4;
1303 }
1304 s->status = READY_STAT | SEEK_STAT;
1305 ide_set_irq(s->bus);
1306 break;
1307 case SMART_READ_THRESH:
1308 memset(s->io_buffer, 0, 0x200);
1309 s->io_buffer[0] = 0x01; /* smart struct version */
1310 for (n=0; n<30; n++) {
1311 if (smart_attributes[n][0] == 0)
1312 break;
1313 s->io_buffer[2+0+(n*12)] = smart_attributes[n][0];
1314 s->io_buffer[2+1+(n*12)] = smart_attributes[n][11];
1315 }
1316 for (n=0; n<511; n++) /* checksum */
1317 s->io_buffer[511] += s->io_buffer[n];
1318 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1319 s->status = READY_STAT | SEEK_STAT;
1320 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1321 ide_set_irq(s->bus);
1322 break;
1323 case SMART_READ_DATA:
1324 memset(s->io_buffer, 0, 0x200);
1325 s->io_buffer[0] = 0x01; /* smart struct version */
1326 for (n=0; n<30; n++) {
1327 if (smart_attributes[n][0] == 0) {
1328 break;
1329 }
1330 int i;
1331 for(i = 0; i < 11; i++) {
1332 s->io_buffer[2+i+(n*12)] = smart_attributes[n][i];
1333 }
1334 }
1335 s->io_buffer[362] = 0x02 | (s->smart_autosave?0x80:0x00);
1336 if (s->smart_selftest_count == 0) {
1337 s->io_buffer[363] = 0;
1338 } else {
1339 s->io_buffer[363] =
1340 s->smart_selftest_data[3 +
1341 (s->smart_selftest_count - 1) *
1342 24];
1343 }
1344 s->io_buffer[364] = 0x20;
1345 s->io_buffer[365] = 0x01;
1346 /* offline data collection capacity: execute + self-test*/
1347 s->io_buffer[367] = (1<<4 | 1<<3 | 1);
1348 s->io_buffer[368] = 0x03; /* smart capability (1) */
1349 s->io_buffer[369] = 0x00; /* smart capability (2) */
1350 s->io_buffer[370] = 0x01; /* error logging supported */
1351 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1352 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1353 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1354
1355 for (n=0; n<511; n++)
1356 s->io_buffer[511] += s->io_buffer[n];
1357 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1358 s->status = READY_STAT | SEEK_STAT;
1359 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1360 ide_set_irq(s->bus);
1361 break;
1362 case SMART_READ_LOG:
1363 switch (s->sector) {
1364 case 0x01: /* summary smart error log */
1365 memset(s->io_buffer, 0, 0x200);
1366 s->io_buffer[0] = 0x01;
1367 s->io_buffer[1] = 0x00; /* no error entries */
1368 s->io_buffer[452] = s->smart_errors & 0xff;
1369 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1370
1371 for (n=0; n<511; n++)
1372 s->io_buffer[511] += s->io_buffer[n];
1373 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1374 break;
1375 case 0x06: /* smart self test log */
1376 memset(s->io_buffer, 0, 0x200);
1377 s->io_buffer[0] = 0x01;
1378 if (s->smart_selftest_count == 0) {
1379 s->io_buffer[508] = 0;
1380 } else {
1381 s->io_buffer[508] = s->smart_selftest_count;
1382 for (n=2; n<506; n++)
1383 s->io_buffer[n] = s->smart_selftest_data[n];
1384 }
1385 for (n=0; n<511; n++)
1386 s->io_buffer[511] += s->io_buffer[n];
1387 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1388 break;
1389 default:
1390 goto abort_cmd;
1391 }
1392 s->status = READY_STAT | SEEK_STAT;
1393 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1394 ide_set_irq(s->bus);
1395 break;
1396 case SMART_EXECUTE_OFFLINE:
1397 switch (s->sector) {
1398 case 0: /* off-line routine */
1399 case 1: /* short self test */
1400 case 2: /* extended self test */
1401 s->smart_selftest_count++;
1402 if(s->smart_selftest_count > 21)
1403 s->smart_selftest_count = 0;
1404 n = 2 + (s->smart_selftest_count - 1) * 24;
1405 s->smart_selftest_data[n] = s->sector;
1406 s->smart_selftest_data[n+1] = 0x00; /* OK and finished */
1407 s->smart_selftest_data[n+2] = 0x34; /* hour count lsb */
1408 s->smart_selftest_data[n+3] = 0x12; /* hour count msb */
1409 s->status = READY_STAT | SEEK_STAT;
1410 ide_set_irq(s->bus);
1411 break;
1412 default:
1413 goto abort_cmd;
1414 }
1415 break;
1416 default:
1417 goto abort_cmd;
1418 }
1419 break;
1420 default:
1421 abort_cmd:
1422 ide_abort_command(s);
1423 ide_set_irq(s->bus);
1424 break;
1425 }
1426}
1427
1428uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
1429{
1430 IDEBus *bus = opaque;
1431 IDEState *s = idebus_active_if(bus);
1432 uint32_t addr;
1433 int ret, hob;
1434
1435 addr = addr1 & 7;
1436 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1437 //hob = s->select & (1 << 7);
1438 hob = 0;
1439 switch(addr) {
1440 case 0:
1441 ret = 0xff;
1442 break;
1443 case 1:
1444 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1445 (s != bus->ifs && !s->bs))
1446 ret = 0;
1447 else if (!hob)
1448 ret = s->error;
1449 else
1450 ret = s->hob_feature;
1451 break;
1452 case 2:
1453 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1454 ret = 0;
1455 else if (!hob)
1456 ret = s->nsector & 0xff;
1457 else
1458 ret = s->hob_nsector;
1459 break;
1460 case 3:
1461 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1462 ret = 0;
1463 else if (!hob)
1464 ret = s->sector;
1465 else
1466 ret = s->hob_sector;
1467 break;
1468 case 4:
1469 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1470 ret = 0;
1471 else if (!hob)
1472 ret = s->lcyl;
1473 else
1474 ret = s->hob_lcyl;
1475 break;
1476 case 5:
1477 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1478 ret = 0;
1479 else if (!hob)
1480 ret = s->hcyl;
1481 else
1482 ret = s->hob_hcyl;
1483 break;
1484 case 6:
1485 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1486 ret = 0;
1487 else
1488 ret = s->select;
1489 break;
1490 default:
1491 case 7:
1492 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1493 (s != bus->ifs && !s->bs))
1494 ret = 0;
1495 else
1496 ret = s->status;
1497 qemu_irq_lower(bus->irq);
1498 break;
1499 }
1500#ifdef DEBUG_IDE
1501 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1502#endif
1503 return ret;
1504}
1505
1506uint32_t ide_status_read(void *opaque, uint32_t addr)
1507{
1508 IDEBus *bus = opaque;
1509 IDEState *s = idebus_active_if(bus);
1510 int ret;
1511
1512 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1513 (s != bus->ifs && !s->bs))
1514 ret = 0;
1515 else
1516 ret = s->status;
1517#ifdef DEBUG_IDE
1518 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1519#endif
1520 return ret;
1521}
1522
1523void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
1524{
1525 IDEBus *bus = opaque;
1526 IDEState *s;
1527 int i;
1528
1529#ifdef DEBUG_IDE
1530 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1531#endif
1532 /* common for both drives */
1533 if (!(bus->cmd & IDE_CMD_RESET) &&
1534 (val & IDE_CMD_RESET)) {
1535 /* reset low to high */
1536 for(i = 0;i < 2; i++) {
1537 s = &bus->ifs[i];
1538 s->status = BUSY_STAT | SEEK_STAT;
1539 s->error = 0x01;
1540 }
1541 } else if ((bus->cmd & IDE_CMD_RESET) &&
1542 !(val & IDE_CMD_RESET)) {
1543 /* high to low */
1544 for(i = 0;i < 2; i++) {
1545 s = &bus->ifs[i];
1546 if (s->drive_kind == IDE_CD)
1547 s->status = 0x00; /* NOTE: READY is _not_ set */
1548 else
1549 s->status = READY_STAT | SEEK_STAT;
1550 ide_set_signature(s);
1551 }
1552 }
1553
1554 bus->cmd = val;
1555}
1556
1557/*
1558 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1559 * transferred from the device to the guest), false if it's a PIO in
1560 */
1561static bool ide_is_pio_out(IDEState *s)
1562{
1563 if (s->end_transfer_func == ide_sector_write ||
1564 s->end_transfer_func == ide_atapi_cmd) {
1565 return false;
1566 } else if (s->end_transfer_func == ide_sector_read ||
1567 s->end_transfer_func == ide_transfer_stop ||
1568 s->end_transfer_func == ide_atapi_cmd_reply_end ||
1569 s->end_transfer_func == ide_dummy_transfer_stop) {
1570 return true;
1571 }
1572
1573 abort();
1574}
1575
1576void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
1577{
1578 IDEBus *bus = opaque;
1579 IDEState *s = idebus_active_if(bus);
1580 uint8_t *p;
1581
1582 /* PIO data access allowed only when DRQ bit is set. The result of a write
1583 * during PIO out is indeterminate, just ignore it. */
1584 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
1585 return;
1586 }
1587
1588 p = s->data_ptr;
1589 *(uint16_t *)p = le16_to_cpu(val);
1590 p += 2;
1591 s->data_ptr = p;
1592 if (p >= s->data_end)
1593 s->end_transfer_func(s);
1594}
1595
1596uint32_t ide_data_readw(void *opaque, uint32_t addr)
1597{
1598 IDEBus *bus = opaque;
1599 IDEState *s = idebus_active_if(bus);
1600 uint8_t *p;
1601 int ret;
1602
1603 /* PIO data access allowed only when DRQ bit is set. The result of a read
1604 * during PIO in is indeterminate, return 0 and don't move forward. */
1605 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
1606 return 0;
1607 }
1608
1609 p = s->data_ptr;
1610 ret = cpu_to_le16(*(uint16_t *)p);
1611 p += 2;
1612 s->data_ptr = p;
1613 if (p >= s->data_end)
1614 s->end_transfer_func(s);
1615 return ret;
1616}
1617
1618void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
1619{
1620 IDEBus *bus = opaque;
1621 IDEState *s = idebus_active_if(bus);
1622 uint8_t *p;
1623
1624 /* PIO data access allowed only when DRQ bit is set. The result of a write
1625 * during PIO out is indeterminate, just ignore it. */
1626 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
1627 return;
1628 }
1629
1630 p = s->data_ptr;
1631 *(uint32_t *)p = le32_to_cpu(val);
1632 p += 4;
1633 s->data_ptr = p;
1634 if (p >= s->data_end)
1635 s->end_transfer_func(s);
1636}
1637
1638uint32_t ide_data_readl(void *opaque, uint32_t addr)
1639{
1640 IDEBus *bus = opaque;
1641 IDEState *s = idebus_active_if(bus);
1642 uint8_t *p;
1643 int ret;
1644
1645 /* PIO data access allowed only when DRQ bit is set. The result of a read
1646 * during PIO in is indeterminate, return 0 and don't move forward. */
1647 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
1648 return 0;
1649 }
1650
1651 p = s->data_ptr;
1652 ret = cpu_to_le32(*(uint32_t *)p);
1653 p += 4;
1654 s->data_ptr = p;
1655 if (p >= s->data_end)
1656 s->end_transfer_func(s);
1657 return ret;
1658}
1659
1660static void ide_dummy_transfer_stop(IDEState *s)
1661{
1662 s->data_ptr = s->io_buffer;
1663 s->data_end = s->io_buffer;
1664 s->io_buffer[0] = 0xff;
1665 s->io_buffer[1] = 0xff;
1666 s->io_buffer[2] = 0xff;
1667 s->io_buffer[3] = 0xff;
1668}
1669
1670static void ide_reset(IDEState *s)
1671{
1672#ifdef DEBUG_IDE
1673 printf("ide: reset\n");
1674#endif
1675 if (s->drive_kind == IDE_CFATA)
1676 s->mult_sectors = 0;
1677 else
1678 s->mult_sectors = MAX_MULT_SECTORS;
1679 /* ide regs */
1680 s->feature = 0;
1681 s->error = 0;
1682 s->nsector = 0;
1683 s->sector = 0;
1684 s->lcyl = 0;
1685 s->hcyl = 0;
1686
1687 /* lba48 */
1688 s->hob_feature = 0;
1689 s->hob_sector = 0;
1690 s->hob_nsector = 0;
1691 s->hob_lcyl = 0;
1692 s->hob_hcyl = 0;
1693
1694 s->select = 0xa0;
1695 s->status = READY_STAT | SEEK_STAT;
1696
1697 s->lba48 = 0;
1698
1699 /* ATAPI specific */
1700 s->sense_key = 0;
1701 s->asc = 0;
1702 s->cdrom_changed = 0;
1703 s->packet_transfer_size = 0;
1704 s->elementary_transfer_size = 0;
1705 s->io_buffer_index = 0;
1706 s->cd_sector_size = 0;
1707 s->atapi_dma = 0;
1708 /* ATA DMA state */
1709 s->io_buffer_size = 0;
1710 s->req_nb_sectors = 0;
1711
1712 ide_set_signature(s);
1713 /* init the transfer handler so that 0xffff is returned on data
1714 accesses */
1715 s->end_transfer_func = ide_dummy_transfer_stop;
1716 ide_dummy_transfer_stop(s);
1717 s->media_changed = 0;
1718}
1719
1720void ide_bus_reset(IDEBus *bus)
1721{
1722 bus->unit = 0;
1723 bus->cmd = 0;
1724 ide_reset(&bus->ifs[0]);
1725 ide_reset(&bus->ifs[1]);
1726 ide_clear_hob(bus);
1727
1728 /* pending async DMA */
1729 if (bus->dma->aiocb) {
1730#ifdef DEBUG_AIO
1731 printf("aio_cancel\n");
1732#endif
1733 bdrv_aio_cancel(bus->dma->aiocb);
1734 bus->dma->aiocb = NULL;
1735 }
1736
1737 /* reset dma provider too */
1738 bus->dma->ops->reset(bus->dma);
1739}
1740
1741static const BlockDevOps ide_cd_block_ops = {
1742 .change_media_cb = ide_cd_change_cb,
1743};
1744
1745int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind,
1746 const char *version, const char *serial)
1747{
1748 int cylinders, heads, secs;
1749 uint64_t nb_sectors;
1750
1751 s->bs = bs;
1752 s->drive_kind = kind;
1753
1754 bdrv_get_geometry(bs, &nb_sectors);
1755 bdrv_guess_geometry(bs, &cylinders, &heads, &secs);
1756 if (cylinders < 1 || cylinders > 16383) {
1757 error_report("cyls must be between 1 and 16383");
1758 return -1;
1759 }
1760 if (heads < 1 || heads > 16) {
1761 error_report("heads must be between 1 and 16");
1762 return -1;
1763 }
1764 if (secs < 1 || secs > 63) {
1765 error_report("secs must be between 1 and 63");
1766 return -1;
1767 }
1768 s->cylinders = cylinders;
1769 s->heads = heads;
1770 s->sectors = secs;
1771 s->nb_sectors = nb_sectors;
1772 /* The SMART values should be preserved across power cycles
1773 but they aren't. */
1774 s->smart_enabled = 1;
1775 s->smart_autosave = 1;
1776 s->smart_errors = 0;
1777 s->smart_selftest_count = 0;
1778 if (kind == IDE_CD) {
1779 bdrv_set_dev_ops(bs, &ide_cd_block_ops, s);
1780 bs->buffer_alignment = 2048;
1781 } else {
1782 if (!bdrv_is_inserted(s->bs)) {
1783 error_report("Device needs media, but drive is empty");
1784 return -1;
1785 }
1786 if (bdrv_is_read_only(bs)) {
1787 error_report("Can't use a read-only drive");
1788 return -1;
1789 }
1790 }
1791 if (serial) {
1792 strncpy(s->drive_serial_str, serial, sizeof(s->drive_serial_str));
1793 } else {
1794 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
1795 "QM%05d", s->drive_serial);
1796 }
1797 if (version) {
1798 pstrcpy(s->version, sizeof(s->version), version);
1799 } else {
1800 pstrcpy(s->version, sizeof(s->version), QEMU_VERSION);
1801 }
1802
1803 ide_reset(s);
1804 bdrv_set_removable(bs, s->drive_kind == IDE_CD);
1805 return 0;
1806}
1807
1808static void ide_init1(IDEBus *bus, int unit)
1809{
1810 static int drive_serial = 1;
1811 IDEState *s = &bus->ifs[unit];
1812
1813 s->bus = bus;
1814 s->unit = unit;
1815 s->drive_serial = drive_serial++;
1816 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
1817 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
1818 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
1819 memset(s->io_buffer, 0, s->io_buffer_total_len);
1820
1821 s->smart_selftest_data = qemu_blockalign(s->bs, 512);
1822 memset(s->smart_selftest_data, 0, 512);
1823
1824 s->sector_write_timer = qemu_new_timer_ns(vm_clock,
1825 ide_sector_write_timer_cb, s);
1826}
1827
1828static void ide_nop_start(IDEDMA *dma, IDEState *s,
1829 BlockDriverCompletionFunc *cb)
1830{
1831}
1832
1833static int ide_nop(IDEDMA *dma)
1834{
1835 return 0;
1836}
1837
1838static int ide_nop_int(IDEDMA *dma, int x)
1839{
1840 return 0;
1841}
1842
1843static void ide_nop_restart(void *opaque, int x, int y)
1844{
1845}
1846
1847static const IDEDMAOps ide_dma_nop_ops = {
1848 .start_dma = ide_nop_start,
1849 .start_transfer = ide_nop,
1850 .prepare_buf = ide_nop_int,
1851 .rw_buf = ide_nop_int,
1852 .set_unit = ide_nop_int,
1853 .add_status = ide_nop_int,
1854 .set_inactive = ide_nop,
1855 .restart_cb = ide_nop_restart,
1856 .reset = ide_nop,
1857};
1858
1859static IDEDMA ide_dma_nop = {
1860 .ops = &ide_dma_nop_ops,
1861 .aiocb = NULL,
1862};
1863
1864void ide_init2(IDEBus *bus, qemu_irq irq)
1865{
1866 int i;
1867
1868 for(i = 0; i < 2; i++) {
1869 ide_init1(bus, i);
1870 ide_reset(&bus->ifs[i]);
1871 }
1872 bus->irq = irq;
1873 bus->dma = &ide_dma_nop;
1874}
1875
1876/* TODO convert users to qdev and remove */
1877void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0,
1878 DriveInfo *hd1, qemu_irq irq)
1879{
1880 int i;
1881 DriveInfo *dinfo;
1882
1883 for(i = 0; i < 2; i++) {
1884 dinfo = i == 0 ? hd0 : hd1;
1885 ide_init1(bus, i);
1886 if (dinfo) {
1887 if (ide_init_drive(&bus->ifs[i], dinfo->bdrv,
1888 dinfo->media_cd ? IDE_CD : IDE_HD, NULL,
1889 *dinfo->serial ? dinfo->serial : NULL) < 0) {
1890 error_report("Can't set up IDE drive %s", dinfo->id);
1891 exit(1);
1892 }
1893 bdrv_attach_dev_nofail(dinfo->bdrv, &bus->ifs[i]);
1894 } else {
1895 ide_reset(&bus->ifs[i]);
1896 }
1897 }
1898 bus->irq = irq;
1899 bus->dma = &ide_dma_nop;
1900}
1901
1902void ide_init_ioport(IDEBus *bus, int iobase, int iobase2)
1903{
1904 register_ioport_write(iobase, 8, 1, ide_ioport_write, bus);
1905 register_ioport_read(iobase, 8, 1, ide_ioport_read, bus);
1906 if (iobase2) {
1907 register_ioport_read(iobase2, 1, 1, ide_status_read, bus);
1908 register_ioport_write(iobase2, 1, 1, ide_cmd_write, bus);
1909 }
1910
1911 /* data ports */
1912 register_ioport_write(iobase, 2, 2, ide_data_writew, bus);
1913 register_ioport_read(iobase, 2, 2, ide_data_readw, bus);
1914 register_ioport_write(iobase, 4, 4, ide_data_writel, bus);
1915 register_ioport_read(iobase, 4, 4, ide_data_readl, bus);
1916}
1917
1918static bool is_identify_set(void *opaque, int version_id)
1919{
1920 IDEState *s = opaque;
1921
1922 return s->identify_set != 0;
1923}
1924
1925static EndTransferFunc* transfer_end_table[] = {
1926 ide_sector_read,
1927 ide_sector_write,
1928 ide_transfer_stop,
1929 ide_atapi_cmd_reply_end,
1930 ide_atapi_cmd,
1931 ide_dummy_transfer_stop,
1932};
1933
1934static int transfer_end_table_idx(EndTransferFunc *fn)
1935{
1936 int i;
1937
1938 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
1939 if (transfer_end_table[i] == fn)
1940 return i;
1941
1942 return -1;
1943}
1944
1945static int ide_drive_post_load(void *opaque, int version_id)
1946{
1947 IDEState *s = opaque;
1948
1949 if (version_id < 3) {
1950 if (s->sense_key == SENSE_UNIT_ATTENTION &&
1951 s->asc == ASC_MEDIUM_MAY_HAVE_CHANGED) {
1952 s->cdrom_changed = 1;
1953 }
1954 }
1955 return 0;
1956}
1957
1958static int ide_drive_pio_post_load(void *opaque, int version_id)
1959{
1960 IDEState *s = opaque;
1961
1962 if (s->end_transfer_fn_idx > ARRAY_SIZE(transfer_end_table)) {
1963 return -EINVAL;
1964 }
1965 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
1966 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
1967 s->data_end = s->data_ptr + s->cur_io_buffer_len;
1968
1969 return 0;
1970}
1971
1972static void ide_drive_pio_pre_save(void *opaque)
1973{
1974 IDEState *s = opaque;
1975 int idx;
1976
1977 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
1978 s->cur_io_buffer_len = s->data_end - s->data_ptr;
1979
1980 idx = transfer_end_table_idx(s->end_transfer_func);
1981 if (idx == -1) {
1982 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
1983 __func__);
1984 s->end_transfer_fn_idx = 2;
1985 } else {
1986 s->end_transfer_fn_idx = idx;
1987 }
1988}
1989
1990static bool ide_drive_pio_state_needed(void *opaque)
1991{
1992 IDEState *s = opaque;
1993
1994 return ((s->status & DRQ_STAT) != 0)
1995 || (s->bus->error_status & BM_STATUS_PIO_RETRY);
1996}
1997
1998static bool ide_atapi_gesn_needed(void *opaque)
1999{
2000 IDEState *s = opaque;
2001
2002 return s->events.new_media || s->events.eject_request;
2003}
2004
2005static bool ide_error_needed(void *opaque)
2006{
2007 IDEBus *bus = opaque;
2008
2009 return (bus->error_status != 0);
2010}
2011
2012/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
2013const VMStateDescription vmstate_ide_atapi_gesn_state = {
2014 .name ="ide_drive/atapi/gesn_state",
2015 .version_id = 1,
2016 .minimum_version_id = 1,
2017 .minimum_version_id_old = 1,
2018 .fields = (VMStateField []) {
2019 VMSTATE_BOOL(events.new_media, IDEState),
2020 VMSTATE_BOOL(events.eject_request, IDEState),
2021 VMSTATE_END_OF_LIST()
2022 }
2023};
2024
2025const VMStateDescription vmstate_ide_drive_pio_state = {
2026 .name = "ide_drive/pio_state",
2027 .version_id = 1,
2028 .minimum_version_id = 1,
2029 .minimum_version_id_old = 1,
2030 .pre_save = ide_drive_pio_pre_save,
2031 .post_load = ide_drive_pio_post_load,
2032 .fields = (VMStateField []) {
2033 VMSTATE_INT32(req_nb_sectors, IDEState),
2034 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2035 vmstate_info_uint8, uint8_t),
2036 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2037 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2038 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2039 VMSTATE_INT32(elementary_transfer_size, IDEState),
2040 VMSTATE_INT32(packet_transfer_size, IDEState),
2041 VMSTATE_END_OF_LIST()
2042 }
2043};
2044
2045const VMStateDescription vmstate_ide_drive = {
2046 .name = "ide_drive",
2047 .version_id = 3,
2048 .minimum_version_id = 0,
2049 .minimum_version_id_old = 0,
2050 .post_load = ide_drive_post_load,
2051 .fields = (VMStateField []) {
2052 VMSTATE_INT32(mult_sectors, IDEState),
2053 VMSTATE_INT32(identify_set, IDEState),
2054 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2055 VMSTATE_UINT8(feature, IDEState),
2056 VMSTATE_UINT8(error, IDEState),
2057 VMSTATE_UINT32(nsector, IDEState),
2058 VMSTATE_UINT8(sector, IDEState),
2059 VMSTATE_UINT8(lcyl, IDEState),
2060 VMSTATE_UINT8(hcyl, IDEState),
2061 VMSTATE_UINT8(hob_feature, IDEState),
2062 VMSTATE_UINT8(hob_sector, IDEState),
2063 VMSTATE_UINT8(hob_nsector, IDEState),
2064 VMSTATE_UINT8(hob_lcyl, IDEState),
2065 VMSTATE_UINT8(hob_hcyl, IDEState),
2066 VMSTATE_UINT8(select, IDEState),
2067 VMSTATE_UINT8(status, IDEState),
2068 VMSTATE_UINT8(lba48, IDEState),
2069 VMSTATE_UINT8(sense_key, IDEState),
2070 VMSTATE_UINT8(asc, IDEState),
2071 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
2072 VMSTATE_END_OF_LIST()
2073 },
2074 .subsections = (VMStateSubsection []) {
2075 {
2076 .vmsd = &vmstate_ide_drive_pio_state,
2077 .needed = ide_drive_pio_state_needed,
2078 }, {
2079 .vmsd = &vmstate_ide_atapi_gesn_state,
2080 .needed = ide_atapi_gesn_needed,
2081 }, {
2082 /* empty */
2083 }
2084 }
2085};
2086
2087const VMStateDescription vmstate_ide_error_status = {
2088 .name ="ide_bus/error",
2089 .version_id = 1,
2090 .minimum_version_id = 1,
2091 .minimum_version_id_old = 1,
2092 .fields = (VMStateField []) {
2093 VMSTATE_INT32(error_status, IDEBus),
2094 VMSTATE_END_OF_LIST()
2095 }
2096};
2097
2098const VMStateDescription vmstate_ide_bus = {
2099 .name = "ide_bus",
2100 .version_id = 1,
2101 .minimum_version_id = 1,
2102 .minimum_version_id_old = 1,
2103 .fields = (VMStateField []) {
2104 VMSTATE_UINT8(cmd, IDEBus),
2105 VMSTATE_UINT8(unit, IDEBus),
2106 VMSTATE_END_OF_LIST()
2107 },
2108 .subsections = (VMStateSubsection []) {
2109 {
2110 .vmsd = &vmstate_ide_error_status,
2111 .needed = ide_error_needed,
2112 }, {
2113 /* empty */
2114 }
2115 }
2116};
2117
2118void ide_drive_get(DriveInfo **hd, int max_bus)
2119{
2120 int i;
2121
2122 if (drive_get_max_bus(IF_IDE) >= max_bus) {
2123 fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
2124 exit(1);
2125 }
2126
2127 for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
2128 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
2129 }
2130}
Qemu copy for testing