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1/*
2 * QEMU IDE disk and CD/DVD-ROM Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25#include <hw/hw.h>
26#include <hw/pc.h>
27#include <hw/pci.h>
28#include "qemu-error.h"
29#include "qemu-timer.h"
30#include "sysemu.h"
31#include "dma.h"
32#include "blockdev.h"
33
34#include <hw/ide/internal.h>
35
36/* These values were based on a Seagate ST3500418AS but have been modified
37 to make more sense in QEMU */
38static const int smart_attributes[][12] = {
39 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
40 /* raw read error rate*/
41 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
42 /* spin up */
43 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
44 /* start stop count */
45 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
46 /* remapped sectors */
47 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
48 /* power on hours */
49 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
50 /* power cycle count */
51 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* airflow-temperature-celsius */
53 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
54 /* end of list */
55 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
56};
57
58static int ide_handle_rw_error(IDEState *s, int error, int op);
59static void ide_dummy_transfer_stop(IDEState *s);
60
61static void padstr(char *str, const char *src, int len)
62{
63 int i, v;
64 for(i = 0; i < len; i++) {
65 if (*src)
66 v = *src++;
67 else
68 v = ' ';
69 str[i^1] = v;
70 }
71}
72
73static void put_le16(uint16_t *p, unsigned int v)
74{
75 *p = cpu_to_le16(v);
76}
77
78static void ide_identify(IDEState *s)
79{
80 uint16_t *p;
81 unsigned int oldsize;
82 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
83
84 if (s->identify_set) {
85 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
86 return;
87 }
88
89 memset(s->io_buffer, 0, 512);
90 p = (uint16_t *)s->io_buffer;
91 put_le16(p + 0, 0x0040);
92 put_le16(p + 1, s->cylinders);
93 put_le16(p + 3, s->heads);
94 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
95 put_le16(p + 5, 512); /* XXX: retired, remove ? */
96 put_le16(p + 6, s->sectors);
97 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
98 put_le16(p + 20, 3); /* XXX: retired, remove ? */
99 put_le16(p + 21, 512); /* cache size in sectors */
100 put_le16(p + 22, 4); /* ecc bytes */
101 padstr((char *)(p + 23), s->version, 8); /* firmware version */
102 padstr((char *)(p + 27), "QEMU HARDDISK", 40); /* model */
103#if MAX_MULT_SECTORS > 1
104 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
105#endif
106 put_le16(p + 48, 1); /* dword I/O */
107 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
108 put_le16(p + 51, 0x200); /* PIO transfer cycle */
109 put_le16(p + 52, 0x200); /* DMA transfer cycle */
110 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
111 put_le16(p + 54, s->cylinders);
112 put_le16(p + 55, s->heads);
113 put_le16(p + 56, s->sectors);
114 oldsize = s->cylinders * s->heads * s->sectors;
115 put_le16(p + 57, oldsize);
116 put_le16(p + 58, oldsize >> 16);
117 if (s->mult_sectors)
118 put_le16(p + 59, 0x100 | s->mult_sectors);
119 put_le16(p + 60, s->nb_sectors);
120 put_le16(p + 61, s->nb_sectors >> 16);
121 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
122 put_le16(p + 63, 0x07); /* mdma0-2 supported */
123 put_le16(p + 64, 0x03); /* pio3-4 supported */
124 put_le16(p + 65, 120);
125 put_le16(p + 66, 120);
126 put_le16(p + 67, 120);
127 put_le16(p + 68, 120);
128 if (dev && dev->conf.discard_granularity) {
129 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
130 }
131
132 if (s->ncq_queues) {
133 put_le16(p + 75, s->ncq_queues - 1);
134 /* NCQ supported */
135 put_le16(p + 76, (1 << 8));
136 }
137
138 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
139 put_le16(p + 81, 0x16); /* conforms to ata5 */
140 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
141 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
142 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
143 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
144 /* 14=set to 1, 1=SMART self test, 0=SMART error logging */
145 put_le16(p + 84, (1 << 14) | 0);
146 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
147 if (bdrv_enable_write_cache(s->bs))
148 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
149 else
150 put_le16(p + 85, (1 << 14) | 1);
151 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
152 put_le16(p + 86, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
153 /* 14=set to 1, 1=smart self test, 0=smart error logging */
154 put_le16(p + 87, (1 << 14) | 0);
155 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
156 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
157 put_le16(p + 100, s->nb_sectors);
158 put_le16(p + 101, s->nb_sectors >> 16);
159 put_le16(p + 102, s->nb_sectors >> 32);
160 put_le16(p + 103, s->nb_sectors >> 48);
161
162 if (dev && dev->conf.physical_block_size)
163 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
164 if (dev && dev->conf.discard_granularity) {
165 put_le16(p + 169, 1); /* TRIM support */
166 }
167
168 memcpy(s->identify_data, p, sizeof(s->identify_data));
169 s->identify_set = 1;
170}
171
172static void ide_atapi_identify(IDEState *s)
173{
174 uint16_t *p;
175
176 if (s->identify_set) {
177 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
178 return;
179 }
180
181 memset(s->io_buffer, 0, 512);
182 p = (uint16_t *)s->io_buffer;
183 /* Removable CDROM, 50us response, 12 byte packets */
184 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
185 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
186 put_le16(p + 20, 3); /* buffer type */
187 put_le16(p + 21, 512); /* cache size in sectors */
188 put_le16(p + 22, 4); /* ecc bytes */
189 padstr((char *)(p + 23), s->version, 8); /* firmware version */
190 padstr((char *)(p + 27), "QEMU DVD-ROM", 40); /* model */
191 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
192#ifdef USE_DMA_CDROM
193 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
194 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
195 put_le16(p + 62, 7); /* single word dma0-2 supported */
196 put_le16(p + 63, 7); /* mdma0-2 supported */
197#else
198 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
199 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
200 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
201#endif
202 put_le16(p + 64, 3); /* pio3-4 supported */
203 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
204 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
205 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
206 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
207
208 put_le16(p + 71, 30); /* in ns */
209 put_le16(p + 72, 30); /* in ns */
210
211 if (s->ncq_queues) {
212 put_le16(p + 75, s->ncq_queues - 1);
213 /* NCQ supported */
214 put_le16(p + 76, (1 << 8));
215 }
216
217 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
218#ifdef USE_DMA_CDROM
219 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
220#endif
221 memcpy(s->identify_data, p, sizeof(s->identify_data));
222 s->identify_set = 1;
223}
224
225static void ide_cfata_identify(IDEState *s)
226{
227 uint16_t *p;
228 uint32_t cur_sec;
229
230 p = (uint16_t *) s->identify_data;
231 if (s->identify_set)
232 goto fill_buffer;
233
234 memset(p, 0, sizeof(s->identify_data));
235
236 cur_sec = s->cylinders * s->heads * s->sectors;
237
238 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
239 put_le16(p + 1, s->cylinders); /* Default cylinders */
240 put_le16(p + 3, s->heads); /* Default heads */
241 put_le16(p + 6, s->sectors); /* Default sectors per track */
242 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
243 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
244 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
245 put_le16(p + 22, 0x0004); /* ECC bytes */
246 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
247 padstr((char *) (p + 27), "QEMU MICRODRIVE", 40);/* Model number */
248#if MAX_MULT_SECTORS > 1
249 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
250#else
251 put_le16(p + 47, 0x0000);
252#endif
253 put_le16(p + 49, 0x0f00); /* Capabilities */
254 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
255 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
256 put_le16(p + 53, 0x0003); /* Translation params valid */
257 put_le16(p + 54, s->cylinders); /* Current cylinders */
258 put_le16(p + 55, s->heads); /* Current heads */
259 put_le16(p + 56, s->sectors); /* Current sectors */
260 put_le16(p + 57, cur_sec); /* Current capacity */
261 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
262 if (s->mult_sectors) /* Multiple sector setting */
263 put_le16(p + 59, 0x100 | s->mult_sectors);
264 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
265 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
266 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
267 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
268 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
269 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
270 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
271 put_le16(p + 82, 0x400c); /* Command Set supported */
272 put_le16(p + 83, 0x7068); /* Command Set supported */
273 put_le16(p + 84, 0x4000); /* Features supported */
274 put_le16(p + 85, 0x000c); /* Command Set enabled */
275 put_le16(p + 86, 0x7044); /* Command Set enabled */
276 put_le16(p + 87, 0x4000); /* Features enabled */
277 put_le16(p + 91, 0x4060); /* Current APM level */
278 put_le16(p + 129, 0x0002); /* Current features option */
279 put_le16(p + 130, 0x0005); /* Reassigned sectors */
280 put_le16(p + 131, 0x0001); /* Initial power mode */
281 put_le16(p + 132, 0x0000); /* User signature */
282 put_le16(p + 160, 0x8100); /* Power requirement */
283 put_le16(p + 161, 0x8001); /* CF command set */
284
285 s->identify_set = 1;
286
287fill_buffer:
288 memcpy(s->io_buffer, p, sizeof(s->identify_data));
289}
290
291static void ide_set_signature(IDEState *s)
292{
293 s->select &= 0xf0; /* clear head */
294 /* put signature */
295 s->nsector = 1;
296 s->sector = 1;
297 if (s->drive_kind == IDE_CD) {
298 s->lcyl = 0x14;
299 s->hcyl = 0xeb;
300 } else if (s->bs) {
301 s->lcyl = 0;
302 s->hcyl = 0;
303 } else {
304 s->lcyl = 0xff;
305 s->hcyl = 0xff;
306 }
307}
308
309typedef struct TrimAIOCB {
310 BlockDriverAIOCB common;
311 QEMUBH *bh;
312 int ret;
313} TrimAIOCB;
314
315static void trim_aio_cancel(BlockDriverAIOCB *acb)
316{
317 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
318
319 qemu_bh_delete(iocb->bh);
320 iocb->bh = NULL;
321 qemu_aio_release(iocb);
322}
323
324static AIOPool trim_aio_pool = {
325 .aiocb_size = sizeof(TrimAIOCB),
326 .cancel = trim_aio_cancel,
327};
328
329static void ide_trim_bh_cb(void *opaque)
330{
331 TrimAIOCB *iocb = opaque;
332
333 iocb->common.cb(iocb->common.opaque, iocb->ret);
334
335 qemu_bh_delete(iocb->bh);
336 iocb->bh = NULL;
337
338 qemu_aio_release(iocb);
339}
340
341BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs,
342 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
343 BlockDriverCompletionFunc *cb, void *opaque)
344{
345 TrimAIOCB *iocb;
346 int i, j, ret;
347
348 iocb = qemu_aio_get(&trim_aio_pool, bs, cb, opaque);
349 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
350 iocb->ret = 0;
351
352 for (j = 0; j < qiov->niov; j++) {
353 uint64_t *buffer = qiov->iov[j].iov_base;
354
355 for (i = 0; i < qiov->iov[j].iov_len / 8; i++) {
356 /* 6-byte LBA + 2-byte range per entry */
357 uint64_t entry = le64_to_cpu(buffer[i]);
358 uint64_t sector = entry & 0x0000ffffffffffffULL;
359 uint16_t count = entry >> 48;
360
361 if (count == 0) {
362 break;
363 }
364
365 ret = bdrv_discard(bs, sector, count);
366 if (!iocb->ret) {
367 iocb->ret = ret;
368 }
369 }
370 }
371
372 qemu_bh_schedule(iocb->bh);
373
374 return &iocb->common;
375}
376
377static inline void ide_abort_command(IDEState *s)
378{
379 s->status = READY_STAT | ERR_STAT;
380 s->error = ABRT_ERR;
381}
382
383/* prepare data transfer and tell what to do after */
384void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
385 EndTransferFunc *end_transfer_func)
386{
387 s->end_transfer_func = end_transfer_func;
388 s->data_ptr = buf;
389 s->data_end = buf + size;
390 if (!(s->status & ERR_STAT)) {
391 s->status |= DRQ_STAT;
392 }
393 s->bus->dma->ops->start_transfer(s->bus->dma);
394}
395
396void ide_transfer_stop(IDEState *s)
397{
398 s->end_transfer_func = ide_transfer_stop;
399 s->data_ptr = s->io_buffer;
400 s->data_end = s->io_buffer;
401 s->status &= ~DRQ_STAT;
402}
403
404int64_t ide_get_sector(IDEState *s)
405{
406 int64_t sector_num;
407 if (s->select & 0x40) {
408 /* lba */
409 if (!s->lba48) {
410 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
411 (s->lcyl << 8) | s->sector;
412 } else {
413 sector_num = ((int64_t)s->hob_hcyl << 40) |
414 ((int64_t) s->hob_lcyl << 32) |
415 ((int64_t) s->hob_sector << 24) |
416 ((int64_t) s->hcyl << 16) |
417 ((int64_t) s->lcyl << 8) | s->sector;
418 }
419 } else {
420 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
421 (s->select & 0x0f) * s->sectors + (s->sector - 1);
422 }
423 return sector_num;
424}
425
426void ide_set_sector(IDEState *s, int64_t sector_num)
427{
428 unsigned int cyl, r;
429 if (s->select & 0x40) {
430 if (!s->lba48) {
431 s->select = (s->select & 0xf0) | (sector_num >> 24);
432 s->hcyl = (sector_num >> 16);
433 s->lcyl = (sector_num >> 8);
434 s->sector = (sector_num);
435 } else {
436 s->sector = sector_num;
437 s->lcyl = sector_num >> 8;
438 s->hcyl = sector_num >> 16;
439 s->hob_sector = sector_num >> 24;
440 s->hob_lcyl = sector_num >> 32;
441 s->hob_hcyl = sector_num >> 40;
442 }
443 } else {
444 cyl = sector_num / (s->heads * s->sectors);
445 r = sector_num % (s->heads * s->sectors);
446 s->hcyl = cyl >> 8;
447 s->lcyl = cyl;
448 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
449 s->sector = (r % s->sectors) + 1;
450 }
451}
452
453static void ide_rw_error(IDEState *s) {
454 ide_abort_command(s);
455 ide_set_irq(s->bus);
456}
457
458void ide_sector_read(IDEState *s)
459{
460 int64_t sector_num;
461 int ret, n;
462
463 s->status = READY_STAT | SEEK_STAT;
464 s->error = 0; /* not needed by IDE spec, but needed by Windows */
465 sector_num = ide_get_sector(s);
466 n = s->nsector;
467 if (n == 0) {
468 /* no more sector to read from disk */
469 ide_transfer_stop(s);
470 } else {
471#if defined(DEBUG_IDE)
472 printf("read sector=%" PRId64 "\n", sector_num);
473#endif
474 if (n > s->req_nb_sectors)
475 n = s->req_nb_sectors;
476
477 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
478 ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
479 bdrv_acct_done(s->bs, &s->acct);
480 if (ret != 0) {
481 if (ide_handle_rw_error(s, -ret,
482 BM_STATUS_PIO_RETRY | BM_STATUS_RETRY_READ))
483 {
484 return;
485 }
486 }
487 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read);
488 ide_set_irq(s->bus);
489 ide_set_sector(s, sector_num + n);
490 s->nsector -= n;
491 }
492}
493
494static void dma_buf_commit(IDEState *s, int is_write)
495{
496 qemu_sglist_destroy(&s->sg);
497}
498
499void ide_set_inactive(IDEState *s)
500{
501 s->bus->dma->aiocb = NULL;
502 s->bus->dma->ops->set_inactive(s->bus->dma);
503}
504
505void ide_dma_error(IDEState *s)
506{
507 ide_transfer_stop(s);
508 s->error = ABRT_ERR;
509 s->status = READY_STAT | ERR_STAT;
510 ide_set_inactive(s);
511 ide_set_irq(s->bus);
512}
513
514static int ide_handle_rw_error(IDEState *s, int error, int op)
515{
516 int is_read = (op & BM_STATUS_RETRY_READ);
517 BlockErrorAction action = bdrv_get_on_error(s->bs, is_read);
518
519 if (action == BLOCK_ERR_IGNORE) {
520 bdrv_mon_event(s->bs, BDRV_ACTION_IGNORE, is_read);
521 return 0;
522 }
523
524 if ((error == ENOSPC && action == BLOCK_ERR_STOP_ENOSPC)
525 || action == BLOCK_ERR_STOP_ANY) {
526 s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
527 s->bus->error_status = op;
528 bdrv_mon_event(s->bs, BDRV_ACTION_STOP, is_read);
529 vm_stop(VMSTOP_DISKFULL);
530 } else {
531 if (op & BM_STATUS_DMA_RETRY) {
532 dma_buf_commit(s, 0);
533 ide_dma_error(s);
534 } else {
535 ide_rw_error(s);
536 }
537 bdrv_mon_event(s->bs, BDRV_ACTION_REPORT, is_read);
538 }
539
540 return 1;
541}
542
543void ide_dma_cb(void *opaque, int ret)
544{
545 IDEState *s = opaque;
546 int n;
547 int64_t sector_num;
548
549handle_rw_error:
550 if (ret < 0) {
551 int op = BM_STATUS_DMA_RETRY;
552
553 if (s->dma_cmd == IDE_DMA_READ)
554 op |= BM_STATUS_RETRY_READ;
555 else if (s->dma_cmd == IDE_DMA_TRIM)
556 op |= BM_STATUS_RETRY_TRIM;
557
558 if (ide_handle_rw_error(s, -ret, op)) {
559 return;
560 }
561 }
562
563 n = s->io_buffer_size >> 9;
564 sector_num = ide_get_sector(s);
565 if (n > 0) {
566 dma_buf_commit(s, ide_cmd_is_read(s));
567 sector_num += n;
568 ide_set_sector(s, sector_num);
569 s->nsector -= n;
570 }
571
572 /* end of transfer ? */
573 if (s->nsector == 0) {
574 s->status = READY_STAT | SEEK_STAT;
575 ide_set_irq(s->bus);
576 goto eot;
577 }
578
579 /* launch next transfer */
580 n = s->nsector;
581 s->io_buffer_index = 0;
582 s->io_buffer_size = n * 512;
583 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
584 /* The PRDs were too short. Reset the Active bit, but don't raise an
585 * interrupt. */
586 goto eot;
587 }
588
589#ifdef DEBUG_AIO
590 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
591 sector_num, n, s->dma_cmd);
592#endif
593
594 switch (s->dma_cmd) {
595 case IDE_DMA_READ:
596 s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
597 ide_dma_cb, s);
598 break;
599 case IDE_DMA_WRITE:
600 s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
601 ide_dma_cb, s);
602 break;
603 case IDE_DMA_TRIM:
604 s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
605 ide_issue_trim, ide_dma_cb, s, 1);
606 break;
607 }
608
609 if (!s->bus->dma->aiocb) {
610 ret = -1;
611 goto handle_rw_error;
612 }
613 return;
614
615eot:
616 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
617 bdrv_acct_done(s->bs, &s->acct);
618 }
619 ide_set_inactive(s);
620}
621
622static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
623{
624 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
625 s->io_buffer_index = 0;
626 s->io_buffer_size = 0;
627 s->dma_cmd = dma_cmd;
628
629 switch (dma_cmd) {
630 case IDE_DMA_READ:
631 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
632 BDRV_ACCT_READ);
633 break;
634 case IDE_DMA_WRITE:
635 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
636 BDRV_ACCT_WRITE);
637 break;
638 default:
639 break;
640 }
641
642 s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb);
643}
644
645static void ide_sector_write_timer_cb(void *opaque)
646{
647 IDEState *s = opaque;
648 ide_set_irq(s->bus);
649}
650
651void ide_sector_write(IDEState *s)
652{
653 int64_t sector_num;
654 int ret, n, n1;
655
656 s->status = READY_STAT | SEEK_STAT;
657 sector_num = ide_get_sector(s);
658#if defined(DEBUG_IDE)
659 printf("write sector=%" PRId64 "\n", sector_num);
660#endif
661 n = s->nsector;
662 if (n > s->req_nb_sectors)
663 n = s->req_nb_sectors;
664
665 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
666 ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
667 bdrv_acct_done(s->bs, &s->acct);
668
669 if (ret != 0) {
670 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY))
671 return;
672 }
673
674 s->nsector -= n;
675 if (s->nsector == 0) {
676 /* no more sectors to write */
677 ide_transfer_stop(s);
678 } else {
679 n1 = s->nsector;
680 if (n1 > s->req_nb_sectors)
681 n1 = s->req_nb_sectors;
682 ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);
683 }
684 ide_set_sector(s, sector_num + n);
685
686 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
687 /* It seems there is a bug in the Windows 2000 installer HDD
688 IDE driver which fills the disk with empty logs when the
689 IDE write IRQ comes too early. This hack tries to correct
690 that at the expense of slower write performances. Use this
691 option _only_ to install Windows 2000. You must disable it
692 for normal use. */
693 qemu_mod_timer(s->sector_write_timer,
694 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000));
695 } else {
696 ide_set_irq(s->bus);
697 }
698}
699
700static void ide_flush_cb(void *opaque, int ret)
701{
702 IDEState *s = opaque;
703
704 if (ret < 0) {
705 /* XXX: What sector number to set here? */
706 if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) {
707 return;
708 }
709 }
710
711 bdrv_acct_done(s->bs, &s->acct);
712 s->status = READY_STAT | SEEK_STAT;
713 ide_set_irq(s->bus);
714}
715
716void ide_flush_cache(IDEState *s)
717{
718 BlockDriverAIOCB *acb;
719
720 if (s->bs == NULL) {
721 ide_flush_cb(s, 0);
722 return;
723 }
724
725 bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH);
726 acb = bdrv_aio_flush(s->bs, ide_flush_cb, s);
727 if (acb == NULL) {
728 ide_flush_cb(s, -EIO);
729 }
730}
731
732static void ide_cfata_metadata_inquiry(IDEState *s)
733{
734 uint16_t *p;
735 uint32_t spd;
736
737 p = (uint16_t *) s->io_buffer;
738 memset(p, 0, 0x200);
739 spd = ((s->mdata_size - 1) >> 9) + 1;
740
741 put_le16(p + 0, 0x0001); /* Data format revision */
742 put_le16(p + 1, 0x0000); /* Media property: silicon */
743 put_le16(p + 2, s->media_changed); /* Media status */
744 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
745 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
746 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
747 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
748}
749
750static void ide_cfata_metadata_read(IDEState *s)
751{
752 uint16_t *p;
753
754 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
755 s->status = ERR_STAT;
756 s->error = ABRT_ERR;
757 return;
758 }
759
760 p = (uint16_t *) s->io_buffer;
761 memset(p, 0, 0x200);
762
763 put_le16(p + 0, s->media_changed); /* Media status */
764 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
765 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
766 s->nsector << 9), 0x200 - 2));
767}
768
769static void ide_cfata_metadata_write(IDEState *s)
770{
771 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
772 s->status = ERR_STAT;
773 s->error = ABRT_ERR;
774 return;
775 }
776
777 s->media_changed = 0;
778
779 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
780 s->io_buffer + 2,
781 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
782 s->nsector << 9), 0x200 - 2));
783}
784
785/* called when the inserted state of the media has changed */
786static void ide_cd_change_cb(void *opaque)
787{
788 IDEState *s = opaque;
789 uint64_t nb_sectors;
790
791 bdrv_get_geometry(s->bs, &nb_sectors);
792 s->nb_sectors = nb_sectors;
793
794 /*
795 * First indicate to the guest that a CD has been removed. That's
796 * done on the next command the guest sends us.
797 *
798 * Then we set SENSE_UNIT_ATTENTION, by which the guest will
799 * detect a new CD in the drive. See ide_atapi_cmd() for details.
800 */
801 s->cdrom_changed = 1;
802 s->events.new_media = true;
803 ide_set_irq(s->bus);
804}
805
806static void ide_cmd_lba48_transform(IDEState *s, int lba48)
807{
808 s->lba48 = lba48;
809
810 /* handle the 'magic' 0 nsector count conversion here. to avoid
811 * fiddling with the rest of the read logic, we just store the
812 * full sector count in ->nsector and ignore ->hob_nsector from now
813 */
814 if (!s->lba48) {
815 if (!s->nsector)
816 s->nsector = 256;
817 } else {
818 if (!s->nsector && !s->hob_nsector)
819 s->nsector = 65536;
820 else {
821 int lo = s->nsector;
822 int hi = s->hob_nsector;
823
824 s->nsector = (hi << 8) | lo;
825 }
826 }
827}
828
829static void ide_clear_hob(IDEBus *bus)
830{
831 /* any write clears HOB high bit of device control register */
832 bus->ifs[0].select &= ~(1 << 7);
833 bus->ifs[1].select &= ~(1 << 7);
834}
835
836void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
837{
838 IDEBus *bus = opaque;
839
840#ifdef DEBUG_IDE
841 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
842#endif
843
844 addr &= 7;
845
846 /* ignore writes to command block while busy with previous command */
847 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
848 return;
849
850 switch(addr) {
851 case 0:
852 break;
853 case 1:
854 ide_clear_hob(bus);
855 /* NOTE: data is written to the two drives */
856 bus->ifs[0].hob_feature = bus->ifs[0].feature;
857 bus->ifs[1].hob_feature = bus->ifs[1].feature;
858 bus->ifs[0].feature = val;
859 bus->ifs[1].feature = val;
860 break;
861 case 2:
862 ide_clear_hob(bus);
863 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
864 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
865 bus->ifs[0].nsector = val;
866 bus->ifs[1].nsector = val;
867 break;
868 case 3:
869 ide_clear_hob(bus);
870 bus->ifs[0].hob_sector = bus->ifs[0].sector;
871 bus->ifs[1].hob_sector = bus->ifs[1].sector;
872 bus->ifs[0].sector = val;
873 bus->ifs[1].sector = val;
874 break;
875 case 4:
876 ide_clear_hob(bus);
877 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
878 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
879 bus->ifs[0].lcyl = val;
880 bus->ifs[1].lcyl = val;
881 break;
882 case 5:
883 ide_clear_hob(bus);
884 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
885 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
886 bus->ifs[0].hcyl = val;
887 bus->ifs[1].hcyl = val;
888 break;
889 case 6:
890 /* FIXME: HOB readback uses bit 7 */
891 bus->ifs[0].select = (val & ~0x10) | 0xa0;
892 bus->ifs[1].select = (val | 0x10) | 0xa0;
893 /* select drive */
894 bus->unit = (val >> 4) & 1;
895 break;
896 default:
897 case 7:
898 /* command */
899 ide_exec_cmd(bus, val);
900 break;
901 }
902}
903
904#define HD_OK (1u << IDE_HD)
905#define CD_OK (1u << IDE_CD)
906#define CFA_OK (1u << IDE_CFATA)
907#define HD_CFA_OK (HD_OK | CFA_OK)
908#define ALL_OK (HD_OK | CD_OK | CFA_OK)
909
910/* See ACS-2 T13/2015-D Table B.2 Command codes */
911static const uint8_t ide_cmd_table[0x100] = {
912 /* NOP not implemented, mandatory for CD */
913 [CFA_REQ_EXT_ERROR_CODE] = CFA_OK,
914 [WIN_DSM] = ALL_OK,
915 [WIN_DEVICE_RESET] = CD_OK,
916 [WIN_RECAL] = HD_CFA_OK,
917 [WIN_READ] = ALL_OK,
918 [WIN_READ_ONCE] = ALL_OK,
919 [WIN_READ_EXT] = HD_CFA_OK,
920 [WIN_READDMA_EXT] = HD_CFA_OK,
921 [WIN_READ_NATIVE_MAX_EXT] = HD_CFA_OK,
922 [WIN_MULTREAD_EXT] = HD_CFA_OK,
923 [WIN_WRITE] = HD_CFA_OK,
924 [WIN_WRITE_ONCE] = HD_CFA_OK,
925 [WIN_WRITE_EXT] = HD_CFA_OK,
926 [WIN_WRITEDMA_EXT] = HD_CFA_OK,
927 [CFA_WRITE_SECT_WO_ERASE] = CFA_OK,
928 [WIN_MULTWRITE_EXT] = HD_CFA_OK,
929 [WIN_WRITE_VERIFY] = HD_CFA_OK,
930 [WIN_VERIFY] = HD_CFA_OK,
931 [WIN_VERIFY_ONCE] = HD_CFA_OK,
932 [WIN_VERIFY_EXT] = HD_CFA_OK,
933 [WIN_SEEK] = HD_CFA_OK,
934 [CFA_TRANSLATE_SECTOR] = CFA_OK,
935 [WIN_DIAGNOSE] = ALL_OK,
936 [WIN_SPECIFY] = HD_CFA_OK,
937 [WIN_STANDBYNOW2] = ALL_OK,
938 [WIN_IDLEIMMEDIATE2] = ALL_OK,
939 [WIN_STANDBY2] = ALL_OK,
940 [WIN_SETIDLE2] = ALL_OK,
941 [WIN_CHECKPOWERMODE2] = ALL_OK,
942 [WIN_SLEEPNOW2] = ALL_OK,
943 [WIN_PACKETCMD] = CD_OK,
944 [WIN_PIDENTIFY] = CD_OK,
945 [WIN_SMART] = HD_CFA_OK,
946 [CFA_ACCESS_METADATA_STORAGE] = CFA_OK,
947 [CFA_ERASE_SECTORS] = CFA_OK,
948 [WIN_MULTREAD] = HD_CFA_OK,
949 [WIN_MULTWRITE] = HD_CFA_OK,
950 [WIN_SETMULT] = HD_CFA_OK,
951 [WIN_READDMA] = HD_CFA_OK,
952 [WIN_READDMA_ONCE] = HD_CFA_OK,
953 [WIN_WRITEDMA] = HD_CFA_OK,
954 [WIN_WRITEDMA_ONCE] = HD_CFA_OK,
955 [CFA_WRITE_MULTI_WO_ERASE] = CFA_OK,
956 [WIN_STANDBYNOW1] = ALL_OK,
957 [WIN_IDLEIMMEDIATE] = ALL_OK,
958 [WIN_STANDBY] = ALL_OK,
959 [WIN_SETIDLE1] = ALL_OK,
960 [WIN_CHECKPOWERMODE1] = ALL_OK,
961 [WIN_SLEEPNOW1] = ALL_OK,
962 [WIN_FLUSH_CACHE] = ALL_OK,
963 [WIN_FLUSH_CACHE_EXT] = HD_CFA_OK,
964 [WIN_IDENTIFY] = ALL_OK,
965 [WIN_SETFEATURES] = ALL_OK,
966 [IBM_SENSE_CONDITION] = CFA_OK,
967 [CFA_WEAR_LEVEL] = CFA_OK,
968 [WIN_READ_NATIVE_MAX] = ALL_OK,
969};
970
971static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
972{
973 return cmd < ARRAY_SIZE(ide_cmd_table)
974 && (ide_cmd_table[cmd] & (1u << s->drive_kind));
975}
976
977void ide_exec_cmd(IDEBus *bus, uint32_t val)
978{
979 IDEState *s;
980 int n;
981 int lba48 = 0;
982
983#if defined(DEBUG_IDE)
984 printf("ide: CMD=%02x\n", val);
985#endif
986 s = idebus_active_if(bus);
987 /* ignore commands to non existant slave */
988 if (s != bus->ifs && !s->bs)
989 return;
990
991 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
992 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
993 return;
994
995 if (!ide_cmd_permitted(s, val)) {
996 goto abort_cmd;
997 }
998
999 switch(val) {
1000 case WIN_DSM:
1001 switch (s->feature) {
1002 case DSM_TRIM:
1003 if (!s->bs) {
1004 goto abort_cmd;
1005 }
1006 ide_sector_start_dma(s, IDE_DMA_TRIM);
1007 break;
1008 default:
1009 goto abort_cmd;
1010 }
1011 break;
1012 case WIN_IDENTIFY:
1013 if (s->bs && s->drive_kind != IDE_CD) {
1014 if (s->drive_kind != IDE_CFATA)
1015 ide_identify(s);
1016 else
1017 ide_cfata_identify(s);
1018 s->status = READY_STAT | SEEK_STAT;
1019 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1020 } else {
1021 if (s->drive_kind == IDE_CD) {
1022 ide_set_signature(s);
1023 }
1024 ide_abort_command(s);
1025 }
1026 ide_set_irq(s->bus);
1027 break;
1028 case WIN_SPECIFY:
1029 case WIN_RECAL:
1030 s->error = 0;
1031 s->status = READY_STAT | SEEK_STAT;
1032 ide_set_irq(s->bus);
1033 break;
1034 case WIN_SETMULT:
1035 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1036 /* Disable Read and Write Multiple */
1037 s->mult_sectors = 0;
1038 s->status = READY_STAT | SEEK_STAT;
1039 } else if ((s->nsector & 0xff) != 0 &&
1040 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1041 (s->nsector & (s->nsector - 1)) != 0)) {
1042 ide_abort_command(s);
1043 } else {
1044 s->mult_sectors = s->nsector & 0xff;
1045 s->status = READY_STAT | SEEK_STAT;
1046 }
1047 ide_set_irq(s->bus);
1048 break;
1049 case WIN_VERIFY_EXT:
1050 lba48 = 1;
1051 case WIN_VERIFY:
1052 case WIN_VERIFY_ONCE:
1053 /* do sector number check ? */
1054 ide_cmd_lba48_transform(s, lba48);
1055 s->status = READY_STAT | SEEK_STAT;
1056 ide_set_irq(s->bus);
1057 break;
1058 case WIN_READ_EXT:
1059 lba48 = 1;
1060 case WIN_READ:
1061 case WIN_READ_ONCE:
1062 if (s->drive_kind == IDE_CD) {
1063 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1064 goto abort_cmd;
1065 }
1066 ide_cmd_lba48_transform(s, lba48);
1067 s->req_nb_sectors = 1;
1068 ide_sector_read(s);
1069 break;
1070 case WIN_WRITE_EXT:
1071 lba48 = 1;
1072 case WIN_WRITE:
1073 case WIN_WRITE_ONCE:
1074 case CFA_WRITE_SECT_WO_ERASE:
1075 case WIN_WRITE_VERIFY:
1076 ide_cmd_lba48_transform(s, lba48);
1077 s->error = 0;
1078 s->status = SEEK_STAT | READY_STAT;
1079 s->req_nb_sectors = 1;
1080 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1081 s->media_changed = 1;
1082 break;
1083 case WIN_MULTREAD_EXT:
1084 lba48 = 1;
1085 case WIN_MULTREAD:
1086 if (!s->mult_sectors)
1087 goto abort_cmd;
1088 ide_cmd_lba48_transform(s, lba48);
1089 s->req_nb_sectors = s->mult_sectors;
1090 ide_sector_read(s);
1091 break;
1092 case WIN_MULTWRITE_EXT:
1093 lba48 = 1;
1094 case WIN_MULTWRITE:
1095 case CFA_WRITE_MULTI_WO_ERASE:
1096 if (!s->mult_sectors)
1097 goto abort_cmd;
1098 ide_cmd_lba48_transform(s, lba48);
1099 s->error = 0;
1100 s->status = SEEK_STAT | READY_STAT;
1101 s->req_nb_sectors = s->mult_sectors;
1102 n = s->nsector;
1103 if (n > s->req_nb_sectors)
1104 n = s->req_nb_sectors;
1105 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1106 s->media_changed = 1;
1107 break;
1108 case WIN_READDMA_EXT:
1109 lba48 = 1;
1110 case WIN_READDMA:
1111 case WIN_READDMA_ONCE:
1112 if (!s->bs)
1113 goto abort_cmd;
1114 ide_cmd_lba48_transform(s, lba48);
1115 ide_sector_start_dma(s, IDE_DMA_READ);
1116 break;
1117 case WIN_WRITEDMA_EXT:
1118 lba48 = 1;
1119 case WIN_WRITEDMA:
1120 case WIN_WRITEDMA_ONCE:
1121 if (!s->bs)
1122 goto abort_cmd;
1123 ide_cmd_lba48_transform(s, lba48);
1124 ide_sector_start_dma(s, IDE_DMA_WRITE);
1125 s->media_changed = 1;
1126 break;
1127 case WIN_READ_NATIVE_MAX_EXT:
1128 lba48 = 1;
1129 case WIN_READ_NATIVE_MAX:
1130 ide_cmd_lba48_transform(s, lba48);
1131 ide_set_sector(s, s->nb_sectors - 1);
1132 s->status = READY_STAT | SEEK_STAT;
1133 ide_set_irq(s->bus);
1134 break;
1135 case WIN_CHECKPOWERMODE1:
1136 case WIN_CHECKPOWERMODE2:
1137 s->error = 0;
1138 s->nsector = 0xff; /* device active or idle */
1139 s->status = READY_STAT | SEEK_STAT;
1140 ide_set_irq(s->bus);
1141 break;
1142 case WIN_SETFEATURES:
1143 if (!s->bs)
1144 goto abort_cmd;
1145 /* XXX: valid for CDROM ? */
1146 switch(s->feature) {
1147 case 0xcc: /* reverting to power-on defaults enable */
1148 case 0x66: /* reverting to power-on defaults disable */
1149 case 0x02: /* write cache enable */
1150 case 0x82: /* write cache disable */
1151 case 0xaa: /* read look-ahead enable */
1152 case 0x55: /* read look-ahead disable */
1153 case 0x05: /* set advanced power management mode */
1154 case 0x85: /* disable advanced power management mode */
1155 case 0x69: /* NOP */
1156 case 0x67: /* NOP */
1157 case 0x96: /* NOP */
1158 case 0x9a: /* NOP */
1159 case 0x42: /* enable Automatic Acoustic Mode */
1160 case 0xc2: /* disable Automatic Acoustic Mode */
1161 s->status = READY_STAT | SEEK_STAT;
1162 ide_set_irq(s->bus);
1163 break;
1164 case 0x03: { /* set transfer mode */
1165 uint8_t val = s->nsector & 0x07;
1166 uint16_t *identify_data = (uint16_t *)s->identify_data;
1167
1168 switch (s->nsector >> 3) {
1169 case 0x00: /* pio default */
1170 case 0x01: /* pio mode */
1171 put_le16(identify_data + 62,0x07);
1172 put_le16(identify_data + 63,0x07);
1173 put_le16(identify_data + 88,0x3f);
1174 break;
1175 case 0x02: /* sigle word dma mode*/
1176 put_le16(identify_data + 62,0x07 | (1 << (val + 8)));
1177 put_le16(identify_data + 63,0x07);
1178 put_le16(identify_data + 88,0x3f);
1179 break;
1180 case 0x04: /* mdma mode */
1181 put_le16(identify_data + 62,0x07);
1182 put_le16(identify_data + 63,0x07 | (1 << (val + 8)));
1183 put_le16(identify_data + 88,0x3f);
1184 break;
1185 case 0x08: /* udma mode */
1186 put_le16(identify_data + 62,0x07);
1187 put_le16(identify_data + 63,0x07);
1188 put_le16(identify_data + 88,0x3f | (1 << (val + 8)));
1189 break;
1190 default:
1191 goto abort_cmd;
1192 }
1193 s->status = READY_STAT | SEEK_STAT;
1194 ide_set_irq(s->bus);
1195 break;
1196 }
1197 default:
1198 goto abort_cmd;
1199 }
1200 break;
1201 case WIN_FLUSH_CACHE:
1202 case WIN_FLUSH_CACHE_EXT:
1203 ide_flush_cache(s);
1204 break;
1205 case WIN_STANDBY:
1206 case WIN_STANDBY2:
1207 case WIN_STANDBYNOW1:
1208 case WIN_STANDBYNOW2:
1209 case WIN_IDLEIMMEDIATE:
1210 case WIN_IDLEIMMEDIATE2:
1211 case WIN_SETIDLE1:
1212 case WIN_SETIDLE2:
1213 case WIN_SLEEPNOW1:
1214 case WIN_SLEEPNOW2:
1215 s->status = READY_STAT;
1216 ide_set_irq(s->bus);
1217 break;
1218 case WIN_SEEK:
1219 /* XXX: Check that seek is within bounds */
1220 s->status = READY_STAT | SEEK_STAT;
1221 ide_set_irq(s->bus);
1222 break;
1223 /* ATAPI commands */
1224 case WIN_PIDENTIFY:
1225 ide_atapi_identify(s);
1226 s->status = READY_STAT | SEEK_STAT;
1227 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1228 ide_set_irq(s->bus);
1229 break;
1230 case WIN_DIAGNOSE:
1231 ide_set_signature(s);
1232 if (s->drive_kind == IDE_CD)
1233 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1234 * devices to return a clear status register
1235 * with READY_STAT *not* set. */
1236 else
1237 s->status = READY_STAT | SEEK_STAT;
1238 s->error = 0x01; /* Device 0 passed, Device 1 passed or not
1239 * present.
1240 */
1241 ide_set_irq(s->bus);
1242 break;
1243 case WIN_DEVICE_RESET:
1244 ide_set_signature(s);
1245 s->status = 0x00; /* NOTE: READY is _not_ set */
1246 s->error = 0x01;
1247 break;
1248 case WIN_PACKETCMD:
1249 /* overlapping commands not supported */
1250 if (s->feature & 0x02)
1251 goto abort_cmd;
1252 s->status = READY_STAT | SEEK_STAT;
1253 s->atapi_dma = s->feature & 1;
1254 s->nsector = 1;
1255 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1256 ide_atapi_cmd);
1257 break;
1258 /* CF-ATA commands */
1259 case CFA_REQ_EXT_ERROR_CODE:
1260 s->error = 0x09; /* miscellaneous error */
1261 s->status = READY_STAT | SEEK_STAT;
1262 ide_set_irq(s->bus);
1263 break;
1264 case CFA_ERASE_SECTORS:
1265 case CFA_WEAR_LEVEL:
1266 if (val == CFA_WEAR_LEVEL)
1267 s->nsector = 0;
1268 if (val == CFA_ERASE_SECTORS)
1269 s->media_changed = 1;
1270 s->error = 0x00;
1271 s->status = READY_STAT | SEEK_STAT;
1272 ide_set_irq(s->bus);
1273 break;
1274 case CFA_TRANSLATE_SECTOR:
1275 s->error = 0x00;
1276 s->status = READY_STAT | SEEK_STAT;
1277 memset(s->io_buffer, 0, 0x200);
1278 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1279 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1280 s->io_buffer[0x02] = s->select; /* Head */
1281 s->io_buffer[0x03] = s->sector; /* Sector */
1282 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1283 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1284 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1285 s->io_buffer[0x13] = 0x00; /* Erase flag */
1286 s->io_buffer[0x18] = 0x00; /* Hot count */
1287 s->io_buffer[0x19] = 0x00; /* Hot count */
1288 s->io_buffer[0x1a] = 0x01; /* Hot count */
1289 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1290 ide_set_irq(s->bus);
1291 break;
1292 case CFA_ACCESS_METADATA_STORAGE:
1293 switch (s->feature) {
1294 case 0x02: /* Inquiry Metadata Storage */
1295 ide_cfata_metadata_inquiry(s);
1296 break;
1297 case 0x03: /* Read Metadata Storage */
1298 ide_cfata_metadata_read(s);
1299 break;
1300 case 0x04: /* Write Metadata Storage */
1301 ide_cfata_metadata_write(s);
1302 break;
1303 default:
1304 goto abort_cmd;
1305 }
1306 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1307 s->status = 0x00; /* NOTE: READY is _not_ set */
1308 ide_set_irq(s->bus);
1309 break;
1310 case IBM_SENSE_CONDITION:
1311 switch (s->feature) {
1312 case 0x01: /* sense temperature in device */
1313 s->nsector = 0x50; /* +20 C */
1314 break;
1315 default:
1316 goto abort_cmd;
1317 }
1318 s->status = READY_STAT | SEEK_STAT;
1319 ide_set_irq(s->bus);
1320 break;
1321
1322 case WIN_SMART:
1323 if (s->hcyl != 0xc2 || s->lcyl != 0x4f)
1324 goto abort_cmd;
1325 if (!s->smart_enabled && s->feature != SMART_ENABLE)
1326 goto abort_cmd;
1327 switch (s->feature) {
1328 case SMART_DISABLE:
1329 s->smart_enabled = 0;
1330 s->status = READY_STAT | SEEK_STAT;
1331 ide_set_irq(s->bus);
1332 break;
1333 case SMART_ENABLE:
1334 s->smart_enabled = 1;
1335 s->status = READY_STAT | SEEK_STAT;
1336 ide_set_irq(s->bus);
1337 break;
1338 case SMART_ATTR_AUTOSAVE:
1339 switch (s->sector) {
1340 case 0x00:
1341 s->smart_autosave = 0;
1342 break;
1343 case 0xf1:
1344 s->smart_autosave = 1;
1345 break;
1346 default:
1347 goto abort_cmd;
1348 }
1349 s->status = READY_STAT | SEEK_STAT;
1350 ide_set_irq(s->bus);
1351 break;
1352 case SMART_STATUS:
1353 if (!s->smart_errors) {
1354 s->hcyl = 0xc2;
1355 s->lcyl = 0x4f;
1356 } else {
1357 s->hcyl = 0x2c;
1358 s->lcyl = 0xf4;
1359 }
1360 s->status = READY_STAT | SEEK_STAT;
1361 ide_set_irq(s->bus);
1362 break;
1363 case SMART_READ_THRESH:
1364 memset(s->io_buffer, 0, 0x200);
1365 s->io_buffer[0] = 0x01; /* smart struct version */
1366 for (n=0; n<30; n++) {
1367 if (smart_attributes[n][0] == 0)
1368 break;
1369 s->io_buffer[2+0+(n*12)] = smart_attributes[n][0];
1370 s->io_buffer[2+1+(n*12)] = smart_attributes[n][11];
1371 }
1372 for (n=0; n<511; n++) /* checksum */
1373 s->io_buffer[511] += s->io_buffer[n];
1374 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1375 s->status = READY_STAT | SEEK_STAT;
1376 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1377 ide_set_irq(s->bus);
1378 break;
1379 case SMART_READ_DATA:
1380 memset(s->io_buffer, 0, 0x200);
1381 s->io_buffer[0] = 0x01; /* smart struct version */
1382 for (n=0; n<30; n++) {
1383 if (smart_attributes[n][0] == 0) {
1384 break;
1385 }
1386 int i;
1387 for(i = 0; i < 11; i++) {
1388 s->io_buffer[2+i+(n*12)] = smart_attributes[n][i];
1389 }
1390 }
1391 s->io_buffer[362] = 0x02 | (s->smart_autosave?0x80:0x00);
1392 if (s->smart_selftest_count == 0) {
1393 s->io_buffer[363] = 0;
1394 } else {
1395 s->io_buffer[363] =
1396 s->smart_selftest_data[3 +
1397 (s->smart_selftest_count - 1) *
1398 24];
1399 }
1400 s->io_buffer[364] = 0x20;
1401 s->io_buffer[365] = 0x01;
1402 /* offline data collection capacity: execute + self-test*/
1403 s->io_buffer[367] = (1<<4 | 1<<3 | 1);
1404 s->io_buffer[368] = 0x03; /* smart capability (1) */
1405 s->io_buffer[369] = 0x00; /* smart capability (2) */
1406 s->io_buffer[370] = 0x01; /* error logging supported */
1407 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1408 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1409 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1410
1411 for (n=0; n<511; n++)
1412 s->io_buffer[511] += s->io_buffer[n];
1413 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1414 s->status = READY_STAT | SEEK_STAT;
1415 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1416 ide_set_irq(s->bus);
1417 break;
1418 case SMART_READ_LOG:
1419 switch (s->sector) {
1420 case 0x01: /* summary smart error log */
1421 memset(s->io_buffer, 0, 0x200);
1422 s->io_buffer[0] = 0x01;
1423 s->io_buffer[1] = 0x00; /* no error entries */
1424 s->io_buffer[452] = s->smart_errors & 0xff;
1425 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1426
1427 for (n=0; n<511; n++)
1428 s->io_buffer[511] += s->io_buffer[n];
1429 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1430 break;
1431 case 0x06: /* smart self test log */
1432 memset(s->io_buffer, 0, 0x200);
1433 s->io_buffer[0] = 0x01;
1434 if (s->smart_selftest_count == 0) {
1435 s->io_buffer[508] = 0;
1436 } else {
1437 s->io_buffer[508] = s->smart_selftest_count;
1438 for (n=2; n<506; n++)
1439 s->io_buffer[n] = s->smart_selftest_data[n];
1440 }
1441 for (n=0; n<511; n++)
1442 s->io_buffer[511] += s->io_buffer[n];
1443 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1444 break;
1445 default:
1446 goto abort_cmd;
1447 }
1448 s->status = READY_STAT | SEEK_STAT;
1449 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1450 ide_set_irq(s->bus);
1451 break;
1452 case SMART_EXECUTE_OFFLINE:
1453 switch (s->sector) {
1454 case 0: /* off-line routine */
1455 case 1: /* short self test */
1456 case 2: /* extended self test */
1457 s->smart_selftest_count++;
1458 if(s->smart_selftest_count > 21)
1459 s->smart_selftest_count = 0;
1460 n = 2 + (s->smart_selftest_count - 1) * 24;
1461 s->smart_selftest_data[n] = s->sector;
1462 s->smart_selftest_data[n+1] = 0x00; /* OK and finished */
1463 s->smart_selftest_data[n+2] = 0x34; /* hour count lsb */
1464 s->smart_selftest_data[n+3] = 0x12; /* hour count msb */
1465 s->status = READY_STAT | SEEK_STAT;
1466 ide_set_irq(s->bus);
1467 break;
1468 default:
1469 goto abort_cmd;
1470 }
1471 break;
1472 default:
1473 goto abort_cmd;
1474 }
1475 break;
1476 default:
1477 /* should not be reachable */
1478 abort_cmd:
1479 ide_abort_command(s);
1480 ide_set_irq(s->bus);
1481 break;
1482 }
1483}
1484
1485uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
1486{
1487 IDEBus *bus = opaque;
1488 IDEState *s = idebus_active_if(bus);
1489 uint32_t addr;
1490 int ret, hob;
1491
1492 addr = addr1 & 7;
1493 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1494 //hob = s->select & (1 << 7);
1495 hob = 0;
1496 switch(addr) {
1497 case 0:
1498 ret = 0xff;
1499 break;
1500 case 1:
1501 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1502 (s != bus->ifs && !s->bs))
1503 ret = 0;
1504 else if (!hob)
1505 ret = s->error;
1506 else
1507 ret = s->hob_feature;
1508 break;
1509 case 2:
1510 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1511 ret = 0;
1512 else if (!hob)
1513 ret = s->nsector & 0xff;
1514 else
1515 ret = s->hob_nsector;
1516 break;
1517 case 3:
1518 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1519 ret = 0;
1520 else if (!hob)
1521 ret = s->sector;
1522 else
1523 ret = s->hob_sector;
1524 break;
1525 case 4:
1526 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1527 ret = 0;
1528 else if (!hob)
1529 ret = s->lcyl;
1530 else
1531 ret = s->hob_lcyl;
1532 break;
1533 case 5:
1534 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1535 ret = 0;
1536 else if (!hob)
1537 ret = s->hcyl;
1538 else
1539 ret = s->hob_hcyl;
1540 break;
1541 case 6:
1542 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1543 ret = 0;
1544 else
1545 ret = s->select;
1546 break;
1547 default:
1548 case 7:
1549 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1550 (s != bus->ifs && !s->bs))
1551 ret = 0;
1552 else
1553 ret = s->status;
1554 qemu_irq_lower(bus->irq);
1555 break;
1556 }
1557#ifdef DEBUG_IDE
1558 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1559#endif
1560 return ret;
1561}
1562
1563uint32_t ide_status_read(void *opaque, uint32_t addr)
1564{
1565 IDEBus *bus = opaque;
1566 IDEState *s = idebus_active_if(bus);
1567 int ret;
1568
1569 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1570 (s != bus->ifs && !s->bs))
1571 ret = 0;
1572 else
1573 ret = s->status;
1574#ifdef DEBUG_IDE
1575 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1576#endif
1577 return ret;
1578}
1579
1580void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
1581{
1582 IDEBus *bus = opaque;
1583 IDEState *s;
1584 int i;
1585
1586#ifdef DEBUG_IDE
1587 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1588#endif
1589 /* common for both drives */
1590 if (!(bus->cmd & IDE_CMD_RESET) &&
1591 (val & IDE_CMD_RESET)) {
1592 /* reset low to high */
1593 for(i = 0;i < 2; i++) {
1594 s = &bus->ifs[i];
1595 s->status = BUSY_STAT | SEEK_STAT;
1596 s->error = 0x01;
1597 }
1598 } else if ((bus->cmd & IDE_CMD_RESET) &&
1599 !(val & IDE_CMD_RESET)) {
1600 /* high to low */
1601 for(i = 0;i < 2; i++) {
1602 s = &bus->ifs[i];
1603 if (s->drive_kind == IDE_CD)
1604 s->status = 0x00; /* NOTE: READY is _not_ set */
1605 else
1606 s->status = READY_STAT | SEEK_STAT;
1607 ide_set_signature(s);
1608 }
1609 }
1610
1611 bus->cmd = val;
1612}
1613
1614/*
1615 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1616 * transferred from the device to the guest), false if it's a PIO in
1617 */
1618static bool ide_is_pio_out(IDEState *s)
1619{
1620 if (s->end_transfer_func == ide_sector_write ||
1621 s->end_transfer_func == ide_atapi_cmd) {
1622 return false;
1623 } else if (s->end_transfer_func == ide_sector_read ||
1624 s->end_transfer_func == ide_transfer_stop ||
1625 s->end_transfer_func == ide_atapi_cmd_reply_end ||
1626 s->end_transfer_func == ide_dummy_transfer_stop) {
1627 return true;
1628 }
1629
1630 abort();
1631}
1632
1633void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
1634{
1635 IDEBus *bus = opaque;
1636 IDEState *s = idebus_active_if(bus);
1637 uint8_t *p;
1638
1639 /* PIO data access allowed only when DRQ bit is set. The result of a write
1640 * during PIO out is indeterminate, just ignore it. */
1641 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
1642 return;
1643 }
1644
1645 p = s->data_ptr;
1646 *(uint16_t *)p = le16_to_cpu(val);
1647 p += 2;
1648 s->data_ptr = p;
1649 if (p >= s->data_end)
1650 s->end_transfer_func(s);
1651}
1652
1653uint32_t ide_data_readw(void *opaque, uint32_t addr)
1654{
1655 IDEBus *bus = opaque;
1656 IDEState *s = idebus_active_if(bus);
1657 uint8_t *p;
1658 int ret;
1659
1660 /* PIO data access allowed only when DRQ bit is set. The result of a read
1661 * during PIO in is indeterminate, return 0 and don't move forward. */
1662 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
1663 return 0;
1664 }
1665
1666 p = s->data_ptr;
1667 ret = cpu_to_le16(*(uint16_t *)p);
1668 p += 2;
1669 s->data_ptr = p;
1670 if (p >= s->data_end)
1671 s->end_transfer_func(s);
1672 return ret;
1673}
1674
1675void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
1676{
1677 IDEBus *bus = opaque;
1678 IDEState *s = idebus_active_if(bus);
1679 uint8_t *p;
1680
1681 /* PIO data access allowed only when DRQ bit is set. The result of a write
1682 * during PIO out is indeterminate, just ignore it. */
1683 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
1684 return;
1685 }
1686
1687 p = s->data_ptr;
1688 *(uint32_t *)p = le32_to_cpu(val);
1689 p += 4;
1690 s->data_ptr = p;
1691 if (p >= s->data_end)
1692 s->end_transfer_func(s);
1693}
1694
1695uint32_t ide_data_readl(void *opaque, uint32_t addr)
1696{
1697 IDEBus *bus = opaque;
1698 IDEState *s = idebus_active_if(bus);
1699 uint8_t *p;
1700 int ret;
1701
1702 /* PIO data access allowed only when DRQ bit is set. The result of a read
1703 * during PIO in is indeterminate, return 0 and don't move forward. */
1704 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
1705 return 0;
1706 }
1707
1708 p = s->data_ptr;
1709 ret = cpu_to_le32(*(uint32_t *)p);
1710 p += 4;
1711 s->data_ptr = p;
1712 if (p >= s->data_end)
1713 s->end_transfer_func(s);
1714 return ret;
1715}
1716
1717static void ide_dummy_transfer_stop(IDEState *s)
1718{
1719 s->data_ptr = s->io_buffer;
1720 s->data_end = s->io_buffer;
1721 s->io_buffer[0] = 0xff;
1722 s->io_buffer[1] = 0xff;
1723 s->io_buffer[2] = 0xff;
1724 s->io_buffer[3] = 0xff;
1725}
1726
1727static void ide_reset(IDEState *s)
1728{
1729#ifdef DEBUG_IDE
1730 printf("ide: reset\n");
1731#endif
1732 if (s->drive_kind == IDE_CFATA)
1733 s->mult_sectors = 0;
1734 else
1735 s->mult_sectors = MAX_MULT_SECTORS;
1736 /* ide regs */
1737 s->feature = 0;
1738 s->error = 0;
1739 s->nsector = 0;
1740 s->sector = 0;
1741 s->lcyl = 0;
1742 s->hcyl = 0;
1743
1744 /* lba48 */
1745 s->hob_feature = 0;
1746 s->hob_sector = 0;
1747 s->hob_nsector = 0;
1748 s->hob_lcyl = 0;
1749 s->hob_hcyl = 0;
1750
1751 s->select = 0xa0;
1752 s->status = READY_STAT | SEEK_STAT;
1753
1754 s->lba48 = 0;
1755
1756 /* ATAPI specific */
1757 s->sense_key = 0;
1758 s->asc = 0;
1759 s->cdrom_changed = 0;
1760 s->packet_transfer_size = 0;
1761 s->elementary_transfer_size = 0;
1762 s->io_buffer_index = 0;
1763 s->cd_sector_size = 0;
1764 s->atapi_dma = 0;
1765 /* ATA DMA state */
1766 s->io_buffer_size = 0;
1767 s->req_nb_sectors = 0;
1768
1769 ide_set_signature(s);
1770 /* init the transfer handler so that 0xffff is returned on data
1771 accesses */
1772 s->end_transfer_func = ide_dummy_transfer_stop;
1773 ide_dummy_transfer_stop(s);
1774 s->media_changed = 0;
1775}
1776
1777void ide_bus_reset(IDEBus *bus)
1778{
1779 bus->unit = 0;
1780 bus->cmd = 0;
1781 ide_reset(&bus->ifs[0]);
1782 ide_reset(&bus->ifs[1]);
1783 ide_clear_hob(bus);
1784
1785 /* pending async DMA */
1786 if (bus->dma->aiocb) {
1787#ifdef DEBUG_AIO
1788 printf("aio_cancel\n");
1789#endif
1790 bdrv_aio_cancel(bus->dma->aiocb);
1791 bus->dma->aiocb = NULL;
1792 }
1793
1794 /* reset dma provider too */
1795 bus->dma->ops->reset(bus->dma);
1796}
1797
1798static bool ide_cd_is_medium_locked(void *opaque)
1799{
1800 return ((IDEState *)opaque)->tray_locked;
1801}
1802
1803static const BlockDevOps ide_cd_block_ops = {
1804 .change_media_cb = ide_cd_change_cb,
1805 .is_medium_locked = ide_cd_is_medium_locked,
1806};
1807
1808int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind,
1809 const char *version, const char *serial)
1810{
1811 int cylinders, heads, secs;
1812 uint64_t nb_sectors;
1813
1814 s->bs = bs;
1815 s->drive_kind = kind;
1816
1817 bdrv_get_geometry(bs, &nb_sectors);
1818 bdrv_guess_geometry(bs, &cylinders, &heads, &secs);
1819 if (cylinders < 1 || cylinders > 16383) {
1820 error_report("cyls must be between 1 and 16383");
1821 return -1;
1822 }
1823 if (heads < 1 || heads > 16) {
1824 error_report("heads must be between 1 and 16");
1825 return -1;
1826 }
1827 if (secs < 1 || secs > 63) {
1828 error_report("secs must be between 1 and 63");
1829 return -1;
1830 }
1831 s->cylinders = cylinders;
1832 s->heads = heads;
1833 s->sectors = secs;
1834 s->nb_sectors = nb_sectors;
1835 /* The SMART values should be preserved across power cycles
1836 but they aren't. */
1837 s->smart_enabled = 1;
1838 s->smart_autosave = 1;
1839 s->smart_errors = 0;
1840 s->smart_selftest_count = 0;
1841 if (kind == IDE_CD) {
1842 bdrv_set_dev_ops(bs, &ide_cd_block_ops, s);
1843 bs->buffer_alignment = 2048;
1844 } else {
1845 if (!bdrv_is_inserted(s->bs)) {
1846 error_report("Device needs media, but drive is empty");
1847 return -1;
1848 }
1849 if (bdrv_is_read_only(bs)) {
1850 error_report("Can't use a read-only drive");
1851 return -1;
1852 }
1853 }
1854 if (serial) {
1855 strncpy(s->drive_serial_str, serial, sizeof(s->drive_serial_str));
1856 } else {
1857 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
1858 "QM%05d", s->drive_serial);
1859 }
1860 if (version) {
1861 pstrcpy(s->version, sizeof(s->version), version);
1862 } else {
1863 pstrcpy(s->version, sizeof(s->version), QEMU_VERSION);
1864 }
1865
1866 ide_reset(s);
1867 return 0;
1868}
1869
1870static void ide_init1(IDEBus *bus, int unit)
1871{
1872 static int drive_serial = 1;
1873 IDEState *s = &bus->ifs[unit];
1874
1875 s->bus = bus;
1876 s->unit = unit;
1877 s->drive_serial = drive_serial++;
1878 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
1879 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
1880 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
1881 memset(s->io_buffer, 0, s->io_buffer_total_len);
1882
1883 s->smart_selftest_data = qemu_blockalign(s->bs, 512);
1884 memset(s->smart_selftest_data, 0, 512);
1885
1886 s->sector_write_timer = qemu_new_timer_ns(vm_clock,
1887 ide_sector_write_timer_cb, s);
1888}
1889
1890static void ide_nop_start(IDEDMA *dma, IDEState *s,
1891 BlockDriverCompletionFunc *cb)
1892{
1893}
1894
1895static int ide_nop(IDEDMA *dma)
1896{
1897 return 0;
1898}
1899
1900static int ide_nop_int(IDEDMA *dma, int x)
1901{
1902 return 0;
1903}
1904
1905static void ide_nop_restart(void *opaque, int x, int y)
1906{
1907}
1908
1909static const IDEDMAOps ide_dma_nop_ops = {
1910 .start_dma = ide_nop_start,
1911 .start_transfer = ide_nop,
1912 .prepare_buf = ide_nop_int,
1913 .rw_buf = ide_nop_int,
1914 .set_unit = ide_nop_int,
1915 .add_status = ide_nop_int,
1916 .set_inactive = ide_nop,
1917 .restart_cb = ide_nop_restart,
1918 .reset = ide_nop,
1919};
1920
1921static IDEDMA ide_dma_nop = {
1922 .ops = &ide_dma_nop_ops,
1923 .aiocb = NULL,
1924};
1925
1926void ide_init2(IDEBus *bus, qemu_irq irq)
1927{
1928 int i;
1929
1930 for(i = 0; i < 2; i++) {
1931 ide_init1(bus, i);
1932 ide_reset(&bus->ifs[i]);
1933 }
1934 bus->irq = irq;
1935 bus->dma = &ide_dma_nop;
1936}
1937
1938/* TODO convert users to qdev and remove */
1939void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0,
1940 DriveInfo *hd1, qemu_irq irq)
1941{
1942 int i;
1943 DriveInfo *dinfo;
1944
1945 for(i = 0; i < 2; i++) {
1946 dinfo = i == 0 ? hd0 : hd1;
1947 ide_init1(bus, i);
1948 if (dinfo) {
1949 if (ide_init_drive(&bus->ifs[i], dinfo->bdrv,
1950 dinfo->media_cd ? IDE_CD : IDE_HD, NULL,
1951 *dinfo->serial ? dinfo->serial : NULL) < 0) {
1952 error_report("Can't set up IDE drive %s", dinfo->id);
1953 exit(1);
1954 }
1955 bdrv_attach_dev_nofail(dinfo->bdrv, &bus->ifs[i]);
1956 } else {
1957 ide_reset(&bus->ifs[i]);
1958 }
1959 }
1960 bus->irq = irq;
1961 bus->dma = &ide_dma_nop;
1962}
1963
1964void ide_init_ioport(IDEBus *bus, int iobase, int iobase2)
1965{
1966 register_ioport_write(iobase, 8, 1, ide_ioport_write, bus);
1967 register_ioport_read(iobase, 8, 1, ide_ioport_read, bus);
1968 if (iobase2) {
1969 register_ioport_read(iobase2, 1, 1, ide_status_read, bus);
1970 register_ioport_write(iobase2, 1, 1, ide_cmd_write, bus);
1971 }
1972
1973 /* data ports */
1974 register_ioport_write(iobase, 2, 2, ide_data_writew, bus);
1975 register_ioport_read(iobase, 2, 2, ide_data_readw, bus);
1976 register_ioport_write(iobase, 4, 4, ide_data_writel, bus);
1977 register_ioport_read(iobase, 4, 4, ide_data_readl, bus);
1978}
1979
1980static bool is_identify_set(void *opaque, int version_id)
1981{
1982 IDEState *s = opaque;
1983
1984 return s->identify_set != 0;
1985}
1986
1987static EndTransferFunc* transfer_end_table[] = {
1988 ide_sector_read,
1989 ide_sector_write,
1990 ide_transfer_stop,
1991 ide_atapi_cmd_reply_end,
1992 ide_atapi_cmd,
1993 ide_dummy_transfer_stop,
1994};
1995
1996static int transfer_end_table_idx(EndTransferFunc *fn)
1997{
1998 int i;
1999
2000 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2001 if (transfer_end_table[i] == fn)
2002 return i;
2003
2004 return -1;
2005}
2006
2007static int ide_drive_post_load(void *opaque, int version_id)
2008{
2009 IDEState *s = opaque;
2010
2011 if (version_id < 3) {
2012 if (s->sense_key == SENSE_UNIT_ATTENTION &&
2013 s->asc == ASC_MEDIUM_MAY_HAVE_CHANGED) {
2014 s->cdrom_changed = 1;
2015 }
2016 }
2017 return 0;
2018}
2019
2020static int ide_drive_pio_post_load(void *opaque, int version_id)
2021{
2022 IDEState *s = opaque;
2023
2024 if (s->end_transfer_fn_idx > ARRAY_SIZE(transfer_end_table)) {
2025 return -EINVAL;
2026 }
2027 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2028 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2029 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2030
2031 return 0;
2032}
2033
2034static void ide_drive_pio_pre_save(void *opaque)
2035{
2036 IDEState *s = opaque;
2037 int idx;
2038
2039 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2040 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2041
2042 idx = transfer_end_table_idx(s->end_transfer_func);
2043 if (idx == -1) {
2044 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2045 __func__);
2046 s->end_transfer_fn_idx = 2;
2047 } else {
2048 s->end_transfer_fn_idx = idx;
2049 }
2050}
2051
2052static bool ide_drive_pio_state_needed(void *opaque)
2053{
2054 IDEState *s = opaque;
2055
2056 return ((s->status & DRQ_STAT) != 0)
2057 || (s->bus->error_status & BM_STATUS_PIO_RETRY);
2058}
2059
2060static int ide_tray_state_post_load(void *opaque, int version_id)
2061{
2062 IDEState *s = opaque;
2063
2064 bdrv_eject(s->bs, s->tray_open);
2065 bdrv_lock_medium(s->bs, s->tray_locked);
2066 return 0;
2067}
2068
2069static bool ide_tray_state_needed(void *opaque)
2070{
2071 IDEState *s = opaque;
2072
2073 return s->tray_open || s->tray_locked;
2074}
2075
2076static bool ide_atapi_gesn_needed(void *opaque)
2077{
2078 IDEState *s = opaque;
2079
2080 return s->events.new_media || s->events.eject_request;
2081}
2082
2083static bool ide_error_needed(void *opaque)
2084{
2085 IDEBus *bus = opaque;
2086
2087 return (bus->error_status != 0);
2088}
2089
2090/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
2091static const VMStateDescription vmstate_ide_atapi_gesn_state = {
2092 .name ="ide_drive/atapi/gesn_state",
2093 .version_id = 1,
2094 .minimum_version_id = 1,
2095 .minimum_version_id_old = 1,
2096 .fields = (VMStateField []) {
2097 VMSTATE_BOOL(events.new_media, IDEState),
2098 VMSTATE_BOOL(events.eject_request, IDEState),
2099 VMSTATE_END_OF_LIST()
2100 }
2101};
2102
2103static const VMStateDescription vmstate_ide_tray_state = {
2104 .name = "ide_drive/tray_state",
2105 .version_id = 1,
2106 .minimum_version_id = 1,
2107 .minimum_version_id_old = 1,
2108 .post_load = ide_tray_state_post_load,
2109 .fields = (VMStateField[]) {
2110 VMSTATE_BOOL(tray_open, IDEState),
2111 VMSTATE_BOOL(tray_locked, IDEState),
2112 VMSTATE_END_OF_LIST()
2113 }
2114};
2115
2116static const VMStateDescription vmstate_ide_drive_pio_state = {
2117 .name = "ide_drive/pio_state",
2118 .version_id = 1,
2119 .minimum_version_id = 1,
2120 .minimum_version_id_old = 1,
2121 .pre_save = ide_drive_pio_pre_save,
2122 .post_load = ide_drive_pio_post_load,
2123 .fields = (VMStateField []) {
2124 VMSTATE_INT32(req_nb_sectors, IDEState),
2125 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2126 vmstate_info_uint8, uint8_t),
2127 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2128 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2129 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2130 VMSTATE_INT32(elementary_transfer_size, IDEState),
2131 VMSTATE_INT32(packet_transfer_size, IDEState),
2132 VMSTATE_END_OF_LIST()
2133 }
2134};
2135
2136const VMStateDescription vmstate_ide_drive = {
2137 .name = "ide_drive",
2138 .version_id = 3,
2139 .minimum_version_id = 0,
2140 .minimum_version_id_old = 0,
2141 .post_load = ide_drive_post_load,
2142 .fields = (VMStateField []) {
2143 VMSTATE_INT32(mult_sectors, IDEState),
2144 VMSTATE_INT32(identify_set, IDEState),
2145 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2146 VMSTATE_UINT8(feature, IDEState),
2147 VMSTATE_UINT8(error, IDEState),
2148 VMSTATE_UINT32(nsector, IDEState),
2149 VMSTATE_UINT8(sector, IDEState),
2150 VMSTATE_UINT8(lcyl, IDEState),
2151 VMSTATE_UINT8(hcyl, IDEState),
2152 VMSTATE_UINT8(hob_feature, IDEState),
2153 VMSTATE_UINT8(hob_sector, IDEState),
2154 VMSTATE_UINT8(hob_nsector, IDEState),
2155 VMSTATE_UINT8(hob_lcyl, IDEState),
2156 VMSTATE_UINT8(hob_hcyl, IDEState),
2157 VMSTATE_UINT8(select, IDEState),
2158 VMSTATE_UINT8(status, IDEState),
2159 VMSTATE_UINT8(lba48, IDEState),
2160 VMSTATE_UINT8(sense_key, IDEState),
2161 VMSTATE_UINT8(asc, IDEState),
2162 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
2163 VMSTATE_END_OF_LIST()
2164 },
2165 .subsections = (VMStateSubsection []) {
2166 {
2167 .vmsd = &vmstate_ide_drive_pio_state,
2168 .needed = ide_drive_pio_state_needed,
2169 }, {
2170 .vmsd = &vmstate_ide_tray_state,
2171 .needed = ide_tray_state_needed,
2172 }, {
2173 .vmsd = &vmstate_ide_atapi_gesn_state,
2174 .needed = ide_atapi_gesn_needed,
2175 }, {
2176 /* empty */
2177 }
2178 }
2179};
2180
2181static const VMStateDescription vmstate_ide_error_status = {
2182 .name ="ide_bus/error",
2183 .version_id = 1,
2184 .minimum_version_id = 1,
2185 .minimum_version_id_old = 1,
2186 .fields = (VMStateField []) {
2187 VMSTATE_INT32(error_status, IDEBus),
2188 VMSTATE_END_OF_LIST()
2189 }
2190};
2191
2192const VMStateDescription vmstate_ide_bus = {
2193 .name = "ide_bus",
2194 .version_id = 1,
2195 .minimum_version_id = 1,
2196 .minimum_version_id_old = 1,
2197 .fields = (VMStateField []) {
2198 VMSTATE_UINT8(cmd, IDEBus),
2199 VMSTATE_UINT8(unit, IDEBus),
2200 VMSTATE_END_OF_LIST()
2201 },
2202 .subsections = (VMStateSubsection []) {
2203 {
2204 .vmsd = &vmstate_ide_error_status,
2205 .needed = ide_error_needed,
2206 }, {
2207 /* empty */
2208 }
2209 }
2210};
2211
2212void ide_drive_get(DriveInfo **hd, int max_bus)
2213{
2214 int i;
2215
2216 if (drive_get_max_bus(IF_IDE) >= max_bus) {
2217 fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
2218 exit(1);
2219 }
2220
2221 for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
2222 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
2223 }
2224}
Qemu copy for testing