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1 | /* | |
2 | * QEMU/MIPS pseudo-board | |
3 | * | |
4 | * emulates a simple machine with ISA-like bus. | |
5 | * ISA IO space mapped to the 0x14000000 (PHYS) and | |
6 | * ISA memory at the 0x10000000 (PHYS, 16Mb in size). | |
7 | * All peripherial devices are attached to this "bus" with | |
8 | * the standard PC ISA addresses. | |
9 | */ | |
10 | #include "hw.h" | |
11 | #include "mips.h" | |
12 | #include "mips_cpudevs.h" | |
13 | #include "pc.h" | |
14 | #include "serial.h" | |
15 | #include "isa.h" | |
16 | #include "net.h" | |
17 | #include "sysemu.h" | |
18 | #include "boards.h" | |
19 | #include "flash.h" | |
20 | #include "qemu-log.h" | |
21 | #include "mips-bios.h" | |
22 | #include "ide.h" | |
23 | #include "loader.h" | |
24 | #include "elf.h" | |
25 | #include "mc146818rtc.h" | |
26 | #include "i8254.h" | |
27 | #include "blockdev.h" | |
28 | #include "exec-memory.h" | |
29 | ||
30 | #define MAX_IDE_BUS 2 | |
31 | ||
32 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; | |
33 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
34 | static const int ide_irq[2] = { 14, 15 }; | |
35 | ||
36 | static ISADevice *pit; /* PIT i8254 */ | |
37 | ||
38 | /* i8254 PIT is attached to the IRQ0 at PIC i8259 */ | |
39 | ||
40 | static struct _loaderparams { | |
41 | int ram_size; | |
42 | const char *kernel_filename; | |
43 | const char *kernel_cmdline; | |
44 | const char *initrd_filename; | |
45 | } loaderparams; | |
46 | ||
47 | static void mips_qemu_write (void *opaque, hwaddr addr, | |
48 | uint64_t val, unsigned size) | |
49 | { | |
50 | if ((addr & 0xffff) == 0 && val == 42) | |
51 | qemu_system_reset_request (); | |
52 | else if ((addr & 0xffff) == 4 && val == 42) | |
53 | qemu_system_shutdown_request (); | |
54 | } | |
55 | ||
56 | static uint64_t mips_qemu_read (void *opaque, hwaddr addr, | |
57 | unsigned size) | |
58 | { | |
59 | return 0; | |
60 | } | |
61 | ||
62 | static const MemoryRegionOps mips_qemu_ops = { | |
63 | .read = mips_qemu_read, | |
64 | .write = mips_qemu_write, | |
65 | .endianness = DEVICE_NATIVE_ENDIAN, | |
66 | }; | |
67 | ||
68 | typedef struct ResetData { | |
69 | MIPSCPU *cpu; | |
70 | uint64_t vector; | |
71 | } ResetData; | |
72 | ||
73 | static int64_t load_kernel(void) | |
74 | { | |
75 | int64_t entry, kernel_high; | |
76 | long kernel_size, initrd_size, params_size; | |
77 | ram_addr_t initrd_offset; | |
78 | uint32_t *params_buf; | |
79 | int big_endian; | |
80 | ||
81 | #ifdef TARGET_WORDS_BIGENDIAN | |
82 | big_endian = 1; | |
83 | #else | |
84 | big_endian = 0; | |
85 | #endif | |
86 | kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, | |
87 | NULL, (uint64_t *)&entry, NULL, | |
88 | (uint64_t *)&kernel_high, big_endian, | |
89 | ELF_MACHINE, 1); | |
90 | if (kernel_size >= 0) { | |
91 | if ((entry & ~0x7fffffffULL) == 0x80000000) | |
92 | entry = (int32_t)entry; | |
93 | } else { | |
94 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
95 | loaderparams.kernel_filename); | |
96 | exit(1); | |
97 | } | |
98 | ||
99 | /* load initrd */ | |
100 | initrd_size = 0; | |
101 | initrd_offset = 0; | |
102 | if (loaderparams.initrd_filename) { | |
103 | initrd_size = get_image_size (loaderparams.initrd_filename); | |
104 | if (initrd_size > 0) { | |
105 | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; | |
106 | if (initrd_offset + initrd_size > ram_size) { | |
107 | fprintf(stderr, | |
108 | "qemu: memory too small for initial ram disk '%s'\n", | |
109 | loaderparams.initrd_filename); | |
110 | exit(1); | |
111 | } | |
112 | initrd_size = load_image_targphys(loaderparams.initrd_filename, | |
113 | initrd_offset, | |
114 | ram_size - initrd_offset); | |
115 | } | |
116 | if (initrd_size == (target_ulong) -1) { | |
117 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
118 | loaderparams.initrd_filename); | |
119 | exit(1); | |
120 | } | |
121 | } | |
122 | ||
123 | /* Store command line. */ | |
124 | params_size = 264; | |
125 | params_buf = g_malloc(params_size); | |
126 | ||
127 | params_buf[0] = tswap32(ram_size); | |
128 | params_buf[1] = tswap32(0x12345678); | |
129 | ||
130 | if (initrd_size > 0) { | |
131 | snprintf((char *)params_buf + 8, 256, "rd_start=0x%" PRIx64 " rd_size=%li %s", | |
132 | cpu_mips_phys_to_kseg0(NULL, initrd_offset), | |
133 | initrd_size, loaderparams.kernel_cmdline); | |
134 | } else { | |
135 | snprintf((char *)params_buf + 8, 256, "%s", loaderparams.kernel_cmdline); | |
136 | } | |
137 | ||
138 | rom_add_blob_fixed("params", params_buf, params_size, | |
139 | (16 << 20) - 264); | |
140 | ||
141 | return entry; | |
142 | } | |
143 | ||
144 | static void main_cpu_reset(void *opaque) | |
145 | { | |
146 | ResetData *s = (ResetData *)opaque; | |
147 | CPUMIPSState *env = &s->cpu->env; | |
148 | ||
149 | cpu_reset(CPU(s->cpu)); | |
150 | env->active_tc.PC = s->vector; | |
151 | } | |
152 | ||
153 | static const int sector_len = 32 * 1024; | |
154 | static | |
155 | void mips_r4k_init(QEMUMachineInitArgs *args) | |
156 | { | |
157 | ram_addr_t ram_size = args->ram_size; | |
158 | const char *cpu_model = args->cpu_model; | |
159 | const char *kernel_filename = args->kernel_filename; | |
160 | const char *kernel_cmdline = args->kernel_cmdline; | |
161 | const char *initrd_filename = args->initrd_filename; | |
162 | char *filename; | |
163 | MemoryRegion *address_space_mem = get_system_memory(); | |
164 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
165 | MemoryRegion *bios; | |
166 | MemoryRegion *iomem = g_new(MemoryRegion, 1); | |
167 | int bios_size; | |
168 | MIPSCPU *cpu; | |
169 | CPUMIPSState *env; | |
170 | ResetData *reset_info; | |
171 | int i; | |
172 | qemu_irq *i8259; | |
173 | ISABus *isa_bus; | |
174 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; | |
175 | DriveInfo *dinfo; | |
176 | int be; | |
177 | ||
178 | /* init CPUs */ | |
179 | if (cpu_model == NULL) { | |
180 | #ifdef TARGET_MIPS64 | |
181 | cpu_model = "R4000"; | |
182 | #else | |
183 | cpu_model = "24Kf"; | |
184 | #endif | |
185 | } | |
186 | cpu = cpu_mips_init(cpu_model); | |
187 | if (cpu == NULL) { | |
188 | fprintf(stderr, "Unable to find CPU definition\n"); | |
189 | exit(1); | |
190 | } | |
191 | env = &cpu->env; | |
192 | ||
193 | reset_info = g_malloc0(sizeof(ResetData)); | |
194 | reset_info->cpu = cpu; | |
195 | reset_info->vector = env->active_tc.PC; | |
196 | qemu_register_reset(main_cpu_reset, reset_info); | |
197 | ||
198 | /* allocate RAM */ | |
199 | if (ram_size > (256 << 20)) { | |
200 | fprintf(stderr, | |
201 | "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n", | |
202 | ((unsigned int)ram_size / (1 << 20))); | |
203 | exit(1); | |
204 | } | |
205 | memory_region_init_ram(ram, "mips_r4k.ram", ram_size); | |
206 | vmstate_register_ram_global(ram); | |
207 | ||
208 | memory_region_add_subregion(address_space_mem, 0, ram); | |
209 | ||
210 | memory_region_init_io(iomem, &mips_qemu_ops, NULL, "mips-qemu", 0x10000); | |
211 | memory_region_add_subregion(address_space_mem, 0x1fbf0000, iomem); | |
212 | ||
213 | /* Try to load a BIOS image. If this fails, we continue regardless, | |
214 | but initialize the hardware ourselves. When a kernel gets | |
215 | preloaded we also initialize the hardware, since the BIOS wasn't | |
216 | run. */ | |
217 | if (bios_name == NULL) | |
218 | bios_name = BIOS_FILENAME; | |
219 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
220 | if (filename) { | |
221 | bios_size = get_image_size(filename); | |
222 | } else { | |
223 | bios_size = -1; | |
224 | } | |
225 | #ifdef TARGET_WORDS_BIGENDIAN | |
226 | be = 1; | |
227 | #else | |
228 | be = 0; | |
229 | #endif | |
230 | if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { | |
231 | bios = g_new(MemoryRegion, 1); | |
232 | memory_region_init_ram(bios, "mips_r4k.bios", BIOS_SIZE); | |
233 | vmstate_register_ram_global(bios); | |
234 | memory_region_set_readonly(bios, true); | |
235 | memory_region_add_subregion(get_system_memory(), 0x1fc00000, bios); | |
236 | ||
237 | load_image_targphys(filename, 0x1fc00000, BIOS_SIZE); | |
238 | } else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) { | |
239 | uint32_t mips_rom = 0x00400000; | |
240 | if (!pflash_cfi01_register(0x1fc00000, NULL, "mips_r4k.bios", mips_rom, | |
241 | dinfo->bdrv, sector_len, | |
242 | mips_rom / sector_len, | |
243 | 4, 0, 0, 0, 0, be)) { | |
244 | fprintf(stderr, "qemu: Error registering flash memory.\n"); | |
245 | } | |
246 | } | |
247 | else { | |
248 | /* not fatal */ | |
249 | fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n", | |
250 | bios_name); | |
251 | } | |
252 | if (filename) { | |
253 | g_free(filename); | |
254 | } | |
255 | ||
256 | if (kernel_filename) { | |
257 | loaderparams.ram_size = ram_size; | |
258 | loaderparams.kernel_filename = kernel_filename; | |
259 | loaderparams.kernel_cmdline = kernel_cmdline; | |
260 | loaderparams.initrd_filename = initrd_filename; | |
261 | reset_info->vector = load_kernel(); | |
262 | } | |
263 | ||
264 | /* Init CPU internal devices */ | |
265 | cpu_mips_irq_init_cpu(env); | |
266 | cpu_mips_clock_init(env); | |
267 | ||
268 | /* The PIC is attached to the MIPS CPU INT0 pin */ | |
269 | isa_bus = isa_bus_new(NULL, get_system_io()); | |
270 | i8259 = i8259_init(isa_bus, env->irq[2]); | |
271 | isa_bus_irqs(isa_bus, i8259); | |
272 | ||
273 | rtc_init(isa_bus, 2000, NULL); | |
274 | ||
275 | /* Register 64 KB of ISA IO space at 0x14000000 */ | |
276 | isa_mmio_init(0x14000000, 0x00010000); | |
277 | isa_mem_base = 0x10000000; | |
278 | ||
279 | pit = pit_init(isa_bus, 0x40, 0, NULL); | |
280 | ||
281 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
282 | if (serial_hds[i]) { | |
283 | serial_isa_init(isa_bus, i, serial_hds[i]); | |
284 | } | |
285 | } | |
286 | ||
287 | isa_vga_init(isa_bus); | |
288 | ||
289 | if (nd_table[0].used) | |
290 | isa_ne2000_init(isa_bus, 0x300, 9, &nd_table[0]); | |
291 | ||
292 | ide_drive_get(hd, MAX_IDE_BUS); | |
293 | for(i = 0; i < MAX_IDE_BUS; i++) | |
294 | isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i], | |
295 | hd[MAX_IDE_DEVS * i], | |
296 | hd[MAX_IDE_DEVS * i + 1]); | |
297 | ||
298 | isa_create_simple(isa_bus, "i8042"); | |
299 | } | |
300 | ||
301 | static QEMUMachine mips_machine = { | |
302 | .name = "mips", | |
303 | .desc = "mips r4k platform", | |
304 | .init = mips_r4k_init, | |
305 | }; | |
306 | ||
307 | static void mips_machine_init(void) | |
308 | { | |
309 | qemu_register_machine(&mips_machine); | |
310 | } | |
311 | ||
312 | machine_init(mips_machine_init); |