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Commit | Line | Data |
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1 | /* | |
2 | * QEMU/MIPS pseudo-board | |
3 | * | |
4 | * emulates a simple machine with ISA-like bus. | |
5 | * ISA IO space mapped to the 0x14000000 (PHYS) and | |
6 | * ISA memory at the 0x10000000 (PHYS, 16Mb in size). | |
7 | * All peripherial devices are attached to this "bus" with | |
8 | * the standard PC ISA addresses. | |
9 | */ | |
10 | #include "hw.h" | |
11 | #include "mips.h" | |
12 | #include "pc.h" | |
13 | #include "isa.h" | |
14 | #include "net.h" | |
15 | #include "sysemu.h" | |
16 | #include "boards.h" | |
17 | #include "flash.h" | |
18 | #include "qemu-log.h" | |
19 | #include "mips-bios.h" | |
20 | ||
21 | #define PHYS_TO_VIRT(x) ((x) | ~(target_ulong)0x7fffffff) | |
22 | ||
23 | #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) | |
24 | ||
25 | #define MAX_IDE_BUS 2 | |
26 | ||
27 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; | |
28 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
29 | static const int ide_irq[2] = { 14, 15 }; | |
30 | ||
31 | static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; | |
32 | static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; | |
33 | ||
34 | static PITState *pit; /* PIT i8254 */ | |
35 | ||
36 | /* i8254 PIT is attached to the IRQ0 at PIC i8259 */ | |
37 | ||
38 | static struct _loaderparams { | |
39 | int ram_size; | |
40 | const char *kernel_filename; | |
41 | const char *kernel_cmdline; | |
42 | const char *initrd_filename; | |
43 | } loaderparams; | |
44 | ||
45 | static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, | |
46 | uint32_t val) | |
47 | { | |
48 | if ((addr & 0xffff) == 0 && val == 42) | |
49 | qemu_system_reset_request (); | |
50 | else if ((addr & 0xffff) == 4 && val == 42) | |
51 | qemu_system_shutdown_request (); | |
52 | } | |
53 | ||
54 | static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) | |
55 | { | |
56 | return 0; | |
57 | } | |
58 | ||
59 | static CPUWriteMemoryFunc * const mips_qemu_write[] = { | |
60 | &mips_qemu_writel, | |
61 | &mips_qemu_writel, | |
62 | &mips_qemu_writel, | |
63 | }; | |
64 | ||
65 | static CPUReadMemoryFunc * const mips_qemu_read[] = { | |
66 | &mips_qemu_readl, | |
67 | &mips_qemu_readl, | |
68 | &mips_qemu_readl, | |
69 | }; | |
70 | ||
71 | static int mips_qemu_iomemtype = 0; | |
72 | ||
73 | static void load_kernel (CPUState *env) | |
74 | { | |
75 | int64_t entry, kernel_low, kernel_high; | |
76 | long kernel_size, initrd_size; | |
77 | ram_addr_t initrd_offset; | |
78 | int ret; | |
79 | ||
80 | kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND, | |
81 | (uint64_t *)&entry, (uint64_t *)&kernel_low, | |
82 | (uint64_t *)&kernel_high); | |
83 | if (kernel_size >= 0) { | |
84 | if ((entry & ~0x7fffffffULL) == 0x80000000) | |
85 | entry = (int32_t)entry; | |
86 | env->active_tc.PC = entry; | |
87 | } else { | |
88 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
89 | loaderparams.kernel_filename); | |
90 | exit(1); | |
91 | } | |
92 | ||
93 | /* load initrd */ | |
94 | initrd_size = 0; | |
95 | initrd_offset = 0; | |
96 | if (loaderparams.initrd_filename) { | |
97 | initrd_size = get_image_size (loaderparams.initrd_filename); | |
98 | if (initrd_size > 0) { | |
99 | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; | |
100 | if (initrd_offset + initrd_size > ram_size) { | |
101 | fprintf(stderr, | |
102 | "qemu: memory too small for initial ram disk '%s'\n", | |
103 | loaderparams.initrd_filename); | |
104 | exit(1); | |
105 | } | |
106 | initrd_size = load_image_targphys(loaderparams.initrd_filename, | |
107 | initrd_offset, | |
108 | ram_size - initrd_offset); | |
109 | } | |
110 | if (initrd_size == (target_ulong) -1) { | |
111 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
112 | loaderparams.initrd_filename); | |
113 | exit(1); | |
114 | } | |
115 | } | |
116 | ||
117 | /* Store command line. */ | |
118 | if (initrd_size > 0) { | |
119 | char buf[64]; | |
120 | ret = snprintf(buf, 64, "rd_start=0x" TARGET_FMT_lx " rd_size=%li ", | |
121 | PHYS_TO_VIRT((uint32_t)initrd_offset), | |
122 | initrd_size); | |
123 | cpu_physical_memory_write((16 << 20) - 256, (void *)buf, 64); | |
124 | } else { | |
125 | ret = 0; | |
126 | } | |
127 | pstrcpy_targphys((16 << 20) - 256 + ret, 256, | |
128 | loaderparams.kernel_cmdline); | |
129 | ||
130 | stl_phys((16 << 20) - 260, 0x12345678); | |
131 | stl_phys((16 << 20) - 264, ram_size); | |
132 | } | |
133 | ||
134 | static void main_cpu_reset(void *opaque) | |
135 | { | |
136 | CPUState *env = opaque; | |
137 | cpu_reset(env); | |
138 | ||
139 | if (loaderparams.kernel_filename) | |
140 | load_kernel (env); | |
141 | } | |
142 | ||
143 | static const int sector_len = 32 * 1024; | |
144 | static | |
145 | void mips_r4k_init (ram_addr_t ram_size, | |
146 | const char *boot_device, | |
147 | const char *kernel_filename, const char *kernel_cmdline, | |
148 | const char *initrd_filename, const char *cpu_model) | |
149 | { | |
150 | char *filename; | |
151 | ram_addr_t ram_offset; | |
152 | ram_addr_t bios_offset; | |
153 | int bios_size; | |
154 | CPUState *env; | |
155 | RTCState *rtc_state; | |
156 | int i; | |
157 | qemu_irq *i8259; | |
158 | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; | |
159 | DriveInfo *dinfo; | |
160 | ||
161 | /* init CPUs */ | |
162 | if (cpu_model == NULL) { | |
163 | #ifdef TARGET_MIPS64 | |
164 | cpu_model = "R4000"; | |
165 | #else | |
166 | cpu_model = "24Kf"; | |
167 | #endif | |
168 | } | |
169 | env = cpu_init(cpu_model); | |
170 | if (!env) { | |
171 | fprintf(stderr, "Unable to find CPU definition\n"); | |
172 | exit(1); | |
173 | } | |
174 | qemu_register_reset(main_cpu_reset, env); | |
175 | ||
176 | /* allocate RAM */ | |
177 | if (ram_size > (256 << 20)) { | |
178 | fprintf(stderr, | |
179 | "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n", | |
180 | ((unsigned int)ram_size / (1 << 20))); | |
181 | exit(1); | |
182 | } | |
183 | ram_offset = qemu_ram_alloc(ram_size); | |
184 | ||
185 | cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); | |
186 | ||
187 | if (!mips_qemu_iomemtype) { | |
188 | mips_qemu_iomemtype = cpu_register_io_memory(mips_qemu_read, | |
189 | mips_qemu_write, NULL); | |
190 | } | |
191 | cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype); | |
192 | ||
193 | /* Try to load a BIOS image. If this fails, we continue regardless, | |
194 | but initialize the hardware ourselves. When a kernel gets | |
195 | preloaded we also initialize the hardware, since the BIOS wasn't | |
196 | run. */ | |
197 | if (bios_name == NULL) | |
198 | bios_name = BIOS_FILENAME; | |
199 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
200 | if (filename) { | |
201 | bios_size = get_image_size(filename); | |
202 | } else { | |
203 | bios_size = -1; | |
204 | } | |
205 | if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { | |
206 | bios_offset = qemu_ram_alloc(BIOS_SIZE); | |
207 | cpu_register_physical_memory(0x1fc00000, BIOS_SIZE, | |
208 | bios_offset | IO_MEM_ROM); | |
209 | ||
210 | load_image_targphys(filename, 0x1fc00000, BIOS_SIZE); | |
211 | } else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) { | |
212 | uint32_t mips_rom = 0x00400000; | |
213 | bios_offset = qemu_ram_alloc(mips_rom); | |
214 | if (!pflash_cfi01_register(0x1fc00000, bios_offset, | |
215 | dinfo->bdrv, sector_len, mips_rom / sector_len, | |
216 | 4, 0, 0, 0, 0)) { | |
217 | fprintf(stderr, "qemu: Error registering flash memory.\n"); | |
218 | } | |
219 | } | |
220 | else { | |
221 | /* not fatal */ | |
222 | fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n", | |
223 | bios_name); | |
224 | } | |
225 | if (filename) { | |
226 | qemu_free(filename); | |
227 | } | |
228 | ||
229 | if (kernel_filename) { | |
230 | loaderparams.ram_size = ram_size; | |
231 | loaderparams.kernel_filename = kernel_filename; | |
232 | loaderparams.kernel_cmdline = kernel_cmdline; | |
233 | loaderparams.initrd_filename = initrd_filename; | |
234 | load_kernel (env); | |
235 | } | |
236 | ||
237 | /* Init CPU internal devices */ | |
238 | cpu_mips_irq_init_cpu(env); | |
239 | cpu_mips_clock_init(env); | |
240 | ||
241 | /* The PIC is attached to the MIPS CPU INT0 pin */ | |
242 | i8259 = i8259_init(env->irq[2]); | |
243 | ||
244 | rtc_state = rtc_init(0x70, i8259[8], 2000); | |
245 | ||
246 | /* Register 64 KB of ISA IO space at 0x14000000 */ | |
247 | isa_mmio_init(0x14000000, 0x00010000); | |
248 | isa_mem_base = 0x10000000; | |
249 | ||
250 | pit = pit_init(0x40, i8259[0]); | |
251 | ||
252 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
253 | if (serial_hds[i]) { | |
254 | serial_init(serial_io[i], i8259[serial_irq[i]], 115200, | |
255 | serial_hds[i]); | |
256 | } | |
257 | } | |
258 | ||
259 | isa_vga_init(); | |
260 | ||
261 | if (nd_table[0].vlan) | |
262 | isa_ne2000_init(0x300, i8259[9], &nd_table[0]); | |
263 | ||
264 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { | |
265 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
266 | exit(1); | |
267 | } | |
268 | ||
269 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
270 | dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); | |
271 | hd[i] = dinfo ? dinfo->bdrv : NULL; | |
272 | } | |
273 | ||
274 | for(i = 0; i < MAX_IDE_BUS; i++) | |
275 | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], | |
276 | hd[MAX_IDE_DEVS * i], | |
277 | hd[MAX_IDE_DEVS * i + 1]); | |
278 | ||
279 | i8042_init(i8259[1], i8259[12], 0x60); | |
280 | } | |
281 | ||
282 | static QEMUMachine mips_machine = { | |
283 | .name = "mips", | |
284 | .desc = "mips r4k platform", | |
285 | .init = mips_r4k_init, | |
286 | }; | |
287 | ||
288 | static void mips_machine_init(void) | |
289 | { | |
290 | qemu_register_machine(&mips_machine); | |
291 | } | |
292 | ||
293 | machine_init(mips_machine_init); |