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Commit | Line | Data |
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1 | /* | |
2 | * QEMU/MIPS pseudo-board | |
3 | * | |
4 | * emulates a simple machine with ISA-like bus. | |
5 | * ISA IO space mapped to the 0x14000000 (PHYS) and | |
6 | * ISA memory at the 0x10000000 (PHYS, 16Mb in size). | |
7 | * All peripherial devices are attached to this "bus" with | |
8 | * the standard PC ISA addresses. | |
9 | */ | |
10 | #include "hw.h" | |
11 | #include "mips.h" | |
12 | #include "mips_cpudevs.h" | |
13 | #include "pc.h" | |
14 | #include "isa.h" | |
15 | #include "net.h" | |
16 | #include "sysemu.h" | |
17 | #include "boards.h" | |
18 | #include "flash.h" | |
19 | #include "qemu-log.h" | |
20 | #include "mips-bios.h" | |
21 | #include "ide.h" | |
22 | #include "loader.h" | |
23 | #include "elf.h" | |
24 | #include "mc146818rtc.h" | |
25 | #include "blockdev.h" | |
26 | ||
27 | #define MAX_IDE_BUS 2 | |
28 | ||
29 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; | |
30 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
31 | static const int ide_irq[2] = { 14, 15 }; | |
32 | ||
33 | static ISADevice *pit; /* PIT i8254 */ | |
34 | ||
35 | /* i8254 PIT is attached to the IRQ0 at PIC i8259 */ | |
36 | ||
37 | static struct _loaderparams { | |
38 | int ram_size; | |
39 | const char *kernel_filename; | |
40 | const char *kernel_cmdline; | |
41 | const char *initrd_filename; | |
42 | } loaderparams; | |
43 | ||
44 | static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, | |
45 | uint32_t val) | |
46 | { | |
47 | if ((addr & 0xffff) == 0 && val == 42) | |
48 | qemu_system_reset_request (); | |
49 | else if ((addr & 0xffff) == 4 && val == 42) | |
50 | qemu_system_shutdown_request (); | |
51 | } | |
52 | ||
53 | static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) | |
54 | { | |
55 | return 0; | |
56 | } | |
57 | ||
58 | static CPUWriteMemoryFunc * const mips_qemu_write[] = { | |
59 | &mips_qemu_writel, | |
60 | &mips_qemu_writel, | |
61 | &mips_qemu_writel, | |
62 | }; | |
63 | ||
64 | static CPUReadMemoryFunc * const mips_qemu_read[] = { | |
65 | &mips_qemu_readl, | |
66 | &mips_qemu_readl, | |
67 | &mips_qemu_readl, | |
68 | }; | |
69 | ||
70 | static int mips_qemu_iomemtype = 0; | |
71 | ||
72 | typedef struct ResetData { | |
73 | CPUState *env; | |
74 | uint64_t vector; | |
75 | } ResetData; | |
76 | ||
77 | static int64_t load_kernel(void) | |
78 | { | |
79 | int64_t entry, kernel_high; | |
80 | long kernel_size, initrd_size, params_size; | |
81 | ram_addr_t initrd_offset; | |
82 | uint32_t *params_buf; | |
83 | int big_endian; | |
84 | ||
85 | #ifdef TARGET_WORDS_BIGENDIAN | |
86 | big_endian = 1; | |
87 | #else | |
88 | big_endian = 0; | |
89 | #endif | |
90 | kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, | |
91 | NULL, (uint64_t *)&entry, NULL, | |
92 | (uint64_t *)&kernel_high, big_endian, | |
93 | ELF_MACHINE, 1); | |
94 | if (kernel_size >= 0) { | |
95 | if ((entry & ~0x7fffffffULL) == 0x80000000) | |
96 | entry = (int32_t)entry; | |
97 | } else { | |
98 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
99 | loaderparams.kernel_filename); | |
100 | exit(1); | |
101 | } | |
102 | ||
103 | /* load initrd */ | |
104 | initrd_size = 0; | |
105 | initrd_offset = 0; | |
106 | if (loaderparams.initrd_filename) { | |
107 | initrd_size = get_image_size (loaderparams.initrd_filename); | |
108 | if (initrd_size > 0) { | |
109 | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; | |
110 | if (initrd_offset + initrd_size > ram_size) { | |
111 | fprintf(stderr, | |
112 | "qemu: memory too small for initial ram disk '%s'\n", | |
113 | loaderparams.initrd_filename); | |
114 | exit(1); | |
115 | } | |
116 | initrd_size = load_image_targphys(loaderparams.initrd_filename, | |
117 | initrd_offset, | |
118 | ram_size - initrd_offset); | |
119 | } | |
120 | if (initrd_size == (target_ulong) -1) { | |
121 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
122 | loaderparams.initrd_filename); | |
123 | exit(1); | |
124 | } | |
125 | } | |
126 | ||
127 | /* Store command line. */ | |
128 | params_size = 264; | |
129 | params_buf = qemu_malloc(params_size); | |
130 | ||
131 | params_buf[0] = tswap32(ram_size); | |
132 | params_buf[1] = tswap32(0x12345678); | |
133 | ||
134 | if (initrd_size > 0) { | |
135 | snprintf((char *)params_buf + 8, 256, "rd_start=0x%" PRIx64 " rd_size=%li %s", | |
136 | cpu_mips_phys_to_kseg0(NULL, initrd_offset), | |
137 | initrd_size, loaderparams.kernel_cmdline); | |
138 | } else { | |
139 | snprintf((char *)params_buf + 8, 256, "%s", loaderparams.kernel_cmdline); | |
140 | } | |
141 | ||
142 | rom_add_blob_fixed("params", params_buf, params_size, | |
143 | (16 << 20) - 264); | |
144 | ||
145 | return entry; | |
146 | } | |
147 | ||
148 | static void main_cpu_reset(void *opaque) | |
149 | { | |
150 | ResetData *s = (ResetData *)opaque; | |
151 | CPUState *env = s->env; | |
152 | ||
153 | cpu_reset(env); | |
154 | env->active_tc.PC = s->vector; | |
155 | } | |
156 | ||
157 | static const int sector_len = 32 * 1024; | |
158 | static | |
159 | void mips_r4k_init (ram_addr_t ram_size, | |
160 | const char *boot_device, | |
161 | const char *kernel_filename, const char *kernel_cmdline, | |
162 | const char *initrd_filename, const char *cpu_model) | |
163 | { | |
164 | char *filename; | |
165 | ram_addr_t ram_offset; | |
166 | ram_addr_t bios_offset; | |
167 | int bios_size; | |
168 | CPUState *env; | |
169 | ResetData *reset_info; | |
170 | int i; | |
171 | qemu_irq *i8259; | |
172 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; | |
173 | DriveInfo *dinfo; | |
174 | int be; | |
175 | ||
176 | /* init CPUs */ | |
177 | if (cpu_model == NULL) { | |
178 | #ifdef TARGET_MIPS64 | |
179 | cpu_model = "R4000"; | |
180 | #else | |
181 | cpu_model = "24Kf"; | |
182 | #endif | |
183 | } | |
184 | env = cpu_init(cpu_model); | |
185 | if (!env) { | |
186 | fprintf(stderr, "Unable to find CPU definition\n"); | |
187 | exit(1); | |
188 | } | |
189 | reset_info = qemu_mallocz(sizeof(ResetData)); | |
190 | reset_info->env = env; | |
191 | reset_info->vector = env->active_tc.PC; | |
192 | qemu_register_reset(main_cpu_reset, reset_info); | |
193 | ||
194 | /* allocate RAM */ | |
195 | if (ram_size > (256 << 20)) { | |
196 | fprintf(stderr, | |
197 | "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n", | |
198 | ((unsigned int)ram_size / (1 << 20))); | |
199 | exit(1); | |
200 | } | |
201 | ram_offset = qemu_ram_alloc(NULL, "mips_r4k.ram", ram_size); | |
202 | ||
203 | cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); | |
204 | ||
205 | if (!mips_qemu_iomemtype) { | |
206 | mips_qemu_iomemtype = cpu_register_io_memory(mips_qemu_read, | |
207 | mips_qemu_write, NULL, | |
208 | DEVICE_NATIVE_ENDIAN); | |
209 | } | |
210 | cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype); | |
211 | ||
212 | /* Try to load a BIOS image. If this fails, we continue regardless, | |
213 | but initialize the hardware ourselves. When a kernel gets | |
214 | preloaded we also initialize the hardware, since the BIOS wasn't | |
215 | run. */ | |
216 | if (bios_name == NULL) | |
217 | bios_name = BIOS_FILENAME; | |
218 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
219 | if (filename) { | |
220 | bios_size = get_image_size(filename); | |
221 | } else { | |
222 | bios_size = -1; | |
223 | } | |
224 | #ifdef TARGET_WORDS_BIGENDIAN | |
225 | be = 1; | |
226 | #else | |
227 | be = 0; | |
228 | #endif | |
229 | if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { | |
230 | bios_offset = qemu_ram_alloc(NULL, "mips_r4k.bios", BIOS_SIZE); | |
231 | cpu_register_physical_memory(0x1fc00000, BIOS_SIZE, | |
232 | bios_offset | IO_MEM_ROM); | |
233 | ||
234 | load_image_targphys(filename, 0x1fc00000, BIOS_SIZE); | |
235 | } else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) { | |
236 | uint32_t mips_rom = 0x00400000; | |
237 | bios_offset = qemu_ram_alloc(NULL, "mips_r4k.bios", mips_rom); | |
238 | if (!pflash_cfi01_register(0x1fc00000, bios_offset, | |
239 | dinfo->bdrv, sector_len, | |
240 | mips_rom / sector_len, | |
241 | 4, 0, 0, 0, 0, be)) { | |
242 | fprintf(stderr, "qemu: Error registering flash memory.\n"); | |
243 | } | |
244 | } | |
245 | else { | |
246 | /* not fatal */ | |
247 | fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n", | |
248 | bios_name); | |
249 | } | |
250 | if (filename) { | |
251 | qemu_free(filename); | |
252 | } | |
253 | ||
254 | if (kernel_filename) { | |
255 | loaderparams.ram_size = ram_size; | |
256 | loaderparams.kernel_filename = kernel_filename; | |
257 | loaderparams.kernel_cmdline = kernel_cmdline; | |
258 | loaderparams.initrd_filename = initrd_filename; | |
259 | reset_info->vector = load_kernel(); | |
260 | } | |
261 | ||
262 | /* Init CPU internal devices */ | |
263 | cpu_mips_irq_init_cpu(env); | |
264 | cpu_mips_clock_init(env); | |
265 | ||
266 | /* The PIC is attached to the MIPS CPU INT0 pin */ | |
267 | i8259 = i8259_init(env->irq[2]); | |
268 | isa_bus_new(NULL); | |
269 | isa_bus_irqs(i8259); | |
270 | ||
271 | rtc_init(2000, NULL); | |
272 | ||
273 | /* Register 64 KB of ISA IO space at 0x14000000 */ | |
274 | isa_mmio_init(0x14000000, 0x00010000); | |
275 | isa_mem_base = 0x10000000; | |
276 | ||
277 | pit = pit_init(0x40, 0); | |
278 | ||
279 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
280 | if (serial_hds[i]) { | |
281 | serial_isa_init(i, serial_hds[i]); | |
282 | } | |
283 | } | |
284 | ||
285 | isa_vga_init(); | |
286 | ||
287 | if (nd_table[0].vlan) | |
288 | isa_ne2000_init(0x300, 9, &nd_table[0]); | |
289 | ||
290 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { | |
291 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
292 | exit(1); | |
293 | } | |
294 | ||
295 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
296 | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); | |
297 | } | |
298 | ||
299 | for(i = 0; i < MAX_IDE_BUS; i++) | |
300 | isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], | |
301 | hd[MAX_IDE_DEVS * i], | |
302 | hd[MAX_IDE_DEVS * i + 1]); | |
303 | ||
304 | isa_create_simple("i8042"); | |
305 | } | |
306 | ||
307 | static QEMUMachine mips_machine = { | |
308 | .name = "mips", | |
309 | .desc = "mips r4k platform", | |
310 | .init = mips_r4k_init, | |
311 | }; | |
312 | ||
313 | static void mips_machine_init(void) | |
314 | { | |
315 | qemu_register_machine(&mips_machine); | |
316 | } | |
317 | ||
318 | machine_init(mips_machine_init); |