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Commit | Line | Data |
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1 | /* | |
2 | * QEMU/MIPS pseudo-board | |
3 | * | |
4 | * emulates a simple machine with ISA-like bus. | |
5 | * ISA IO space mapped to the 0x14000000 (PHYS) and | |
6 | * ISA memory at the 0x10000000 (PHYS, 16Mb in size). | |
7 | * All peripherial devices are attached to this "bus" with | |
8 | * the standard PC ISA addresses. | |
9 | */ | |
10 | #include "hw.h" | |
11 | #include "mips.h" | |
12 | #include "pc.h" | |
13 | #include "isa.h" | |
14 | #include "net.h" | |
15 | #include "sysemu.h" | |
16 | #include "boards.h" | |
17 | #include "flash.h" | |
18 | #include "qemu-log.h" | |
19 | ||
20 | #ifdef TARGET_WORDS_BIGENDIAN | |
21 | #define BIOS_FILENAME "mips_bios.bin" | |
22 | #else | |
23 | #define BIOS_FILENAME "mipsel_bios.bin" | |
24 | #endif | |
25 | ||
26 | #define PHYS_TO_VIRT(x) ((x) | ~(target_ulong)0x7fffffff) | |
27 | ||
28 | #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) | |
29 | ||
30 | #define MAX_IDE_BUS 2 | |
31 | ||
32 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; | |
33 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
34 | static const int ide_irq[2] = { 14, 15 }; | |
35 | ||
36 | static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; | |
37 | static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; | |
38 | ||
39 | static PITState *pit; /* PIT i8254 */ | |
40 | ||
41 | /* i8254 PIT is attached to the IRQ0 at PIC i8259 */ | |
42 | ||
43 | static struct _loaderparams { | |
44 | int ram_size; | |
45 | const char *kernel_filename; | |
46 | const char *kernel_cmdline; | |
47 | const char *initrd_filename; | |
48 | } loaderparams; | |
49 | ||
50 | static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, | |
51 | uint32_t val) | |
52 | { | |
53 | if ((addr & 0xffff) == 0 && val == 42) | |
54 | qemu_system_reset_request (); | |
55 | else if ((addr & 0xffff) == 4 && val == 42) | |
56 | qemu_system_shutdown_request (); | |
57 | } | |
58 | ||
59 | static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) | |
60 | { | |
61 | return 0; | |
62 | } | |
63 | ||
64 | static CPUWriteMemoryFunc *mips_qemu_write[] = { | |
65 | &mips_qemu_writel, | |
66 | &mips_qemu_writel, | |
67 | &mips_qemu_writel, | |
68 | }; | |
69 | ||
70 | static CPUReadMemoryFunc *mips_qemu_read[] = { | |
71 | &mips_qemu_readl, | |
72 | &mips_qemu_readl, | |
73 | &mips_qemu_readl, | |
74 | }; | |
75 | ||
76 | static int mips_qemu_iomemtype = 0; | |
77 | ||
78 | static void load_kernel (CPUState *env) | |
79 | { | |
80 | int64_t entry, kernel_low, kernel_high; | |
81 | long kernel_size, initrd_size; | |
82 | ram_addr_t initrd_offset; | |
83 | int ret; | |
84 | ||
85 | kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND, | |
86 | (uint64_t *)&entry, (uint64_t *)&kernel_low, | |
87 | (uint64_t *)&kernel_high); | |
88 | if (kernel_size >= 0) { | |
89 | if ((entry & ~0x7fffffffULL) == 0x80000000) | |
90 | entry = (int32_t)entry; | |
91 | env->active_tc.PC = entry; | |
92 | } else { | |
93 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
94 | loaderparams.kernel_filename); | |
95 | exit(1); | |
96 | } | |
97 | ||
98 | /* load initrd */ | |
99 | initrd_size = 0; | |
100 | initrd_offset = 0; | |
101 | if (loaderparams.initrd_filename) { | |
102 | initrd_size = get_image_size (loaderparams.initrd_filename); | |
103 | if (initrd_size > 0) { | |
104 | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; | |
105 | if (initrd_offset + initrd_size > ram_size) { | |
106 | fprintf(stderr, | |
107 | "qemu: memory too small for initial ram disk '%s'\n", | |
108 | loaderparams.initrd_filename); | |
109 | exit(1); | |
110 | } | |
111 | initrd_size = load_image_targphys(loaderparams.initrd_filename, | |
112 | initrd_offset, | |
113 | ram_size - initrd_offset); | |
114 | } | |
115 | if (initrd_size == (target_ulong) -1) { | |
116 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
117 | loaderparams.initrd_filename); | |
118 | exit(1); | |
119 | } | |
120 | } | |
121 | ||
122 | /* Store command line. */ | |
123 | if (initrd_size > 0) { | |
124 | char buf[64]; | |
125 | ret = snprintf(buf, 64, "rd_start=0x" TARGET_FMT_lx " rd_size=%li ", | |
126 | PHYS_TO_VIRT((uint32_t)initrd_offset), | |
127 | initrd_size); | |
128 | cpu_physical_memory_write((16 << 20) - 256, (void *)buf, 64); | |
129 | } else { | |
130 | ret = 0; | |
131 | } | |
132 | pstrcpy_targphys((16 << 20) - 256 + ret, 256, | |
133 | loaderparams.kernel_cmdline); | |
134 | ||
135 | stl_phys((16 << 20) - 260, 0x12345678); | |
136 | stl_phys((16 << 20) - 264, ram_size); | |
137 | } | |
138 | ||
139 | static void main_cpu_reset(void *opaque) | |
140 | { | |
141 | CPUState *env = opaque; | |
142 | cpu_reset(env); | |
143 | ||
144 | if (loaderparams.kernel_filename) | |
145 | load_kernel (env); | |
146 | } | |
147 | ||
148 | static const int sector_len = 32 * 1024; | |
149 | static | |
150 | void mips_r4k_init (ram_addr_t ram_size, | |
151 | const char *boot_device, | |
152 | const char *kernel_filename, const char *kernel_cmdline, | |
153 | const char *initrd_filename, const char *cpu_model) | |
154 | { | |
155 | char buf[1024]; | |
156 | ram_addr_t ram_offset; | |
157 | ram_addr_t bios_offset; | |
158 | int bios_size; | |
159 | CPUState *env; | |
160 | RTCState *rtc_state; | |
161 | int i; | |
162 | qemu_irq *i8259; | |
163 | int index; | |
164 | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; | |
165 | ||
166 | /* init CPUs */ | |
167 | if (cpu_model == NULL) { | |
168 | #ifdef TARGET_MIPS64 | |
169 | cpu_model = "R4000"; | |
170 | #else | |
171 | cpu_model = "24Kf"; | |
172 | #endif | |
173 | } | |
174 | env = cpu_init(cpu_model); | |
175 | if (!env) { | |
176 | fprintf(stderr, "Unable to find CPU definition\n"); | |
177 | exit(1); | |
178 | } | |
179 | qemu_register_reset(main_cpu_reset, env); | |
180 | ||
181 | /* allocate RAM */ | |
182 | if (ram_size > (256 << 20)) { | |
183 | fprintf(stderr, | |
184 | "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n", | |
185 | ((unsigned int)ram_size / (1 << 20))); | |
186 | exit(1); | |
187 | } | |
188 | ram_offset = qemu_ram_alloc(ram_size); | |
189 | ||
190 | cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); | |
191 | ||
192 | if (!mips_qemu_iomemtype) { | |
193 | mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read, | |
194 | mips_qemu_write, NULL); | |
195 | } | |
196 | cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype); | |
197 | ||
198 | /* Try to load a BIOS image. If this fails, we continue regardless, | |
199 | but initialize the hardware ourselves. When a kernel gets | |
200 | preloaded we also initialize the hardware, since the BIOS wasn't | |
201 | run. */ | |
202 | if (bios_name == NULL) | |
203 | bios_name = BIOS_FILENAME; | |
204 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
205 | bios_size = get_image_size(buf); | |
206 | if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { | |
207 | bios_offset = qemu_ram_alloc(BIOS_SIZE); | |
208 | cpu_register_physical_memory(0x1fc00000, BIOS_SIZE, | |
209 | bios_offset | IO_MEM_ROM); | |
210 | ||
211 | load_image_targphys(buf, 0x1fc00000, BIOS_SIZE); | |
212 | } else if ((index = drive_get_index(IF_PFLASH, 0, 0)) > -1) { | |
213 | uint32_t mips_rom = 0x00400000; | |
214 | bios_offset = qemu_ram_alloc(mips_rom); | |
215 | if (!pflash_cfi01_register(0x1fc00000, bios_offset, | |
216 | drives_table[index].bdrv, sector_len, mips_rom / sector_len, | |
217 | 4, 0, 0, 0, 0)) { | |
218 | fprintf(stderr, "qemu: Error registering flash memory.\n"); | |
219 | } | |
220 | } | |
221 | else { | |
222 | /* not fatal */ | |
223 | fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n", | |
224 | buf); | |
225 | } | |
226 | ||
227 | if (kernel_filename) { | |
228 | loaderparams.ram_size = ram_size; | |
229 | loaderparams.kernel_filename = kernel_filename; | |
230 | loaderparams.kernel_cmdline = kernel_cmdline; | |
231 | loaderparams.initrd_filename = initrd_filename; | |
232 | load_kernel (env); | |
233 | } | |
234 | ||
235 | /* Init CPU internal devices */ | |
236 | cpu_mips_irq_init_cpu(env); | |
237 | cpu_mips_clock_init(env); | |
238 | ||
239 | /* The PIC is attached to the MIPS CPU INT0 pin */ | |
240 | i8259 = i8259_init(env->irq[2]); | |
241 | ||
242 | rtc_state = rtc_init(0x70, i8259[8], 2000); | |
243 | ||
244 | /* Register 64 KB of ISA IO space at 0x14000000 */ | |
245 | isa_mmio_init(0x14000000, 0x00010000); | |
246 | isa_mem_base = 0x10000000; | |
247 | ||
248 | pit = pit_init(0x40, i8259[0]); | |
249 | ||
250 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
251 | if (serial_hds[i]) { | |
252 | serial_init(serial_io[i], i8259[serial_irq[i]], 115200, | |
253 | serial_hds[i]); | |
254 | } | |
255 | } | |
256 | ||
257 | isa_vga_init(); | |
258 | ||
259 | if (nd_table[0].vlan) | |
260 | isa_ne2000_init(0x300, i8259[9], &nd_table[0]); | |
261 | ||
262 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { | |
263 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
264 | exit(1); | |
265 | } | |
266 | ||
267 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
268 | index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); | |
269 | if (index != -1) | |
270 | hd[i] = drives_table[index].bdrv; | |
271 | else | |
272 | hd[i] = NULL; | |
273 | } | |
274 | ||
275 | for(i = 0; i < MAX_IDE_BUS; i++) | |
276 | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], | |
277 | hd[MAX_IDE_DEVS * i], | |
278 | hd[MAX_IDE_DEVS * i + 1]); | |
279 | ||
280 | i8042_init(i8259[1], i8259[12], 0x60); | |
281 | } | |
282 | ||
283 | QEMUMachine mips_machine = { | |
284 | .name = "mips", | |
285 | .desc = "mips r4k platform", | |
286 | .init = mips_r4k_init, | |
287 | }; |