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1/*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24#include "hw/hw.h"
25#include "hw/pci/pci.h"
26#include "hw/pci/pci_bridge.h"
27#include "hw/pci/pci_bus.h"
28#include "hw/pci/pci_host.h"
29#include "monitor/monitor.h"
30#include "net/net.h"
31#include "sysemu/sysemu.h"
32#include "hw/loader.h"
33#include "qemu/range.h"
34#include "qmp-commands.h"
35#include "hw/pci/msi.h"
36#include "hw/pci/msix.h"
37#include "exec/address-spaces.h"
38
39//#define DEBUG_PCI
40#ifdef DEBUG_PCI
41# define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
42#else
43# define PCI_DPRINTF(format, ...) do { } while (0)
44#endif
45
46static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
47static char *pcibus_get_dev_path(DeviceState *dev);
48static char *pcibus_get_fw_dev_path(DeviceState *dev);
49static int pcibus_reset(BusState *qbus);
50
51static Property pci_props[] = {
52 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
53 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
54 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
55 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
56 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
57 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
58 QEMU_PCI_CAP_SERR_BITNR, true),
59 DEFINE_PROP_END_OF_LIST()
60};
61
62static void pci_bus_class_init(ObjectClass *klass, void *data)
63{
64 BusClass *k = BUS_CLASS(klass);
65
66 k->print_dev = pcibus_dev_print;
67 k->get_dev_path = pcibus_get_dev_path;
68 k->get_fw_dev_path = pcibus_get_fw_dev_path;
69 k->reset = pcibus_reset;
70}
71
72static const TypeInfo pci_bus_info = {
73 .name = TYPE_PCI_BUS,
74 .parent = TYPE_BUS,
75 .instance_size = sizeof(PCIBus),
76 .class_init = pci_bus_class_init,
77};
78
79static const TypeInfo pcie_bus_info = {
80 .name = TYPE_PCIE_BUS,
81 .parent = TYPE_PCI_BUS,
82};
83
84static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
85static void pci_update_mappings(PCIDevice *d);
86static void pci_set_irq(void *opaque, int irq_num, int level);
87static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
88static void pci_del_option_rom(PCIDevice *pdev);
89
90static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
91static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
92
93static QLIST_HEAD(, PCIHostState) pci_host_bridges;
94
95static const VMStateDescription vmstate_pcibus = {
96 .name = "PCIBUS",
97 .version_id = 1,
98 .minimum_version_id = 1,
99 .minimum_version_id_old = 1,
100 .fields = (VMStateField []) {
101 VMSTATE_INT32_EQUAL(nirq, PCIBus),
102 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
103 VMSTATE_END_OF_LIST()
104 }
105};
106static int pci_bar(PCIDevice *d, int reg)
107{
108 uint8_t type;
109
110 if (reg != PCI_ROM_SLOT)
111 return PCI_BASE_ADDRESS_0 + reg * 4;
112
113 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
114 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
115}
116
117static inline int pci_irq_state(PCIDevice *d, int irq_num)
118{
119 return (d->irq_state >> irq_num) & 0x1;
120}
121
122static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
123{
124 d->irq_state &= ~(0x1 << irq_num);
125 d->irq_state |= level << irq_num;
126}
127
128static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
129{
130 PCIBus *bus;
131 for (;;) {
132 bus = pci_dev->bus;
133 irq_num = bus->map_irq(pci_dev, irq_num);
134 if (bus->set_irq)
135 break;
136 pci_dev = bus->parent_dev;
137 }
138 bus->irq_count[irq_num] += change;
139 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
140}
141
142int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
143{
144 assert(irq_num >= 0);
145 assert(irq_num < bus->nirq);
146 return !!bus->irq_count[irq_num];
147}
148
149/* Update interrupt status bit in config space on interrupt
150 * state change. */
151static void pci_update_irq_status(PCIDevice *dev)
152{
153 if (dev->irq_state) {
154 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
155 } else {
156 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
157 }
158}
159
160void pci_device_deassert_intx(PCIDevice *dev)
161{
162 int i;
163 for (i = 0; i < PCI_NUM_PINS; ++i) {
164 qemu_set_irq(dev->irq[i], 0);
165 }
166}
167
168/*
169 * This function is called on #RST and FLR.
170 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
171 */
172void pci_device_reset(PCIDevice *dev)
173{
174 int r;
175
176 qdev_reset_all(&dev->qdev);
177
178 dev->irq_state = 0;
179 pci_update_irq_status(dev);
180 pci_device_deassert_intx(dev);
181 /* Clear all writable bits */
182 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
183 pci_get_word(dev->wmask + PCI_COMMAND) |
184 pci_get_word(dev->w1cmask + PCI_COMMAND));
185 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
186 pci_get_word(dev->wmask + PCI_STATUS) |
187 pci_get_word(dev->w1cmask + PCI_STATUS));
188 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
189 dev->config[PCI_INTERRUPT_LINE] = 0x0;
190 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
191 PCIIORegion *region = &dev->io_regions[r];
192 if (!region->size) {
193 continue;
194 }
195
196 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
197 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
198 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
199 } else {
200 pci_set_long(dev->config + pci_bar(dev, r), region->type);
201 }
202 }
203 pci_update_mappings(dev);
204
205 msi_reset(dev);
206 msix_reset(dev);
207}
208
209/*
210 * Trigger pci bus reset under a given bus.
211 * To be called on RST# assert.
212 */
213void pci_bus_reset(PCIBus *bus)
214{
215 int i;
216
217 for (i = 0; i < bus->nirq; i++) {
218 bus->irq_count[i] = 0;
219 }
220 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
221 if (bus->devices[i]) {
222 pci_device_reset(bus->devices[i]);
223 }
224 }
225}
226
227static int pcibus_reset(BusState *qbus)
228{
229 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
230
231 /* topology traverse is done by pci_bus_reset().
232 Tell qbus/qdev walker not to traverse the tree */
233 return 1;
234}
235
236static void pci_host_bus_register(PCIBus *bus, DeviceState *parent)
237{
238 PCIHostState *host_bridge = PCI_HOST_BRIDGE(parent);
239
240 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
241}
242
243PCIBus *pci_find_primary_bus(void)
244{
245 PCIBus *primary_bus = NULL;
246 PCIHostState *host;
247
248 QLIST_FOREACH(host, &pci_host_bridges, next) {
249 if (primary_bus) {
250 /* We have multiple root buses, refuse to select a primary */
251 return NULL;
252 }
253 primary_bus = host->bus;
254 }
255
256 return primary_bus;
257}
258
259PCIBus *pci_device_root_bus(const PCIDevice *d)
260{
261 PCIBus *bus = d->bus;
262
263 while ((d = bus->parent_dev) != NULL) {
264 bus = d->bus;
265 }
266
267 return bus;
268}
269
270const char *pci_root_bus_path(PCIDevice *dev)
271{
272 PCIBus *rootbus = pci_device_root_bus(dev);
273 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
274 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
275
276 assert(!rootbus->parent_dev);
277 assert(host_bridge->bus == rootbus);
278
279 if (hc->root_bus_path) {
280 return (*hc->root_bus_path)(host_bridge, rootbus);
281 }
282
283 return rootbus->qbus.name;
284}
285
286static void pci_bus_init(PCIBus *bus, DeviceState *parent,
287 const char *name,
288 MemoryRegion *address_space_mem,
289 MemoryRegion *address_space_io,
290 uint8_t devfn_min)
291{
292 assert(PCI_FUNC(devfn_min) == 0);
293 bus->devfn_min = devfn_min;
294 bus->address_space_mem = address_space_mem;
295 bus->address_space_io = address_space_io;
296
297 /* host bridge */
298 QLIST_INIT(&bus->child);
299
300 pci_host_bus_register(bus, parent);
301
302 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
303}
304
305bool pci_bus_is_express(PCIBus *bus)
306{
307 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
308}
309
310bool pci_bus_is_root(PCIBus *bus)
311{
312 return !bus->parent_dev;
313}
314
315void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
316 const char *name,
317 MemoryRegion *address_space_mem,
318 MemoryRegion *address_space_io,
319 uint8_t devfn_min, const char *typename)
320{
321 qbus_create_inplace(bus, bus_size, typename, parent, name);
322 pci_bus_init(bus, parent, name, address_space_mem,
323 address_space_io, devfn_min);
324}
325
326PCIBus *pci_bus_new(DeviceState *parent, const char *name,
327 MemoryRegion *address_space_mem,
328 MemoryRegion *address_space_io,
329 uint8_t devfn_min, const char *typename)
330{
331 PCIBus *bus;
332
333 bus = PCI_BUS(qbus_create(typename, parent, name));
334 pci_bus_init(bus, parent, name, address_space_mem,
335 address_space_io, devfn_min);
336 return bus;
337}
338
339void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
340 void *irq_opaque, int nirq)
341{
342 bus->set_irq = set_irq;
343 bus->map_irq = map_irq;
344 bus->irq_opaque = irq_opaque;
345 bus->nirq = nirq;
346 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
347}
348
349void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
350{
351 bus->qbus.allow_hotplug = 1;
352 bus->hotplug = hotplug;
353 bus->hotplug_qdev = qdev;
354}
355
356PCIBus *pci_register_bus(DeviceState *parent, const char *name,
357 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
358 void *irq_opaque,
359 MemoryRegion *address_space_mem,
360 MemoryRegion *address_space_io,
361 uint8_t devfn_min, int nirq, const char *typename)
362{
363 PCIBus *bus;
364
365 bus = pci_bus_new(parent, name, address_space_mem,
366 address_space_io, devfn_min, typename);
367 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
368 return bus;
369}
370
371int pci_bus_num(PCIBus *s)
372{
373 if (pci_bus_is_root(s))
374 return 0; /* pci host bridge */
375 return s->parent_dev->config[PCI_SECONDARY_BUS];
376}
377
378static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
379{
380 PCIDevice *s = container_of(pv, PCIDevice, config);
381 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
382 uint8_t *config;
383 int i;
384
385 assert(size == pci_config_size(s));
386 config = g_malloc(size);
387
388 qemu_get_buffer(f, config, size);
389 for (i = 0; i < size; ++i) {
390 if ((config[i] ^ s->config[i]) &
391 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
392 g_free(config);
393 return -EINVAL;
394 }
395 }
396 memcpy(s->config, config, size);
397
398 pci_update_mappings(s);
399 if (pc->is_bridge) {
400 PCIBridge *b = PCI_BRIDGE(s);
401 pci_bridge_update_mappings(b);
402 }
403
404 memory_region_set_enabled(&s->bus_master_enable_region,
405 pci_get_word(s->config + PCI_COMMAND)
406 & PCI_COMMAND_MASTER);
407
408 g_free(config);
409 return 0;
410}
411
412/* just put buffer */
413static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
414{
415 const uint8_t **v = pv;
416 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
417 qemu_put_buffer(f, *v, size);
418}
419
420static VMStateInfo vmstate_info_pci_config = {
421 .name = "pci config",
422 .get = get_pci_config_device,
423 .put = put_pci_config_device,
424};
425
426static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
427{
428 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
429 uint32_t irq_state[PCI_NUM_PINS];
430 int i;
431 for (i = 0; i < PCI_NUM_PINS; ++i) {
432 irq_state[i] = qemu_get_be32(f);
433 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
434 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
435 irq_state[i]);
436 return -EINVAL;
437 }
438 }
439
440 for (i = 0; i < PCI_NUM_PINS; ++i) {
441 pci_set_irq_state(s, i, irq_state[i]);
442 }
443
444 return 0;
445}
446
447static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
448{
449 int i;
450 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
451
452 for (i = 0; i < PCI_NUM_PINS; ++i) {
453 qemu_put_be32(f, pci_irq_state(s, i));
454 }
455}
456
457static VMStateInfo vmstate_info_pci_irq_state = {
458 .name = "pci irq state",
459 .get = get_pci_irq_state,
460 .put = put_pci_irq_state,
461};
462
463const VMStateDescription vmstate_pci_device = {
464 .name = "PCIDevice",
465 .version_id = 2,
466 .minimum_version_id = 1,
467 .minimum_version_id_old = 1,
468 .fields = (VMStateField []) {
469 VMSTATE_INT32_LE(version_id, PCIDevice),
470 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
471 vmstate_info_pci_config,
472 PCI_CONFIG_SPACE_SIZE),
473 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
474 vmstate_info_pci_irq_state,
475 PCI_NUM_PINS * sizeof(int32_t)),
476 VMSTATE_END_OF_LIST()
477 }
478};
479
480const VMStateDescription vmstate_pcie_device = {
481 .name = "PCIEDevice",
482 .version_id = 2,
483 .minimum_version_id = 1,
484 .minimum_version_id_old = 1,
485 .fields = (VMStateField []) {
486 VMSTATE_INT32_LE(version_id, PCIDevice),
487 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
488 vmstate_info_pci_config,
489 PCIE_CONFIG_SPACE_SIZE),
490 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
491 vmstate_info_pci_irq_state,
492 PCI_NUM_PINS * sizeof(int32_t)),
493 VMSTATE_END_OF_LIST()
494 }
495};
496
497static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
498{
499 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
500}
501
502void pci_device_save(PCIDevice *s, QEMUFile *f)
503{
504 /* Clear interrupt status bit: it is implicit
505 * in irq_state which we are saving.
506 * This makes us compatible with old devices
507 * which never set or clear this bit. */
508 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
509 vmstate_save_state(f, pci_get_vmstate(s), s);
510 /* Restore the interrupt status bit. */
511 pci_update_irq_status(s);
512}
513
514int pci_device_load(PCIDevice *s, QEMUFile *f)
515{
516 int ret;
517 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
518 /* Restore the interrupt status bit. */
519 pci_update_irq_status(s);
520 return ret;
521}
522
523static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
524{
525 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
526 pci_default_sub_vendor_id);
527 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
528 pci_default_sub_device_id);
529}
530
531/*
532 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
533 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
534 */
535int pci_parse_devaddr(const char *addr, int *domp, int *busp,
536 unsigned int *slotp, unsigned int *funcp)
537{
538 const char *p;
539 char *e;
540 unsigned long val;
541 unsigned long dom = 0, bus = 0;
542 unsigned int slot = 0;
543 unsigned int func = 0;
544
545 p = addr;
546 val = strtoul(p, &e, 16);
547 if (e == p)
548 return -1;
549 if (*e == ':') {
550 bus = val;
551 p = e + 1;
552 val = strtoul(p, &e, 16);
553 if (e == p)
554 return -1;
555 if (*e == ':') {
556 dom = bus;
557 bus = val;
558 p = e + 1;
559 val = strtoul(p, &e, 16);
560 if (e == p)
561 return -1;
562 }
563 }
564
565 slot = val;
566
567 if (funcp != NULL) {
568 if (*e != '.')
569 return -1;
570
571 p = e + 1;
572 val = strtoul(p, &e, 16);
573 if (e == p)
574 return -1;
575
576 func = val;
577 }
578
579 /* if funcp == NULL func is 0 */
580 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
581 return -1;
582
583 if (*e)
584 return -1;
585
586 *domp = dom;
587 *busp = bus;
588 *slotp = slot;
589 if (funcp != NULL)
590 *funcp = func;
591 return 0;
592}
593
594PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr)
595{
596 int dom, bus;
597 unsigned slot;
598
599 assert(!root->parent_dev);
600
601 if (!root) {
602 fprintf(stderr, "No primary PCI bus\n");
603 return NULL;
604 }
605
606 if (!devaddr) {
607 *devfnp = -1;
608 return pci_find_bus_nr(root, 0);
609 }
610
611 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
612 return NULL;
613 }
614
615 if (dom != 0) {
616 fprintf(stderr, "No support for non-zero PCI domains\n");
617 return NULL;
618 }
619
620 *devfnp = PCI_DEVFN(slot, 0);
621 return pci_find_bus_nr(root, bus);
622}
623
624static void pci_init_cmask(PCIDevice *dev)
625{
626 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
627 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
628 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
629 dev->cmask[PCI_REVISION_ID] = 0xff;
630 dev->cmask[PCI_CLASS_PROG] = 0xff;
631 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
632 dev->cmask[PCI_HEADER_TYPE] = 0xff;
633 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
634}
635
636static void pci_init_wmask(PCIDevice *dev)
637{
638 int config_size = pci_config_size(dev);
639
640 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
641 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
642 pci_set_word(dev->wmask + PCI_COMMAND,
643 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
644 PCI_COMMAND_INTX_DISABLE);
645 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
646 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
647 }
648
649 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
650 config_size - PCI_CONFIG_HEADER_SIZE);
651}
652
653static void pci_init_w1cmask(PCIDevice *dev)
654{
655 /*
656 * Note: It's okay to set w1cmask even for readonly bits as
657 * long as their value is hardwired to 0.
658 */
659 pci_set_word(dev->w1cmask + PCI_STATUS,
660 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
661 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
662 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
663}
664
665static void pci_init_mask_bridge(PCIDevice *d)
666{
667 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
668 PCI_SEC_LETENCY_TIMER */
669 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
670
671 /* base and limit */
672 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
673 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
674 pci_set_word(d->wmask + PCI_MEMORY_BASE,
675 PCI_MEMORY_RANGE_MASK & 0xffff);
676 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
677 PCI_MEMORY_RANGE_MASK & 0xffff);
678 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
679 PCI_PREF_RANGE_MASK & 0xffff);
680 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
681 PCI_PREF_RANGE_MASK & 0xffff);
682
683 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
684 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
685
686 /* Supported memory and i/o types */
687 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
688 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
689 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
690 PCI_PREF_RANGE_TYPE_64);
691 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
692 PCI_PREF_RANGE_TYPE_64);
693
694 /*
695 * TODO: Bridges default to 10-bit VGA decoding but we currently only
696 * implement 16-bit decoding (no alias support).
697 */
698 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
699 PCI_BRIDGE_CTL_PARITY |
700 PCI_BRIDGE_CTL_SERR |
701 PCI_BRIDGE_CTL_ISA |
702 PCI_BRIDGE_CTL_VGA |
703 PCI_BRIDGE_CTL_VGA_16BIT |
704 PCI_BRIDGE_CTL_MASTER_ABORT |
705 PCI_BRIDGE_CTL_BUS_RESET |
706 PCI_BRIDGE_CTL_FAST_BACK |
707 PCI_BRIDGE_CTL_DISCARD |
708 PCI_BRIDGE_CTL_SEC_DISCARD |
709 PCI_BRIDGE_CTL_DISCARD_SERR);
710 /* Below does not do anything as we never set this bit, put here for
711 * completeness. */
712 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
713 PCI_BRIDGE_CTL_DISCARD_STATUS);
714 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
715 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
716 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
717 PCI_PREF_RANGE_TYPE_MASK);
718 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
719 PCI_PREF_RANGE_TYPE_MASK);
720}
721
722static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
723{
724 uint8_t slot = PCI_SLOT(dev->devfn);
725 uint8_t func;
726
727 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
728 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
729 }
730
731 /*
732 * multifunction bit is interpreted in two ways as follows.
733 * - all functions must set the bit to 1.
734 * Example: Intel X53
735 * - function 0 must set the bit, but the rest function (> 0)
736 * is allowed to leave the bit to 0.
737 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
738 *
739 * So OS (at least Linux) checks the bit of only function 0,
740 * and doesn't see the bit of function > 0.
741 *
742 * The below check allows both interpretation.
743 */
744 if (PCI_FUNC(dev->devfn)) {
745 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
746 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
747 /* function 0 should set multifunction bit */
748 error_report("PCI: single function device can't be populated "
749 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
750 return -1;
751 }
752 return 0;
753 }
754
755 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
756 return 0;
757 }
758 /* function 0 indicates single function, so function > 0 must be NULL */
759 for (func = 1; func < PCI_FUNC_MAX; ++func) {
760 if (bus->devices[PCI_DEVFN(slot, func)]) {
761 error_report("PCI: %x.0 indicates single function, "
762 "but %x.%x is already populated.",
763 slot, slot, func);
764 return -1;
765 }
766 }
767 return 0;
768}
769
770static void pci_config_alloc(PCIDevice *pci_dev)
771{
772 int config_size = pci_config_size(pci_dev);
773
774 pci_dev->config = g_malloc0(config_size);
775 pci_dev->cmask = g_malloc0(config_size);
776 pci_dev->wmask = g_malloc0(config_size);
777 pci_dev->w1cmask = g_malloc0(config_size);
778 pci_dev->used = g_malloc0(config_size);
779}
780
781static void pci_config_free(PCIDevice *pci_dev)
782{
783 g_free(pci_dev->config);
784 g_free(pci_dev->cmask);
785 g_free(pci_dev->wmask);
786 g_free(pci_dev->w1cmask);
787 g_free(pci_dev->used);
788}
789
790/* -1 for devfn means auto assign */
791static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
792 const char *name, int devfn)
793{
794 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
795 PCIConfigReadFunc *config_read = pc->config_read;
796 PCIConfigWriteFunc *config_write = pc->config_write;
797 AddressSpace *dma_as;
798
799 if (devfn < 0) {
800 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
801 devfn += PCI_FUNC_MAX) {
802 if (!bus->devices[devfn])
803 goto found;
804 }
805 error_report("PCI: no slot/function available for %s, all in use", name);
806 return NULL;
807 found: ;
808 } else if (bus->devices[devfn]) {
809 error_report("PCI: slot %d function %d not available for %s, in use by %s",
810 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
811 return NULL;
812 }
813
814 pci_dev->bus = bus;
815 dma_as = pci_device_iommu_address_space(pci_dev);
816
817 memory_region_init_alias(&pci_dev->bus_master_enable_region,
818 OBJECT(pci_dev), "bus master",
819 dma_as->root, 0, memory_region_size(dma_as->root));
820 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
821 address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region,
822 name);
823
824 pci_dev->devfn = devfn;
825 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
826 pci_dev->irq_state = 0;
827 pci_config_alloc(pci_dev);
828
829 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
830 pci_config_set_device_id(pci_dev->config, pc->device_id);
831 pci_config_set_revision(pci_dev->config, pc->revision);
832 pci_config_set_class(pci_dev->config, pc->class_id);
833
834 if (!pc->is_bridge) {
835 if (pc->subsystem_vendor_id || pc->subsystem_id) {
836 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
837 pc->subsystem_vendor_id);
838 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
839 pc->subsystem_id);
840 } else {
841 pci_set_default_subsystem_id(pci_dev);
842 }
843 } else {
844 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
845 assert(!pc->subsystem_vendor_id);
846 assert(!pc->subsystem_id);
847 }
848 pci_init_cmask(pci_dev);
849 pci_init_wmask(pci_dev);
850 pci_init_w1cmask(pci_dev);
851 if (pc->is_bridge) {
852 pci_init_mask_bridge(pci_dev);
853 }
854 if (pci_init_multifunction(bus, pci_dev)) {
855 pci_config_free(pci_dev);
856 return NULL;
857 }
858
859 if (!config_read)
860 config_read = pci_default_read_config;
861 if (!config_write)
862 config_write = pci_default_write_config;
863 pci_dev->config_read = config_read;
864 pci_dev->config_write = config_write;
865 bus->devices[devfn] = pci_dev;
866 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
867 pci_dev->version_id = 2; /* Current pci device vmstate version */
868 return pci_dev;
869}
870
871static void do_pci_unregister_device(PCIDevice *pci_dev)
872{
873 qemu_free_irqs(pci_dev->irq);
874 pci_dev->bus->devices[pci_dev->devfn] = NULL;
875 pci_config_free(pci_dev);
876
877 address_space_destroy(&pci_dev->bus_master_as);
878 memory_region_destroy(&pci_dev->bus_master_enable_region);
879}
880
881static void pci_unregister_io_regions(PCIDevice *pci_dev)
882{
883 PCIIORegion *r;
884 int i;
885
886 for(i = 0; i < PCI_NUM_REGIONS; i++) {
887 r = &pci_dev->io_regions[i];
888 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
889 continue;
890 memory_region_del_subregion(r->address_space, r->memory);
891 }
892
893 pci_unregister_vga(pci_dev);
894}
895
896static int pci_unregister_device(DeviceState *dev)
897{
898 PCIDevice *pci_dev = PCI_DEVICE(dev);
899 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
900
901 pci_unregister_io_regions(pci_dev);
902 pci_del_option_rom(pci_dev);
903
904 if (pc->exit) {
905 pc->exit(pci_dev);
906 }
907
908 do_pci_unregister_device(pci_dev);
909 return 0;
910}
911
912void pci_register_bar(PCIDevice *pci_dev, int region_num,
913 uint8_t type, MemoryRegion *memory)
914{
915 PCIIORegion *r;
916 uint32_t addr;
917 uint64_t wmask;
918 pcibus_t size = memory_region_size(memory);
919
920 assert(region_num >= 0);
921 assert(region_num < PCI_NUM_REGIONS);
922 if (size & (size-1)) {
923 fprintf(stderr, "ERROR: PCI region size must be pow2 "
924 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
925 exit(1);
926 }
927
928 r = &pci_dev->io_regions[region_num];
929 r->addr = PCI_BAR_UNMAPPED;
930 r->size = size;
931 r->type = type;
932 r->memory = NULL;
933
934 wmask = ~(size - 1);
935 addr = pci_bar(pci_dev, region_num);
936 if (region_num == PCI_ROM_SLOT) {
937 /* ROM enable bit is writable */
938 wmask |= PCI_ROM_ADDRESS_ENABLE;
939 }
940 pci_set_long(pci_dev->config + addr, type);
941 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
942 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
943 pci_set_quad(pci_dev->wmask + addr, wmask);
944 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
945 } else {
946 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
947 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
948 }
949 pci_dev->io_regions[region_num].memory = memory;
950 pci_dev->io_regions[region_num].address_space
951 = type & PCI_BASE_ADDRESS_SPACE_IO
952 ? pci_dev->bus->address_space_io
953 : pci_dev->bus->address_space_mem;
954}
955
956static void pci_update_vga(PCIDevice *pci_dev)
957{
958 uint16_t cmd;
959
960 if (!pci_dev->has_vga) {
961 return;
962 }
963
964 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
965
966 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
967 cmd & PCI_COMMAND_MEMORY);
968 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
969 cmd & PCI_COMMAND_IO);
970 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
971 cmd & PCI_COMMAND_IO);
972}
973
974void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
975 MemoryRegion *io_lo, MemoryRegion *io_hi)
976{
977 assert(!pci_dev->has_vga);
978
979 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
980 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
981 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem,
982 QEMU_PCI_VGA_MEM_BASE, mem, 1);
983
984 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
985 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
986 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
987 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
988
989 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
990 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
991 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
992 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
993 pci_dev->has_vga = true;
994
995 pci_update_vga(pci_dev);
996}
997
998void pci_unregister_vga(PCIDevice *pci_dev)
999{
1000 if (!pci_dev->has_vga) {
1001 return;
1002 }
1003
1004 memory_region_del_subregion(pci_dev->bus->address_space_mem,
1005 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
1006 memory_region_del_subregion(pci_dev->bus->address_space_io,
1007 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
1008 memory_region_del_subregion(pci_dev->bus->address_space_io,
1009 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1010 pci_dev->has_vga = false;
1011}
1012
1013pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1014{
1015 return pci_dev->io_regions[region_num].addr;
1016}
1017
1018static pcibus_t pci_bar_address(PCIDevice *d,
1019 int reg, uint8_t type, pcibus_t size)
1020{
1021 pcibus_t new_addr, last_addr;
1022 int bar = pci_bar(d, reg);
1023 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1024
1025 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1026 if (!(cmd & PCI_COMMAND_IO)) {
1027 return PCI_BAR_UNMAPPED;
1028 }
1029 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1030 last_addr = new_addr + size - 1;
1031 /* NOTE: we have only 64K ioports on PC */
1032 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
1033 return PCI_BAR_UNMAPPED;
1034 }
1035 return new_addr;
1036 }
1037
1038 if (!(cmd & PCI_COMMAND_MEMORY)) {
1039 return PCI_BAR_UNMAPPED;
1040 }
1041 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1042 new_addr = pci_get_quad(d->config + bar);
1043 } else {
1044 new_addr = pci_get_long(d->config + bar);
1045 }
1046 /* the ROM slot has a specific enable bit */
1047 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1048 return PCI_BAR_UNMAPPED;
1049 }
1050 new_addr &= ~(size - 1);
1051 last_addr = new_addr + size - 1;
1052 /* NOTE: we do not support wrapping */
1053 /* XXX: as we cannot support really dynamic
1054 mappings, we handle specific values as invalid
1055 mappings. */
1056 if (last_addr <= new_addr || new_addr == 0 ||
1057 last_addr == PCI_BAR_UNMAPPED) {
1058 return PCI_BAR_UNMAPPED;
1059 }
1060
1061 /* Now pcibus_t is 64bit.
1062 * Check if 32 bit BAR wraps around explicitly.
1063 * Without this, PC ide doesn't work well.
1064 * TODO: remove this work around.
1065 */
1066 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1067 return PCI_BAR_UNMAPPED;
1068 }
1069
1070 /*
1071 * OS is allowed to set BAR beyond its addressable
1072 * bits. For example, 32 bit OS can set 64bit bar
1073 * to >4G. Check it. TODO: we might need to support
1074 * it in the future for e.g. PAE.
1075 */
1076 if (last_addr >= HWADDR_MAX) {
1077 return PCI_BAR_UNMAPPED;
1078 }
1079
1080 return new_addr;
1081}
1082
1083static void pci_update_mappings(PCIDevice *d)
1084{
1085 PCIIORegion *r;
1086 int i;
1087 pcibus_t new_addr;
1088
1089 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1090 r = &d->io_regions[i];
1091
1092 /* this region isn't registered */
1093 if (!r->size)
1094 continue;
1095
1096 new_addr = pci_bar_address(d, i, r->type, r->size);
1097
1098 /* This bar isn't changed */
1099 if (new_addr == r->addr)
1100 continue;
1101
1102 /* now do the real mapping */
1103 if (r->addr != PCI_BAR_UNMAPPED) {
1104 memory_region_del_subregion(r->address_space, r->memory);
1105 }
1106 r->addr = new_addr;
1107 if (r->addr != PCI_BAR_UNMAPPED) {
1108 memory_region_add_subregion_overlap(r->address_space,
1109 r->addr, r->memory, 1);
1110 }
1111 }
1112
1113 pci_update_vga(d);
1114}
1115
1116static inline int pci_irq_disabled(PCIDevice *d)
1117{
1118 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1119}
1120
1121/* Called after interrupt disabled field update in config space,
1122 * assert/deassert interrupts if necessary.
1123 * Gets original interrupt disable bit value (before update). */
1124static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1125{
1126 int i, disabled = pci_irq_disabled(d);
1127 if (disabled == was_irq_disabled)
1128 return;
1129 for (i = 0; i < PCI_NUM_PINS; ++i) {
1130 int state = pci_irq_state(d, i);
1131 pci_change_irq_level(d, i, disabled ? -state : state);
1132 }
1133}
1134
1135uint32_t pci_default_read_config(PCIDevice *d,
1136 uint32_t address, int len)
1137{
1138 uint32_t val = 0;
1139
1140 memcpy(&val, d->config + address, len);
1141 return le32_to_cpu(val);
1142}
1143
1144void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1145{
1146 int i, was_irq_disabled = pci_irq_disabled(d);
1147
1148 for (i = 0; i < l; val >>= 8, ++i) {
1149 uint8_t wmask = d->wmask[addr + i];
1150 uint8_t w1cmask = d->w1cmask[addr + i];
1151 assert(!(wmask & w1cmask));
1152 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1153 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1154 }
1155 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1156 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1157 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1158 range_covers_byte(addr, l, PCI_COMMAND))
1159 pci_update_mappings(d);
1160
1161 if (range_covers_byte(addr, l, PCI_COMMAND)) {
1162 pci_update_irq_disabled(d, was_irq_disabled);
1163 memory_region_set_enabled(&d->bus_master_enable_region,
1164 pci_get_word(d->config + PCI_COMMAND)
1165 & PCI_COMMAND_MASTER);
1166 }
1167
1168 msi_write_config(d, addr, val, l);
1169 msix_write_config(d, addr, val, l);
1170}
1171
1172/***********************************************************/
1173/* generic PCI irq support */
1174
1175/* 0 <= irq_num <= 3. level must be 0 or 1 */
1176static void pci_set_irq(void *opaque, int irq_num, int level)
1177{
1178 PCIDevice *pci_dev = opaque;
1179 int change;
1180
1181 change = level - pci_irq_state(pci_dev, irq_num);
1182 if (!change)
1183 return;
1184
1185 pci_set_irq_state(pci_dev, irq_num, level);
1186 pci_update_irq_status(pci_dev);
1187 if (pci_irq_disabled(pci_dev))
1188 return;
1189 pci_change_irq_level(pci_dev, irq_num, change);
1190}
1191
1192/* Special hooks used by device assignment */
1193void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1194{
1195 assert(pci_bus_is_root(bus));
1196 bus->route_intx_to_irq = route_intx_to_irq;
1197}
1198
1199PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1200{
1201 PCIBus *bus;
1202
1203 do {
1204 bus = dev->bus;
1205 pin = bus->map_irq(dev, pin);
1206 dev = bus->parent_dev;
1207 } while (dev);
1208
1209 if (!bus->route_intx_to_irq) {
1210 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1211 object_get_typename(OBJECT(bus->qbus.parent)));
1212 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1213 }
1214
1215 return bus->route_intx_to_irq(bus->irq_opaque, pin);
1216}
1217
1218bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1219{
1220 return old->mode != new->mode || old->irq != new->irq;
1221}
1222
1223void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1224{
1225 PCIDevice *dev;
1226 PCIBus *sec;
1227 int i;
1228
1229 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1230 dev = bus->devices[i];
1231 if (dev && dev->intx_routing_notifier) {
1232 dev->intx_routing_notifier(dev);
1233 }
1234 }
1235
1236 QLIST_FOREACH(sec, &bus->child, sibling) {
1237 pci_bus_fire_intx_routing_notifier(sec);
1238 }
1239}
1240
1241void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1242 PCIINTxRoutingNotifier notifier)
1243{
1244 dev->intx_routing_notifier = notifier;
1245}
1246
1247/*
1248 * PCI-to-PCI bridge specification
1249 * 9.1: Interrupt routing. Table 9-1
1250 *
1251 * the PCI Express Base Specification, Revision 2.1
1252 * 2.2.8.1: INTx interrutp signaling - Rules
1253 * the Implementation Note
1254 * Table 2-20
1255 */
1256/*
1257 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1258 * 0-origin unlike PCI interrupt pin register.
1259 */
1260int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1261{
1262 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
1263}
1264
1265/***********************************************************/
1266/* monitor info on PCI */
1267
1268typedef struct {
1269 uint16_t class;
1270 const char *desc;
1271 const char *fw_name;
1272 uint16_t fw_ign_bits;
1273} pci_class_desc;
1274
1275static const pci_class_desc pci_class_descriptions[] =
1276{
1277 { 0x0001, "VGA controller", "display"},
1278 { 0x0100, "SCSI controller", "scsi"},
1279 { 0x0101, "IDE controller", "ide"},
1280 { 0x0102, "Floppy controller", "fdc"},
1281 { 0x0103, "IPI controller", "ipi"},
1282 { 0x0104, "RAID controller", "raid"},
1283 { 0x0106, "SATA controller"},
1284 { 0x0107, "SAS controller"},
1285 { 0x0180, "Storage controller"},
1286 { 0x0200, "Ethernet controller", "ethernet"},
1287 { 0x0201, "Token Ring controller", "token-ring"},
1288 { 0x0202, "FDDI controller", "fddi"},
1289 { 0x0203, "ATM controller", "atm"},
1290 { 0x0280, "Network controller"},
1291 { 0x0300, "VGA controller", "display", 0x00ff},
1292 { 0x0301, "XGA controller"},
1293 { 0x0302, "3D controller"},
1294 { 0x0380, "Display controller"},
1295 { 0x0400, "Video controller", "video"},
1296 { 0x0401, "Audio controller", "sound"},
1297 { 0x0402, "Phone"},
1298 { 0x0403, "Audio controller", "sound"},
1299 { 0x0480, "Multimedia controller"},
1300 { 0x0500, "RAM controller", "memory"},
1301 { 0x0501, "Flash controller", "flash"},
1302 { 0x0580, "Memory controller"},
1303 { 0x0600, "Host bridge", "host"},
1304 { 0x0601, "ISA bridge", "isa"},
1305 { 0x0602, "EISA bridge", "eisa"},
1306 { 0x0603, "MC bridge", "mca"},
1307 { 0x0604, "PCI bridge", "pci"},
1308 { 0x0605, "PCMCIA bridge", "pcmcia"},
1309 { 0x0606, "NUBUS bridge", "nubus"},
1310 { 0x0607, "CARDBUS bridge", "cardbus"},
1311 { 0x0608, "RACEWAY bridge"},
1312 { 0x0680, "Bridge"},
1313 { 0x0700, "Serial port", "serial"},
1314 { 0x0701, "Parallel port", "parallel"},
1315 { 0x0800, "Interrupt controller", "interrupt-controller"},
1316 { 0x0801, "DMA controller", "dma-controller"},
1317 { 0x0802, "Timer", "timer"},
1318 { 0x0803, "RTC", "rtc"},
1319 { 0x0900, "Keyboard", "keyboard"},
1320 { 0x0901, "Pen", "pen"},
1321 { 0x0902, "Mouse", "mouse"},
1322 { 0x0A00, "Dock station", "dock", 0x00ff},
1323 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1324 { 0x0c00, "Fireware contorller", "fireware"},
1325 { 0x0c01, "Access bus controller", "access-bus"},
1326 { 0x0c02, "SSA controller", "ssa"},
1327 { 0x0c03, "USB controller", "usb"},
1328 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1329 { 0x0c05, "SMBus"},
1330 { 0, NULL}
1331};
1332
1333static void pci_for_each_device_under_bus(PCIBus *bus,
1334 void (*fn)(PCIBus *b, PCIDevice *d,
1335 void *opaque),
1336 void *opaque)
1337{
1338 PCIDevice *d;
1339 int devfn;
1340
1341 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1342 d = bus->devices[devfn];
1343 if (d) {
1344 fn(bus, d, opaque);
1345 }
1346 }
1347}
1348
1349void pci_for_each_device(PCIBus *bus, int bus_num,
1350 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1351 void *opaque)
1352{
1353 bus = pci_find_bus_nr(bus, bus_num);
1354
1355 if (bus) {
1356 pci_for_each_device_under_bus(bus, fn, opaque);
1357 }
1358}
1359
1360static const pci_class_desc *get_class_desc(int class)
1361{
1362 const pci_class_desc *desc;
1363
1364 desc = pci_class_descriptions;
1365 while (desc->desc && class != desc->class) {
1366 desc++;
1367 }
1368
1369 return desc;
1370}
1371
1372static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1373
1374static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1375{
1376 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1377 int i;
1378
1379 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1380 const PCIIORegion *r = &dev->io_regions[i];
1381 PciMemoryRegionList *region;
1382
1383 if (!r->size) {
1384 continue;
1385 }
1386
1387 region = g_malloc0(sizeof(*region));
1388 region->value = g_malloc0(sizeof(*region->value));
1389
1390 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1391 region->value->type = g_strdup("io");
1392 } else {
1393 region->value->type = g_strdup("memory");
1394 region->value->has_prefetch = true;
1395 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1396 region->value->has_mem_type_64 = true;
1397 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1398 }
1399
1400 region->value->bar = i;
1401 region->value->address = r->addr;
1402 region->value->size = r->size;
1403
1404 /* XXX: waiting for the qapi to support GSList */
1405 if (!cur_item) {
1406 head = cur_item = region;
1407 } else {
1408 cur_item->next = region;
1409 cur_item = region;
1410 }
1411 }
1412
1413 return head;
1414}
1415
1416static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1417 int bus_num)
1418{
1419 PciBridgeInfo *info;
1420
1421 info = g_malloc0(sizeof(*info));
1422
1423 info->bus.number = dev->config[PCI_PRIMARY_BUS];
1424 info->bus.secondary = dev->config[PCI_SECONDARY_BUS];
1425 info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS];
1426
1427 info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range));
1428 info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1429 info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1430
1431 info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range));
1432 info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1433 info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1434
1435 info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range));
1436 info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1437 info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1438
1439 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1440 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
1441 if (child_bus) {
1442 info->has_devices = true;
1443 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1444 }
1445 }
1446
1447 return info;
1448}
1449
1450static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1451 int bus_num)
1452{
1453 const pci_class_desc *desc;
1454 PciDeviceInfo *info;
1455 uint8_t type;
1456 int class;
1457
1458 info = g_malloc0(sizeof(*info));
1459 info->bus = bus_num;
1460 info->slot = PCI_SLOT(dev->devfn);
1461 info->function = PCI_FUNC(dev->devfn);
1462
1463 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1464 info->class_info.q_class = class;
1465 desc = get_class_desc(class);
1466 if (desc->desc) {
1467 info->class_info.has_desc = true;
1468 info->class_info.desc = g_strdup(desc->desc);
1469 }
1470
1471 info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1472 info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID);
1473 info->regions = qmp_query_pci_regions(dev);
1474 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1475
1476 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1477 info->has_irq = true;
1478 info->irq = dev->config[PCI_INTERRUPT_LINE];
1479 }
1480
1481 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1482 if (type == PCI_HEADER_TYPE_BRIDGE) {
1483 info->has_pci_bridge = true;
1484 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1485 }
1486
1487 return info;
1488}
1489
1490static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1491{
1492 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
1493 PCIDevice *dev;
1494 int devfn;
1495
1496 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1497 dev = bus->devices[devfn];
1498 if (dev) {
1499 info = g_malloc0(sizeof(*info));
1500 info->value = qmp_query_pci_device(dev, bus, bus_num);
1501
1502 /* XXX: waiting for the qapi to support GSList */
1503 if (!cur_item) {
1504 head = cur_item = info;
1505 } else {
1506 cur_item->next = info;
1507 cur_item = info;
1508 }
1509 }
1510 }
1511
1512 return head;
1513}
1514
1515static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1516{
1517 PciInfo *info = NULL;
1518
1519 bus = pci_find_bus_nr(bus, bus_num);
1520 if (bus) {
1521 info = g_malloc0(sizeof(*info));
1522 info->bus = bus_num;
1523 info->devices = qmp_query_pci_devices(bus, bus_num);
1524 }
1525
1526 return info;
1527}
1528
1529PciInfoList *qmp_query_pci(Error **errp)
1530{
1531 PciInfoList *info, *head = NULL, *cur_item = NULL;
1532 PCIHostState *host_bridge;
1533
1534 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
1535 info = g_malloc0(sizeof(*info));
1536 info->value = qmp_query_pci_bus(host_bridge->bus, 0);
1537
1538 /* XXX: waiting for the qapi to support GSList */
1539 if (!cur_item) {
1540 head = cur_item = info;
1541 } else {
1542 cur_item->next = info;
1543 cur_item = info;
1544 }
1545 }
1546
1547 return head;
1548}
1549
1550static const char * const pci_nic_models[] = {
1551 "ne2k_pci",
1552 "i82551",
1553 "i82557b",
1554 "i82559er",
1555 "rtl8139",
1556 "e1000",
1557 "pcnet",
1558 "virtio",
1559 NULL
1560};
1561
1562static const char * const pci_nic_names[] = {
1563 "ne2k_pci",
1564 "i82551",
1565 "i82557b",
1566 "i82559er",
1567 "rtl8139",
1568 "e1000",
1569 "pcnet",
1570 "virtio-net-pci",
1571 NULL
1572};
1573
1574/* Initialize a PCI NIC. */
1575/* FIXME callers should check for failure, but don't */
1576PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus,
1577 const char *default_model,
1578 const char *default_devaddr)
1579{
1580 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1581 PCIBus *bus;
1582 int devfn;
1583 PCIDevice *pci_dev;
1584 DeviceState *dev;
1585 int i;
1586
1587 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1588 if (i < 0)
1589 return NULL;
1590
1591 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
1592 if (!bus) {
1593 error_report("Invalid PCI device address %s for device %s",
1594 devaddr, pci_nic_names[i]);
1595 return NULL;
1596 }
1597
1598 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1599 dev = &pci_dev->qdev;
1600 qdev_set_nic_properties(dev, nd);
1601 if (qdev_init(dev) < 0)
1602 return NULL;
1603 return pci_dev;
1604}
1605
1606PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
1607 const char *default_model,
1608 const char *default_devaddr)
1609{
1610 PCIDevice *res;
1611
1612 if (qemu_show_nic_models(nd->model, pci_nic_models))
1613 exit(0);
1614
1615 res = pci_nic_init(nd, rootbus, default_model, default_devaddr);
1616 if (!res)
1617 exit(1);
1618 return res;
1619}
1620
1621PCIDevice *pci_vga_init(PCIBus *bus)
1622{
1623 switch (vga_interface_type) {
1624 case VGA_CIRRUS:
1625 return pci_create_simple(bus, -1, "cirrus-vga");
1626 case VGA_QXL:
1627 return pci_create_simple(bus, -1, "qxl-vga");
1628 case VGA_STD:
1629 return pci_create_simple(bus, -1, "VGA");
1630 case VGA_VMWARE:
1631 return pci_create_simple(bus, -1, "vmware-svga");
1632 case VGA_NONE:
1633 default: /* Other non-PCI types. Checking for unsupported types is already
1634 done in vl.c. */
1635 return NULL;
1636 }
1637}
1638
1639/* Whether a given bus number is in range of the secondary
1640 * bus of the given bridge device. */
1641static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1642{
1643 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1644 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1645 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1646 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1647}
1648
1649static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
1650{
1651 PCIBus *sec;
1652
1653 if (!bus) {
1654 return NULL;
1655 }
1656
1657 if (pci_bus_num(bus) == bus_num) {
1658 return bus;
1659 }
1660
1661 /* Consider all bus numbers in range for the host pci bridge. */
1662 if (!pci_bus_is_root(bus) &&
1663 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1664 return NULL;
1665 }
1666
1667 /* try child bus */
1668 for (; bus; bus = sec) {
1669 QLIST_FOREACH(sec, &bus->child, sibling) {
1670 assert(!pci_bus_is_root(sec));
1671 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1672 return sec;
1673 }
1674 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1675 break;
1676 }
1677 }
1678 }
1679
1680 return NULL;
1681}
1682
1683PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1684{
1685 bus = pci_find_bus_nr(bus, bus_num);
1686
1687 if (!bus)
1688 return NULL;
1689
1690 return bus->devices[devfn];
1691}
1692
1693static int pci_qdev_init(DeviceState *qdev)
1694{
1695 PCIDevice *pci_dev = (PCIDevice *)qdev;
1696 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1697 PCIBus *bus;
1698 int rc;
1699 bool is_default_rom;
1700
1701 /* initialize cap_present for pci_is_express() and pci_config_size() */
1702 if (pc->is_express) {
1703 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1704 }
1705
1706 bus = PCI_BUS(qdev_get_parent_bus(qdev));
1707 pci_dev = do_pci_register_device(pci_dev, bus,
1708 object_get_typename(OBJECT(qdev)),
1709 pci_dev->devfn);
1710 if (pci_dev == NULL)
1711 return -1;
1712 if (qdev->hotplugged && pc->no_hotplug) {
1713 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(pci_dev)));
1714 do_pci_unregister_device(pci_dev);
1715 return -1;
1716 }
1717 if (pc->init) {
1718 rc = pc->init(pci_dev);
1719 if (rc != 0) {
1720 do_pci_unregister_device(pci_dev);
1721 return rc;
1722 }
1723 }
1724
1725 /* rom loading */
1726 is_default_rom = false;
1727 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
1728 pci_dev->romfile = g_strdup(pc->romfile);
1729 is_default_rom = true;
1730 }
1731 pci_add_option_rom(pci_dev, is_default_rom);
1732
1733 if (bus->hotplug) {
1734 /* Let buses differentiate between hotplug and when device is
1735 * enabled during qemu machine creation. */
1736 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1737 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1738 PCI_COLDPLUG_ENABLED);
1739 if (rc != 0) {
1740 int r = pci_unregister_device(&pci_dev->qdev);
1741 assert(!r);
1742 return rc;
1743 }
1744 }
1745 return 0;
1746}
1747
1748static int pci_unplug_device(DeviceState *qdev)
1749{
1750 PCIDevice *dev = PCI_DEVICE(qdev);
1751 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
1752
1753 if (pc->no_hotplug) {
1754 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(dev)));
1755 return -1;
1756 }
1757 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1758 PCI_HOTPLUG_DISABLED);
1759}
1760
1761PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1762 const char *name)
1763{
1764 DeviceState *dev;
1765
1766 dev = qdev_create(&bus->qbus, name);
1767 qdev_prop_set_int32(dev, "addr", devfn);
1768 qdev_prop_set_bit(dev, "multifunction", multifunction);
1769 return PCI_DEVICE(dev);
1770}
1771
1772PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1773 bool multifunction,
1774 const char *name)
1775{
1776 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1777 qdev_init_nofail(&dev->qdev);
1778 return dev;
1779}
1780
1781PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1782{
1783 return pci_create_multifunction(bus, devfn, false, name);
1784}
1785
1786PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1787{
1788 return pci_create_simple_multifunction(bus, devfn, false, name);
1789}
1790
1791static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
1792{
1793 int offset = PCI_CONFIG_HEADER_SIZE;
1794 int i;
1795 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
1796 if (pdev->used[i])
1797 offset = i + 1;
1798 else if (i - offset + 1 == size)
1799 return offset;
1800 }
1801 return 0;
1802}
1803
1804static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1805 uint8_t *prev_p)
1806{
1807 uint8_t next, prev;
1808
1809 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1810 return 0;
1811
1812 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1813 prev = next + PCI_CAP_LIST_NEXT)
1814 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1815 break;
1816
1817 if (prev_p)
1818 *prev_p = prev;
1819 return next;
1820}
1821
1822static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
1823{
1824 uint8_t next, prev, found = 0;
1825
1826 if (!(pdev->used[offset])) {
1827 return 0;
1828 }
1829
1830 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
1831
1832 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1833 prev = next + PCI_CAP_LIST_NEXT) {
1834 if (next <= offset && next > found) {
1835 found = next;
1836 }
1837 }
1838 return found;
1839}
1840
1841/* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1842 This is needed for an option rom which is used for more than one device. */
1843static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1844{
1845 uint16_t vendor_id;
1846 uint16_t device_id;
1847 uint16_t rom_vendor_id;
1848 uint16_t rom_device_id;
1849 uint16_t rom_magic;
1850 uint16_t pcir_offset;
1851 uint8_t checksum;
1852
1853 /* Words in rom data are little endian (like in PCI configuration),
1854 so they can be read / written with pci_get_word / pci_set_word. */
1855
1856 /* Only a valid rom will be patched. */
1857 rom_magic = pci_get_word(ptr);
1858 if (rom_magic != 0xaa55) {
1859 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1860 return;
1861 }
1862 pcir_offset = pci_get_word(ptr + 0x18);
1863 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1864 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1865 return;
1866 }
1867
1868 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1869 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1870 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1871 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1872
1873 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1874 vendor_id, device_id, rom_vendor_id, rom_device_id);
1875
1876 checksum = ptr[6];
1877
1878 if (vendor_id != rom_vendor_id) {
1879 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1880 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1881 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1882 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1883 ptr[6] = checksum;
1884 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1885 }
1886
1887 if (device_id != rom_device_id) {
1888 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1889 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1890 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1891 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1892 ptr[6] = checksum;
1893 pci_set_word(ptr + pcir_offset + 6, device_id);
1894 }
1895}
1896
1897/* Add an option rom for the device */
1898static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1899{
1900 int size;
1901 char *path;
1902 void *ptr;
1903 char name[32];
1904 const VMStateDescription *vmsd;
1905
1906 if (!pdev->romfile)
1907 return 0;
1908 if (strlen(pdev->romfile) == 0)
1909 return 0;
1910
1911 if (!pdev->rom_bar) {
1912 /*
1913 * Load rom via fw_cfg instead of creating a rom bar,
1914 * for 0.11 compatibility.
1915 */
1916 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1917 if (class == 0x0300) {
1918 rom_add_vga(pdev->romfile);
1919 } else {
1920 rom_add_option(pdev->romfile, -1);
1921 }
1922 return 0;
1923 }
1924
1925 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1926 if (path == NULL) {
1927 path = g_strdup(pdev->romfile);
1928 }
1929
1930 size = get_image_size(path);
1931 if (size < 0) {
1932 error_report("%s: failed to find romfile \"%s\"",
1933 __func__, pdev->romfile);
1934 g_free(path);
1935 return -1;
1936 } else if (size == 0) {
1937 error_report("%s: ignoring empty romfile \"%s\"",
1938 __func__, pdev->romfile);
1939 g_free(path);
1940 return -1;
1941 }
1942 if (size & (size - 1)) {
1943 size = 1 << qemu_fls(size);
1944 }
1945
1946 vmsd = qdev_get_vmsd(DEVICE(pdev));
1947
1948 if (vmsd) {
1949 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
1950 } else {
1951 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
1952 }
1953 pdev->has_rom = true;
1954 memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size);
1955 vmstate_register_ram(&pdev->rom, &pdev->qdev);
1956 ptr = memory_region_get_ram_ptr(&pdev->rom);
1957 load_image(path, ptr);
1958 g_free(path);
1959
1960 if (is_default_rom) {
1961 /* Only the default rom images will be patched (if needed). */
1962 pci_patch_ids(pdev, ptr, size);
1963 }
1964
1965 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
1966
1967 return 0;
1968}
1969
1970static void pci_del_option_rom(PCIDevice *pdev)
1971{
1972 if (!pdev->has_rom)
1973 return;
1974
1975 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
1976 memory_region_destroy(&pdev->rom);
1977 pdev->has_rom = false;
1978}
1979
1980/*
1981 * if !offset
1982 * Reserve space and add capability to the linked list in pci config space
1983 *
1984 * if offset = 0,
1985 * Find and reserve space and add capability to the linked list
1986 * in pci config space */
1987int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1988 uint8_t offset, uint8_t size)
1989{
1990 uint8_t *config;
1991 int i, overlapping_cap;
1992
1993 if (!offset) {
1994 offset = pci_find_space(pdev, size);
1995 if (!offset) {
1996 return -ENOSPC;
1997 }
1998 } else {
1999 /* Verify that capabilities don't overlap. Note: device assignment
2000 * depends on this check to verify that the device is not broken.
2001 * Should never trigger for emulated devices, but it's helpful
2002 * for debugging these. */
2003 for (i = offset; i < offset + size; i++) {
2004 overlapping_cap = pci_find_capability_at_offset(pdev, i);
2005 if (overlapping_cap) {
2006 fprintf(stderr, "ERROR: %s:%02x:%02x.%x "
2007 "Attempt to add PCI capability %x at offset "
2008 "%x overlaps existing capability %x at offset %x\n",
2009 pci_root_bus_path(pdev), pci_bus_num(pdev->bus),
2010 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2011 cap_id, offset, overlapping_cap, i);
2012 return -EINVAL;
2013 }
2014 }
2015 }
2016
2017 config = pdev->config + offset;
2018 config[PCI_CAP_LIST_ID] = cap_id;
2019 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2020 pdev->config[PCI_CAPABILITY_LIST] = offset;
2021 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2022 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
2023 /* Make capability read-only by default */
2024 memset(pdev->wmask + offset, 0, size);
2025 /* Check capability by default */
2026 memset(pdev->cmask + offset, 0xFF, size);
2027 return offset;
2028}
2029
2030/* Unlink capability from the pci config space. */
2031void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2032{
2033 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2034 if (!offset)
2035 return;
2036 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
2037 /* Make capability writable again */
2038 memset(pdev->wmask + offset, 0xff, size);
2039 memset(pdev->w1cmask + offset, 0, size);
2040 /* Clear cmask as device-specific registers can't be checked */
2041 memset(pdev->cmask + offset, 0, size);
2042 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
2043
2044 if (!pdev->config[PCI_CAPABILITY_LIST])
2045 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2046}
2047
2048uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2049{
2050 return pci_find_capability_list(pdev, cap_id, NULL);
2051}
2052
2053static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2054{
2055 PCIDevice *d = (PCIDevice *)dev;
2056 const pci_class_desc *desc;
2057 char ctxt[64];
2058 PCIIORegion *r;
2059 int i, class;
2060
2061 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2062 desc = pci_class_descriptions;
2063 while (desc->desc && class != desc->class)
2064 desc++;
2065 if (desc->desc) {
2066 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2067 } else {
2068 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2069 }
2070
2071 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2072 "pci id %04x:%04x (sub %04x:%04x)\n",
2073 indent, "", ctxt, pci_bus_num(d->bus),
2074 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2075 pci_get_word(d->config + PCI_VENDOR_ID),
2076 pci_get_word(d->config + PCI_DEVICE_ID),
2077 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2078 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2079 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2080 r = &d->io_regions[i];
2081 if (!r->size)
2082 continue;
2083 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2084 " [0x%"FMT_PCIBUS"]\n",
2085 indent, "",
2086 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2087 r->addr, r->addr + r->size - 1);
2088 }
2089}
2090
2091static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2092{
2093 PCIDevice *d = (PCIDevice *)dev;
2094 const char *name = NULL;
2095 const pci_class_desc *desc = pci_class_descriptions;
2096 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2097
2098 while (desc->desc &&
2099 (class & ~desc->fw_ign_bits) !=
2100 (desc->class & ~desc->fw_ign_bits)) {
2101 desc++;
2102 }
2103
2104 if (desc->desc) {
2105 name = desc->fw_name;
2106 }
2107
2108 if (name) {
2109 pstrcpy(buf, len, name);
2110 } else {
2111 snprintf(buf, len, "pci%04x,%04x",
2112 pci_get_word(d->config + PCI_VENDOR_ID),
2113 pci_get_word(d->config + PCI_DEVICE_ID));
2114 }
2115
2116 return buf;
2117}
2118
2119static char *pcibus_get_fw_dev_path(DeviceState *dev)
2120{
2121 PCIDevice *d = (PCIDevice *)dev;
2122 char path[50], name[33];
2123 int off;
2124
2125 off = snprintf(path, sizeof(path), "%s@%x",
2126 pci_dev_fw_name(dev, name, sizeof name),
2127 PCI_SLOT(d->devfn));
2128 if (PCI_FUNC(d->devfn))
2129 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2130 return g_strdup(path);
2131}
2132
2133static char *pcibus_get_dev_path(DeviceState *dev)
2134{
2135 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2136 PCIDevice *t;
2137 int slot_depth;
2138 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2139 * 00 is added here to make this format compatible with
2140 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2141 * Slot.Function list specifies the slot and function numbers for all
2142 * devices on the path from root to the specific device. */
2143 const char *root_bus_path;
2144 int root_bus_len;
2145 char slot[] = ":SS.F";
2146 int slot_len = sizeof slot - 1 /* For '\0' */;
2147 int path_len;
2148 char *path, *p;
2149 int s;
2150
2151 root_bus_path = pci_root_bus_path(d);
2152 root_bus_len = strlen(root_bus_path);
2153
2154 /* Calculate # of slots on path between device and root. */;
2155 slot_depth = 0;
2156 for (t = d; t; t = t->bus->parent_dev) {
2157 ++slot_depth;
2158 }
2159
2160 path_len = root_bus_len + slot_len * slot_depth;
2161
2162 /* Allocate memory, fill in the terminating null byte. */
2163 path = g_malloc(path_len + 1 /* For '\0' */);
2164 path[path_len] = '\0';
2165
2166 memcpy(path, root_bus_path, root_bus_len);
2167
2168 /* Fill in slot numbers. We walk up from device to root, so need to print
2169 * them in the reverse order, last to first. */
2170 p = path + path_len;
2171 for (t = d; t; t = t->bus->parent_dev) {
2172 p -= slot_len;
2173 s = snprintf(slot, sizeof slot, ":%02x.%x",
2174 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2175 assert(s == slot_len);
2176 memcpy(p, slot, slot_len);
2177 }
2178
2179 return path;
2180}
2181
2182static int pci_qdev_find_recursive(PCIBus *bus,
2183 const char *id, PCIDevice **pdev)
2184{
2185 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2186 if (!qdev) {
2187 return -ENODEV;
2188 }
2189
2190 /* roughly check if given qdev is pci device */
2191 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
2192 *pdev = PCI_DEVICE(qdev);
2193 return 0;
2194 }
2195 return -EINVAL;
2196}
2197
2198int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2199{
2200 PCIHostState *host_bridge;
2201 int rc = -ENODEV;
2202
2203 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2204 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
2205 if (!tmp) {
2206 rc = 0;
2207 break;
2208 }
2209 if (tmp != -ENODEV) {
2210 rc = tmp;
2211 }
2212 }
2213
2214 return rc;
2215}
2216
2217MemoryRegion *pci_address_space(PCIDevice *dev)
2218{
2219 return dev->bus->address_space_mem;
2220}
2221
2222MemoryRegion *pci_address_space_io(PCIDevice *dev)
2223{
2224 return dev->bus->address_space_io;
2225}
2226
2227static void pci_device_class_init(ObjectClass *klass, void *data)
2228{
2229 DeviceClass *k = DEVICE_CLASS(klass);
2230 k->init = pci_qdev_init;
2231 k->unplug = pci_unplug_device;
2232 k->exit = pci_unregister_device;
2233 k->bus_type = TYPE_PCI_BUS;
2234 k->props = pci_props;
2235}
2236
2237AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2238{
2239 PCIBus *bus = PCI_BUS(dev->bus);
2240
2241 if (bus->iommu_fn) {
2242 return bus->iommu_fn(bus, bus->iommu_opaque, dev->devfn);
2243 }
2244
2245 if (bus->parent_dev) {
2246 /** We are ignoring the bus master DMA bit of the bridge
2247 * as it would complicate things such as VFIO for no good reason */
2248 return pci_device_iommu_address_space(bus->parent_dev);
2249 }
2250
2251 return &address_space_memory;
2252}
2253
2254void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
2255{
2256 bus->iommu_fn = fn;
2257 bus->iommu_opaque = opaque;
2258}
2259
2260static const TypeInfo pci_device_type_info = {
2261 .name = TYPE_PCI_DEVICE,
2262 .parent = TYPE_DEVICE,
2263 .instance_size = sizeof(PCIDevice),
2264 .abstract = true,
2265 .class_size = sizeof(PCIDeviceClass),
2266 .class_init = pci_device_class_init,
2267};
2268
2269static void pci_register_types(void)
2270{
2271 type_register_static(&pci_bus_info);
2272 type_register_static(&pcie_bus_info);
2273 type_register_static(&pci_device_type_info);
2274}
2275
2276type_init(pci_register_types)
Qemu copy for testing