]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * QEMU PCI bus manager | |
3 | * | |
4 | * Copyright (c) 2004 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "hw.h" | |
25 | #include "pci.h" | |
26 | #include "console.h" | |
27 | #include "net.h" | |
28 | #include "virtio-net.h" | |
29 | ||
30 | //#define DEBUG_PCI | |
31 | ||
32 | struct PCIBus { | |
33 | int bus_num; | |
34 | int devfn_min; | |
35 | pci_set_irq_fn set_irq; | |
36 | pci_map_irq_fn map_irq; | |
37 | uint32_t config_reg; /* XXX: suppress */ | |
38 | /* low level pic */ | |
39 | SetIRQFunc *low_set_irq; | |
40 | qemu_irq *irq_opaque; | |
41 | PCIDevice *devices[256]; | |
42 | PCIDevice *parent_dev; | |
43 | PCIBus *next; | |
44 | /* The bus IRQ state is the logical OR of the connected devices. | |
45 | Keep a count of the number of devices with raised IRQs. */ | |
46 | int nirq; | |
47 | int irq_count[]; | |
48 | }; | |
49 | ||
50 | static void pci_update_mappings(PCIDevice *d); | |
51 | static void pci_set_irq(void *opaque, int irq_num, int level); | |
52 | ||
53 | target_phys_addr_t pci_mem_base; | |
54 | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; | |
55 | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; | |
56 | static int pci_irq_index; | |
57 | static PCIBus *first_bus; | |
58 | ||
59 | static void pcibus_save(QEMUFile *f, void *opaque) | |
60 | { | |
61 | PCIBus *bus = (PCIBus *)opaque; | |
62 | int i; | |
63 | ||
64 | qemu_put_be32(f, bus->nirq); | |
65 | for (i = 0; i < bus->nirq; i++) | |
66 | qemu_put_be32(f, bus->irq_count[i]); | |
67 | } | |
68 | ||
69 | static int pcibus_load(QEMUFile *f, void *opaque, int version_id) | |
70 | { | |
71 | PCIBus *bus = (PCIBus *)opaque; | |
72 | int i, nirq; | |
73 | ||
74 | if (version_id != 1) | |
75 | return -EINVAL; | |
76 | ||
77 | nirq = qemu_get_be32(f); | |
78 | if (bus->nirq != nirq) { | |
79 | fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n", | |
80 | nirq, bus->nirq); | |
81 | return -EINVAL; | |
82 | } | |
83 | ||
84 | for (i = 0; i < nirq; i++) | |
85 | bus->irq_count[i] = qemu_get_be32(f); | |
86 | ||
87 | return 0; | |
88 | } | |
89 | ||
90 | PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
91 | qemu_irq *pic, int devfn_min, int nirq) | |
92 | { | |
93 | PCIBus *bus; | |
94 | static int nbus = 0; | |
95 | ||
96 | bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int))); | |
97 | bus->set_irq = set_irq; | |
98 | bus->map_irq = map_irq; | |
99 | bus->irq_opaque = pic; | |
100 | bus->devfn_min = devfn_min; | |
101 | bus->nirq = nirq; | |
102 | first_bus = bus; | |
103 | register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus); | |
104 | return bus; | |
105 | } | |
106 | ||
107 | static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq) | |
108 | { | |
109 | PCIBus *bus; | |
110 | bus = qemu_mallocz(sizeof(PCIBus)); | |
111 | bus->map_irq = map_irq; | |
112 | bus->parent_dev = dev; | |
113 | bus->next = dev->bus->next; | |
114 | dev->bus->next = bus; | |
115 | return bus; | |
116 | } | |
117 | ||
118 | int pci_bus_num(PCIBus *s) | |
119 | { | |
120 | return s->bus_num; | |
121 | } | |
122 | ||
123 | void pci_device_save(PCIDevice *s, QEMUFile *f) | |
124 | { | |
125 | int i; | |
126 | ||
127 | qemu_put_be32(f, 2); /* PCI device version */ | |
128 | qemu_put_buffer(f, s->config, 256); | |
129 | for (i = 0; i < 4; i++) | |
130 | qemu_put_be32(f, s->irq_state[i]); | |
131 | } | |
132 | ||
133 | int pci_device_load(PCIDevice *s, QEMUFile *f) | |
134 | { | |
135 | uint32_t version_id; | |
136 | int i; | |
137 | ||
138 | version_id = qemu_get_be32(f); | |
139 | if (version_id > 2) | |
140 | return -EINVAL; | |
141 | qemu_get_buffer(f, s->config, 256); | |
142 | pci_update_mappings(s); | |
143 | ||
144 | if (version_id >= 2) | |
145 | for (i = 0; i < 4; i ++) | |
146 | s->irq_state[i] = qemu_get_be32(f); | |
147 | ||
148 | return 0; | |
149 | } | |
150 | ||
151 | static int pci_set_default_subsystem_id(PCIDevice *pci_dev) | |
152 | { | |
153 | uint16_t *id; | |
154 | ||
155 | id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]); | |
156 | id[0] = cpu_to_le16(pci_default_sub_vendor_id); | |
157 | id[1] = cpu_to_le16(pci_default_sub_device_id); | |
158 | return 0; | |
159 | } | |
160 | ||
161 | /* -1 for devfn means auto assign */ | |
162 | PCIDevice *pci_register_device(PCIBus *bus, const char *name, | |
163 | int instance_size, int devfn, | |
164 | PCIConfigReadFunc *config_read, | |
165 | PCIConfigWriteFunc *config_write) | |
166 | { | |
167 | PCIDevice *pci_dev; | |
168 | ||
169 | if (pci_irq_index >= PCI_DEVICES_MAX) | |
170 | return NULL; | |
171 | ||
172 | if (devfn < 0) { | |
173 | for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { | |
174 | if (!bus->devices[devfn]) | |
175 | goto found; | |
176 | } | |
177 | return NULL; | |
178 | found: ; | |
179 | } | |
180 | pci_dev = qemu_mallocz(instance_size); | |
181 | if (!pci_dev) | |
182 | return NULL; | |
183 | pci_dev->bus = bus; | |
184 | pci_dev->devfn = devfn; | |
185 | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); | |
186 | memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); | |
187 | pci_set_default_subsystem_id(pci_dev); | |
188 | ||
189 | if (!config_read) | |
190 | config_read = pci_default_read_config; | |
191 | if (!config_write) | |
192 | config_write = pci_default_write_config; | |
193 | pci_dev->config_read = config_read; | |
194 | pci_dev->config_write = config_write; | |
195 | pci_dev->irq_index = pci_irq_index++; | |
196 | bus->devices[devfn] = pci_dev; | |
197 | pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4); | |
198 | return pci_dev; | |
199 | } | |
200 | ||
201 | void pci_register_io_region(PCIDevice *pci_dev, int region_num, | |
202 | uint32_t size, int type, | |
203 | PCIMapIORegionFunc *map_func) | |
204 | { | |
205 | PCIIORegion *r; | |
206 | uint32_t addr; | |
207 | ||
208 | if ((unsigned int)region_num >= PCI_NUM_REGIONS) | |
209 | return; | |
210 | r = &pci_dev->io_regions[region_num]; | |
211 | r->addr = -1; | |
212 | r->size = size; | |
213 | r->type = type; | |
214 | r->map_func = map_func; | |
215 | if (region_num == PCI_ROM_SLOT) { | |
216 | addr = 0x30; | |
217 | } else { | |
218 | addr = 0x10 + region_num * 4; | |
219 | } | |
220 | *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type); | |
221 | } | |
222 | ||
223 | static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr) | |
224 | { | |
225 | return addr + pci_mem_base; | |
226 | } | |
227 | ||
228 | static void pci_update_mappings(PCIDevice *d) | |
229 | { | |
230 | PCIIORegion *r; | |
231 | int cmd, i; | |
232 | uint32_t last_addr, new_addr, config_ofs; | |
233 | ||
234 | cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); | |
235 | for(i = 0; i < PCI_NUM_REGIONS; i++) { | |
236 | r = &d->io_regions[i]; | |
237 | if (i == PCI_ROM_SLOT) { | |
238 | config_ofs = 0x30; | |
239 | } else { | |
240 | config_ofs = 0x10 + i * 4; | |
241 | } | |
242 | if (r->size != 0) { | |
243 | if (r->type & PCI_ADDRESS_SPACE_IO) { | |
244 | if (cmd & PCI_COMMAND_IO) { | |
245 | new_addr = le32_to_cpu(*(uint32_t *)(d->config + | |
246 | config_ofs)); | |
247 | new_addr = new_addr & ~(r->size - 1); | |
248 | last_addr = new_addr + r->size - 1; | |
249 | /* NOTE: we have only 64K ioports on PC */ | |
250 | if (last_addr <= new_addr || new_addr == 0 || | |
251 | last_addr >= 0x10000) { | |
252 | new_addr = -1; | |
253 | } | |
254 | } else { | |
255 | new_addr = -1; | |
256 | } | |
257 | } else { | |
258 | if (cmd & PCI_COMMAND_MEMORY) { | |
259 | new_addr = le32_to_cpu(*(uint32_t *)(d->config + | |
260 | config_ofs)); | |
261 | /* the ROM slot has a specific enable bit */ | |
262 | if (i == PCI_ROM_SLOT && !(new_addr & 1)) | |
263 | goto no_mem_map; | |
264 | new_addr = new_addr & ~(r->size - 1); | |
265 | last_addr = new_addr + r->size - 1; | |
266 | /* NOTE: we do not support wrapping */ | |
267 | /* XXX: as we cannot support really dynamic | |
268 | mappings, we handle specific values as invalid | |
269 | mappings. */ | |
270 | if (last_addr <= new_addr || new_addr == 0 || | |
271 | last_addr == -1) { | |
272 | new_addr = -1; | |
273 | } | |
274 | } else { | |
275 | no_mem_map: | |
276 | new_addr = -1; | |
277 | } | |
278 | } | |
279 | /* now do the real mapping */ | |
280 | if (new_addr != r->addr) { | |
281 | if (r->addr != -1) { | |
282 | if (r->type & PCI_ADDRESS_SPACE_IO) { | |
283 | int class; | |
284 | /* NOTE: specific hack for IDE in PC case: | |
285 | only one byte must be mapped. */ | |
286 | class = d->config[0x0a] | (d->config[0x0b] << 8); | |
287 | if (class == 0x0101 && r->size == 4) { | |
288 | isa_unassign_ioport(r->addr + 2, 1); | |
289 | } else { | |
290 | isa_unassign_ioport(r->addr, r->size); | |
291 | } | |
292 | } else { | |
293 | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), | |
294 | r->size, | |
295 | IO_MEM_UNASSIGNED); | |
296 | qemu_unregister_coalesced_mmio(r->addr, r->size); | |
297 | } | |
298 | } | |
299 | r->addr = new_addr; | |
300 | if (r->addr != -1) { | |
301 | r->map_func(d, i, r->addr, r->size, r->type); | |
302 | } | |
303 | } | |
304 | } | |
305 | } | |
306 | } | |
307 | ||
308 | uint32_t pci_default_read_config(PCIDevice *d, | |
309 | uint32_t address, int len) | |
310 | { | |
311 | uint32_t val; | |
312 | ||
313 | switch(len) { | |
314 | default: | |
315 | case 4: | |
316 | if (address <= 0xfc) { | |
317 | val = le32_to_cpu(*(uint32_t *)(d->config + address)); | |
318 | break; | |
319 | } | |
320 | /* fall through */ | |
321 | case 2: | |
322 | if (address <= 0xfe) { | |
323 | val = le16_to_cpu(*(uint16_t *)(d->config + address)); | |
324 | break; | |
325 | } | |
326 | /* fall through */ | |
327 | case 1: | |
328 | val = d->config[address]; | |
329 | break; | |
330 | } | |
331 | return val; | |
332 | } | |
333 | ||
334 | void pci_default_write_config(PCIDevice *d, | |
335 | uint32_t address, uint32_t val, int len) | |
336 | { | |
337 | int can_write, i; | |
338 | uint32_t end, addr; | |
339 | ||
340 | if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) || | |
341 | (address >= 0x30 && address < 0x34))) { | |
342 | PCIIORegion *r; | |
343 | int reg; | |
344 | ||
345 | if ( address >= 0x30 ) { | |
346 | reg = PCI_ROM_SLOT; | |
347 | }else{ | |
348 | reg = (address - 0x10) >> 2; | |
349 | } | |
350 | r = &d->io_regions[reg]; | |
351 | if (r->size == 0) | |
352 | goto default_config; | |
353 | /* compute the stored value */ | |
354 | if (reg == PCI_ROM_SLOT) { | |
355 | /* keep ROM enable bit */ | |
356 | val &= (~(r->size - 1)) | 1; | |
357 | } else { | |
358 | val &= ~(r->size - 1); | |
359 | val |= r->type; | |
360 | } | |
361 | *(uint32_t *)(d->config + address) = cpu_to_le32(val); | |
362 | pci_update_mappings(d); | |
363 | return; | |
364 | } | |
365 | default_config: | |
366 | /* not efficient, but simple */ | |
367 | addr = address; | |
368 | for(i = 0; i < len; i++) { | |
369 | /* default read/write accesses */ | |
370 | switch(d->config[0x0e]) { | |
371 | case 0x00: | |
372 | case 0x80: | |
373 | switch(addr) { | |
374 | case 0x00: | |
375 | case 0x01: | |
376 | case 0x02: | |
377 | case 0x03: | |
378 | case 0x08: | |
379 | case 0x09: | |
380 | case 0x0a: | |
381 | case 0x0b: | |
382 | case 0x0e: | |
383 | case 0x10 ... 0x27: /* base */ | |
384 | case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ | |
385 | case 0x30 ... 0x33: /* rom */ | |
386 | case 0x3d: | |
387 | can_write = 0; | |
388 | break; | |
389 | default: | |
390 | can_write = 1; | |
391 | break; | |
392 | } | |
393 | break; | |
394 | default: | |
395 | case 0x01: | |
396 | switch(addr) { | |
397 | case 0x00: | |
398 | case 0x01: | |
399 | case 0x02: | |
400 | case 0x03: | |
401 | case 0x08: | |
402 | case 0x09: | |
403 | case 0x0a: | |
404 | case 0x0b: | |
405 | case 0x0e: | |
406 | case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ | |
407 | case 0x38 ... 0x3b: /* rom */ | |
408 | case 0x3d: | |
409 | can_write = 0; | |
410 | break; | |
411 | default: | |
412 | can_write = 1; | |
413 | break; | |
414 | } | |
415 | break; | |
416 | } | |
417 | if (can_write) { | |
418 | /* Mask out writes to reserved bits in registers */ | |
419 | switch (addr) { | |
420 | case 0x05: | |
421 | val &= ~PCI_COMMAND_RESERVED_MASK_HI; | |
422 | break; | |
423 | case 0x06: | |
424 | val &= ~PCI_STATUS_RESERVED_MASK_LO; | |
425 | break; | |
426 | case 0x07: | |
427 | val &= ~PCI_STATUS_RESERVED_MASK_HI; | |
428 | break; | |
429 | } | |
430 | d->config[addr] = val; | |
431 | } | |
432 | if (++addr > 0xff) | |
433 | break; | |
434 | val >>= 8; | |
435 | } | |
436 | ||
437 | end = address + len; | |
438 | if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) { | |
439 | /* if the command register is modified, we must modify the mappings */ | |
440 | pci_update_mappings(d); | |
441 | } | |
442 | } | |
443 | ||
444 | void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) | |
445 | { | |
446 | PCIBus *s = opaque; | |
447 | PCIDevice *pci_dev; | |
448 | int config_addr, bus_num; | |
449 | ||
450 | #if defined(DEBUG_PCI) && 0 | |
451 | printf("pci_data_write: addr=%08x val=%08x len=%d\n", | |
452 | addr, val, len); | |
453 | #endif | |
454 | bus_num = (addr >> 16) & 0xff; | |
455 | while (s && s->bus_num != bus_num) | |
456 | s = s->next; | |
457 | if (!s) | |
458 | return; | |
459 | pci_dev = s->devices[(addr >> 8) & 0xff]; | |
460 | if (!pci_dev) | |
461 | return; | |
462 | config_addr = addr & 0xff; | |
463 | #if defined(DEBUG_PCI) | |
464 | printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n", | |
465 | pci_dev->name, config_addr, val, len); | |
466 | #endif | |
467 | pci_dev->config_write(pci_dev, config_addr, val, len); | |
468 | } | |
469 | ||
470 | uint32_t pci_data_read(void *opaque, uint32_t addr, int len) | |
471 | { | |
472 | PCIBus *s = opaque; | |
473 | PCIDevice *pci_dev; | |
474 | int config_addr, bus_num; | |
475 | uint32_t val; | |
476 | ||
477 | bus_num = (addr >> 16) & 0xff; | |
478 | while (s && s->bus_num != bus_num) | |
479 | s= s->next; | |
480 | if (!s) | |
481 | goto fail; | |
482 | pci_dev = s->devices[(addr >> 8) & 0xff]; | |
483 | if (!pci_dev) { | |
484 | fail: | |
485 | switch(len) { | |
486 | case 1: | |
487 | val = 0xff; | |
488 | break; | |
489 | case 2: | |
490 | val = 0xffff; | |
491 | break; | |
492 | default: | |
493 | case 4: | |
494 | val = 0xffffffff; | |
495 | break; | |
496 | } | |
497 | goto the_end; | |
498 | } | |
499 | config_addr = addr & 0xff; | |
500 | val = pci_dev->config_read(pci_dev, config_addr, len); | |
501 | #if defined(DEBUG_PCI) | |
502 | printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n", | |
503 | pci_dev->name, config_addr, val, len); | |
504 | #endif | |
505 | the_end: | |
506 | #if defined(DEBUG_PCI) && 0 | |
507 | printf("pci_data_read: addr=%08x val=%08x len=%d\n", | |
508 | addr, val, len); | |
509 | #endif | |
510 | return val; | |
511 | } | |
512 | ||
513 | /***********************************************************/ | |
514 | /* generic PCI irq support */ | |
515 | ||
516 | /* 0 <= irq_num <= 3. level must be 0 or 1 */ | |
517 | static void pci_set_irq(void *opaque, int irq_num, int level) | |
518 | { | |
519 | PCIDevice *pci_dev = (PCIDevice *)opaque; | |
520 | PCIBus *bus; | |
521 | int change; | |
522 | ||
523 | change = level - pci_dev->irq_state[irq_num]; | |
524 | if (!change) | |
525 | return; | |
526 | ||
527 | pci_dev->irq_state[irq_num] = level; | |
528 | for (;;) { | |
529 | bus = pci_dev->bus; | |
530 | irq_num = bus->map_irq(pci_dev, irq_num); | |
531 | if (bus->set_irq) | |
532 | break; | |
533 | pci_dev = bus->parent_dev; | |
534 | } | |
535 | bus->irq_count[irq_num] += change; | |
536 | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); | |
537 | } | |
538 | ||
539 | /***********************************************************/ | |
540 | /* monitor info on PCI */ | |
541 | ||
542 | typedef struct { | |
543 | uint16_t class; | |
544 | const char *desc; | |
545 | } pci_class_desc; | |
546 | ||
547 | static const pci_class_desc pci_class_descriptions[] = | |
548 | { | |
549 | { 0x0100, "SCSI controller"}, | |
550 | { 0x0101, "IDE controller"}, | |
551 | { 0x0102, "Floppy controller"}, | |
552 | { 0x0103, "IPI controller"}, | |
553 | { 0x0104, "RAID controller"}, | |
554 | { 0x0106, "SATA controller"}, | |
555 | { 0x0107, "SAS controller"}, | |
556 | { 0x0180, "Storage controller"}, | |
557 | { 0x0200, "Ethernet controller"}, | |
558 | { 0x0201, "Token Ring controller"}, | |
559 | { 0x0202, "FDDI controller"}, | |
560 | { 0x0203, "ATM controller"}, | |
561 | { 0x0280, "Network controller"}, | |
562 | { 0x0300, "VGA controller"}, | |
563 | { 0x0301, "XGA controller"}, | |
564 | { 0x0302, "3D controller"}, | |
565 | { 0x0380, "Display controller"}, | |
566 | { 0x0400, "Video controller"}, | |
567 | { 0x0401, "Audio controller"}, | |
568 | { 0x0402, "Phone"}, | |
569 | { 0x0480, "Multimedia controller"}, | |
570 | { 0x0500, "RAM controller"}, | |
571 | { 0x0501, "Flash controller"}, | |
572 | { 0x0580, "Memory controller"}, | |
573 | { 0x0600, "Host bridge"}, | |
574 | { 0x0601, "ISA bridge"}, | |
575 | { 0x0602, "EISA bridge"}, | |
576 | { 0x0603, "MC bridge"}, | |
577 | { 0x0604, "PCI bridge"}, | |
578 | { 0x0605, "PCMCIA bridge"}, | |
579 | { 0x0606, "NUBUS bridge"}, | |
580 | { 0x0607, "CARDBUS bridge"}, | |
581 | { 0x0608, "RACEWAY bridge"}, | |
582 | { 0x0680, "Bridge"}, | |
583 | { 0x0c03, "USB controller"}, | |
584 | { 0, NULL} | |
585 | }; | |
586 | ||
587 | static void pci_info_device(PCIDevice *d) | |
588 | { | |
589 | int i, class; | |
590 | PCIIORegion *r; | |
591 | const pci_class_desc *desc; | |
592 | ||
593 | term_printf(" Bus %2d, device %3d, function %d:\n", | |
594 | d->bus->bus_num, d->devfn >> 3, d->devfn & 7); | |
595 | class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); | |
596 | term_printf(" "); | |
597 | desc = pci_class_descriptions; | |
598 | while (desc->desc && class != desc->class) | |
599 | desc++; | |
600 | if (desc->desc) { | |
601 | term_printf("%s", desc->desc); | |
602 | } else { | |
603 | term_printf("Class %04x", class); | |
604 | } | |
605 | term_printf(": PCI device %04x:%04x\n", | |
606 | le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), | |
607 | le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); | |
608 | ||
609 | if (d->config[PCI_INTERRUPT_PIN] != 0) { | |
610 | term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]); | |
611 | } | |
612 | if (class == 0x0604) { | |
613 | term_printf(" BUS %d.\n", d->config[0x19]); | |
614 | } | |
615 | for(i = 0;i < PCI_NUM_REGIONS; i++) { | |
616 | r = &d->io_regions[i]; | |
617 | if (r->size != 0) { | |
618 | term_printf(" BAR%d: ", i); | |
619 | if (r->type & PCI_ADDRESS_SPACE_IO) { | |
620 | term_printf("I/O at 0x%04x [0x%04x].\n", | |
621 | r->addr, r->addr + r->size - 1); | |
622 | } else { | |
623 | term_printf("32 bit memory at 0x%08x [0x%08x].\n", | |
624 | r->addr, r->addr + r->size - 1); | |
625 | } | |
626 | } | |
627 | } | |
628 | if (class == 0x0604 && d->config[0x19] != 0) { | |
629 | pci_for_each_device(d->config[0x19], pci_info_device); | |
630 | } | |
631 | } | |
632 | ||
633 | void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)) | |
634 | { | |
635 | PCIBus *bus = first_bus; | |
636 | PCIDevice *d; | |
637 | int devfn; | |
638 | ||
639 | while (bus && bus->bus_num != bus_num) | |
640 | bus = bus->next; | |
641 | if (bus) { | |
642 | for(devfn = 0; devfn < 256; devfn++) { | |
643 | d = bus->devices[devfn]; | |
644 | if (d) | |
645 | fn(d); | |
646 | } | |
647 | } | |
648 | } | |
649 | ||
650 | void pci_info(void) | |
651 | { | |
652 | pci_for_each_device(0, pci_info_device); | |
653 | } | |
654 | ||
655 | /* Initialize a PCI NIC. */ | |
656 | void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn) | |
657 | { | |
658 | if (strcmp(nd->model, "ne2k_pci") == 0) { | |
659 | pci_ne2000_init(bus, nd, devfn); | |
660 | } else if (strcmp(nd->model, "i82551") == 0) { | |
661 | pci_i82551_init(bus, nd, devfn); | |
662 | } else if (strcmp(nd->model, "i82557b") == 0) { | |
663 | pci_i82557b_init(bus, nd, devfn); | |
664 | } else if (strcmp(nd->model, "i82559er") == 0) { | |
665 | pci_i82559er_init(bus, nd, devfn); | |
666 | } else if (strcmp(nd->model, "rtl8139") == 0) { | |
667 | pci_rtl8139_init(bus, nd, devfn); | |
668 | } else if (strcmp(nd->model, "e1000") == 0) { | |
669 | pci_e1000_init(bus, nd, devfn); | |
670 | } else if (strcmp(nd->model, "pcnet") == 0) { | |
671 | pci_pcnet_init(bus, nd, devfn); | |
672 | } else if (strcmp(nd->model, "virtio") == 0) { | |
673 | virtio_net_init(bus, nd, devfn); | |
674 | } else if (strcmp(nd->model, "?") == 0) { | |
675 | fprintf(stderr, "qemu: Supported PCI NICs: i82551 i82557b i82559er" | |
676 | " ne2k_pci pcnet rtl8139 e1000 virtio\n"); | |
677 | exit (1); | |
678 | } else { | |
679 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model); | |
680 | exit (1); | |
681 | } | |
682 | } | |
683 | ||
684 | typedef struct { | |
685 | PCIDevice dev; | |
686 | PCIBus *bus; | |
687 | } PCIBridge; | |
688 | ||
689 | static void pci_bridge_write_config(PCIDevice *d, | |
690 | uint32_t address, uint32_t val, int len) | |
691 | { | |
692 | PCIBridge *s = (PCIBridge *)d; | |
693 | ||
694 | if (address == 0x19 || (address == 0x18 && len > 1)) { | |
695 | if (address == 0x19) | |
696 | s->bus->bus_num = val & 0xff; | |
697 | else | |
698 | s->bus->bus_num = (val >> 8) & 0xff; | |
699 | #if defined(DEBUG_PCI) | |
700 | printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num); | |
701 | #endif | |
702 | } | |
703 | pci_default_write_config(d, address, val, len); | |
704 | } | |
705 | ||
706 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id, | |
707 | pci_map_irq_fn map_irq, const char *name) | |
708 | { | |
709 | PCIBridge *s; | |
710 | s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge), | |
711 | devfn, NULL, pci_bridge_write_config); | |
712 | s->dev.config[0x00] = id >> 16; | |
713 | s->dev.config[0x01] = id >> 24; | |
714 | s->dev.config[0x02] = id; // device_id | |
715 | s->dev.config[0x03] = id >> 8; | |
716 | s->dev.config[0x04] = 0x06; // command = bus master, pci mem | |
717 | s->dev.config[0x05] = 0x00; | |
718 | s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
719 | s->dev.config[0x07] = 0x00; // status = fast devsel | |
720 | s->dev.config[0x08] = 0x00; // revision | |
721 | s->dev.config[0x09] = 0x00; // programming i/f | |
722 | s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge | |
723 | s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge | |
724 | s->dev.config[0x0D] = 0x10; // latency_timer | |
725 | s->dev.config[0x0E] = 0x81; // header_type | |
726 | s->dev.config[0x1E] = 0xa0; // secondary status | |
727 | ||
728 | s->bus = pci_register_secondary_bus(&s->dev, map_irq); | |
729 | return s->bus; | |
730 | } |