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cadence_uart: Fix buffer overflow
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1/*
2 * Arm PrimeCell PL041 Advanced Audio Codec Interface
3 *
4 * Copyright (c) 2011
5 * Written by Mathieu Sonet - www.elasticsheep.com
6 *
7 * This code is licensed under the GPL.
8 *
9 * *****************************************************************
10 */
11
12#ifndef HW_PL041_H
13#define HW_PL041_H
14
15/* Register file */
16#define REGISTER(name, offset) uint32_t name;
17typedef struct {
18 #include "pl041.hx"
19} pl041_regfile;
20#undef REGISTER
21
22/* Register addresses */
23#define REGISTER(name, offset) PL041_##name = offset,
24enum {
25 #include "pl041.hx"
26
27 PL041_periphid0 = 0xFE0,
28 PL041_periphid1 = 0xFE4,
29 PL041_periphid2 = 0xFE8,
30 PL041_periphid3 = 0xFEC,
31 PL041_pcellid0 = 0xFF0,
32 PL041_pcellid1 = 0xFF4,
33 PL041_pcellid2 = 0xFF8,
34 PL041_pcellid3 = 0xFFC,
35};
36#undef REGISTER
37
38/* Register bits */
39
40/* IEx */
41#define TXCIE (1 << 0)
42#define RXTIE (1 << 1)
43#define TXIE (1 << 2)
44#define RXIE (1 << 3)
45#define RXOIE (1 << 4)
46#define TXUIE (1 << 5)
47#define RXTOIE (1 << 6)
48
49/* TXCRx */
50#define TXEN (1 << 0)
51#define TXSLOT1 (1 << 1)
52#define TXSLOT2 (1 << 2)
53#define TXSLOT3 (1 << 3)
54#define TXSLOT4 (1 << 4)
55#define TXCOMPACT (1 << 15)
56#define TXFEN (1 << 16)
57
58#define TXSLOT_MASK_BIT (1)
59#define TXSLOT_MASK (0xFFF << TXSLOT_MASK_BIT)
60
61#define TSIZE_MASK_BIT (13)
62#define TSIZE_MASK (0x3 << TSIZE_MASK_BIT)
63
64#define TSIZE_16BITS (0x0 << TSIZE_MASK_BIT)
65#define TSIZE_18BITS (0x1 << TSIZE_MASK_BIT)
66#define TSIZE_20BITS (0x2 << TSIZE_MASK_BIT)
67#define TSIZE_12BITS (0x3 << TSIZE_MASK_BIT)
68
69/* SRx */
70#define RXFE (1 << 0)
71#define TXFE (1 << 1)
72#define RXHF (1 << 2)
73#define TXHE (1 << 3)
74#define RXFF (1 << 4)
75#define TXFF (1 << 5)
76#define RXBUSY (1 << 6)
77#define TXBUSY (1 << 7)
78#define RXOVERRUN (1 << 8)
79#define TXUNDERRUN (1 << 9)
80#define RXTIMEOUT (1 << 10)
81#define RXTOFE (1 << 11)
82
83/* ISRx */
84#define TXCINTR (1 << 0)
85#define RXTOINTR (1 << 1)
86#define TXINTR (1 << 2)
87#define RXINTR (1 << 3)
88#define ORINTR (1 << 4)
89#define URINTR (1 << 5)
90#define RXTOFEINTR (1 << 6)
91
92/* SLFR */
93#define SL1RXBUSY (1 << 0)
94#define SL1TXBUSY (1 << 1)
95#define SL2RXBUSY (1 << 2)
96#define SL2TXBUSY (1 << 3)
97#define SL12RXBUSY (1 << 4)
98#define SL12TXBUSY (1 << 5)
99#define SL1RXVALID (1 << 6)
100#define SL1TXEMPTY (1 << 7)
101#define SL2RXVALID (1 << 8)
102#define SL2TXEMPTY (1 << 9)
103#define SL12RXVALID (1 << 10)
104#define SL12TXEMPTY (1 << 11)
105#define RAWGPIOINT (1 << 12)
106#define RWIS (1 << 13)
107
108/* MAINCR */
109#define AACIFE (1 << 0)
110#define LOOPBACK (1 << 1)
111#define LOWPOWER (1 << 2)
112#define SL1RXEN (1 << 3)
113#define SL1TXEN (1 << 4)
114#define SL2RXEN (1 << 5)
115#define SL2TXEN (1 << 6)
116#define SL12RXEN (1 << 7)
117#define SL12TXEN (1 << 8)
118#define DMAENABLE (1 << 9)
119
120/* INTCLR */
121#define WISC (1 << 0)
122#define RXOEC1 (1 << 1)
123#define RXOEC2 (1 << 2)
124#define RXOEC3 (1 << 3)
125#define RXOEC4 (1 << 4)
126#define TXUEC1 (1 << 5)
127#define TXUEC2 (1 << 6)
128#define TXUEC3 (1 << 7)
129#define TXUEC4 (1 << 8)
130#define RXTOFEC1 (1 << 9)
131#define RXTOFEC2 (1 << 10)
132#define RXTOFEC3 (1 << 11)
133#define RXTOFEC4 (1 << 12)
134
135#endif /* #ifndef HW_PL041_H */