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1 | /* | |
2 | * QEMU generic PowerPC hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2003-2007 Jocelyn Mayer | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "hw.h" | |
25 | #include "ppc.h" | |
26 | #include "qemu-timer.h" | |
27 | #include "sysemu.h" | |
28 | #include "nvram.h" | |
29 | ||
30 | //#define PPC_DEBUG_IRQ | |
31 | //#define PPC_DEBUG_TB | |
32 | ||
33 | extern FILE *logfile; | |
34 | extern int loglevel; | |
35 | ||
36 | static void cpu_ppc_tb_stop (CPUState *env); | |
37 | static void cpu_ppc_tb_start (CPUState *env); | |
38 | ||
39 | static void ppc_set_irq (CPUState *env, int n_IRQ, int level) | |
40 | { | |
41 | if (level) { | |
42 | env->pending_interrupts |= 1 << n_IRQ; | |
43 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
44 | } else { | |
45 | env->pending_interrupts &= ~(1 << n_IRQ); | |
46 | if (env->pending_interrupts == 0) | |
47 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
48 | } | |
49 | #if defined(PPC_DEBUG_IRQ) | |
50 | if (loglevel & CPU_LOG_INT) { | |
51 | fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08x req %08x\n", | |
52 | __func__, env, n_IRQ, level, | |
53 | env->pending_interrupts, env->interrupt_request); | |
54 | } | |
55 | #endif | |
56 | } | |
57 | ||
58 | /* PowerPC 6xx / 7xx internal IRQ controller */ | |
59 | static void ppc6xx_set_irq (void *opaque, int pin, int level) | |
60 | { | |
61 | CPUState *env = opaque; | |
62 | int cur_level; | |
63 | ||
64 | #if defined(PPC_DEBUG_IRQ) | |
65 | if (loglevel & CPU_LOG_INT) { | |
66 | fprintf(logfile, "%s: env %p pin %d level %d\n", __func__, | |
67 | env, pin, level); | |
68 | } | |
69 | #endif | |
70 | cur_level = (env->irq_input_state >> pin) & 1; | |
71 | /* Don't generate spurious events */ | |
72 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { | |
73 | switch (pin) { | |
74 | case PPC6xx_INPUT_TBEN: | |
75 | /* Level sensitive - active high */ | |
76 | #if defined(PPC_DEBUG_IRQ) | |
77 | if (loglevel & CPU_LOG_INT) { | |
78 | fprintf(logfile, "%s: %s the time base\n", | |
79 | __func__, level ? "start" : "stop"); | |
80 | } | |
81 | #endif | |
82 | if (level) { | |
83 | cpu_ppc_tb_start(env); | |
84 | } else { | |
85 | cpu_ppc_tb_stop(env); | |
86 | } | |
87 | case PPC6xx_INPUT_INT: | |
88 | /* Level sensitive - active high */ | |
89 | #if defined(PPC_DEBUG_IRQ) | |
90 | if (loglevel & CPU_LOG_INT) { | |
91 | fprintf(logfile, "%s: set the external IRQ state to %d\n", | |
92 | __func__, level); | |
93 | } | |
94 | #endif | |
95 | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); | |
96 | break; | |
97 | case PPC6xx_INPUT_SMI: | |
98 | /* Level sensitive - active high */ | |
99 | #if defined(PPC_DEBUG_IRQ) | |
100 | if (loglevel & CPU_LOG_INT) { | |
101 | fprintf(logfile, "%s: set the SMI IRQ state to %d\n", | |
102 | __func__, level); | |
103 | } | |
104 | #endif | |
105 | ppc_set_irq(env, PPC_INTERRUPT_SMI, level); | |
106 | break; | |
107 | case PPC6xx_INPUT_MCP: | |
108 | /* Negative edge sensitive */ | |
109 | /* XXX: TODO: actual reaction may depends on HID0 status | |
110 | * 603/604/740/750: check HID0[EMCP] | |
111 | */ | |
112 | if (cur_level == 1 && level == 0) { | |
113 | #if defined(PPC_DEBUG_IRQ) | |
114 | if (loglevel & CPU_LOG_INT) { | |
115 | fprintf(logfile, "%s: raise machine check state\n", | |
116 | __func__); | |
117 | } | |
118 | #endif | |
119 | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1); | |
120 | } | |
121 | break; | |
122 | case PPC6xx_INPUT_CKSTP_IN: | |
123 | /* Level sensitive - active low */ | |
124 | /* XXX: TODO: relay the signal to CKSTP_OUT pin */ | |
125 | /* XXX: Note that the only way to restart the CPU is to reset it */ | |
126 | if (level) { | |
127 | #if defined(PPC_DEBUG_IRQ) | |
128 | if (loglevel & CPU_LOG_INT) { | |
129 | fprintf(logfile, "%s: stop the CPU\n", __func__); | |
130 | } | |
131 | #endif | |
132 | env->halted = 1; | |
133 | } | |
134 | break; | |
135 | case PPC6xx_INPUT_HRESET: | |
136 | /* Level sensitive - active low */ | |
137 | if (level) { | |
138 | #if defined(PPC_DEBUG_IRQ) | |
139 | if (loglevel & CPU_LOG_INT) { | |
140 | fprintf(logfile, "%s: reset the CPU\n", __func__); | |
141 | } | |
142 | #endif | |
143 | env->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
144 | /* XXX: TOFIX */ | |
145 | #if 0 | |
146 | cpu_ppc_reset(env); | |
147 | #else | |
148 | qemu_system_reset_request(); | |
149 | #endif | |
150 | } | |
151 | break; | |
152 | case PPC6xx_INPUT_SRESET: | |
153 | #if defined(PPC_DEBUG_IRQ) | |
154 | if (loglevel & CPU_LOG_INT) { | |
155 | fprintf(logfile, "%s: set the RESET IRQ state to %d\n", | |
156 | __func__, level); | |
157 | } | |
158 | #endif | |
159 | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); | |
160 | break; | |
161 | default: | |
162 | /* Unknown pin - do nothing */ | |
163 | #if defined(PPC_DEBUG_IRQ) | |
164 | if (loglevel & CPU_LOG_INT) { | |
165 | fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin); | |
166 | } | |
167 | #endif | |
168 | return; | |
169 | } | |
170 | if (level) | |
171 | env->irq_input_state |= 1 << pin; | |
172 | else | |
173 | env->irq_input_state &= ~(1 << pin); | |
174 | } | |
175 | } | |
176 | ||
177 | void ppc6xx_irq_init (CPUState *env) | |
178 | { | |
179 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, | |
180 | PPC6xx_INPUT_NB); | |
181 | } | |
182 | ||
183 | #if defined(TARGET_PPC64) | |
184 | /* PowerPC 970 internal IRQ controller */ | |
185 | static void ppc970_set_irq (void *opaque, int pin, int level) | |
186 | { | |
187 | CPUState *env = opaque; | |
188 | int cur_level; | |
189 | ||
190 | #if defined(PPC_DEBUG_IRQ) | |
191 | if (loglevel & CPU_LOG_INT) { | |
192 | fprintf(logfile, "%s: env %p pin %d level %d\n", __func__, | |
193 | env, pin, level); | |
194 | } | |
195 | #endif | |
196 | cur_level = (env->irq_input_state >> pin) & 1; | |
197 | /* Don't generate spurious events */ | |
198 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { | |
199 | switch (pin) { | |
200 | case PPC970_INPUT_INT: | |
201 | /* Level sensitive - active high */ | |
202 | #if defined(PPC_DEBUG_IRQ) | |
203 | if (loglevel & CPU_LOG_INT) { | |
204 | fprintf(logfile, "%s: set the external IRQ state to %d\n", | |
205 | __func__, level); | |
206 | } | |
207 | #endif | |
208 | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); | |
209 | break; | |
210 | case PPC970_INPUT_THINT: | |
211 | /* Level sensitive - active high */ | |
212 | #if defined(PPC_DEBUG_IRQ) | |
213 | if (loglevel & CPU_LOG_INT) { | |
214 | fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__, | |
215 | level); | |
216 | } | |
217 | #endif | |
218 | ppc_set_irq(env, PPC_INTERRUPT_THERM, level); | |
219 | break; | |
220 | case PPC970_INPUT_MCP: | |
221 | /* Negative edge sensitive */ | |
222 | /* XXX: TODO: actual reaction may depends on HID0 status | |
223 | * 603/604/740/750: check HID0[EMCP] | |
224 | */ | |
225 | if (cur_level == 1 && level == 0) { | |
226 | #if defined(PPC_DEBUG_IRQ) | |
227 | if (loglevel & CPU_LOG_INT) { | |
228 | fprintf(logfile, "%s: raise machine check state\n", | |
229 | __func__); | |
230 | } | |
231 | #endif | |
232 | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1); | |
233 | } | |
234 | break; | |
235 | case PPC970_INPUT_CKSTP: | |
236 | /* Level sensitive - active low */ | |
237 | /* XXX: TODO: relay the signal to CKSTP_OUT pin */ | |
238 | if (level) { | |
239 | #if defined(PPC_DEBUG_IRQ) | |
240 | if (loglevel & CPU_LOG_INT) { | |
241 | fprintf(logfile, "%s: stop the CPU\n", __func__); | |
242 | } | |
243 | #endif | |
244 | env->halted = 1; | |
245 | } else { | |
246 | #if defined(PPC_DEBUG_IRQ) | |
247 | if (loglevel & CPU_LOG_INT) { | |
248 | fprintf(logfile, "%s: restart the CPU\n", __func__); | |
249 | } | |
250 | #endif | |
251 | env->halted = 0; | |
252 | } | |
253 | break; | |
254 | case PPC970_INPUT_HRESET: | |
255 | /* Level sensitive - active low */ | |
256 | if (level) { | |
257 | #if 0 // XXX: TOFIX | |
258 | #if defined(PPC_DEBUG_IRQ) | |
259 | if (loglevel & CPU_LOG_INT) { | |
260 | fprintf(logfile, "%s: reset the CPU\n", __func__); | |
261 | } | |
262 | #endif | |
263 | cpu_reset(env); | |
264 | #endif | |
265 | } | |
266 | break; | |
267 | case PPC970_INPUT_SRESET: | |
268 | #if defined(PPC_DEBUG_IRQ) | |
269 | if (loglevel & CPU_LOG_INT) { | |
270 | fprintf(logfile, "%s: set the RESET IRQ state to %d\n", | |
271 | __func__, level); | |
272 | } | |
273 | #endif | |
274 | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); | |
275 | break; | |
276 | case PPC970_INPUT_TBEN: | |
277 | #if defined(PPC_DEBUG_IRQ) | |
278 | if (loglevel & CPU_LOG_INT) { | |
279 | fprintf(logfile, "%s: set the TBEN state to %d\n", __func__, | |
280 | level); | |
281 | } | |
282 | #endif | |
283 | /* XXX: TODO */ | |
284 | break; | |
285 | default: | |
286 | /* Unknown pin - do nothing */ | |
287 | #if defined(PPC_DEBUG_IRQ) | |
288 | if (loglevel & CPU_LOG_INT) { | |
289 | fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin); | |
290 | } | |
291 | #endif | |
292 | return; | |
293 | } | |
294 | if (level) | |
295 | env->irq_input_state |= 1 << pin; | |
296 | else | |
297 | env->irq_input_state &= ~(1 << pin); | |
298 | } | |
299 | } | |
300 | ||
301 | void ppc970_irq_init (CPUState *env) | |
302 | { | |
303 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, | |
304 | PPC970_INPUT_NB); | |
305 | } | |
306 | #endif /* defined(TARGET_PPC64) */ | |
307 | ||
308 | /* PowerPC 40x internal IRQ controller */ | |
309 | static void ppc40x_set_irq (void *opaque, int pin, int level) | |
310 | { | |
311 | CPUState *env = opaque; | |
312 | int cur_level; | |
313 | ||
314 | #if defined(PPC_DEBUG_IRQ) | |
315 | if (loglevel & CPU_LOG_INT) { | |
316 | fprintf(logfile, "%s: env %p pin %d level %d\n", __func__, | |
317 | env, pin, level); | |
318 | } | |
319 | #endif | |
320 | cur_level = (env->irq_input_state >> pin) & 1; | |
321 | /* Don't generate spurious events */ | |
322 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { | |
323 | switch (pin) { | |
324 | case PPC40x_INPUT_RESET_SYS: | |
325 | if (level) { | |
326 | #if defined(PPC_DEBUG_IRQ) | |
327 | if (loglevel & CPU_LOG_INT) { | |
328 | fprintf(logfile, "%s: reset the PowerPC system\n", | |
329 | __func__); | |
330 | } | |
331 | #endif | |
332 | ppc40x_system_reset(env); | |
333 | } | |
334 | break; | |
335 | case PPC40x_INPUT_RESET_CHIP: | |
336 | if (level) { | |
337 | #if defined(PPC_DEBUG_IRQ) | |
338 | if (loglevel & CPU_LOG_INT) { | |
339 | fprintf(logfile, "%s: reset the PowerPC chip\n", __func__); | |
340 | } | |
341 | #endif | |
342 | ppc40x_chip_reset(env); | |
343 | } | |
344 | break; | |
345 | case PPC40x_INPUT_RESET_CORE: | |
346 | /* XXX: TODO: update DBSR[MRR] */ | |
347 | if (level) { | |
348 | #if defined(PPC_DEBUG_IRQ) | |
349 | if (loglevel & CPU_LOG_INT) { | |
350 | fprintf(logfile, "%s: reset the PowerPC core\n", __func__); | |
351 | } | |
352 | #endif | |
353 | ppc40x_core_reset(env); | |
354 | } | |
355 | break; | |
356 | case PPC40x_INPUT_CINT: | |
357 | /* Level sensitive - active high */ | |
358 | #if defined(PPC_DEBUG_IRQ) | |
359 | if (loglevel & CPU_LOG_INT) { | |
360 | fprintf(logfile, "%s: set the critical IRQ state to %d\n", | |
361 | __func__, level); | |
362 | } | |
363 | #endif | |
364 | ppc_set_irq(env, PPC_INTERRUPT_CEXT, level); | |
365 | break; | |
366 | case PPC40x_INPUT_INT: | |
367 | /* Level sensitive - active high */ | |
368 | #if defined(PPC_DEBUG_IRQ) | |
369 | if (loglevel & CPU_LOG_INT) { | |
370 | fprintf(logfile, "%s: set the external IRQ state to %d\n", | |
371 | __func__, level); | |
372 | } | |
373 | #endif | |
374 | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); | |
375 | break; | |
376 | case PPC40x_INPUT_HALT: | |
377 | /* Level sensitive - active low */ | |
378 | if (level) { | |
379 | #if defined(PPC_DEBUG_IRQ) | |
380 | if (loglevel & CPU_LOG_INT) { | |
381 | fprintf(logfile, "%s: stop the CPU\n", __func__); | |
382 | } | |
383 | #endif | |
384 | env->halted = 1; | |
385 | } else { | |
386 | #if defined(PPC_DEBUG_IRQ) | |
387 | if (loglevel & CPU_LOG_INT) { | |
388 | fprintf(logfile, "%s: restart the CPU\n", __func__); | |
389 | } | |
390 | #endif | |
391 | env->halted = 0; | |
392 | } | |
393 | break; | |
394 | case PPC40x_INPUT_DEBUG: | |
395 | /* Level sensitive - active high */ | |
396 | #if defined(PPC_DEBUG_IRQ) | |
397 | if (loglevel & CPU_LOG_INT) { | |
398 | fprintf(logfile, "%s: set the debug pin state to %d\n", | |
399 | __func__, level); | |
400 | } | |
401 | #endif | |
402 | ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level); | |
403 | break; | |
404 | default: | |
405 | /* Unknown pin - do nothing */ | |
406 | #if defined(PPC_DEBUG_IRQ) | |
407 | if (loglevel & CPU_LOG_INT) { | |
408 | fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin); | |
409 | } | |
410 | #endif | |
411 | return; | |
412 | } | |
413 | if (level) | |
414 | env->irq_input_state |= 1 << pin; | |
415 | else | |
416 | env->irq_input_state &= ~(1 << pin); | |
417 | } | |
418 | } | |
419 | ||
420 | void ppc40x_irq_init (CPUState *env) | |
421 | { | |
422 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq, | |
423 | env, PPC40x_INPUT_NB); | |
424 | } | |
425 | ||
426 | /*****************************************************************************/ | |
427 | /* PowerPC time base and decrementer emulation */ | |
428 | struct ppc_tb_t { | |
429 | /* Time base management */ | |
430 | int64_t tb_offset; /* Compensation */ | |
431 | int64_t atb_offset; /* Compensation */ | |
432 | uint32_t tb_freq; /* TB frequency */ | |
433 | /* Decrementer management */ | |
434 | uint64_t decr_next; /* Tick for next decr interrupt */ | |
435 | uint32_t decr_freq; /* decrementer frequency */ | |
436 | struct QEMUTimer *decr_timer; | |
437 | /* Hypervisor decrementer management */ | |
438 | uint64_t hdecr_next; /* Tick for next hdecr interrupt */ | |
439 | struct QEMUTimer *hdecr_timer; | |
440 | uint64_t purr_load; | |
441 | uint64_t purr_start; | |
442 | void *opaque; | |
443 | }; | |
444 | ||
445 | static always_inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env, uint64_t vmclk, | |
446 | int64_t tb_offset) | |
447 | { | |
448 | /* TB time in tb periods */ | |
449 | return muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec) + tb_offset; | |
450 | } | |
451 | ||
452 | uint32_t cpu_ppc_load_tbl (CPUState *env) | |
453 | { | |
454 | ppc_tb_t *tb_env = env->tb_env; | |
455 | uint64_t tb; | |
456 | ||
457 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); | |
458 | #if defined(PPC_DEBUG_TB) | |
459 | if (loglevel != 0) { | |
460 | fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb); | |
461 | } | |
462 | #endif | |
463 | ||
464 | return tb & 0xFFFFFFFF; | |
465 | } | |
466 | ||
467 | static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env) | |
468 | { | |
469 | ppc_tb_t *tb_env = env->tb_env; | |
470 | uint64_t tb; | |
471 | ||
472 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); | |
473 | #if defined(PPC_DEBUG_TB) | |
474 | if (loglevel != 0) { | |
475 | fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb); | |
476 | } | |
477 | #endif | |
478 | ||
479 | return tb >> 32; | |
480 | } | |
481 | ||
482 | uint32_t cpu_ppc_load_tbu (CPUState *env) | |
483 | { | |
484 | return _cpu_ppc_load_tbu(env); | |
485 | } | |
486 | ||
487 | static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t vmclk, | |
488 | int64_t *tb_offsetp, | |
489 | uint64_t value) | |
490 | { | |
491 | *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec); | |
492 | #ifdef PPC_DEBUG_TB | |
493 | if (loglevel != 0) { | |
494 | fprintf(logfile, "%s: tb=0x%016lx offset=%08lx\n", __func__, value, | |
495 | *tb_offsetp); | |
496 | } | |
497 | #endif | |
498 | } | |
499 | ||
500 | void cpu_ppc_store_tbl (CPUState *env, uint32_t value) | |
501 | { | |
502 | ppc_tb_t *tb_env = env->tb_env; | |
503 | uint64_t tb; | |
504 | ||
505 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); | |
506 | tb &= 0xFFFFFFFF00000000ULL; | |
507 | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), | |
508 | &tb_env->tb_offset, tb | (uint64_t)value); | |
509 | } | |
510 | ||
511 | static always_inline void _cpu_ppc_store_tbu (CPUState *env, uint32_t value) | |
512 | { | |
513 | ppc_tb_t *tb_env = env->tb_env; | |
514 | uint64_t tb; | |
515 | ||
516 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); | |
517 | tb &= 0x00000000FFFFFFFFULL; | |
518 | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), | |
519 | &tb_env->tb_offset, ((uint64_t)value << 32) | tb); | |
520 | } | |
521 | ||
522 | void cpu_ppc_store_tbu (CPUState *env, uint32_t value) | |
523 | { | |
524 | _cpu_ppc_store_tbu(env, value); | |
525 | } | |
526 | ||
527 | uint32_t cpu_ppc_load_atbl (CPUState *env) | |
528 | { | |
529 | ppc_tb_t *tb_env = env->tb_env; | |
530 | uint64_t tb; | |
531 | ||
532 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); | |
533 | #if defined(PPC_DEBUG_TB) | |
534 | if (loglevel != 0) { | |
535 | fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb); | |
536 | } | |
537 | #endif | |
538 | ||
539 | return tb & 0xFFFFFFFF; | |
540 | } | |
541 | ||
542 | uint32_t cpu_ppc_load_atbu (CPUState *env) | |
543 | { | |
544 | ppc_tb_t *tb_env = env->tb_env; | |
545 | uint64_t tb; | |
546 | ||
547 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); | |
548 | #if defined(PPC_DEBUG_TB) | |
549 | if (loglevel != 0) { | |
550 | fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb); | |
551 | } | |
552 | #endif | |
553 | ||
554 | return tb >> 32; | |
555 | } | |
556 | ||
557 | void cpu_ppc_store_atbl (CPUState *env, uint32_t value) | |
558 | { | |
559 | ppc_tb_t *tb_env = env->tb_env; | |
560 | uint64_t tb; | |
561 | ||
562 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); | |
563 | tb &= 0xFFFFFFFF00000000ULL; | |
564 | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), | |
565 | &tb_env->atb_offset, tb | (uint64_t)value); | |
566 | } | |
567 | ||
568 | void cpu_ppc_store_atbu (CPUState *env, uint32_t value) | |
569 | { | |
570 | ppc_tb_t *tb_env = env->tb_env; | |
571 | uint64_t tb; | |
572 | ||
573 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); | |
574 | tb &= 0x00000000FFFFFFFFULL; | |
575 | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), | |
576 | &tb_env->atb_offset, ((uint64_t)value << 32) | tb); | |
577 | } | |
578 | ||
579 | static void cpu_ppc_tb_stop (CPUState *env) | |
580 | { | |
581 | ppc_tb_t *tb_env = env->tb_env; | |
582 | uint64_t tb, atb, vmclk; | |
583 | ||
584 | /* If the time base is already frozen, do nothing */ | |
585 | if (tb_env->tb_freq != 0) { | |
586 | vmclk = qemu_get_clock(vm_clock); | |
587 | /* Get the time base */ | |
588 | tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); | |
589 | /* Get the alternate time base */ | |
590 | atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); | |
591 | /* Store the time base value (ie compute the current offset) */ | |
592 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); | |
593 | /* Store the alternate time base value (compute the current offset) */ | |
594 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); | |
595 | /* Set the time base frequency to zero */ | |
596 | tb_env->tb_freq = 0; | |
597 | /* Now, the time bases are frozen to tb_offset / atb_offset value */ | |
598 | } | |
599 | } | |
600 | ||
601 | static void cpu_ppc_tb_start (CPUState *env) | |
602 | { | |
603 | ppc_tb_t *tb_env = env->tb_env; | |
604 | uint64_t tb, atb, vmclk; | |
605 | ||
606 | /* If the time base is not frozen, do nothing */ | |
607 | if (tb_env->tb_freq == 0) { | |
608 | vmclk = qemu_get_clock(vm_clock); | |
609 | /* Get the time base from tb_offset */ | |
610 | tb = tb_env->tb_offset; | |
611 | /* Get the alternate time base from atb_offset */ | |
612 | atb = tb_env->atb_offset; | |
613 | /* Restore the tb frequency from the decrementer frequency */ | |
614 | tb_env->tb_freq = tb_env->decr_freq; | |
615 | /* Store the time base value */ | |
616 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); | |
617 | /* Store the alternate time base value */ | |
618 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); | |
619 | } | |
620 | } | |
621 | ||
622 | static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env, | |
623 | uint64_t *next) | |
624 | { | |
625 | ppc_tb_t *tb_env = env->tb_env; | |
626 | uint32_t decr; | |
627 | int64_t diff; | |
628 | ||
629 | diff = tb_env->decr_next - qemu_get_clock(vm_clock); | |
630 | if (diff >= 0) | |
631 | decr = muldiv64(diff, tb_env->decr_freq, ticks_per_sec); | |
632 | else | |
633 | decr = -muldiv64(-diff, tb_env->decr_freq, ticks_per_sec); | |
634 | #if defined(PPC_DEBUG_TB) | |
635 | if (loglevel != 0) { | |
636 | fprintf(logfile, "%s: 0x%08x\n", __func__, decr); | |
637 | } | |
638 | #endif | |
639 | ||
640 | return decr; | |
641 | } | |
642 | ||
643 | uint32_t cpu_ppc_load_decr (CPUState *env) | |
644 | { | |
645 | ppc_tb_t *tb_env = env->tb_env; | |
646 | ||
647 | return _cpu_ppc_load_decr(env, &tb_env->decr_next); | |
648 | } | |
649 | ||
650 | uint32_t cpu_ppc_load_hdecr (CPUState *env) | |
651 | { | |
652 | ppc_tb_t *tb_env = env->tb_env; | |
653 | ||
654 | return _cpu_ppc_load_decr(env, &tb_env->hdecr_next); | |
655 | } | |
656 | ||
657 | uint64_t cpu_ppc_load_purr (CPUState *env) | |
658 | { | |
659 | ppc_tb_t *tb_env = env->tb_env; | |
660 | uint64_t diff; | |
661 | ||
662 | diff = qemu_get_clock(vm_clock) - tb_env->purr_start; | |
663 | ||
664 | return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec); | |
665 | } | |
666 | ||
667 | /* When decrementer expires, | |
668 | * all we need to do is generate or queue a CPU exception | |
669 | */ | |
670 | static always_inline void cpu_ppc_decr_excp (CPUState *env) | |
671 | { | |
672 | /* Raise it */ | |
673 | #ifdef PPC_DEBUG_TB | |
674 | if (loglevel != 0) { | |
675 | fprintf(logfile, "raise decrementer exception\n"); | |
676 | } | |
677 | #endif | |
678 | ppc_set_irq(env, PPC_INTERRUPT_DECR, 1); | |
679 | } | |
680 | ||
681 | static always_inline void cpu_ppc_hdecr_excp (CPUState *env) | |
682 | { | |
683 | /* Raise it */ | |
684 | #ifdef PPC_DEBUG_TB | |
685 | if (loglevel != 0) { | |
686 | fprintf(logfile, "raise decrementer exception\n"); | |
687 | } | |
688 | #endif | |
689 | ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1); | |
690 | } | |
691 | ||
692 | static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, | |
693 | struct QEMUTimer *timer, | |
694 | void (*raise_excp)(CPUState *), | |
695 | uint32_t decr, uint32_t value, | |
696 | int is_excp) | |
697 | { | |
698 | ppc_tb_t *tb_env = env->tb_env; | |
699 | uint64_t now, next; | |
700 | ||
701 | #ifdef PPC_DEBUG_TB | |
702 | if (loglevel != 0) { | |
703 | fprintf(logfile, "%s: 0x%08x => 0x%08x\n", __func__, decr, value); | |
704 | } | |
705 | #endif | |
706 | now = qemu_get_clock(vm_clock); | |
707 | next = now + muldiv64(value, ticks_per_sec, tb_env->decr_freq); | |
708 | if (is_excp) | |
709 | next += *nextp - now; | |
710 | if (next == now) | |
711 | next++; | |
712 | *nextp = next; | |
713 | /* Adjust timer */ | |
714 | qemu_mod_timer(timer, next); | |
715 | /* If we set a negative value and the decrementer was positive, | |
716 | * raise an exception. | |
717 | */ | |
718 | if ((value & 0x80000000) && !(decr & 0x80000000)) | |
719 | (*raise_excp)(env); | |
720 | } | |
721 | ||
722 | static always_inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr, | |
723 | uint32_t value, int is_excp) | |
724 | { | |
725 | ppc_tb_t *tb_env = env->tb_env; | |
726 | ||
727 | __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer, | |
728 | &cpu_ppc_decr_excp, decr, value, is_excp); | |
729 | } | |
730 | ||
731 | void cpu_ppc_store_decr (CPUState *env, uint32_t value) | |
732 | { | |
733 | _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0); | |
734 | } | |
735 | ||
736 | static void cpu_ppc_decr_cb (void *opaque) | |
737 | { | |
738 | _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); | |
739 | } | |
740 | ||
741 | static always_inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr, | |
742 | uint32_t value, int is_excp) | |
743 | { | |
744 | ppc_tb_t *tb_env = env->tb_env; | |
745 | ||
746 | if (tb_env->hdecr_timer != NULL) { | |
747 | __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer, | |
748 | &cpu_ppc_hdecr_excp, hdecr, value, is_excp); | |
749 | } | |
750 | } | |
751 | ||
752 | void cpu_ppc_store_hdecr (CPUState *env, uint32_t value) | |
753 | { | |
754 | _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0); | |
755 | } | |
756 | ||
757 | static void cpu_ppc_hdecr_cb (void *opaque) | |
758 | { | |
759 | _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1); | |
760 | } | |
761 | ||
762 | void cpu_ppc_store_purr (CPUState *env, uint64_t value) | |
763 | { | |
764 | ppc_tb_t *tb_env = env->tb_env; | |
765 | ||
766 | tb_env->purr_load = value; | |
767 | tb_env->purr_start = qemu_get_clock(vm_clock); | |
768 | } | |
769 | ||
770 | static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) | |
771 | { | |
772 | CPUState *env = opaque; | |
773 | ppc_tb_t *tb_env = env->tb_env; | |
774 | ||
775 | tb_env->tb_freq = freq; | |
776 | tb_env->decr_freq = freq; | |
777 | /* There is a bug in Linux 2.4 kernels: | |
778 | * if a decrementer exception is pending when it enables msr_ee at startup, | |
779 | * it's not ready to handle it... | |
780 | */ | |
781 | _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); | |
782 | _cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); | |
783 | cpu_ppc_store_purr(env, 0x0000000000000000ULL); | |
784 | } | |
785 | ||
786 | /* Set up (once) timebase frequency (in Hz) */ | |
787 | clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq) | |
788 | { | |
789 | ppc_tb_t *tb_env; | |
790 | ||
791 | tb_env = qemu_mallocz(sizeof(ppc_tb_t)); | |
792 | if (tb_env == NULL) | |
793 | return NULL; | |
794 | env->tb_env = tb_env; | |
795 | /* Create new timer */ | |
796 | tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env); | |
797 | if (0) { | |
798 | /* XXX: find a suitable condition to enable the hypervisor decrementer | |
799 | */ | |
800 | tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env); | |
801 | } else { | |
802 | tb_env->hdecr_timer = NULL; | |
803 | } | |
804 | cpu_ppc_set_tb_clk(env, freq); | |
805 | ||
806 | return &cpu_ppc_set_tb_clk; | |
807 | } | |
808 | ||
809 | /* Specific helpers for POWER & PowerPC 601 RTC */ | |
810 | clk_setup_cb cpu_ppc601_rtc_init (CPUState *env) | |
811 | { | |
812 | return cpu_ppc_tb_init(env, 7812500); | |
813 | } | |
814 | ||
815 | void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value) | |
816 | { | |
817 | _cpu_ppc_store_tbu(env, value); | |
818 | } | |
819 | ||
820 | uint32_t cpu_ppc601_load_rtcu (CPUState *env) | |
821 | { | |
822 | return _cpu_ppc_load_tbu(env); | |
823 | } | |
824 | ||
825 | void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value) | |
826 | { | |
827 | cpu_ppc_store_tbl(env, value & 0x3FFFFF80); | |
828 | } | |
829 | ||
830 | uint32_t cpu_ppc601_load_rtcl (CPUState *env) | |
831 | { | |
832 | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; | |
833 | } | |
834 | ||
835 | /*****************************************************************************/ | |
836 | /* Embedded PowerPC timers */ | |
837 | ||
838 | /* PIT, FIT & WDT */ | |
839 | typedef struct ppcemb_timer_t ppcemb_timer_t; | |
840 | struct ppcemb_timer_t { | |
841 | uint64_t pit_reload; /* PIT auto-reload value */ | |
842 | uint64_t fit_next; /* Tick for next FIT interrupt */ | |
843 | struct QEMUTimer *fit_timer; | |
844 | uint64_t wdt_next; /* Tick for next WDT interrupt */ | |
845 | struct QEMUTimer *wdt_timer; | |
846 | }; | |
847 | ||
848 | /* Fixed interval timer */ | |
849 | static void cpu_4xx_fit_cb (void *opaque) | |
850 | { | |
851 | CPUState *env; | |
852 | ppc_tb_t *tb_env; | |
853 | ppcemb_timer_t *ppcemb_timer; | |
854 | uint64_t now, next; | |
855 | ||
856 | env = opaque; | |
857 | tb_env = env->tb_env; | |
858 | ppcemb_timer = tb_env->opaque; | |
859 | now = qemu_get_clock(vm_clock); | |
860 | switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { | |
861 | case 0: | |
862 | next = 1 << 9; | |
863 | break; | |
864 | case 1: | |
865 | next = 1 << 13; | |
866 | break; | |
867 | case 2: | |
868 | next = 1 << 17; | |
869 | break; | |
870 | case 3: | |
871 | next = 1 << 21; | |
872 | break; | |
873 | default: | |
874 | /* Cannot occur, but makes gcc happy */ | |
875 | return; | |
876 | } | |
877 | next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); | |
878 | if (next == now) | |
879 | next++; | |
880 | qemu_mod_timer(ppcemb_timer->fit_timer, next); | |
881 | env->spr[SPR_40x_TSR] |= 1 << 26; | |
882 | if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) | |
883 | ppc_set_irq(env, PPC_INTERRUPT_FIT, 1); | |
884 | #ifdef PPC_DEBUG_TB | |
885 | if (loglevel != 0) { | |
886 | fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__, | |
887 | (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), | |
888 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); | |
889 | } | |
890 | #endif | |
891 | } | |
892 | ||
893 | /* Programmable interval timer */ | |
894 | static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) | |
895 | { | |
896 | ppcemb_timer_t *ppcemb_timer; | |
897 | uint64_t now, next; | |
898 | ||
899 | ppcemb_timer = tb_env->opaque; | |
900 | if (ppcemb_timer->pit_reload <= 1 || | |
901 | !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || | |
902 | (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { | |
903 | /* Stop PIT */ | |
904 | #ifdef PPC_DEBUG_TB | |
905 | if (loglevel != 0) { | |
906 | fprintf(logfile, "%s: stop PIT\n", __func__); | |
907 | } | |
908 | #endif | |
909 | qemu_del_timer(tb_env->decr_timer); | |
910 | } else { | |
911 | #ifdef PPC_DEBUG_TB | |
912 | if (loglevel != 0) { | |
913 | fprintf(logfile, "%s: start PIT 0x" REGX "\n", | |
914 | __func__, ppcemb_timer->pit_reload); | |
915 | } | |
916 | #endif | |
917 | now = qemu_get_clock(vm_clock); | |
918 | next = now + muldiv64(ppcemb_timer->pit_reload, | |
919 | ticks_per_sec, tb_env->decr_freq); | |
920 | if (is_excp) | |
921 | next += tb_env->decr_next - now; | |
922 | if (next == now) | |
923 | next++; | |
924 | qemu_mod_timer(tb_env->decr_timer, next); | |
925 | tb_env->decr_next = next; | |
926 | } | |
927 | } | |
928 | ||
929 | static void cpu_4xx_pit_cb (void *opaque) | |
930 | { | |
931 | CPUState *env; | |
932 | ppc_tb_t *tb_env; | |
933 | ppcemb_timer_t *ppcemb_timer; | |
934 | ||
935 | env = opaque; | |
936 | tb_env = env->tb_env; | |
937 | ppcemb_timer = tb_env->opaque; | |
938 | env->spr[SPR_40x_TSR] |= 1 << 27; | |
939 | if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) | |
940 | ppc_set_irq(env, PPC_INTERRUPT_PIT, 1); | |
941 | start_stop_pit(env, tb_env, 1); | |
942 | #ifdef PPC_DEBUG_TB | |
943 | if (loglevel != 0) { | |
944 | fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " " | |
945 | "%016" PRIx64 "\n", __func__, | |
946 | (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), | |
947 | (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), | |
948 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], | |
949 | ppcemb_timer->pit_reload); | |
950 | } | |
951 | #endif | |
952 | } | |
953 | ||
954 | /* Watchdog timer */ | |
955 | static void cpu_4xx_wdt_cb (void *opaque) | |
956 | { | |
957 | CPUState *env; | |
958 | ppc_tb_t *tb_env; | |
959 | ppcemb_timer_t *ppcemb_timer; | |
960 | uint64_t now, next; | |
961 | ||
962 | env = opaque; | |
963 | tb_env = env->tb_env; | |
964 | ppcemb_timer = tb_env->opaque; | |
965 | now = qemu_get_clock(vm_clock); | |
966 | switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { | |
967 | case 0: | |
968 | next = 1 << 17; | |
969 | break; | |
970 | case 1: | |
971 | next = 1 << 21; | |
972 | break; | |
973 | case 2: | |
974 | next = 1 << 25; | |
975 | break; | |
976 | case 3: | |
977 | next = 1 << 29; | |
978 | break; | |
979 | default: | |
980 | /* Cannot occur, but makes gcc happy */ | |
981 | return; | |
982 | } | |
983 | next = now + muldiv64(next, ticks_per_sec, tb_env->decr_freq); | |
984 | if (next == now) | |
985 | next++; | |
986 | #ifdef PPC_DEBUG_TB | |
987 | if (loglevel != 0) { | |
988 | fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__, | |
989 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); | |
990 | } | |
991 | #endif | |
992 | switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { | |
993 | case 0x0: | |
994 | case 0x1: | |
995 | qemu_mod_timer(ppcemb_timer->wdt_timer, next); | |
996 | ppcemb_timer->wdt_next = next; | |
997 | env->spr[SPR_40x_TSR] |= 1 << 31; | |
998 | break; | |
999 | case 0x2: | |
1000 | qemu_mod_timer(ppcemb_timer->wdt_timer, next); | |
1001 | ppcemb_timer->wdt_next = next; | |
1002 | env->spr[SPR_40x_TSR] |= 1 << 30; | |
1003 | if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) | |
1004 | ppc_set_irq(env, PPC_INTERRUPT_WDT, 1); | |
1005 | break; | |
1006 | case 0x3: | |
1007 | env->spr[SPR_40x_TSR] &= ~0x30000000; | |
1008 | env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; | |
1009 | switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { | |
1010 | case 0x0: | |
1011 | /* No reset */ | |
1012 | break; | |
1013 | case 0x1: /* Core reset */ | |
1014 | ppc40x_core_reset(env); | |
1015 | break; | |
1016 | case 0x2: /* Chip reset */ | |
1017 | ppc40x_chip_reset(env); | |
1018 | break; | |
1019 | case 0x3: /* System reset */ | |
1020 | ppc40x_system_reset(env); | |
1021 | break; | |
1022 | } | |
1023 | } | |
1024 | } | |
1025 | ||
1026 | void store_40x_pit (CPUState *env, target_ulong val) | |
1027 | { | |
1028 | ppc_tb_t *tb_env; | |
1029 | ppcemb_timer_t *ppcemb_timer; | |
1030 | ||
1031 | tb_env = env->tb_env; | |
1032 | ppcemb_timer = tb_env->opaque; | |
1033 | #ifdef PPC_DEBUG_TB | |
1034 | if (loglevel != 0) { | |
1035 | fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer); | |
1036 | } | |
1037 | #endif | |
1038 | ppcemb_timer->pit_reload = val; | |
1039 | start_stop_pit(env, tb_env, 0); | |
1040 | } | |
1041 | ||
1042 | target_ulong load_40x_pit (CPUState *env) | |
1043 | { | |
1044 | return cpu_ppc_load_decr(env); | |
1045 | } | |
1046 | ||
1047 | void store_booke_tsr (CPUState *env, target_ulong val) | |
1048 | { | |
1049 | #ifdef PPC_DEBUG_TB | |
1050 | if (loglevel != 0) { | |
1051 | fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val); | |
1052 | } | |
1053 | #endif | |
1054 | env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000); | |
1055 | if (val & 0x80000000) | |
1056 | ppc_set_irq(env, PPC_INTERRUPT_PIT, 0); | |
1057 | } | |
1058 | ||
1059 | void store_booke_tcr (CPUState *env, target_ulong val) | |
1060 | { | |
1061 | ppc_tb_t *tb_env; | |
1062 | ||
1063 | tb_env = env->tb_env; | |
1064 | #ifdef PPC_DEBUG_TB | |
1065 | if (loglevel != 0) { | |
1066 | fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val); | |
1067 | } | |
1068 | #endif | |
1069 | env->spr[SPR_40x_TCR] = val & 0xFFC00000; | |
1070 | start_stop_pit(env, tb_env, 1); | |
1071 | cpu_4xx_wdt_cb(env); | |
1072 | } | |
1073 | ||
1074 | static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq) | |
1075 | { | |
1076 | CPUState *env = opaque; | |
1077 | ppc_tb_t *tb_env = env->tb_env; | |
1078 | ||
1079 | #ifdef PPC_DEBUG_TB | |
1080 | if (loglevel != 0) { | |
1081 | fprintf(logfile, "%s set new frequency to %u\n", __func__, freq); | |
1082 | } | |
1083 | #endif | |
1084 | tb_env->tb_freq = freq; | |
1085 | tb_env->decr_freq = freq; | |
1086 | /* XXX: we should also update all timers */ | |
1087 | } | |
1088 | ||
1089 | clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq) | |
1090 | { | |
1091 | ppc_tb_t *tb_env; | |
1092 | ppcemb_timer_t *ppcemb_timer; | |
1093 | ||
1094 | tb_env = qemu_mallocz(sizeof(ppc_tb_t)); | |
1095 | if (tb_env == NULL) { | |
1096 | return NULL; | |
1097 | } | |
1098 | env->tb_env = tb_env; | |
1099 | ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t)); | |
1100 | tb_env->tb_freq = freq; | |
1101 | tb_env->decr_freq = freq; | |
1102 | tb_env->opaque = ppcemb_timer; | |
1103 | #ifdef PPC_DEBUG_TB | |
1104 | if (loglevel != 0) { | |
1105 | fprintf(logfile, "%s %p %p %p\n", __func__, tb_env, ppcemb_timer, | |
1106 | &ppc_emb_set_tb_clk); | |
1107 | } | |
1108 | #endif | |
1109 | if (ppcemb_timer != NULL) { | |
1110 | /* We use decr timer for PIT */ | |
1111 | tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env); | |
1112 | ppcemb_timer->fit_timer = | |
1113 | qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env); | |
1114 | ppcemb_timer->wdt_timer = | |
1115 | qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env); | |
1116 | } | |
1117 | ||
1118 | return &ppc_emb_set_tb_clk; | |
1119 | } | |
1120 | ||
1121 | /*****************************************************************************/ | |
1122 | /* Embedded PowerPC Device Control Registers */ | |
1123 | typedef struct ppc_dcrn_t ppc_dcrn_t; | |
1124 | struct ppc_dcrn_t { | |
1125 | dcr_read_cb dcr_read; | |
1126 | dcr_write_cb dcr_write; | |
1127 | void *opaque; | |
1128 | }; | |
1129 | ||
1130 | /* XXX: on 460, DCR addresses are 32 bits wide, | |
1131 | * using DCRIPR to get the 22 upper bits of the DCR address | |
1132 | */ | |
1133 | #define DCRN_NB 1024 | |
1134 | struct ppc_dcr_t { | |
1135 | ppc_dcrn_t dcrn[DCRN_NB]; | |
1136 | int (*read_error)(int dcrn); | |
1137 | int (*write_error)(int dcrn); | |
1138 | }; | |
1139 | ||
1140 | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) | |
1141 | { | |
1142 | ppc_dcrn_t *dcr; | |
1143 | ||
1144 | if (dcrn < 0 || dcrn >= DCRN_NB) | |
1145 | goto error; | |
1146 | dcr = &dcr_env->dcrn[dcrn]; | |
1147 | if (dcr->dcr_read == NULL) | |
1148 | goto error; | |
1149 | *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); | |
1150 | ||
1151 | return 0; | |
1152 | ||
1153 | error: | |
1154 | if (dcr_env->read_error != NULL) | |
1155 | return (*dcr_env->read_error)(dcrn); | |
1156 | ||
1157 | return -1; | |
1158 | } | |
1159 | ||
1160 | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val) | |
1161 | { | |
1162 | ppc_dcrn_t *dcr; | |
1163 | ||
1164 | if (dcrn < 0 || dcrn >= DCRN_NB) | |
1165 | goto error; | |
1166 | dcr = &dcr_env->dcrn[dcrn]; | |
1167 | if (dcr->dcr_write == NULL) | |
1168 | goto error; | |
1169 | (*dcr->dcr_write)(dcr->opaque, dcrn, val); | |
1170 | ||
1171 | return 0; | |
1172 | ||
1173 | error: | |
1174 | if (dcr_env->write_error != NULL) | |
1175 | return (*dcr_env->write_error)(dcrn); | |
1176 | ||
1177 | return -1; | |
1178 | } | |
1179 | ||
1180 | int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, | |
1181 | dcr_read_cb dcr_read, dcr_write_cb dcr_write) | |
1182 | { | |
1183 | ppc_dcr_t *dcr_env; | |
1184 | ppc_dcrn_t *dcr; | |
1185 | ||
1186 | dcr_env = env->dcr_env; | |
1187 | if (dcr_env == NULL) | |
1188 | return -1; | |
1189 | if (dcrn < 0 || dcrn >= DCRN_NB) | |
1190 | return -1; | |
1191 | dcr = &dcr_env->dcrn[dcrn]; | |
1192 | if (dcr->opaque != NULL || | |
1193 | dcr->dcr_read != NULL || | |
1194 | dcr->dcr_write != NULL) | |
1195 | return -1; | |
1196 | dcr->opaque = opaque; | |
1197 | dcr->dcr_read = dcr_read; | |
1198 | dcr->dcr_write = dcr_write; | |
1199 | ||
1200 | return 0; | |
1201 | } | |
1202 | ||
1203 | int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn), | |
1204 | int (*write_error)(int dcrn)) | |
1205 | { | |
1206 | ppc_dcr_t *dcr_env; | |
1207 | ||
1208 | dcr_env = qemu_mallocz(sizeof(ppc_dcr_t)); | |
1209 | if (dcr_env == NULL) | |
1210 | return -1; | |
1211 | dcr_env->read_error = read_error; | |
1212 | dcr_env->write_error = write_error; | |
1213 | env->dcr_env = dcr_env; | |
1214 | ||
1215 | return 0; | |
1216 | } | |
1217 | ||
1218 | #if 0 | |
1219 | /*****************************************************************************/ | |
1220 | /* Handle system reset (for now, just stop emulation) */ | |
1221 | void cpu_ppc_reset (CPUState *env) | |
1222 | { | |
1223 | printf("Reset asked... Stop emulation\n"); | |
1224 | abort(); | |
1225 | } | |
1226 | #endif | |
1227 | ||
1228 | /*****************************************************************************/ | |
1229 | /* Debug port */ | |
1230 | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) | |
1231 | { | |
1232 | addr &= 0xF; | |
1233 | switch (addr) { | |
1234 | case 0: | |
1235 | printf("%c", val); | |
1236 | break; | |
1237 | case 1: | |
1238 | printf("\n"); | |
1239 | fflush(stdout); | |
1240 | break; | |
1241 | case 2: | |
1242 | printf("Set loglevel to %04x\n", val); | |
1243 | cpu_set_log(val | 0x100); | |
1244 | break; | |
1245 | } | |
1246 | } | |
1247 | ||
1248 | /*****************************************************************************/ | |
1249 | /* NVRAM helpers */ | |
1250 | static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr) | |
1251 | { | |
1252 | return (*nvram->read_fn)(nvram->opaque, addr);; | |
1253 | } | |
1254 | ||
1255 | static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val) | |
1256 | { | |
1257 | (*nvram->write_fn)(nvram->opaque, addr, val); | |
1258 | } | |
1259 | ||
1260 | void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value) | |
1261 | { | |
1262 | nvram_write(nvram, addr, value); | |
1263 | } | |
1264 | ||
1265 | uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr) | |
1266 | { | |
1267 | return nvram_read(nvram, addr); | |
1268 | } | |
1269 | ||
1270 | void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value) | |
1271 | { | |
1272 | nvram_write(nvram, addr, value >> 8); | |
1273 | nvram_write(nvram, addr + 1, value & 0xFF); | |
1274 | } | |
1275 | ||
1276 | uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr) | |
1277 | { | |
1278 | uint16_t tmp; | |
1279 | ||
1280 | tmp = nvram_read(nvram, addr) << 8; | |
1281 | tmp |= nvram_read(nvram, addr + 1); | |
1282 | ||
1283 | return tmp; | |
1284 | } | |
1285 | ||
1286 | void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value) | |
1287 | { | |
1288 | nvram_write(nvram, addr, value >> 24); | |
1289 | nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); | |
1290 | nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); | |
1291 | nvram_write(nvram, addr + 3, value & 0xFF); | |
1292 | } | |
1293 | ||
1294 | uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr) | |
1295 | { | |
1296 | uint32_t tmp; | |
1297 | ||
1298 | tmp = nvram_read(nvram, addr) << 24; | |
1299 | tmp |= nvram_read(nvram, addr + 1) << 16; | |
1300 | tmp |= nvram_read(nvram, addr + 2) << 8; | |
1301 | tmp |= nvram_read(nvram, addr + 3); | |
1302 | ||
1303 | return tmp; | |
1304 | } | |
1305 | ||
1306 | void NVRAM_set_string (nvram_t *nvram, uint32_t addr, | |
1307 | const unsigned char *str, uint32_t max) | |
1308 | { | |
1309 | int i; | |
1310 | ||
1311 | for (i = 0; i < max && str[i] != '\0'; i++) { | |
1312 | nvram_write(nvram, addr + i, str[i]); | |
1313 | } | |
1314 | nvram_write(nvram, addr + i, str[i]); | |
1315 | nvram_write(nvram, addr + max - 1, '\0'); | |
1316 | } | |
1317 | ||
1318 | int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max) | |
1319 | { | |
1320 | int i; | |
1321 | ||
1322 | memset(dst, 0, max); | |
1323 | for (i = 0; i < max; i++) { | |
1324 | dst[i] = NVRAM_get_byte(nvram, addr + i); | |
1325 | if (dst[i] == '\0') | |
1326 | break; | |
1327 | } | |
1328 | ||
1329 | return i; | |
1330 | } | |
1331 | ||
1332 | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) | |
1333 | { | |
1334 | uint16_t tmp; | |
1335 | uint16_t pd, pd1, pd2; | |
1336 | ||
1337 | tmp = prev >> 8; | |
1338 | pd = prev ^ value; | |
1339 | pd1 = pd & 0x000F; | |
1340 | pd2 = ((pd >> 4) & 0x000F) ^ pd1; | |
1341 | tmp ^= (pd1 << 3) | (pd1 << 8); | |
1342 | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); | |
1343 | ||
1344 | return tmp; | |
1345 | } | |
1346 | ||
1347 | uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count) | |
1348 | { | |
1349 | uint32_t i; | |
1350 | uint16_t crc = 0xFFFF; | |
1351 | int odd; | |
1352 | ||
1353 | odd = count & 1; | |
1354 | count &= ~1; | |
1355 | for (i = 0; i != count; i++) { | |
1356 | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); | |
1357 | } | |
1358 | if (odd) { | |
1359 | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); | |
1360 | } | |
1361 | ||
1362 | return crc; | |
1363 | } | |
1364 | ||
1365 | #define CMDLINE_ADDR 0x017ff000 | |
1366 | ||
1367 | int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size, | |
1368 | const unsigned char *arch, | |
1369 | uint32_t RAM_size, int boot_device, | |
1370 | uint32_t kernel_image, uint32_t kernel_size, | |
1371 | const char *cmdline, | |
1372 | uint32_t initrd_image, uint32_t initrd_size, | |
1373 | uint32_t NVRAM_image, | |
1374 | int width, int height, int depth) | |
1375 | { | |
1376 | uint16_t crc; | |
1377 | ||
1378 | /* Set parameters for Open Hack'Ware BIOS */ | |
1379 | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); | |
1380 | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ | |
1381 | NVRAM_set_word(nvram, 0x14, NVRAM_size); | |
1382 | NVRAM_set_string(nvram, 0x20, arch, 16); | |
1383 | NVRAM_set_lword(nvram, 0x30, RAM_size); | |
1384 | NVRAM_set_byte(nvram, 0x34, boot_device); | |
1385 | NVRAM_set_lword(nvram, 0x38, kernel_image); | |
1386 | NVRAM_set_lword(nvram, 0x3C, kernel_size); | |
1387 | if (cmdline) { | |
1388 | /* XXX: put the cmdline in NVRAM too ? */ | |
1389 | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); | |
1390 | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); | |
1391 | NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); | |
1392 | } else { | |
1393 | NVRAM_set_lword(nvram, 0x40, 0); | |
1394 | NVRAM_set_lword(nvram, 0x44, 0); | |
1395 | } | |
1396 | NVRAM_set_lword(nvram, 0x48, initrd_image); | |
1397 | NVRAM_set_lword(nvram, 0x4C, initrd_size); | |
1398 | NVRAM_set_lword(nvram, 0x50, NVRAM_image); | |
1399 | ||
1400 | NVRAM_set_word(nvram, 0x54, width); | |
1401 | NVRAM_set_word(nvram, 0x56, height); | |
1402 | NVRAM_set_word(nvram, 0x58, depth); | |
1403 | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); | |
1404 | NVRAM_set_word(nvram, 0xFC, crc); | |
1405 | ||
1406 | return 0; | |
1407 | } |