]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * QEMU PowerPC 405 embedded processors emulation | |
3 | * | |
4 | * Copyright (c) 2007 Jocelyn Mayer | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "vl.h" | |
25 | #include "ppc405.h" | |
26 | ||
27 | extern int loglevel; | |
28 | extern FILE *logfile; | |
29 | ||
30 | #define DEBUG_OPBA | |
31 | #define DEBUG_SDRAM | |
32 | #define DEBUG_GPIO | |
33 | #define DEBUG_SERIAL | |
34 | #define DEBUG_OCM | |
35 | //#define DEBUG_I2C | |
36 | #define DEBUG_GPT | |
37 | #define DEBUG_MAL | |
38 | #define DEBUG_CLOCKS | |
39 | //#define DEBUG_UNASSIGNED | |
40 | ||
41 | ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, | |
42 | uint32_t flags) | |
43 | { | |
44 | ram_addr_t bdloc; | |
45 | int i, n; | |
46 | ||
47 | /* We put the bd structure at the top of memory */ | |
48 | if (bd->bi_memsize >= 0x01000000UL) | |
49 | bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); | |
50 | else | |
51 | bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); | |
52 | stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart); | |
53 | stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize); | |
54 | stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart); | |
55 | stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize); | |
56 | stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset); | |
57 | stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart); | |
58 | stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize); | |
59 | stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags); | |
60 | stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr); | |
61 | for (i = 0; i < 6; i++) | |
62 | stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]); | |
63 | stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed); | |
64 | stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq); | |
65 | stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq); | |
66 | stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate); | |
67 | for (i = 0; i < 4; i++) | |
68 | stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]); | |
69 | for (i = 0; i < 32; i++) | |
70 | stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]); | |
71 | stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq); | |
72 | stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq); | |
73 | for (i = 0; i < 6; i++) | |
74 | stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); | |
75 | n = 0x6A; | |
76 | if (flags & 0x00000001) { | |
77 | for (i = 0; i < 6; i++) | |
78 | stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]); | |
79 | } | |
80 | stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq); | |
81 | n += 4; | |
82 | for (i = 0; i < 2; i++) { | |
83 | stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]); | |
84 | n += 4; | |
85 | } | |
86 | ||
87 | return bdloc; | |
88 | } | |
89 | ||
90 | /*****************************************************************************/ | |
91 | /* Shared peripherals */ | |
92 | ||
93 | /*****************************************************************************/ | |
94 | /* Peripheral local bus arbitrer */ | |
95 | enum { | |
96 | PLB0_BESR = 0x084, | |
97 | PLB0_BEAR = 0x086, | |
98 | PLB0_ACR = 0x087, | |
99 | }; | |
100 | ||
101 | typedef struct ppc4xx_plb_t ppc4xx_plb_t; | |
102 | struct ppc4xx_plb_t { | |
103 | uint32_t acr; | |
104 | uint32_t bear; | |
105 | uint32_t besr; | |
106 | }; | |
107 | ||
108 | static target_ulong dcr_read_plb (void *opaque, int dcrn) | |
109 | { | |
110 | ppc4xx_plb_t *plb; | |
111 | target_ulong ret; | |
112 | ||
113 | plb = opaque; | |
114 | switch (dcrn) { | |
115 | case PLB0_ACR: | |
116 | ret = plb->acr; | |
117 | break; | |
118 | case PLB0_BEAR: | |
119 | ret = plb->bear; | |
120 | break; | |
121 | case PLB0_BESR: | |
122 | ret = plb->besr; | |
123 | break; | |
124 | default: | |
125 | /* Avoid gcc warning */ | |
126 | ret = 0; | |
127 | break; | |
128 | } | |
129 | ||
130 | return ret; | |
131 | } | |
132 | ||
133 | static void dcr_write_plb (void *opaque, int dcrn, target_ulong val) | |
134 | { | |
135 | ppc4xx_plb_t *plb; | |
136 | ||
137 | plb = opaque; | |
138 | switch (dcrn) { | |
139 | case PLB0_ACR: | |
140 | /* We don't care about the actual parameters written as | |
141 | * we don't manage any priorities on the bus | |
142 | */ | |
143 | plb->acr = val & 0xF8000000; | |
144 | break; | |
145 | case PLB0_BEAR: | |
146 | /* Read only */ | |
147 | break; | |
148 | case PLB0_BESR: | |
149 | /* Write-clear */ | |
150 | plb->besr &= ~val; | |
151 | break; | |
152 | } | |
153 | } | |
154 | ||
155 | static void ppc4xx_plb_reset (void *opaque) | |
156 | { | |
157 | ppc4xx_plb_t *plb; | |
158 | ||
159 | plb = opaque; | |
160 | plb->acr = 0x00000000; | |
161 | plb->bear = 0x00000000; | |
162 | plb->besr = 0x00000000; | |
163 | } | |
164 | ||
165 | void ppc4xx_plb_init (CPUState *env) | |
166 | { | |
167 | ppc4xx_plb_t *plb; | |
168 | ||
169 | plb = qemu_mallocz(sizeof(ppc4xx_plb_t)); | |
170 | if (plb != NULL) { | |
171 | ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); | |
172 | ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); | |
173 | ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); | |
174 | ppc4xx_plb_reset(plb); | |
175 | qemu_register_reset(ppc4xx_plb_reset, plb); | |
176 | } | |
177 | } | |
178 | ||
179 | /*****************************************************************************/ | |
180 | /* PLB to OPB bridge */ | |
181 | enum { | |
182 | POB0_BESR0 = 0x0A0, | |
183 | POB0_BESR1 = 0x0A2, | |
184 | POB0_BEAR = 0x0A4, | |
185 | }; | |
186 | ||
187 | typedef struct ppc4xx_pob_t ppc4xx_pob_t; | |
188 | struct ppc4xx_pob_t { | |
189 | uint32_t bear; | |
190 | uint32_t besr[2]; | |
191 | }; | |
192 | ||
193 | static target_ulong dcr_read_pob (void *opaque, int dcrn) | |
194 | { | |
195 | ppc4xx_pob_t *pob; | |
196 | target_ulong ret; | |
197 | ||
198 | pob = opaque; | |
199 | switch (dcrn) { | |
200 | case POB0_BEAR: | |
201 | ret = pob->bear; | |
202 | break; | |
203 | case POB0_BESR0: | |
204 | case POB0_BESR1: | |
205 | ret = pob->besr[dcrn - POB0_BESR0]; | |
206 | break; | |
207 | default: | |
208 | /* Avoid gcc warning */ | |
209 | ret = 0; | |
210 | break; | |
211 | } | |
212 | ||
213 | return ret; | |
214 | } | |
215 | ||
216 | static void dcr_write_pob (void *opaque, int dcrn, target_ulong val) | |
217 | { | |
218 | ppc4xx_pob_t *pob; | |
219 | ||
220 | pob = opaque; | |
221 | switch (dcrn) { | |
222 | case POB0_BEAR: | |
223 | /* Read only */ | |
224 | break; | |
225 | case POB0_BESR0: | |
226 | case POB0_BESR1: | |
227 | /* Write-clear */ | |
228 | pob->besr[dcrn - POB0_BESR0] &= ~val; | |
229 | break; | |
230 | } | |
231 | } | |
232 | ||
233 | static void ppc4xx_pob_reset (void *opaque) | |
234 | { | |
235 | ppc4xx_pob_t *pob; | |
236 | ||
237 | pob = opaque; | |
238 | /* No error */ | |
239 | pob->bear = 0x00000000; | |
240 | pob->besr[0] = 0x0000000; | |
241 | pob->besr[1] = 0x0000000; | |
242 | } | |
243 | ||
244 | void ppc4xx_pob_init (CPUState *env) | |
245 | { | |
246 | ppc4xx_pob_t *pob; | |
247 | ||
248 | pob = qemu_mallocz(sizeof(ppc4xx_pob_t)); | |
249 | if (pob != NULL) { | |
250 | ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); | |
251 | ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); | |
252 | ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); | |
253 | qemu_register_reset(ppc4xx_pob_reset, pob); | |
254 | ppc4xx_pob_reset(env); | |
255 | } | |
256 | } | |
257 | ||
258 | /*****************************************************************************/ | |
259 | /* OPB arbitrer */ | |
260 | typedef struct ppc4xx_opba_t ppc4xx_opba_t; | |
261 | struct ppc4xx_opba_t { | |
262 | target_phys_addr_t base; | |
263 | uint8_t cr; | |
264 | uint8_t pr; | |
265 | }; | |
266 | ||
267 | static uint32_t opba_readb (void *opaque, target_phys_addr_t addr) | |
268 | { | |
269 | ppc4xx_opba_t *opba; | |
270 | uint32_t ret; | |
271 | ||
272 | #ifdef DEBUG_OPBA | |
273 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
274 | #endif | |
275 | opba = opaque; | |
276 | switch (addr - opba->base) { | |
277 | case 0x00: | |
278 | ret = opba->cr; | |
279 | break; | |
280 | case 0x01: | |
281 | ret = opba->pr; | |
282 | break; | |
283 | default: | |
284 | ret = 0x00; | |
285 | break; | |
286 | } | |
287 | ||
288 | return ret; | |
289 | } | |
290 | ||
291 | static void opba_writeb (void *opaque, | |
292 | target_phys_addr_t addr, uint32_t value) | |
293 | { | |
294 | ppc4xx_opba_t *opba; | |
295 | ||
296 | #ifdef DEBUG_OPBA | |
297 | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); | |
298 | #endif | |
299 | opba = opaque; | |
300 | switch (addr - opba->base) { | |
301 | case 0x00: | |
302 | opba->cr = value & 0xF8; | |
303 | break; | |
304 | case 0x01: | |
305 | opba->pr = value & 0xFF; | |
306 | break; | |
307 | default: | |
308 | break; | |
309 | } | |
310 | } | |
311 | ||
312 | static uint32_t opba_readw (void *opaque, target_phys_addr_t addr) | |
313 | { | |
314 | uint32_t ret; | |
315 | ||
316 | #ifdef DEBUG_OPBA | |
317 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
318 | #endif | |
319 | ret = opba_readb(opaque, addr) << 8; | |
320 | ret |= opba_readb(opaque, addr + 1); | |
321 | ||
322 | return ret; | |
323 | } | |
324 | ||
325 | static void opba_writew (void *opaque, | |
326 | target_phys_addr_t addr, uint32_t value) | |
327 | { | |
328 | #ifdef DEBUG_OPBA | |
329 | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); | |
330 | #endif | |
331 | opba_writeb(opaque, addr, value >> 8); | |
332 | opba_writeb(opaque, addr + 1, value); | |
333 | } | |
334 | ||
335 | static uint32_t opba_readl (void *opaque, target_phys_addr_t addr) | |
336 | { | |
337 | uint32_t ret; | |
338 | ||
339 | #ifdef DEBUG_OPBA | |
340 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
341 | #endif | |
342 | ret = opba_readb(opaque, addr) << 24; | |
343 | ret |= opba_readb(opaque, addr + 1) << 16; | |
344 | ||
345 | return ret; | |
346 | } | |
347 | ||
348 | static void opba_writel (void *opaque, | |
349 | target_phys_addr_t addr, uint32_t value) | |
350 | { | |
351 | #ifdef DEBUG_OPBA | |
352 | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); | |
353 | #endif | |
354 | opba_writeb(opaque, addr, value >> 24); | |
355 | opba_writeb(opaque, addr + 1, value >> 16); | |
356 | } | |
357 | ||
358 | static CPUReadMemoryFunc *opba_read[] = { | |
359 | &opba_readb, | |
360 | &opba_readw, | |
361 | &opba_readl, | |
362 | }; | |
363 | ||
364 | static CPUWriteMemoryFunc *opba_write[] = { | |
365 | &opba_writeb, | |
366 | &opba_writew, | |
367 | &opba_writel, | |
368 | }; | |
369 | ||
370 | static void ppc4xx_opba_reset (void *opaque) | |
371 | { | |
372 | ppc4xx_opba_t *opba; | |
373 | ||
374 | opba = opaque; | |
375 | opba->cr = 0x00; /* No dynamic priorities - park disabled */ | |
376 | opba->pr = 0x11; | |
377 | } | |
378 | ||
379 | void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio, | |
380 | target_phys_addr_t offset) | |
381 | { | |
382 | ppc4xx_opba_t *opba; | |
383 | ||
384 | opba = qemu_mallocz(sizeof(ppc4xx_opba_t)); | |
385 | if (opba != NULL) { | |
386 | opba->base = offset; | |
387 | #ifdef DEBUG_OPBA | |
388 | printf("%s: offset=" PADDRX "\n", __func__, offset); | |
389 | #endif | |
390 | ppc4xx_mmio_register(env, mmio, offset, 0x002, | |
391 | opba_read, opba_write, opba); | |
392 | qemu_register_reset(ppc4xx_opba_reset, opba); | |
393 | ppc4xx_opba_reset(opba); | |
394 | } | |
395 | } | |
396 | ||
397 | /*****************************************************************************/ | |
398 | /* Code decompression controller */ | |
399 | /* XXX: TODO */ | |
400 | ||
401 | /*****************************************************************************/ | |
402 | /* SDRAM controller */ | |
403 | typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; | |
404 | struct ppc4xx_sdram_t { | |
405 | uint32_t addr; | |
406 | int nbanks; | |
407 | target_phys_addr_t ram_bases[4]; | |
408 | target_phys_addr_t ram_sizes[4]; | |
409 | uint32_t besr0; | |
410 | uint32_t besr1; | |
411 | uint32_t bear; | |
412 | uint32_t cfg; | |
413 | uint32_t status; | |
414 | uint32_t rtr; | |
415 | uint32_t pmit; | |
416 | uint32_t bcr[4]; | |
417 | uint32_t tr; | |
418 | uint32_t ecccfg; | |
419 | uint32_t eccesr; | |
420 | qemu_irq irq; | |
421 | }; | |
422 | ||
423 | enum { | |
424 | SDRAM0_CFGADDR = 0x010, | |
425 | SDRAM0_CFGDATA = 0x011, | |
426 | }; | |
427 | ||
428 | static uint32_t sdram_bcr (target_phys_addr_t ram_base, | |
429 | target_phys_addr_t ram_size) | |
430 | { | |
431 | uint32_t bcr; | |
432 | ||
433 | switch (ram_size) { | |
434 | case (4 * 1024 * 1024): | |
435 | bcr = 0x00000000; | |
436 | break; | |
437 | case (8 * 1024 * 1024): | |
438 | bcr = 0x00020000; | |
439 | break; | |
440 | case (16 * 1024 * 1024): | |
441 | bcr = 0x00040000; | |
442 | break; | |
443 | case (32 * 1024 * 1024): | |
444 | bcr = 0x00060000; | |
445 | break; | |
446 | case (64 * 1024 * 1024): | |
447 | bcr = 0x00080000; | |
448 | break; | |
449 | case (128 * 1024 * 1024): | |
450 | bcr = 0x000A0000; | |
451 | break; | |
452 | case (256 * 1024 * 1024): | |
453 | bcr = 0x000C0000; | |
454 | break; | |
455 | default: | |
456 | printf("%s: invalid RAM size " TARGET_FMT_plx "\n", | |
457 | __func__, ram_size); | |
458 | return 0x00000000; | |
459 | } | |
460 | bcr |= ram_base & 0xFF800000; | |
461 | bcr |= 1; | |
462 | ||
463 | return bcr; | |
464 | } | |
465 | ||
466 | static inline target_phys_addr_t sdram_base (uint32_t bcr) | |
467 | { | |
468 | return bcr & 0xFF800000; | |
469 | } | |
470 | ||
471 | static target_ulong sdram_size (uint32_t bcr) | |
472 | { | |
473 | target_ulong size; | |
474 | int sh; | |
475 | ||
476 | sh = (bcr >> 17) & 0x7; | |
477 | if (sh == 7) | |
478 | size = -1; | |
479 | else | |
480 | size = (4 * 1024 * 1024) << sh; | |
481 | ||
482 | return size; | |
483 | } | |
484 | ||
485 | static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled) | |
486 | { | |
487 | if (*bcrp & 0x00000001) { | |
488 | /* Unmap RAM */ | |
489 | #ifdef DEBUG_SDRAM | |
490 | printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", | |
491 | __func__, sdram_base(*bcrp), sdram_size(*bcrp)); | |
492 | #endif | |
493 | cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp), | |
494 | IO_MEM_UNASSIGNED); | |
495 | } | |
496 | *bcrp = bcr & 0xFFDEE001; | |
497 | if (enabled && (bcr & 0x00000001)) { | |
498 | #ifdef DEBUG_SDRAM | |
499 | printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", | |
500 | __func__, sdram_base(bcr), sdram_size(bcr)); | |
501 | #endif | |
502 | cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr), | |
503 | sdram_base(bcr) | IO_MEM_RAM); | |
504 | } | |
505 | } | |
506 | ||
507 | static void sdram_map_bcr (ppc4xx_sdram_t *sdram) | |
508 | { | |
509 | int i; | |
510 | ||
511 | for (i = 0; i < sdram->nbanks; i++) { | |
512 | if (sdram->ram_sizes[i] != 0) { | |
513 | sdram_set_bcr(&sdram->bcr[i], | |
514 | sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]), | |
515 | 1); | |
516 | } else { | |
517 | sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0); | |
518 | } | |
519 | } | |
520 | } | |
521 | ||
522 | static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) | |
523 | { | |
524 | int i; | |
525 | ||
526 | for (i = 0; i < sdram->nbanks; i++) { | |
527 | #ifdef DEBUG_SDRAM | |
528 | printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", | |
529 | __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); | |
530 | #endif | |
531 | cpu_register_physical_memory(sdram_base(sdram->bcr[i]), | |
532 | sdram_size(sdram->bcr[i]), | |
533 | IO_MEM_UNASSIGNED); | |
534 | } | |
535 | } | |
536 | ||
537 | static target_ulong dcr_read_sdram (void *opaque, int dcrn) | |
538 | { | |
539 | ppc4xx_sdram_t *sdram; | |
540 | target_ulong ret; | |
541 | ||
542 | sdram = opaque; | |
543 | switch (dcrn) { | |
544 | case SDRAM0_CFGADDR: | |
545 | ret = sdram->addr; | |
546 | break; | |
547 | case SDRAM0_CFGDATA: | |
548 | switch (sdram->addr) { | |
549 | case 0x00: /* SDRAM_BESR0 */ | |
550 | ret = sdram->besr0; | |
551 | break; | |
552 | case 0x08: /* SDRAM_BESR1 */ | |
553 | ret = sdram->besr1; | |
554 | break; | |
555 | case 0x10: /* SDRAM_BEAR */ | |
556 | ret = sdram->bear; | |
557 | break; | |
558 | case 0x20: /* SDRAM_CFG */ | |
559 | ret = sdram->cfg; | |
560 | break; | |
561 | case 0x24: /* SDRAM_STATUS */ | |
562 | ret = sdram->status; | |
563 | break; | |
564 | case 0x30: /* SDRAM_RTR */ | |
565 | ret = sdram->rtr; | |
566 | break; | |
567 | case 0x34: /* SDRAM_PMIT */ | |
568 | ret = sdram->pmit; | |
569 | break; | |
570 | case 0x40: /* SDRAM_B0CR */ | |
571 | ret = sdram->bcr[0]; | |
572 | break; | |
573 | case 0x44: /* SDRAM_B1CR */ | |
574 | ret = sdram->bcr[1]; | |
575 | break; | |
576 | case 0x48: /* SDRAM_B2CR */ | |
577 | ret = sdram->bcr[2]; | |
578 | break; | |
579 | case 0x4C: /* SDRAM_B3CR */ | |
580 | ret = sdram->bcr[3]; | |
581 | break; | |
582 | case 0x80: /* SDRAM_TR */ | |
583 | ret = -1; /* ? */ | |
584 | break; | |
585 | case 0x94: /* SDRAM_ECCCFG */ | |
586 | ret = sdram->ecccfg; | |
587 | break; | |
588 | case 0x98: /* SDRAM_ECCESR */ | |
589 | ret = sdram->eccesr; | |
590 | break; | |
591 | default: /* Error */ | |
592 | ret = -1; | |
593 | break; | |
594 | } | |
595 | break; | |
596 | default: | |
597 | /* Avoid gcc warning */ | |
598 | ret = 0x00000000; | |
599 | break; | |
600 | } | |
601 | ||
602 | return ret; | |
603 | } | |
604 | ||
605 | static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val) | |
606 | { | |
607 | ppc4xx_sdram_t *sdram; | |
608 | ||
609 | sdram = opaque; | |
610 | switch (dcrn) { | |
611 | case SDRAM0_CFGADDR: | |
612 | sdram->addr = val; | |
613 | break; | |
614 | case SDRAM0_CFGDATA: | |
615 | switch (sdram->addr) { | |
616 | case 0x00: /* SDRAM_BESR0 */ | |
617 | sdram->besr0 &= ~val; | |
618 | break; | |
619 | case 0x08: /* SDRAM_BESR1 */ | |
620 | sdram->besr1 &= ~val; | |
621 | break; | |
622 | case 0x10: /* SDRAM_BEAR */ | |
623 | sdram->bear = val; | |
624 | break; | |
625 | case 0x20: /* SDRAM_CFG */ | |
626 | val &= 0xFFE00000; | |
627 | if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { | |
628 | #ifdef DEBUG_SDRAM | |
629 | printf("%s: enable SDRAM controller\n", __func__); | |
630 | #endif | |
631 | /* validate all RAM mappings */ | |
632 | sdram_map_bcr(sdram); | |
633 | sdram->status &= ~0x80000000; | |
634 | } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { | |
635 | #ifdef DEBUG_SDRAM | |
636 | printf("%s: disable SDRAM controller\n", __func__); | |
637 | #endif | |
638 | /* invalidate all RAM mappings */ | |
639 | sdram_unmap_bcr(sdram); | |
640 | sdram->status |= 0x80000000; | |
641 | } | |
642 | if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) | |
643 | sdram->status |= 0x40000000; | |
644 | else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) | |
645 | sdram->status &= ~0x40000000; | |
646 | sdram->cfg = val; | |
647 | break; | |
648 | case 0x24: /* SDRAM_STATUS */ | |
649 | /* Read-only register */ | |
650 | break; | |
651 | case 0x30: /* SDRAM_RTR */ | |
652 | sdram->rtr = val & 0x3FF80000; | |
653 | break; | |
654 | case 0x34: /* SDRAM_PMIT */ | |
655 | sdram->pmit = (val & 0xF8000000) | 0x07C00000; | |
656 | break; | |
657 | case 0x40: /* SDRAM_B0CR */ | |
658 | sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000); | |
659 | break; | |
660 | case 0x44: /* SDRAM_B1CR */ | |
661 | sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000); | |
662 | break; | |
663 | case 0x48: /* SDRAM_B2CR */ | |
664 | sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000); | |
665 | break; | |
666 | case 0x4C: /* SDRAM_B3CR */ | |
667 | sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000); | |
668 | break; | |
669 | case 0x80: /* SDRAM_TR */ | |
670 | sdram->tr = val & 0x018FC01F; | |
671 | break; | |
672 | case 0x94: /* SDRAM_ECCCFG */ | |
673 | sdram->ecccfg = val & 0x00F00000; | |
674 | break; | |
675 | case 0x98: /* SDRAM_ECCESR */ | |
676 | val &= 0xFFF0F000; | |
677 | if (sdram->eccesr == 0 && val != 0) | |
678 | qemu_irq_raise(sdram->irq); | |
679 | else if (sdram->eccesr != 0 && val == 0) | |
680 | qemu_irq_lower(sdram->irq); | |
681 | sdram->eccesr = val; | |
682 | break; | |
683 | default: /* Error */ | |
684 | break; | |
685 | } | |
686 | break; | |
687 | } | |
688 | } | |
689 | ||
690 | static void sdram_reset (void *opaque) | |
691 | { | |
692 | ppc4xx_sdram_t *sdram; | |
693 | ||
694 | sdram = opaque; | |
695 | sdram->addr = 0x00000000; | |
696 | sdram->bear = 0x00000000; | |
697 | sdram->besr0 = 0x00000000; /* No error */ | |
698 | sdram->besr1 = 0x00000000; /* No error */ | |
699 | sdram->cfg = 0x00000000; | |
700 | sdram->ecccfg = 0x00000000; /* No ECC */ | |
701 | sdram->eccesr = 0x00000000; /* No error */ | |
702 | sdram->pmit = 0x07C00000; | |
703 | sdram->rtr = 0x05F00000; | |
704 | sdram->tr = 0x00854009; | |
705 | /* We pre-initialize RAM banks */ | |
706 | sdram->status = 0x00000000; | |
707 | sdram->cfg = 0x00800000; | |
708 | sdram_unmap_bcr(sdram); | |
709 | } | |
710 | ||
711 | void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks, | |
712 | target_phys_addr_t *ram_bases, | |
713 | target_phys_addr_t *ram_sizes, | |
714 | int do_init) | |
715 | { | |
716 | ppc4xx_sdram_t *sdram; | |
717 | ||
718 | sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t)); | |
719 | if (sdram != NULL) { | |
720 | sdram->irq = irq; | |
721 | sdram->nbanks = nbanks; | |
722 | memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t)); | |
723 | memcpy(sdram->ram_bases, ram_bases, | |
724 | nbanks * sizeof(target_phys_addr_t)); | |
725 | memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t)); | |
726 | memcpy(sdram->ram_sizes, ram_sizes, | |
727 | nbanks * sizeof(target_phys_addr_t)); | |
728 | sdram_reset(sdram); | |
729 | qemu_register_reset(&sdram_reset, sdram); | |
730 | ppc_dcr_register(env, SDRAM0_CFGADDR, | |
731 | sdram, &dcr_read_sdram, &dcr_write_sdram); | |
732 | ppc_dcr_register(env, SDRAM0_CFGDATA, | |
733 | sdram, &dcr_read_sdram, &dcr_write_sdram); | |
734 | if (do_init) | |
735 | sdram_map_bcr(sdram); | |
736 | } | |
737 | } | |
738 | ||
739 | /*****************************************************************************/ | |
740 | /* Peripheral controller */ | |
741 | typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; | |
742 | struct ppc4xx_ebc_t { | |
743 | uint32_t addr; | |
744 | uint32_t bcr[8]; | |
745 | uint32_t bap[8]; | |
746 | uint32_t bear; | |
747 | uint32_t besr0; | |
748 | uint32_t besr1; | |
749 | uint32_t cfg; | |
750 | }; | |
751 | ||
752 | enum { | |
753 | EBC0_CFGADDR = 0x012, | |
754 | EBC0_CFGDATA = 0x013, | |
755 | }; | |
756 | ||
757 | static target_ulong dcr_read_ebc (void *opaque, int dcrn) | |
758 | { | |
759 | ppc4xx_ebc_t *ebc; | |
760 | target_ulong ret; | |
761 | ||
762 | ebc = opaque; | |
763 | switch (dcrn) { | |
764 | case EBC0_CFGADDR: | |
765 | ret = ebc->addr; | |
766 | break; | |
767 | case EBC0_CFGDATA: | |
768 | switch (ebc->addr) { | |
769 | case 0x00: /* B0CR */ | |
770 | ret = ebc->bcr[0]; | |
771 | break; | |
772 | case 0x01: /* B1CR */ | |
773 | ret = ebc->bcr[1]; | |
774 | break; | |
775 | case 0x02: /* B2CR */ | |
776 | ret = ebc->bcr[2]; | |
777 | break; | |
778 | case 0x03: /* B3CR */ | |
779 | ret = ebc->bcr[3]; | |
780 | break; | |
781 | case 0x04: /* B4CR */ | |
782 | ret = ebc->bcr[4]; | |
783 | break; | |
784 | case 0x05: /* B5CR */ | |
785 | ret = ebc->bcr[5]; | |
786 | break; | |
787 | case 0x06: /* B6CR */ | |
788 | ret = ebc->bcr[6]; | |
789 | break; | |
790 | case 0x07: /* B7CR */ | |
791 | ret = ebc->bcr[7]; | |
792 | break; | |
793 | case 0x10: /* B0AP */ | |
794 | ret = ebc->bap[0]; | |
795 | break; | |
796 | case 0x11: /* B1AP */ | |
797 | ret = ebc->bap[1]; | |
798 | break; | |
799 | case 0x12: /* B2AP */ | |
800 | ret = ebc->bap[2]; | |
801 | break; | |
802 | case 0x13: /* B3AP */ | |
803 | ret = ebc->bap[3]; | |
804 | break; | |
805 | case 0x14: /* B4AP */ | |
806 | ret = ebc->bap[4]; | |
807 | break; | |
808 | case 0x15: /* B5AP */ | |
809 | ret = ebc->bap[5]; | |
810 | break; | |
811 | case 0x16: /* B6AP */ | |
812 | ret = ebc->bap[6]; | |
813 | break; | |
814 | case 0x17: /* B7AP */ | |
815 | ret = ebc->bap[7]; | |
816 | break; | |
817 | case 0x20: /* BEAR */ | |
818 | ret = ebc->bear; | |
819 | break; | |
820 | case 0x21: /* BESR0 */ | |
821 | ret = ebc->besr0; | |
822 | break; | |
823 | case 0x22: /* BESR1 */ | |
824 | ret = ebc->besr1; | |
825 | break; | |
826 | case 0x23: /* CFG */ | |
827 | ret = ebc->cfg; | |
828 | break; | |
829 | default: | |
830 | ret = 0x00000000; | |
831 | break; | |
832 | } | |
833 | default: | |
834 | ret = 0x00000000; | |
835 | break; | |
836 | } | |
837 | ||
838 | return ret; | |
839 | } | |
840 | ||
841 | static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val) | |
842 | { | |
843 | ppc4xx_ebc_t *ebc; | |
844 | ||
845 | ebc = opaque; | |
846 | switch (dcrn) { | |
847 | case EBC0_CFGADDR: | |
848 | ebc->addr = val; | |
849 | break; | |
850 | case EBC0_CFGDATA: | |
851 | switch (ebc->addr) { | |
852 | case 0x00: /* B0CR */ | |
853 | break; | |
854 | case 0x01: /* B1CR */ | |
855 | break; | |
856 | case 0x02: /* B2CR */ | |
857 | break; | |
858 | case 0x03: /* B3CR */ | |
859 | break; | |
860 | case 0x04: /* B4CR */ | |
861 | break; | |
862 | case 0x05: /* B5CR */ | |
863 | break; | |
864 | case 0x06: /* B6CR */ | |
865 | break; | |
866 | case 0x07: /* B7CR */ | |
867 | break; | |
868 | case 0x10: /* B0AP */ | |
869 | break; | |
870 | case 0x11: /* B1AP */ | |
871 | break; | |
872 | case 0x12: /* B2AP */ | |
873 | break; | |
874 | case 0x13: /* B3AP */ | |
875 | break; | |
876 | case 0x14: /* B4AP */ | |
877 | break; | |
878 | case 0x15: /* B5AP */ | |
879 | break; | |
880 | case 0x16: /* B6AP */ | |
881 | break; | |
882 | case 0x17: /* B7AP */ | |
883 | break; | |
884 | case 0x20: /* BEAR */ | |
885 | break; | |
886 | case 0x21: /* BESR0 */ | |
887 | break; | |
888 | case 0x22: /* BESR1 */ | |
889 | break; | |
890 | case 0x23: /* CFG */ | |
891 | break; | |
892 | default: | |
893 | break; | |
894 | } | |
895 | break; | |
896 | default: | |
897 | break; | |
898 | } | |
899 | } | |
900 | ||
901 | static void ebc_reset (void *opaque) | |
902 | { | |
903 | ppc4xx_ebc_t *ebc; | |
904 | int i; | |
905 | ||
906 | ebc = opaque; | |
907 | ebc->addr = 0x00000000; | |
908 | ebc->bap[0] = 0x7F8FFE80; | |
909 | ebc->bcr[0] = 0xFFE28000; | |
910 | for (i = 0; i < 8; i++) { | |
911 | ebc->bap[i] = 0x00000000; | |
912 | ebc->bcr[i] = 0x00000000; | |
913 | } | |
914 | ebc->besr0 = 0x00000000; | |
915 | ebc->besr1 = 0x00000000; | |
916 | ebc->cfg = 0x80400000; | |
917 | } | |
918 | ||
919 | void ppc405_ebc_init (CPUState *env) | |
920 | { | |
921 | ppc4xx_ebc_t *ebc; | |
922 | ||
923 | ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t)); | |
924 | if (ebc != NULL) { | |
925 | ebc_reset(ebc); | |
926 | qemu_register_reset(&ebc_reset, ebc); | |
927 | ppc_dcr_register(env, EBC0_CFGADDR, | |
928 | ebc, &dcr_read_ebc, &dcr_write_ebc); | |
929 | ppc_dcr_register(env, EBC0_CFGDATA, | |
930 | ebc, &dcr_read_ebc, &dcr_write_ebc); | |
931 | } | |
932 | } | |
933 | ||
934 | /*****************************************************************************/ | |
935 | /* DMA controller */ | |
936 | enum { | |
937 | DMA0_CR0 = 0x100, | |
938 | DMA0_CT0 = 0x101, | |
939 | DMA0_DA0 = 0x102, | |
940 | DMA0_SA0 = 0x103, | |
941 | DMA0_SG0 = 0x104, | |
942 | DMA0_CR1 = 0x108, | |
943 | DMA0_CT1 = 0x109, | |
944 | DMA0_DA1 = 0x10A, | |
945 | DMA0_SA1 = 0x10B, | |
946 | DMA0_SG1 = 0x10C, | |
947 | DMA0_CR2 = 0x110, | |
948 | DMA0_CT2 = 0x111, | |
949 | DMA0_DA2 = 0x112, | |
950 | DMA0_SA2 = 0x113, | |
951 | DMA0_SG2 = 0x114, | |
952 | DMA0_CR3 = 0x118, | |
953 | DMA0_CT3 = 0x119, | |
954 | DMA0_DA3 = 0x11A, | |
955 | DMA0_SA3 = 0x11B, | |
956 | DMA0_SG3 = 0x11C, | |
957 | DMA0_SR = 0x120, | |
958 | DMA0_SGC = 0x123, | |
959 | DMA0_SLP = 0x125, | |
960 | DMA0_POL = 0x126, | |
961 | }; | |
962 | ||
963 | typedef struct ppc405_dma_t ppc405_dma_t; | |
964 | struct ppc405_dma_t { | |
965 | qemu_irq irqs[4]; | |
966 | uint32_t cr[4]; | |
967 | uint32_t ct[4]; | |
968 | uint32_t da[4]; | |
969 | uint32_t sa[4]; | |
970 | uint32_t sg[4]; | |
971 | uint32_t sr; | |
972 | uint32_t sgc; | |
973 | uint32_t slp; | |
974 | uint32_t pol; | |
975 | }; | |
976 | ||
977 | static target_ulong dcr_read_dma (void *opaque, int dcrn) | |
978 | { | |
979 | ppc405_dma_t *dma; | |
980 | ||
981 | dma = opaque; | |
982 | ||
983 | return 0; | |
984 | } | |
985 | ||
986 | static void dcr_write_dma (void *opaque, int dcrn, target_ulong val) | |
987 | { | |
988 | ppc405_dma_t *dma; | |
989 | ||
990 | dma = opaque; | |
991 | } | |
992 | ||
993 | static void ppc405_dma_reset (void *opaque) | |
994 | { | |
995 | ppc405_dma_t *dma; | |
996 | int i; | |
997 | ||
998 | dma = opaque; | |
999 | for (i = 0; i < 4; i++) { | |
1000 | dma->cr[i] = 0x00000000; | |
1001 | dma->ct[i] = 0x00000000; | |
1002 | dma->da[i] = 0x00000000; | |
1003 | dma->sa[i] = 0x00000000; | |
1004 | dma->sg[i] = 0x00000000; | |
1005 | } | |
1006 | dma->sr = 0x00000000; | |
1007 | dma->sgc = 0x00000000; | |
1008 | dma->slp = 0x7C000000; | |
1009 | dma->pol = 0x00000000; | |
1010 | } | |
1011 | ||
1012 | void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]) | |
1013 | { | |
1014 | ppc405_dma_t *dma; | |
1015 | ||
1016 | dma = qemu_mallocz(sizeof(ppc405_dma_t)); | |
1017 | if (dma != NULL) { | |
1018 | memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); | |
1019 | ppc405_dma_reset(dma); | |
1020 | qemu_register_reset(&ppc405_dma_reset, dma); | |
1021 | ppc_dcr_register(env, DMA0_CR0, | |
1022 | dma, &dcr_read_dma, &dcr_write_dma); | |
1023 | ppc_dcr_register(env, DMA0_CT0, | |
1024 | dma, &dcr_read_dma, &dcr_write_dma); | |
1025 | ppc_dcr_register(env, DMA0_DA0, | |
1026 | dma, &dcr_read_dma, &dcr_write_dma); | |
1027 | ppc_dcr_register(env, DMA0_SA0, | |
1028 | dma, &dcr_read_dma, &dcr_write_dma); | |
1029 | ppc_dcr_register(env, DMA0_SG0, | |
1030 | dma, &dcr_read_dma, &dcr_write_dma); | |
1031 | ppc_dcr_register(env, DMA0_CR1, | |
1032 | dma, &dcr_read_dma, &dcr_write_dma); | |
1033 | ppc_dcr_register(env, DMA0_CT1, | |
1034 | dma, &dcr_read_dma, &dcr_write_dma); | |
1035 | ppc_dcr_register(env, DMA0_DA1, | |
1036 | dma, &dcr_read_dma, &dcr_write_dma); | |
1037 | ppc_dcr_register(env, DMA0_SA1, | |
1038 | dma, &dcr_read_dma, &dcr_write_dma); | |
1039 | ppc_dcr_register(env, DMA0_SG1, | |
1040 | dma, &dcr_read_dma, &dcr_write_dma); | |
1041 | ppc_dcr_register(env, DMA0_CR2, | |
1042 | dma, &dcr_read_dma, &dcr_write_dma); | |
1043 | ppc_dcr_register(env, DMA0_CT2, | |
1044 | dma, &dcr_read_dma, &dcr_write_dma); | |
1045 | ppc_dcr_register(env, DMA0_DA2, | |
1046 | dma, &dcr_read_dma, &dcr_write_dma); | |
1047 | ppc_dcr_register(env, DMA0_SA2, | |
1048 | dma, &dcr_read_dma, &dcr_write_dma); | |
1049 | ppc_dcr_register(env, DMA0_SG2, | |
1050 | dma, &dcr_read_dma, &dcr_write_dma); | |
1051 | ppc_dcr_register(env, DMA0_CR3, | |
1052 | dma, &dcr_read_dma, &dcr_write_dma); | |
1053 | ppc_dcr_register(env, DMA0_CT3, | |
1054 | dma, &dcr_read_dma, &dcr_write_dma); | |
1055 | ppc_dcr_register(env, DMA0_DA3, | |
1056 | dma, &dcr_read_dma, &dcr_write_dma); | |
1057 | ppc_dcr_register(env, DMA0_SA3, | |
1058 | dma, &dcr_read_dma, &dcr_write_dma); | |
1059 | ppc_dcr_register(env, DMA0_SG3, | |
1060 | dma, &dcr_read_dma, &dcr_write_dma); | |
1061 | ppc_dcr_register(env, DMA0_SR, | |
1062 | dma, &dcr_read_dma, &dcr_write_dma); | |
1063 | ppc_dcr_register(env, DMA0_SGC, | |
1064 | dma, &dcr_read_dma, &dcr_write_dma); | |
1065 | ppc_dcr_register(env, DMA0_SLP, | |
1066 | dma, &dcr_read_dma, &dcr_write_dma); | |
1067 | ppc_dcr_register(env, DMA0_POL, | |
1068 | dma, &dcr_read_dma, &dcr_write_dma); | |
1069 | } | |
1070 | } | |
1071 | ||
1072 | /*****************************************************************************/ | |
1073 | /* GPIO */ | |
1074 | typedef struct ppc405_gpio_t ppc405_gpio_t; | |
1075 | struct ppc405_gpio_t { | |
1076 | target_phys_addr_t base; | |
1077 | uint32_t or; | |
1078 | uint32_t tcr; | |
1079 | uint32_t osrh; | |
1080 | uint32_t osrl; | |
1081 | uint32_t tsrh; | |
1082 | uint32_t tsrl; | |
1083 | uint32_t odr; | |
1084 | uint32_t ir; | |
1085 | uint32_t rr1; | |
1086 | uint32_t isr1h; | |
1087 | uint32_t isr1l; | |
1088 | }; | |
1089 | ||
1090 | static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr) | |
1091 | { | |
1092 | ppc405_gpio_t *gpio; | |
1093 | ||
1094 | gpio = opaque; | |
1095 | #ifdef DEBUG_GPIO | |
1096 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
1097 | #endif | |
1098 | ||
1099 | return 0; | |
1100 | } | |
1101 | ||
1102 | static void ppc405_gpio_writeb (void *opaque, | |
1103 | target_phys_addr_t addr, uint32_t value) | |
1104 | { | |
1105 | ppc405_gpio_t *gpio; | |
1106 | ||
1107 | gpio = opaque; | |
1108 | #ifdef DEBUG_GPIO | |
1109 | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); | |
1110 | #endif | |
1111 | } | |
1112 | ||
1113 | static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr) | |
1114 | { | |
1115 | ppc405_gpio_t *gpio; | |
1116 | ||
1117 | gpio = opaque; | |
1118 | #ifdef DEBUG_GPIO | |
1119 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
1120 | #endif | |
1121 | ||
1122 | return 0; | |
1123 | } | |
1124 | ||
1125 | static void ppc405_gpio_writew (void *opaque, | |
1126 | target_phys_addr_t addr, uint32_t value) | |
1127 | { | |
1128 | ppc405_gpio_t *gpio; | |
1129 | ||
1130 | gpio = opaque; | |
1131 | #ifdef DEBUG_GPIO | |
1132 | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); | |
1133 | #endif | |
1134 | } | |
1135 | ||
1136 | static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr) | |
1137 | { | |
1138 | ppc405_gpio_t *gpio; | |
1139 | ||
1140 | gpio = opaque; | |
1141 | #ifdef DEBUG_GPIO | |
1142 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
1143 | #endif | |
1144 | ||
1145 | return 0; | |
1146 | } | |
1147 | ||
1148 | static void ppc405_gpio_writel (void *opaque, | |
1149 | target_phys_addr_t addr, uint32_t value) | |
1150 | { | |
1151 | ppc405_gpio_t *gpio; | |
1152 | ||
1153 | gpio = opaque; | |
1154 | #ifdef DEBUG_GPIO | |
1155 | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); | |
1156 | #endif | |
1157 | } | |
1158 | ||
1159 | static CPUReadMemoryFunc *ppc405_gpio_read[] = { | |
1160 | &ppc405_gpio_readb, | |
1161 | &ppc405_gpio_readw, | |
1162 | &ppc405_gpio_readl, | |
1163 | }; | |
1164 | ||
1165 | static CPUWriteMemoryFunc *ppc405_gpio_write[] = { | |
1166 | &ppc405_gpio_writeb, | |
1167 | &ppc405_gpio_writew, | |
1168 | &ppc405_gpio_writel, | |
1169 | }; | |
1170 | ||
1171 | static void ppc405_gpio_reset (void *opaque) | |
1172 | { | |
1173 | ppc405_gpio_t *gpio; | |
1174 | ||
1175 | gpio = opaque; | |
1176 | } | |
1177 | ||
1178 | void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio, | |
1179 | target_phys_addr_t offset) | |
1180 | { | |
1181 | ppc405_gpio_t *gpio; | |
1182 | ||
1183 | gpio = qemu_mallocz(sizeof(ppc405_gpio_t)); | |
1184 | if (gpio != NULL) { | |
1185 | gpio->base = offset; | |
1186 | ppc405_gpio_reset(gpio); | |
1187 | qemu_register_reset(&ppc405_gpio_reset, gpio); | |
1188 | #ifdef DEBUG_GPIO | |
1189 | printf("%s: offset=" PADDRX "\n", __func__, offset); | |
1190 | #endif | |
1191 | ppc4xx_mmio_register(env, mmio, offset, 0x038, | |
1192 | ppc405_gpio_read, ppc405_gpio_write, gpio); | |
1193 | } | |
1194 | } | |
1195 | ||
1196 | /*****************************************************************************/ | |
1197 | /* Serial ports */ | |
1198 | static CPUReadMemoryFunc *serial_mm_read[] = { | |
1199 | &serial_mm_readb, | |
1200 | &serial_mm_readw, | |
1201 | &serial_mm_readl, | |
1202 | }; | |
1203 | ||
1204 | static CPUWriteMemoryFunc *serial_mm_write[] = { | |
1205 | &serial_mm_writeb, | |
1206 | &serial_mm_writew, | |
1207 | &serial_mm_writel, | |
1208 | }; | |
1209 | ||
1210 | void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio, | |
1211 | target_phys_addr_t offset, qemu_irq irq, | |
1212 | CharDriverState *chr) | |
1213 | { | |
1214 | void *serial; | |
1215 | ||
1216 | #ifdef DEBUG_SERIAL | |
1217 | printf("%s: offset=" PADDRX "\n", __func__, offset); | |
1218 | #endif | |
1219 | serial = serial_mm_init(offset, 0, irq, chr, 0); | |
1220 | ppc4xx_mmio_register(env, mmio, offset, 0x008, | |
1221 | serial_mm_read, serial_mm_write, serial); | |
1222 | } | |
1223 | ||
1224 | /*****************************************************************************/ | |
1225 | /* On Chip Memory */ | |
1226 | enum { | |
1227 | OCM0_ISARC = 0x018, | |
1228 | OCM0_ISACNTL = 0x019, | |
1229 | OCM0_DSARC = 0x01A, | |
1230 | OCM0_DSACNTL = 0x01B, | |
1231 | }; | |
1232 | ||
1233 | typedef struct ppc405_ocm_t ppc405_ocm_t; | |
1234 | struct ppc405_ocm_t { | |
1235 | target_ulong offset; | |
1236 | uint32_t isarc; | |
1237 | uint32_t isacntl; | |
1238 | uint32_t dsarc; | |
1239 | uint32_t dsacntl; | |
1240 | }; | |
1241 | ||
1242 | static void ocm_update_mappings (ppc405_ocm_t *ocm, | |
1243 | uint32_t isarc, uint32_t isacntl, | |
1244 | uint32_t dsarc, uint32_t dsacntl) | |
1245 | { | |
1246 | #ifdef DEBUG_OCM | |
1247 | printf("OCM update ISA %08x %08x (%08x %08x) DSA %08x %08x (%08x %08x)\n", | |
1248 | isarc, isacntl, dsarc, dsacntl, | |
1249 | ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); | |
1250 | #endif | |
1251 | if (ocm->isarc != isarc || | |
1252 | (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { | |
1253 | if (ocm->isacntl & 0x80000000) { | |
1254 | /* Unmap previously assigned memory region */ | |
1255 | printf("OCM unmap ISA %08x\n", ocm->isarc); | |
1256 | cpu_register_physical_memory(ocm->isarc, 0x04000000, | |
1257 | IO_MEM_UNASSIGNED); | |
1258 | } | |
1259 | if (isacntl & 0x80000000) { | |
1260 | /* Map new instruction memory region */ | |
1261 | #ifdef DEBUG_OCM | |
1262 | printf("OCM map ISA %08x\n", isarc); | |
1263 | #endif | |
1264 | cpu_register_physical_memory(isarc, 0x04000000, | |
1265 | ocm->offset | IO_MEM_RAM); | |
1266 | } | |
1267 | } | |
1268 | if (ocm->dsarc != dsarc || | |
1269 | (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { | |
1270 | if (ocm->dsacntl & 0x80000000) { | |
1271 | /* Beware not to unmap the region we just mapped */ | |
1272 | if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { | |
1273 | /* Unmap previously assigned memory region */ | |
1274 | #ifdef DEBUG_OCM | |
1275 | printf("OCM unmap DSA %08x\n", ocm->dsarc); | |
1276 | #endif | |
1277 | cpu_register_physical_memory(ocm->dsarc, 0x04000000, | |
1278 | IO_MEM_UNASSIGNED); | |
1279 | } | |
1280 | } | |
1281 | if (dsacntl & 0x80000000) { | |
1282 | /* Beware not to remap the region we just mapped */ | |
1283 | if (!(isacntl & 0x80000000) || dsarc != isarc) { | |
1284 | /* Map new data memory region */ | |
1285 | #ifdef DEBUG_OCM | |
1286 | printf("OCM map DSA %08x\n", dsarc); | |
1287 | #endif | |
1288 | cpu_register_physical_memory(dsarc, 0x04000000, | |
1289 | ocm->offset | IO_MEM_RAM); | |
1290 | } | |
1291 | } | |
1292 | } | |
1293 | } | |
1294 | ||
1295 | static target_ulong dcr_read_ocm (void *opaque, int dcrn) | |
1296 | { | |
1297 | ppc405_ocm_t *ocm; | |
1298 | target_ulong ret; | |
1299 | ||
1300 | ocm = opaque; | |
1301 | switch (dcrn) { | |
1302 | case OCM0_ISARC: | |
1303 | ret = ocm->isarc; | |
1304 | break; | |
1305 | case OCM0_ISACNTL: | |
1306 | ret = ocm->isacntl; | |
1307 | break; | |
1308 | case OCM0_DSARC: | |
1309 | ret = ocm->dsarc; | |
1310 | break; | |
1311 | case OCM0_DSACNTL: | |
1312 | ret = ocm->dsacntl; | |
1313 | break; | |
1314 | default: | |
1315 | ret = 0; | |
1316 | break; | |
1317 | } | |
1318 | ||
1319 | return ret; | |
1320 | } | |
1321 | ||
1322 | static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val) | |
1323 | { | |
1324 | ppc405_ocm_t *ocm; | |
1325 | uint32_t isarc, dsarc, isacntl, dsacntl; | |
1326 | ||
1327 | ocm = opaque; | |
1328 | isarc = ocm->isarc; | |
1329 | dsarc = ocm->dsarc; | |
1330 | isacntl = ocm->isacntl; | |
1331 | dsacntl = ocm->dsacntl; | |
1332 | switch (dcrn) { | |
1333 | case OCM0_ISARC: | |
1334 | isarc = val & 0xFC000000; | |
1335 | break; | |
1336 | case OCM0_ISACNTL: | |
1337 | isacntl = val & 0xC0000000; | |
1338 | break; | |
1339 | case OCM0_DSARC: | |
1340 | isarc = val & 0xFC000000; | |
1341 | break; | |
1342 | case OCM0_DSACNTL: | |
1343 | isacntl = val & 0xC0000000; | |
1344 | break; | |
1345 | } | |
1346 | ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); | |
1347 | ocm->isarc = isarc; | |
1348 | ocm->dsarc = dsarc; | |
1349 | ocm->isacntl = isacntl; | |
1350 | ocm->dsacntl = dsacntl; | |
1351 | } | |
1352 | ||
1353 | static void ocm_reset (void *opaque) | |
1354 | { | |
1355 | ppc405_ocm_t *ocm; | |
1356 | uint32_t isarc, dsarc, isacntl, dsacntl; | |
1357 | ||
1358 | ocm = opaque; | |
1359 | isarc = 0x00000000; | |
1360 | isacntl = 0x00000000; | |
1361 | dsarc = 0x00000000; | |
1362 | dsacntl = 0x00000000; | |
1363 | ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); | |
1364 | ocm->isarc = isarc; | |
1365 | ocm->dsarc = dsarc; | |
1366 | ocm->isacntl = isacntl; | |
1367 | ocm->dsacntl = dsacntl; | |
1368 | } | |
1369 | ||
1370 | void ppc405_ocm_init (CPUState *env, unsigned long offset) | |
1371 | { | |
1372 | ppc405_ocm_t *ocm; | |
1373 | ||
1374 | ocm = qemu_mallocz(sizeof(ppc405_ocm_t)); | |
1375 | if (ocm != NULL) { | |
1376 | ocm->offset = offset; | |
1377 | ocm_reset(ocm); | |
1378 | qemu_register_reset(&ocm_reset, ocm); | |
1379 | ppc_dcr_register(env, OCM0_ISARC, | |
1380 | ocm, &dcr_read_ocm, &dcr_write_ocm); | |
1381 | ppc_dcr_register(env, OCM0_ISACNTL, | |
1382 | ocm, &dcr_read_ocm, &dcr_write_ocm); | |
1383 | ppc_dcr_register(env, OCM0_DSARC, | |
1384 | ocm, &dcr_read_ocm, &dcr_write_ocm); | |
1385 | ppc_dcr_register(env, OCM0_DSACNTL, | |
1386 | ocm, &dcr_read_ocm, &dcr_write_ocm); | |
1387 | } | |
1388 | } | |
1389 | ||
1390 | /*****************************************************************************/ | |
1391 | /* I2C controller */ | |
1392 | typedef struct ppc4xx_i2c_t ppc4xx_i2c_t; | |
1393 | struct ppc4xx_i2c_t { | |
1394 | target_phys_addr_t base; | |
1395 | qemu_irq irq; | |
1396 | uint8_t mdata; | |
1397 | uint8_t lmadr; | |
1398 | uint8_t hmadr; | |
1399 | uint8_t cntl; | |
1400 | uint8_t mdcntl; | |
1401 | uint8_t sts; | |
1402 | uint8_t extsts; | |
1403 | uint8_t sdata; | |
1404 | uint8_t lsadr; | |
1405 | uint8_t hsadr; | |
1406 | uint8_t clkdiv; | |
1407 | uint8_t intrmsk; | |
1408 | uint8_t xfrcnt; | |
1409 | uint8_t xtcntlss; | |
1410 | uint8_t directcntl; | |
1411 | }; | |
1412 | ||
1413 | static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr) | |
1414 | { | |
1415 | ppc4xx_i2c_t *i2c; | |
1416 | uint32_t ret; | |
1417 | ||
1418 | #ifdef DEBUG_I2C | |
1419 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
1420 | #endif | |
1421 | i2c = opaque; | |
1422 | switch (addr - i2c->base) { | |
1423 | case 0x00: | |
1424 | // i2c_readbyte(&i2c->mdata); | |
1425 | ret = i2c->mdata; | |
1426 | break; | |
1427 | case 0x02: | |
1428 | ret = i2c->sdata; | |
1429 | break; | |
1430 | case 0x04: | |
1431 | ret = i2c->lmadr; | |
1432 | break; | |
1433 | case 0x05: | |
1434 | ret = i2c->hmadr; | |
1435 | break; | |
1436 | case 0x06: | |
1437 | ret = i2c->cntl; | |
1438 | break; | |
1439 | case 0x07: | |
1440 | ret = i2c->mdcntl; | |
1441 | break; | |
1442 | case 0x08: | |
1443 | ret = i2c->sts; | |
1444 | break; | |
1445 | case 0x09: | |
1446 | ret = i2c->extsts; | |
1447 | break; | |
1448 | case 0x0A: | |
1449 | ret = i2c->lsadr; | |
1450 | break; | |
1451 | case 0x0B: | |
1452 | ret = i2c->hsadr; | |
1453 | break; | |
1454 | case 0x0C: | |
1455 | ret = i2c->clkdiv; | |
1456 | break; | |
1457 | case 0x0D: | |
1458 | ret = i2c->intrmsk; | |
1459 | break; | |
1460 | case 0x0E: | |
1461 | ret = i2c->xfrcnt; | |
1462 | break; | |
1463 | case 0x0F: | |
1464 | ret = i2c->xtcntlss; | |
1465 | break; | |
1466 | case 0x10: | |
1467 | ret = i2c->directcntl; | |
1468 | break; | |
1469 | default: | |
1470 | ret = 0x00; | |
1471 | break; | |
1472 | } | |
1473 | #ifdef DEBUG_I2C | |
1474 | printf("%s: addr " PADDRX " %02x\n", __func__, addr, ret); | |
1475 | #endif | |
1476 | ||
1477 | return ret; | |
1478 | } | |
1479 | ||
1480 | static void ppc4xx_i2c_writeb (void *opaque, | |
1481 | target_phys_addr_t addr, uint32_t value) | |
1482 | { | |
1483 | ppc4xx_i2c_t *i2c; | |
1484 | ||
1485 | #ifdef DEBUG_I2C | |
1486 | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); | |
1487 | #endif | |
1488 | i2c = opaque; | |
1489 | switch (addr - i2c->base) { | |
1490 | case 0x00: | |
1491 | i2c->mdata = value; | |
1492 | // i2c_sendbyte(&i2c->mdata); | |
1493 | break; | |
1494 | case 0x02: | |
1495 | i2c->sdata = value; | |
1496 | break; | |
1497 | case 0x04: | |
1498 | i2c->lmadr = value; | |
1499 | break; | |
1500 | case 0x05: | |
1501 | i2c->hmadr = value; | |
1502 | break; | |
1503 | case 0x06: | |
1504 | i2c->cntl = value; | |
1505 | break; | |
1506 | case 0x07: | |
1507 | i2c->mdcntl = value & 0xDF; | |
1508 | break; | |
1509 | case 0x08: | |
1510 | i2c->sts &= ~(value & 0x0A); | |
1511 | break; | |
1512 | case 0x09: | |
1513 | i2c->extsts &= ~(value & 0x8F); | |
1514 | break; | |
1515 | case 0x0A: | |
1516 | i2c->lsadr = value; | |
1517 | break; | |
1518 | case 0x0B: | |
1519 | i2c->hsadr = value; | |
1520 | break; | |
1521 | case 0x0C: | |
1522 | i2c->clkdiv = value; | |
1523 | break; | |
1524 | case 0x0D: | |
1525 | i2c->intrmsk = value; | |
1526 | break; | |
1527 | case 0x0E: | |
1528 | i2c->xfrcnt = value & 0x77; | |
1529 | break; | |
1530 | case 0x0F: | |
1531 | i2c->xtcntlss = value; | |
1532 | break; | |
1533 | case 0x10: | |
1534 | i2c->directcntl = value & 0x7; | |
1535 | break; | |
1536 | } | |
1537 | } | |
1538 | ||
1539 | static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr) | |
1540 | { | |
1541 | uint32_t ret; | |
1542 | ||
1543 | #ifdef DEBUG_I2C | |
1544 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
1545 | #endif | |
1546 | ret = ppc4xx_i2c_readb(opaque, addr) << 8; | |
1547 | ret |= ppc4xx_i2c_readb(opaque, addr + 1); | |
1548 | ||
1549 | return ret; | |
1550 | } | |
1551 | ||
1552 | static void ppc4xx_i2c_writew (void *opaque, | |
1553 | target_phys_addr_t addr, uint32_t value) | |
1554 | { | |
1555 | #ifdef DEBUG_I2C | |
1556 | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); | |
1557 | #endif | |
1558 | ppc4xx_i2c_writeb(opaque, addr, value >> 8); | |
1559 | ppc4xx_i2c_writeb(opaque, addr + 1, value); | |
1560 | } | |
1561 | ||
1562 | static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr) | |
1563 | { | |
1564 | uint32_t ret; | |
1565 | ||
1566 | #ifdef DEBUG_I2C | |
1567 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
1568 | #endif | |
1569 | ret = ppc4xx_i2c_readb(opaque, addr) << 24; | |
1570 | ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16; | |
1571 | ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8; | |
1572 | ret |= ppc4xx_i2c_readb(opaque, addr + 3); | |
1573 | ||
1574 | return ret; | |
1575 | } | |
1576 | ||
1577 | static void ppc4xx_i2c_writel (void *opaque, | |
1578 | target_phys_addr_t addr, uint32_t value) | |
1579 | { | |
1580 | #ifdef DEBUG_I2C | |
1581 | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); | |
1582 | #endif | |
1583 | ppc4xx_i2c_writeb(opaque, addr, value >> 24); | |
1584 | ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16); | |
1585 | ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8); | |
1586 | ppc4xx_i2c_writeb(opaque, addr + 3, value); | |
1587 | } | |
1588 | ||
1589 | static CPUReadMemoryFunc *i2c_read[] = { | |
1590 | &ppc4xx_i2c_readb, | |
1591 | &ppc4xx_i2c_readw, | |
1592 | &ppc4xx_i2c_readl, | |
1593 | }; | |
1594 | ||
1595 | static CPUWriteMemoryFunc *i2c_write[] = { | |
1596 | &ppc4xx_i2c_writeb, | |
1597 | &ppc4xx_i2c_writew, | |
1598 | &ppc4xx_i2c_writel, | |
1599 | }; | |
1600 | ||
1601 | static void ppc4xx_i2c_reset (void *opaque) | |
1602 | { | |
1603 | ppc4xx_i2c_t *i2c; | |
1604 | ||
1605 | i2c = opaque; | |
1606 | i2c->mdata = 0x00; | |
1607 | i2c->sdata = 0x00; | |
1608 | i2c->cntl = 0x00; | |
1609 | i2c->mdcntl = 0x00; | |
1610 | i2c->sts = 0x00; | |
1611 | i2c->extsts = 0x00; | |
1612 | i2c->clkdiv = 0x00; | |
1613 | i2c->xfrcnt = 0x00; | |
1614 | i2c->directcntl = 0x0F; | |
1615 | } | |
1616 | ||
1617 | void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio, | |
1618 | target_phys_addr_t offset, qemu_irq irq) | |
1619 | { | |
1620 | ppc4xx_i2c_t *i2c; | |
1621 | ||
1622 | i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t)); | |
1623 | if (i2c != NULL) { | |
1624 | i2c->base = offset; | |
1625 | i2c->irq = irq; | |
1626 | ppc4xx_i2c_reset(i2c); | |
1627 | #ifdef DEBUG_I2C | |
1628 | printf("%s: offset=" PADDRX "\n", __func__, offset); | |
1629 | #endif | |
1630 | ppc4xx_mmio_register(env, mmio, offset, 0x011, | |
1631 | i2c_read, i2c_write, i2c); | |
1632 | qemu_register_reset(ppc4xx_i2c_reset, i2c); | |
1633 | } | |
1634 | } | |
1635 | ||
1636 | /*****************************************************************************/ | |
1637 | /* General purpose timers */ | |
1638 | typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; | |
1639 | struct ppc4xx_gpt_t { | |
1640 | target_phys_addr_t base; | |
1641 | int64_t tb_offset; | |
1642 | uint32_t tb_freq; | |
1643 | struct QEMUTimer *timer; | |
1644 | qemu_irq irqs[5]; | |
1645 | uint32_t oe; | |
1646 | uint32_t ol; | |
1647 | uint32_t im; | |
1648 | uint32_t is; | |
1649 | uint32_t ie; | |
1650 | uint32_t comp[5]; | |
1651 | uint32_t mask[5]; | |
1652 | }; | |
1653 | ||
1654 | static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr) | |
1655 | { | |
1656 | #ifdef DEBUG_GPT | |
1657 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
1658 | #endif | |
1659 | /* XXX: generate a bus fault */ | |
1660 | return -1; | |
1661 | } | |
1662 | ||
1663 | static void ppc4xx_gpt_writeb (void *opaque, | |
1664 | target_phys_addr_t addr, uint32_t value) | |
1665 | { | |
1666 | #ifdef DEBUG_I2C | |
1667 | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); | |
1668 | #endif | |
1669 | /* XXX: generate a bus fault */ | |
1670 | } | |
1671 | ||
1672 | static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr) | |
1673 | { | |
1674 | #ifdef DEBUG_GPT | |
1675 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
1676 | #endif | |
1677 | /* XXX: generate a bus fault */ | |
1678 | return -1; | |
1679 | } | |
1680 | ||
1681 | static void ppc4xx_gpt_writew (void *opaque, | |
1682 | target_phys_addr_t addr, uint32_t value) | |
1683 | { | |
1684 | #ifdef DEBUG_I2C | |
1685 | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); | |
1686 | #endif | |
1687 | /* XXX: generate a bus fault */ | |
1688 | } | |
1689 | ||
1690 | static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) | |
1691 | { | |
1692 | /* XXX: TODO */ | |
1693 | return 0; | |
1694 | } | |
1695 | ||
1696 | static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) | |
1697 | { | |
1698 | /* XXX: TODO */ | |
1699 | } | |
1700 | ||
1701 | static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) | |
1702 | { | |
1703 | uint32_t mask; | |
1704 | int i; | |
1705 | ||
1706 | mask = 0x80000000; | |
1707 | for (i = 0; i < 5; i++) { | |
1708 | if (gpt->oe & mask) { | |
1709 | /* Output is enabled */ | |
1710 | if (ppc4xx_gpt_compare(gpt, i)) { | |
1711 | /* Comparison is OK */ | |
1712 | ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); | |
1713 | } else { | |
1714 | /* Comparison is KO */ | |
1715 | ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); | |
1716 | } | |
1717 | } | |
1718 | mask = mask >> 1; | |
1719 | } | |
1720 | } | |
1721 | ||
1722 | static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) | |
1723 | { | |
1724 | uint32_t mask; | |
1725 | int i; | |
1726 | ||
1727 | mask = 0x00008000; | |
1728 | for (i = 0; i < 5; i++) { | |
1729 | if (gpt->is & gpt->im & mask) | |
1730 | qemu_irq_raise(gpt->irqs[i]); | |
1731 | else | |
1732 | qemu_irq_lower(gpt->irqs[i]); | |
1733 | mask = mask >> 1; | |
1734 | } | |
1735 | } | |
1736 | ||
1737 | static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) | |
1738 | { | |
1739 | /* XXX: TODO */ | |
1740 | } | |
1741 | ||
1742 | static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr) | |
1743 | { | |
1744 | ppc4xx_gpt_t *gpt; | |
1745 | uint32_t ret; | |
1746 | int idx; | |
1747 | ||
1748 | #ifdef DEBUG_GPT | |
1749 | printf("%s: addr " PADDRX "\n", __func__, addr); | |
1750 | #endif | |
1751 | gpt = opaque; | |
1752 | switch (addr - gpt->base) { | |
1753 | case 0x00: | |
1754 | /* Time base counter */ | |
1755 | ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset, | |
1756 | gpt->tb_freq, ticks_per_sec); | |
1757 | break; | |
1758 | case 0x10: | |
1759 | /* Output enable */ | |
1760 | ret = gpt->oe; | |
1761 | break; | |
1762 | case 0x14: | |
1763 | /* Output level */ | |
1764 | ret = gpt->ol; | |
1765 | break; | |
1766 | case 0x18: | |
1767 | /* Interrupt mask */ | |
1768 | ret = gpt->im; | |
1769 | break; | |
1770 | case 0x1C: | |
1771 | case 0x20: | |
1772 | /* Interrupt status */ | |
1773 | ret = gpt->is; | |
1774 | break; | |
1775 | case 0x24: | |
1776 | /* Interrupt enable */ | |
1777 | ret = gpt->ie; | |
1778 | break; | |
1779 | case 0x80 ... 0x90: | |
1780 | /* Compare timer */ | |
1781 | idx = ((addr - gpt->base) - 0x80) >> 2; | |
1782 | ret = gpt->comp[idx]; | |
1783 | break; | |
1784 | case 0xC0 ... 0xD0: | |
1785 | /* Compare mask */ | |
1786 | idx = ((addr - gpt->base) - 0xC0) >> 2; | |
1787 | ret = gpt->mask[idx]; | |
1788 | break; | |
1789 | default: | |
1790 | ret = -1; | |
1791 | break; | |
1792 | } | |
1793 | ||
1794 | return ret; | |
1795 | } | |
1796 | ||
1797 | static void ppc4xx_gpt_writel (void *opaque, | |
1798 | target_phys_addr_t addr, uint32_t value) | |
1799 | { | |
1800 | ppc4xx_gpt_t *gpt; | |
1801 | int idx; | |
1802 | ||
1803 | #ifdef DEBUG_I2C | |
1804 | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); | |
1805 | #endif | |
1806 | gpt = opaque; | |
1807 | switch (addr - gpt->base) { | |
1808 | case 0x00: | |
1809 | /* Time base counter */ | |
1810 | gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq) | |
1811 | - qemu_get_clock(vm_clock); | |
1812 | ppc4xx_gpt_compute_timer(gpt); | |
1813 | break; | |
1814 | case 0x10: | |
1815 | /* Output enable */ | |
1816 | gpt->oe = value & 0xF8000000; | |
1817 | ppc4xx_gpt_set_outputs(gpt); | |
1818 | break; | |
1819 | case 0x14: | |
1820 | /* Output level */ | |
1821 | gpt->ol = value & 0xF8000000; | |
1822 | ppc4xx_gpt_set_outputs(gpt); | |
1823 | break; | |
1824 | case 0x18: | |
1825 | /* Interrupt mask */ | |
1826 | gpt->im = value & 0x0000F800; | |
1827 | break; | |
1828 | case 0x1C: | |
1829 | /* Interrupt status set */ | |
1830 | gpt->is |= value & 0x0000F800; | |
1831 | ppc4xx_gpt_set_irqs(gpt); | |
1832 | break; | |
1833 | case 0x20: | |
1834 | /* Interrupt status clear */ | |
1835 | gpt->is &= ~(value & 0x0000F800); | |
1836 | ppc4xx_gpt_set_irqs(gpt); | |
1837 | break; | |
1838 | case 0x24: | |
1839 | /* Interrupt enable */ | |
1840 | gpt->ie = value & 0x0000F800; | |
1841 | ppc4xx_gpt_set_irqs(gpt); | |
1842 | break; | |
1843 | case 0x80 ... 0x90: | |
1844 | /* Compare timer */ | |
1845 | idx = ((addr - gpt->base) - 0x80) >> 2; | |
1846 | gpt->comp[idx] = value & 0xF8000000; | |
1847 | ppc4xx_gpt_compute_timer(gpt); | |
1848 | break; | |
1849 | case 0xC0 ... 0xD0: | |
1850 | /* Compare mask */ | |
1851 | idx = ((addr - gpt->base) - 0xC0) >> 2; | |
1852 | gpt->mask[idx] = value & 0xF8000000; | |
1853 | ppc4xx_gpt_compute_timer(gpt); | |
1854 | break; | |
1855 | } | |
1856 | } | |
1857 | ||
1858 | static CPUReadMemoryFunc *gpt_read[] = { | |
1859 | &ppc4xx_gpt_readb, | |
1860 | &ppc4xx_gpt_readw, | |
1861 | &ppc4xx_gpt_readl, | |
1862 | }; | |
1863 | ||
1864 | static CPUWriteMemoryFunc *gpt_write[] = { | |
1865 | &ppc4xx_gpt_writeb, | |
1866 | &ppc4xx_gpt_writew, | |
1867 | &ppc4xx_gpt_writel, | |
1868 | }; | |
1869 | ||
1870 | static void ppc4xx_gpt_cb (void *opaque) | |
1871 | { | |
1872 | ppc4xx_gpt_t *gpt; | |
1873 | ||
1874 | gpt = opaque; | |
1875 | ppc4xx_gpt_set_irqs(gpt); | |
1876 | ppc4xx_gpt_set_outputs(gpt); | |
1877 | ppc4xx_gpt_compute_timer(gpt); | |
1878 | } | |
1879 | ||
1880 | static void ppc4xx_gpt_reset (void *opaque) | |
1881 | { | |
1882 | ppc4xx_gpt_t *gpt; | |
1883 | int i; | |
1884 | ||
1885 | gpt = opaque; | |
1886 | qemu_del_timer(gpt->timer); | |
1887 | gpt->oe = 0x00000000; | |
1888 | gpt->ol = 0x00000000; | |
1889 | gpt->im = 0x00000000; | |
1890 | gpt->is = 0x00000000; | |
1891 | gpt->ie = 0x00000000; | |
1892 | for (i = 0; i < 5; i++) { | |
1893 | gpt->comp[i] = 0x00000000; | |
1894 | gpt->mask[i] = 0x00000000; | |
1895 | } | |
1896 | } | |
1897 | ||
1898 | void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio, | |
1899 | target_phys_addr_t offset, qemu_irq irqs[5]) | |
1900 | { | |
1901 | ppc4xx_gpt_t *gpt; | |
1902 | int i; | |
1903 | ||
1904 | gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t)); | |
1905 | if (gpt != NULL) { | |
1906 | gpt->base = offset; | |
1907 | for (i = 0; i < 5; i++) | |
1908 | gpt->irqs[i] = irqs[i]; | |
1909 | gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt); | |
1910 | ppc4xx_gpt_reset(gpt); | |
1911 | #ifdef DEBUG_GPT | |
1912 | printf("%s: offset=" PADDRX "\n", __func__, offset); | |
1913 | #endif | |
1914 | ppc4xx_mmio_register(env, mmio, offset, 0x0D4, | |
1915 | gpt_read, gpt_write, gpt); | |
1916 | qemu_register_reset(ppc4xx_gpt_reset, gpt); | |
1917 | } | |
1918 | } | |
1919 | ||
1920 | /*****************************************************************************/ | |
1921 | /* MAL */ | |
1922 | enum { | |
1923 | MAL0_CFG = 0x180, | |
1924 | MAL0_ESR = 0x181, | |
1925 | MAL0_IER = 0x182, | |
1926 | MAL0_TXCASR = 0x184, | |
1927 | MAL0_TXCARR = 0x185, | |
1928 | MAL0_TXEOBISR = 0x186, | |
1929 | MAL0_TXDEIR = 0x187, | |
1930 | MAL0_RXCASR = 0x190, | |
1931 | MAL0_RXCARR = 0x191, | |
1932 | MAL0_RXEOBISR = 0x192, | |
1933 | MAL0_RXDEIR = 0x193, | |
1934 | MAL0_TXCTP0R = 0x1A0, | |
1935 | MAL0_TXCTP1R = 0x1A1, | |
1936 | MAL0_TXCTP2R = 0x1A2, | |
1937 | MAL0_TXCTP3R = 0x1A3, | |
1938 | MAL0_RXCTP0R = 0x1C0, | |
1939 | MAL0_RXCTP1R = 0x1C1, | |
1940 | MAL0_RCBS0 = 0x1E0, | |
1941 | MAL0_RCBS1 = 0x1E1, | |
1942 | }; | |
1943 | ||
1944 | typedef struct ppc40x_mal_t ppc40x_mal_t; | |
1945 | struct ppc40x_mal_t { | |
1946 | qemu_irq irqs[4]; | |
1947 | uint32_t cfg; | |
1948 | uint32_t esr; | |
1949 | uint32_t ier; | |
1950 | uint32_t txcasr; | |
1951 | uint32_t txcarr; | |
1952 | uint32_t txeobisr; | |
1953 | uint32_t txdeir; | |
1954 | uint32_t rxcasr; | |
1955 | uint32_t rxcarr; | |
1956 | uint32_t rxeobisr; | |
1957 | uint32_t rxdeir; | |
1958 | uint32_t txctpr[4]; | |
1959 | uint32_t rxctpr[2]; | |
1960 | uint32_t rcbs[2]; | |
1961 | }; | |
1962 | ||
1963 | static void ppc40x_mal_reset (void *opaque); | |
1964 | ||
1965 | static target_ulong dcr_read_mal (void *opaque, int dcrn) | |
1966 | { | |
1967 | ppc40x_mal_t *mal; | |
1968 | target_ulong ret; | |
1969 | ||
1970 | mal = opaque; | |
1971 | switch (dcrn) { | |
1972 | case MAL0_CFG: | |
1973 | ret = mal->cfg; | |
1974 | break; | |
1975 | case MAL0_ESR: | |
1976 | ret = mal->esr; | |
1977 | break; | |
1978 | case MAL0_IER: | |
1979 | ret = mal->ier; | |
1980 | break; | |
1981 | case MAL0_TXCASR: | |
1982 | ret = mal->txcasr; | |
1983 | break; | |
1984 | case MAL0_TXCARR: | |
1985 | ret = mal->txcarr; | |
1986 | break; | |
1987 | case MAL0_TXEOBISR: | |
1988 | ret = mal->txeobisr; | |
1989 | break; | |
1990 | case MAL0_TXDEIR: | |
1991 | ret = mal->txdeir; | |
1992 | break; | |
1993 | case MAL0_RXCASR: | |
1994 | ret = mal->rxcasr; | |
1995 | break; | |
1996 | case MAL0_RXCARR: | |
1997 | ret = mal->rxcarr; | |
1998 | break; | |
1999 | case MAL0_RXEOBISR: | |
2000 | ret = mal->rxeobisr; | |
2001 | break; | |
2002 | case MAL0_RXDEIR: | |
2003 | ret = mal->rxdeir; | |
2004 | break; | |
2005 | case MAL0_TXCTP0R: | |
2006 | ret = mal->txctpr[0]; | |
2007 | break; | |
2008 | case MAL0_TXCTP1R: | |
2009 | ret = mal->txctpr[1]; | |
2010 | break; | |
2011 | case MAL0_TXCTP2R: | |
2012 | ret = mal->txctpr[2]; | |
2013 | break; | |
2014 | case MAL0_TXCTP3R: | |
2015 | ret = mal->txctpr[3]; | |
2016 | break; | |
2017 | case MAL0_RXCTP0R: | |
2018 | ret = mal->rxctpr[0]; | |
2019 | break; | |
2020 | case MAL0_RXCTP1R: | |
2021 | ret = mal->rxctpr[1]; | |
2022 | break; | |
2023 | case MAL0_RCBS0: | |
2024 | ret = mal->rcbs[0]; | |
2025 | break; | |
2026 | case MAL0_RCBS1: | |
2027 | ret = mal->rcbs[1]; | |
2028 | break; | |
2029 | default: | |
2030 | ret = 0; | |
2031 | break; | |
2032 | } | |
2033 | ||
2034 | return ret; | |
2035 | } | |
2036 | ||
2037 | static void dcr_write_mal (void *opaque, int dcrn, target_ulong val) | |
2038 | { | |
2039 | ppc40x_mal_t *mal; | |
2040 | int idx; | |
2041 | ||
2042 | mal = opaque; | |
2043 | switch (dcrn) { | |
2044 | case MAL0_CFG: | |
2045 | if (val & 0x80000000) | |
2046 | ppc40x_mal_reset(mal); | |
2047 | mal->cfg = val & 0x00FFC087; | |
2048 | break; | |
2049 | case MAL0_ESR: | |
2050 | /* Read/clear */ | |
2051 | mal->esr &= ~val; | |
2052 | break; | |
2053 | case MAL0_IER: | |
2054 | mal->ier = val & 0x0000001F; | |
2055 | break; | |
2056 | case MAL0_TXCASR: | |
2057 | mal->txcasr = val & 0xF0000000; | |
2058 | break; | |
2059 | case MAL0_TXCARR: | |
2060 | mal->txcarr = val & 0xF0000000; | |
2061 | break; | |
2062 | case MAL0_TXEOBISR: | |
2063 | /* Read/clear */ | |
2064 | mal->txeobisr &= ~val; | |
2065 | break; | |
2066 | case MAL0_TXDEIR: | |
2067 | /* Read/clear */ | |
2068 | mal->txdeir &= ~val; | |
2069 | break; | |
2070 | case MAL0_RXCASR: | |
2071 | mal->rxcasr = val & 0xC0000000; | |
2072 | break; | |
2073 | case MAL0_RXCARR: | |
2074 | mal->rxcarr = val & 0xC0000000; | |
2075 | break; | |
2076 | case MAL0_RXEOBISR: | |
2077 | /* Read/clear */ | |
2078 | mal->rxeobisr &= ~val; | |
2079 | break; | |
2080 | case MAL0_RXDEIR: | |
2081 | /* Read/clear */ | |
2082 | mal->rxdeir &= ~val; | |
2083 | break; | |
2084 | case MAL0_TXCTP0R: | |
2085 | idx = 0; | |
2086 | goto update_tx_ptr; | |
2087 | case MAL0_TXCTP1R: | |
2088 | idx = 1; | |
2089 | goto update_tx_ptr; | |
2090 | case MAL0_TXCTP2R: | |
2091 | idx = 2; | |
2092 | goto update_tx_ptr; | |
2093 | case MAL0_TXCTP3R: | |
2094 | idx = 3; | |
2095 | update_tx_ptr: | |
2096 | mal->txctpr[idx] = val; | |
2097 | break; | |
2098 | case MAL0_RXCTP0R: | |
2099 | idx = 0; | |
2100 | goto update_rx_ptr; | |
2101 | case MAL0_RXCTP1R: | |
2102 | idx = 1; | |
2103 | update_rx_ptr: | |
2104 | mal->rxctpr[idx] = val; | |
2105 | break; | |
2106 | case MAL0_RCBS0: | |
2107 | idx = 0; | |
2108 | goto update_rx_size; | |
2109 | case MAL0_RCBS1: | |
2110 | idx = 1; | |
2111 | update_rx_size: | |
2112 | mal->rcbs[idx] = val & 0x000000FF; | |
2113 | break; | |
2114 | } | |
2115 | } | |
2116 | ||
2117 | static void ppc40x_mal_reset (void *opaque) | |
2118 | { | |
2119 | ppc40x_mal_t *mal; | |
2120 | ||
2121 | mal = opaque; | |
2122 | mal->cfg = 0x0007C000; | |
2123 | mal->esr = 0x00000000; | |
2124 | mal->ier = 0x00000000; | |
2125 | mal->rxcasr = 0x00000000; | |
2126 | mal->rxdeir = 0x00000000; | |
2127 | mal->rxeobisr = 0x00000000; | |
2128 | mal->txcasr = 0x00000000; | |
2129 | mal->txdeir = 0x00000000; | |
2130 | mal->txeobisr = 0x00000000; | |
2131 | } | |
2132 | ||
2133 | void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]) | |
2134 | { | |
2135 | ppc40x_mal_t *mal; | |
2136 | int i; | |
2137 | ||
2138 | mal = qemu_mallocz(sizeof(ppc40x_mal_t)); | |
2139 | if (mal != NULL) { | |
2140 | for (i = 0; i < 4; i++) | |
2141 | mal->irqs[i] = irqs[i]; | |
2142 | ppc40x_mal_reset(mal); | |
2143 | qemu_register_reset(&ppc40x_mal_reset, mal); | |
2144 | ppc_dcr_register(env, MAL0_CFG, | |
2145 | mal, &dcr_read_mal, &dcr_write_mal); | |
2146 | ppc_dcr_register(env, MAL0_ESR, | |
2147 | mal, &dcr_read_mal, &dcr_write_mal); | |
2148 | ppc_dcr_register(env, MAL0_IER, | |
2149 | mal, &dcr_read_mal, &dcr_write_mal); | |
2150 | ppc_dcr_register(env, MAL0_TXCASR, | |
2151 | mal, &dcr_read_mal, &dcr_write_mal); | |
2152 | ppc_dcr_register(env, MAL0_TXCARR, | |
2153 | mal, &dcr_read_mal, &dcr_write_mal); | |
2154 | ppc_dcr_register(env, MAL0_TXEOBISR, | |
2155 | mal, &dcr_read_mal, &dcr_write_mal); | |
2156 | ppc_dcr_register(env, MAL0_TXDEIR, | |
2157 | mal, &dcr_read_mal, &dcr_write_mal); | |
2158 | ppc_dcr_register(env, MAL0_RXCASR, | |
2159 | mal, &dcr_read_mal, &dcr_write_mal); | |
2160 | ppc_dcr_register(env, MAL0_RXCARR, | |
2161 | mal, &dcr_read_mal, &dcr_write_mal); | |
2162 | ppc_dcr_register(env, MAL0_RXEOBISR, | |
2163 | mal, &dcr_read_mal, &dcr_write_mal); | |
2164 | ppc_dcr_register(env, MAL0_RXDEIR, | |
2165 | mal, &dcr_read_mal, &dcr_write_mal); | |
2166 | ppc_dcr_register(env, MAL0_TXCTP0R, | |
2167 | mal, &dcr_read_mal, &dcr_write_mal); | |
2168 | ppc_dcr_register(env, MAL0_TXCTP1R, | |
2169 | mal, &dcr_read_mal, &dcr_write_mal); | |
2170 | ppc_dcr_register(env, MAL0_TXCTP2R, | |
2171 | mal, &dcr_read_mal, &dcr_write_mal); | |
2172 | ppc_dcr_register(env, MAL0_TXCTP3R, | |
2173 | mal, &dcr_read_mal, &dcr_write_mal); | |
2174 | ppc_dcr_register(env, MAL0_RXCTP0R, | |
2175 | mal, &dcr_read_mal, &dcr_write_mal); | |
2176 | ppc_dcr_register(env, MAL0_RXCTP1R, | |
2177 | mal, &dcr_read_mal, &dcr_write_mal); | |
2178 | ppc_dcr_register(env, MAL0_RCBS0, | |
2179 | mal, &dcr_read_mal, &dcr_write_mal); | |
2180 | ppc_dcr_register(env, MAL0_RCBS1, | |
2181 | mal, &dcr_read_mal, &dcr_write_mal); | |
2182 | } | |
2183 | } | |
2184 | ||
2185 | /*****************************************************************************/ | |
2186 | /* SPR */ | |
2187 | void ppc40x_core_reset (CPUState *env) | |
2188 | { | |
2189 | target_ulong dbsr; | |
2190 | ||
2191 | printf("Reset PowerPC core\n"); | |
2192 | cpu_ppc_reset(env); | |
2193 | dbsr = env->spr[SPR_40x_DBSR]; | |
2194 | dbsr &= ~0x00000300; | |
2195 | dbsr |= 0x00000100; | |
2196 | env->spr[SPR_40x_DBSR] = dbsr; | |
2197 | cpu_loop_exit(); | |
2198 | } | |
2199 | ||
2200 | void ppc40x_chip_reset (CPUState *env) | |
2201 | { | |
2202 | target_ulong dbsr; | |
2203 | ||
2204 | printf("Reset PowerPC chip\n"); | |
2205 | cpu_ppc_reset(env); | |
2206 | /* XXX: TODO reset all internal peripherals */ | |
2207 | dbsr = env->spr[SPR_40x_DBSR]; | |
2208 | dbsr &= ~0x00000300; | |
2209 | dbsr |= 0x00000200; | |
2210 | env->spr[SPR_40x_DBSR] = dbsr; | |
2211 | cpu_loop_exit(); | |
2212 | } | |
2213 | ||
2214 | void ppc40x_system_reset (CPUState *env) | |
2215 | { | |
2216 | printf("Reset PowerPC system\n"); | |
2217 | qemu_system_reset_request(); | |
2218 | } | |
2219 | ||
2220 | void store_40x_dbcr0 (CPUState *env, uint32_t val) | |
2221 | { | |
2222 | switch ((val >> 28) & 0x3) { | |
2223 | case 0x0: | |
2224 | /* No action */ | |
2225 | break; | |
2226 | case 0x1: | |
2227 | /* Core reset */ | |
2228 | ppc40x_core_reset(env); | |
2229 | break; | |
2230 | case 0x2: | |
2231 | /* Chip reset */ | |
2232 | ppc40x_chip_reset(env); | |
2233 | break; | |
2234 | case 0x3: | |
2235 | /* System reset */ | |
2236 | ppc40x_system_reset(env); | |
2237 | break; | |
2238 | } | |
2239 | } | |
2240 | ||
2241 | /*****************************************************************************/ | |
2242 | /* PowerPC 405CR */ | |
2243 | enum { | |
2244 | PPC405CR_CPC0_PLLMR = 0x0B0, | |
2245 | PPC405CR_CPC0_CR0 = 0x0B1, | |
2246 | PPC405CR_CPC0_CR1 = 0x0B2, | |
2247 | PPC405CR_CPC0_PSR = 0x0B4, | |
2248 | PPC405CR_CPC0_JTAGID = 0x0B5, | |
2249 | PPC405CR_CPC0_ER = 0x0B9, | |
2250 | PPC405CR_CPC0_FR = 0x0BA, | |
2251 | PPC405CR_CPC0_SR = 0x0BB, | |
2252 | }; | |
2253 | ||
2254 | enum { | |
2255 | PPC405CR_CPU_CLK = 0, | |
2256 | PPC405CR_TMR_CLK = 1, | |
2257 | PPC405CR_PLB_CLK = 2, | |
2258 | PPC405CR_SDRAM_CLK = 3, | |
2259 | PPC405CR_OPB_CLK = 4, | |
2260 | PPC405CR_EXT_CLK = 5, | |
2261 | PPC405CR_UART_CLK = 6, | |
2262 | PPC405CR_CLK_NB = 7, | |
2263 | }; | |
2264 | ||
2265 | typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; | |
2266 | struct ppc405cr_cpc_t { | |
2267 | clk_setup_t clk_setup[PPC405CR_CLK_NB]; | |
2268 | uint32_t sysclk; | |
2269 | uint32_t psr; | |
2270 | uint32_t cr0; | |
2271 | uint32_t cr1; | |
2272 | uint32_t jtagid; | |
2273 | uint32_t pllmr; | |
2274 | uint32_t er; | |
2275 | uint32_t fr; | |
2276 | }; | |
2277 | ||
2278 | static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) | |
2279 | { | |
2280 | uint64_t VCO_out, PLL_out; | |
2281 | uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk; | |
2282 | int M, D0, D1, D2; | |
2283 | ||
2284 | D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */ | |
2285 | if (cpc->pllmr & 0x80000000) { | |
2286 | D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ | |
2287 | D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ | |
2288 | M = D0 * D1 * D2; | |
2289 | VCO_out = cpc->sysclk * M; | |
2290 | if (VCO_out < 400000000 || VCO_out > 800000000) { | |
2291 | /* PLL cannot lock */ | |
2292 | cpc->pllmr &= ~0x80000000; | |
2293 | goto bypass_pll; | |
2294 | } | |
2295 | PLL_out = VCO_out / D2; | |
2296 | } else { | |
2297 | /* Bypass PLL */ | |
2298 | bypass_pll: | |
2299 | M = D0; | |
2300 | PLL_out = cpc->sysclk * M; | |
2301 | } | |
2302 | CPU_clk = PLL_out; | |
2303 | if (cpc->cr1 & 0x00800000) | |
2304 | TMR_clk = cpc->sysclk; /* Should have a separate clock */ | |
2305 | else | |
2306 | TMR_clk = CPU_clk; | |
2307 | PLB_clk = CPU_clk / D0; | |
2308 | SDRAM_clk = PLB_clk; | |
2309 | D0 = ((cpc->pllmr >> 10) & 0x3) + 1; | |
2310 | OPB_clk = PLB_clk / D0; | |
2311 | D0 = ((cpc->pllmr >> 24) & 0x3) + 2; | |
2312 | EXT_clk = PLB_clk / D0; | |
2313 | D0 = ((cpc->cr0 >> 1) & 0x1F) + 1; | |
2314 | UART_clk = CPU_clk / D0; | |
2315 | /* Setup CPU clocks */ | |
2316 | clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk); | |
2317 | /* Setup time-base clock */ | |
2318 | clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk); | |
2319 | /* Setup PLB clock */ | |
2320 | clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk); | |
2321 | /* Setup SDRAM clock */ | |
2322 | clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk); | |
2323 | /* Setup OPB clock */ | |
2324 | clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk); | |
2325 | /* Setup external clock */ | |
2326 | clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk); | |
2327 | /* Setup UART clock */ | |
2328 | clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); | |
2329 | } | |
2330 | ||
2331 | static target_ulong dcr_read_crcpc (void *opaque, int dcrn) | |
2332 | { | |
2333 | ppc405cr_cpc_t *cpc; | |
2334 | target_ulong ret; | |
2335 | ||
2336 | cpc = opaque; | |
2337 | switch (dcrn) { | |
2338 | case PPC405CR_CPC0_PLLMR: | |
2339 | ret = cpc->pllmr; | |
2340 | break; | |
2341 | case PPC405CR_CPC0_CR0: | |
2342 | ret = cpc->cr0; | |
2343 | break; | |
2344 | case PPC405CR_CPC0_CR1: | |
2345 | ret = cpc->cr1; | |
2346 | break; | |
2347 | case PPC405CR_CPC0_PSR: | |
2348 | ret = cpc->psr; | |
2349 | break; | |
2350 | case PPC405CR_CPC0_JTAGID: | |
2351 | ret = cpc->jtagid; | |
2352 | break; | |
2353 | case PPC405CR_CPC0_ER: | |
2354 | ret = cpc->er; | |
2355 | break; | |
2356 | case PPC405CR_CPC0_FR: | |
2357 | ret = cpc->fr; | |
2358 | break; | |
2359 | case PPC405CR_CPC0_SR: | |
2360 | ret = ~(cpc->er | cpc->fr) & 0xFFFF0000; | |
2361 | break; | |
2362 | default: | |
2363 | /* Avoid gcc warning */ | |
2364 | ret = 0; | |
2365 | break; | |
2366 | } | |
2367 | ||
2368 | return ret; | |
2369 | } | |
2370 | ||
2371 | static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val) | |
2372 | { | |
2373 | ppc405cr_cpc_t *cpc; | |
2374 | ||
2375 | cpc = opaque; | |
2376 | switch (dcrn) { | |
2377 | case PPC405CR_CPC0_PLLMR: | |
2378 | cpc->pllmr = val & 0xFFF77C3F; | |
2379 | break; | |
2380 | case PPC405CR_CPC0_CR0: | |
2381 | cpc->cr0 = val & 0x0FFFFFFE; | |
2382 | break; | |
2383 | case PPC405CR_CPC0_CR1: | |
2384 | cpc->cr1 = val & 0x00800000; | |
2385 | break; | |
2386 | case PPC405CR_CPC0_PSR: | |
2387 | /* Read-only */ | |
2388 | break; | |
2389 | case PPC405CR_CPC0_JTAGID: | |
2390 | /* Read-only */ | |
2391 | break; | |
2392 | case PPC405CR_CPC0_ER: | |
2393 | cpc->er = val & 0xBFFC0000; | |
2394 | break; | |
2395 | case PPC405CR_CPC0_FR: | |
2396 | cpc->fr = val & 0xBFFC0000; | |
2397 | break; | |
2398 | case PPC405CR_CPC0_SR: | |
2399 | /* Read-only */ | |
2400 | break; | |
2401 | } | |
2402 | } | |
2403 | ||
2404 | static void ppc405cr_cpc_reset (void *opaque) | |
2405 | { | |
2406 | ppc405cr_cpc_t *cpc; | |
2407 | int D; | |
2408 | ||
2409 | cpc = opaque; | |
2410 | /* Compute PLLMR value from PSR settings */ | |
2411 | cpc->pllmr = 0x80000000; | |
2412 | /* PFWD */ | |
2413 | switch ((cpc->psr >> 30) & 3) { | |
2414 | case 0: | |
2415 | /* Bypass */ | |
2416 | cpc->pllmr &= ~0x80000000; | |
2417 | break; | |
2418 | case 1: | |
2419 | /* Divide by 3 */ | |
2420 | cpc->pllmr |= 5 << 16; | |
2421 | break; | |
2422 | case 2: | |
2423 | /* Divide by 4 */ | |
2424 | cpc->pllmr |= 4 << 16; | |
2425 | break; | |
2426 | case 3: | |
2427 | /* Divide by 6 */ | |
2428 | cpc->pllmr |= 2 << 16; | |
2429 | break; | |
2430 | } | |
2431 | /* PFBD */ | |
2432 | D = (cpc->psr >> 28) & 3; | |
2433 | cpc->pllmr |= (D + 1) << 20; | |
2434 | /* PT */ | |
2435 | D = (cpc->psr >> 25) & 7; | |
2436 | switch (D) { | |
2437 | case 0x2: | |
2438 | cpc->pllmr |= 0x13; | |
2439 | break; | |
2440 | case 0x4: | |
2441 | cpc->pllmr |= 0x15; | |
2442 | break; | |
2443 | case 0x5: | |
2444 | cpc->pllmr |= 0x16; | |
2445 | break; | |
2446 | default: | |
2447 | break; | |
2448 | } | |
2449 | /* PDC */ | |
2450 | D = (cpc->psr >> 23) & 3; | |
2451 | cpc->pllmr |= D << 26; | |
2452 | /* ODP */ | |
2453 | D = (cpc->psr >> 21) & 3; | |
2454 | cpc->pllmr |= D << 10; | |
2455 | /* EBPD */ | |
2456 | D = (cpc->psr >> 17) & 3; | |
2457 | cpc->pllmr |= D << 24; | |
2458 | cpc->cr0 = 0x0000003C; | |
2459 | cpc->cr1 = 0x2B0D8800; | |
2460 | cpc->er = 0x00000000; | |
2461 | cpc->fr = 0x00000000; | |
2462 | ppc405cr_clk_setup(cpc); | |
2463 | } | |
2464 | ||
2465 | static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) | |
2466 | { | |
2467 | int D; | |
2468 | ||
2469 | /* XXX: this should be read from IO pins */ | |
2470 | cpc->psr = 0x00000000; /* 8 bits ROM */ | |
2471 | /* PFWD */ | |
2472 | D = 0x2; /* Divide by 4 */ | |
2473 | cpc->psr |= D << 30; | |
2474 | /* PFBD */ | |
2475 | D = 0x1; /* Divide by 2 */ | |
2476 | cpc->psr |= D << 28; | |
2477 | /* PDC */ | |
2478 | D = 0x1; /* Divide by 2 */ | |
2479 | cpc->psr |= D << 23; | |
2480 | /* PT */ | |
2481 | D = 0x5; /* M = 16 */ | |
2482 | cpc->psr |= D << 25; | |
2483 | /* ODP */ | |
2484 | D = 0x1; /* Divide by 2 */ | |
2485 | cpc->psr |= D << 21; | |
2486 | /* EBDP */ | |
2487 | D = 0x2; /* Divide by 4 */ | |
2488 | cpc->psr |= D << 17; | |
2489 | } | |
2490 | ||
2491 | static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], | |
2492 | uint32_t sysclk) | |
2493 | { | |
2494 | ppc405cr_cpc_t *cpc; | |
2495 | ||
2496 | cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t)); | |
2497 | if (cpc != NULL) { | |
2498 | memcpy(cpc->clk_setup, clk_setup, | |
2499 | PPC405CR_CLK_NB * sizeof(clk_setup_t)); | |
2500 | cpc->sysclk = sysclk; | |
2501 | cpc->jtagid = 0x42051049; | |
2502 | ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, | |
2503 | &dcr_read_crcpc, &dcr_write_crcpc); | |
2504 | ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, | |
2505 | &dcr_read_crcpc, &dcr_write_crcpc); | |
2506 | ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, | |
2507 | &dcr_read_crcpc, &dcr_write_crcpc); | |
2508 | ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, | |
2509 | &dcr_read_crcpc, &dcr_write_crcpc); | |
2510 | ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, | |
2511 | &dcr_read_crcpc, &dcr_write_crcpc); | |
2512 | ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, | |
2513 | &dcr_read_crcpc, &dcr_write_crcpc); | |
2514 | ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, | |
2515 | &dcr_read_crcpc, &dcr_write_crcpc); | |
2516 | ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, | |
2517 | &dcr_read_crcpc, &dcr_write_crcpc); | |
2518 | ppc405cr_clk_init(cpc); | |
2519 | qemu_register_reset(ppc405cr_cpc_reset, cpc); | |
2520 | ppc405cr_cpc_reset(cpc); | |
2521 | } | |
2522 | } | |
2523 | ||
2524 | CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], | |
2525 | target_phys_addr_t ram_sizes[4], | |
2526 | uint32_t sysclk, qemu_irq **picp, | |
2527 | ram_addr_t *offsetp, int do_init) | |
2528 | { | |
2529 | clk_setup_t clk_setup[PPC405CR_CLK_NB]; | |
2530 | qemu_irq dma_irqs[4]; | |
2531 | CPUState *env; | |
2532 | ppc4xx_mmio_t *mmio; | |
2533 | qemu_irq *pic, *irqs; | |
2534 | ram_addr_t offset; | |
2535 | int i; | |
2536 | ||
2537 | memset(clk_setup, 0, sizeof(clk_setup)); | |
2538 | env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK], | |
2539 | &clk_setup[PPC405CR_TMR_CLK], sysclk); | |
2540 | /* Memory mapped devices registers */ | |
2541 | mmio = ppc4xx_mmio_init(env, 0xEF600000); | |
2542 | /* PLB arbitrer */ | |
2543 | ppc4xx_plb_init(env); | |
2544 | /* PLB to OPB bridge */ | |
2545 | ppc4xx_pob_init(env); | |
2546 | /* OBP arbitrer */ | |
2547 | ppc4xx_opba_init(env, mmio, 0x600); | |
2548 | /* Universal interrupt controller */ | |
2549 | irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); | |
2550 | irqs[PPCUIC_OUTPUT_INT] = | |
2551 | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; | |
2552 | irqs[PPCUIC_OUTPUT_CINT] = | |
2553 | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; | |
2554 | pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); | |
2555 | *picp = pic; | |
2556 | /* SDRAM controller */ | |
2557 | ppc405_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); | |
2558 | offset = 0; | |
2559 | for (i = 0; i < 4; i++) | |
2560 | offset += ram_sizes[i]; | |
2561 | /* External bus controller */ | |
2562 | ppc405_ebc_init(env); | |
2563 | /* DMA controller */ | |
2564 | dma_irqs[0] = pic[26]; | |
2565 | dma_irqs[1] = pic[25]; | |
2566 | dma_irqs[2] = pic[24]; | |
2567 | dma_irqs[3] = pic[23]; | |
2568 | ppc405_dma_init(env, dma_irqs); | |
2569 | /* Serial ports */ | |
2570 | if (serial_hds[0] != NULL) { | |
2571 | ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]); | |
2572 | } | |
2573 | if (serial_hds[1] != NULL) { | |
2574 | ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]); | |
2575 | } | |
2576 | /* IIC controller */ | |
2577 | ppc405_i2c_init(env, mmio, 0x500, pic[29]); | |
2578 | /* GPIO */ | |
2579 | ppc405_gpio_init(env, mmio, 0x700); | |
2580 | /* CPU control */ | |
2581 | ppc405cr_cpc_init(env, clk_setup, sysclk); | |
2582 | *offsetp = offset; | |
2583 | ||
2584 | return env; | |
2585 | } | |
2586 | ||
2587 | /*****************************************************************************/ | |
2588 | /* PowerPC 405EP */ | |
2589 | /* CPU control */ | |
2590 | enum { | |
2591 | PPC405EP_CPC0_PLLMR0 = 0x0F0, | |
2592 | PPC405EP_CPC0_BOOT = 0x0F1, | |
2593 | PPC405EP_CPC0_EPCTL = 0x0F3, | |
2594 | PPC405EP_CPC0_PLLMR1 = 0x0F4, | |
2595 | PPC405EP_CPC0_UCR = 0x0F5, | |
2596 | PPC405EP_CPC0_SRR = 0x0F6, | |
2597 | PPC405EP_CPC0_JTAGID = 0x0F7, | |
2598 | PPC405EP_CPC0_PCI = 0x0F9, | |
2599 | #if 0 | |
2600 | PPC405EP_CPC0_ER = xxx, | |
2601 | PPC405EP_CPC0_FR = xxx, | |
2602 | PPC405EP_CPC0_SR = xxx, | |
2603 | #endif | |
2604 | }; | |
2605 | ||
2606 | enum { | |
2607 | PPC405EP_CPU_CLK = 0, | |
2608 | PPC405EP_PLB_CLK = 1, | |
2609 | PPC405EP_OPB_CLK = 2, | |
2610 | PPC405EP_EBC_CLK = 3, | |
2611 | PPC405EP_MAL_CLK = 4, | |
2612 | PPC405EP_PCI_CLK = 5, | |
2613 | PPC405EP_UART0_CLK = 6, | |
2614 | PPC405EP_UART1_CLK = 7, | |
2615 | PPC405EP_CLK_NB = 8, | |
2616 | }; | |
2617 | ||
2618 | typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; | |
2619 | struct ppc405ep_cpc_t { | |
2620 | uint32_t sysclk; | |
2621 | clk_setup_t clk_setup[PPC405EP_CLK_NB]; | |
2622 | uint32_t boot; | |
2623 | uint32_t epctl; | |
2624 | uint32_t pllmr[2]; | |
2625 | uint32_t ucr; | |
2626 | uint32_t srr; | |
2627 | uint32_t jtagid; | |
2628 | uint32_t pci; | |
2629 | /* Clock and power management */ | |
2630 | uint32_t er; | |
2631 | uint32_t fr; | |
2632 | uint32_t sr; | |
2633 | }; | |
2634 | ||
2635 | static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) | |
2636 | { | |
2637 | uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; | |
2638 | uint32_t UART0_clk, UART1_clk; | |
2639 | uint64_t VCO_out, PLL_out; | |
2640 | int M, D; | |
2641 | ||
2642 | VCO_out = 0; | |
2643 | if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { | |
2644 | M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ | |
2645 | // printf("FBMUL %01x %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); | |
2646 | D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ | |
2647 | // printf("FWDA %01x %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); | |
2648 | VCO_out = cpc->sysclk * M * D; | |
2649 | if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { | |
2650 | /* Error - unlock the PLL */ | |
2651 | printf("VCO out of range %" PRIu64 "\n", VCO_out); | |
2652 | #if 0 | |
2653 | cpc->pllmr[1] &= ~0x80000000; | |
2654 | goto pll_bypass; | |
2655 | #endif | |
2656 | } | |
2657 | PLL_out = VCO_out / D; | |
2658 | /* Pretend the PLL is locked */ | |
2659 | cpc->boot |= 0x00000001; | |
2660 | } else { | |
2661 | #if 0 | |
2662 | pll_bypass: | |
2663 | #endif | |
2664 | PLL_out = cpc->sysclk; | |
2665 | if (cpc->pllmr[1] & 0x40000000) { | |
2666 | /* Pretend the PLL is not locked */ | |
2667 | cpc->boot &= ~0x00000001; | |
2668 | } | |
2669 | } | |
2670 | /* Now, compute all other clocks */ | |
2671 | D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ | |
2672 | #ifdef DEBUG_CLOCKS | |
2673 | // printf("CCDV %01x %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); | |
2674 | #endif | |
2675 | CPU_clk = PLL_out / D; | |
2676 | D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ | |
2677 | #ifdef DEBUG_CLOCKS | |
2678 | // printf("CBDV %01x %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); | |
2679 | #endif | |
2680 | PLB_clk = CPU_clk / D; | |
2681 | D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ | |
2682 | #ifdef DEBUG_CLOCKS | |
2683 | // printf("OPDV %01x %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); | |
2684 | #endif | |
2685 | OPB_clk = PLB_clk / D; | |
2686 | D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ | |
2687 | #ifdef DEBUG_CLOCKS | |
2688 | // printf("EPDV %01x %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); | |
2689 | #endif | |
2690 | EBC_clk = PLB_clk / D; | |
2691 | D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ | |
2692 | #ifdef DEBUG_CLOCKS | |
2693 | // printf("MPDV %01x %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); | |
2694 | #endif | |
2695 | MAL_clk = PLB_clk / D; | |
2696 | D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ | |
2697 | #ifdef DEBUG_CLOCKS | |
2698 | // printf("PPDV %01x %d\n", cpc->pllmr[0] & 0x3, D); | |
2699 | #endif | |
2700 | PCI_clk = PLB_clk / D; | |
2701 | D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ | |
2702 | #ifdef DEBUG_CLOCKS | |
2703 | // printf("U0DIV %01x %d\n", cpc->ucr & 0x7F, D); | |
2704 | #endif | |
2705 | UART0_clk = PLL_out / D; | |
2706 | D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ | |
2707 | #ifdef DEBUG_CLOCKS | |
2708 | // printf("U1DIV %01x %d\n", (cpc->ucr >> 8) & 0x7F, D); | |
2709 | #endif | |
2710 | UART1_clk = PLL_out / D; | |
2711 | #ifdef DEBUG_CLOCKS | |
2712 | printf("Setup PPC405EP clocks - sysclk %d VCO %" PRIu64 | |
2713 | " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); | |
2714 | printf("CPU %d PLB %d OPB %d EBC %d MAL %d PCI %d UART0 %d UART1 %d\n", | |
2715 | CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, | |
2716 | UART0_clk, UART1_clk); | |
2717 | printf("CB %p opaque %p\n", cpc->clk_setup[PPC405EP_CPU_CLK].cb, | |
2718 | cpc->clk_setup[PPC405EP_CPU_CLK].opaque); | |
2719 | #endif | |
2720 | /* Setup CPU clocks */ | |
2721 | clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); | |
2722 | /* Setup PLB clock */ | |
2723 | clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); | |
2724 | /* Setup OPB clock */ | |
2725 | clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); | |
2726 | /* Setup external clock */ | |
2727 | clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); | |
2728 | /* Setup MAL clock */ | |
2729 | clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); | |
2730 | /* Setup PCI clock */ | |
2731 | clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); | |
2732 | /* Setup UART0 clock */ | |
2733 | clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); | |
2734 | /* Setup UART1 clock */ | |
2735 | clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); | |
2736 | } | |
2737 | ||
2738 | static target_ulong dcr_read_epcpc (void *opaque, int dcrn) | |
2739 | { | |
2740 | ppc405ep_cpc_t *cpc; | |
2741 | target_ulong ret; | |
2742 | ||
2743 | cpc = opaque; | |
2744 | switch (dcrn) { | |
2745 | case PPC405EP_CPC0_BOOT: | |
2746 | ret = cpc->boot; | |
2747 | break; | |
2748 | case PPC405EP_CPC0_EPCTL: | |
2749 | ret = cpc->epctl; | |
2750 | break; | |
2751 | case PPC405EP_CPC0_PLLMR0: | |
2752 | ret = cpc->pllmr[0]; | |
2753 | break; | |
2754 | case PPC405EP_CPC0_PLLMR1: | |
2755 | ret = cpc->pllmr[1]; | |
2756 | break; | |
2757 | case PPC405EP_CPC0_UCR: | |
2758 | ret = cpc->ucr; | |
2759 | break; | |
2760 | case PPC405EP_CPC0_SRR: | |
2761 | ret = cpc->srr; | |
2762 | break; | |
2763 | case PPC405EP_CPC0_JTAGID: | |
2764 | ret = cpc->jtagid; | |
2765 | break; | |
2766 | case PPC405EP_CPC0_PCI: | |
2767 | ret = cpc->pci; | |
2768 | break; | |
2769 | default: | |
2770 | /* Avoid gcc warning */ | |
2771 | ret = 0; | |
2772 | break; | |
2773 | } | |
2774 | ||
2775 | return ret; | |
2776 | } | |
2777 | ||
2778 | static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val) | |
2779 | { | |
2780 | ppc405ep_cpc_t *cpc; | |
2781 | ||
2782 | cpc = opaque; | |
2783 | switch (dcrn) { | |
2784 | case PPC405EP_CPC0_BOOT: | |
2785 | /* Read-only register */ | |
2786 | break; | |
2787 | case PPC405EP_CPC0_EPCTL: | |
2788 | /* Don't care for now */ | |
2789 | cpc->epctl = val & 0xC00000F3; | |
2790 | break; | |
2791 | case PPC405EP_CPC0_PLLMR0: | |
2792 | cpc->pllmr[0] = val & 0x00633333; | |
2793 | ppc405ep_compute_clocks(cpc); | |
2794 | break; | |
2795 | case PPC405EP_CPC0_PLLMR1: | |
2796 | cpc->pllmr[1] = val & 0xC0F73FFF; | |
2797 | ppc405ep_compute_clocks(cpc); | |
2798 | break; | |
2799 | case PPC405EP_CPC0_UCR: | |
2800 | /* UART control - don't care for now */ | |
2801 | cpc->ucr = val & 0x003F7F7F; | |
2802 | break; | |
2803 | case PPC405EP_CPC0_SRR: | |
2804 | cpc->srr = val; | |
2805 | break; | |
2806 | case PPC405EP_CPC0_JTAGID: | |
2807 | /* Read-only */ | |
2808 | break; | |
2809 | case PPC405EP_CPC0_PCI: | |
2810 | cpc->pci = val; | |
2811 | break; | |
2812 | } | |
2813 | } | |
2814 | ||
2815 | static void ppc405ep_cpc_reset (void *opaque) | |
2816 | { | |
2817 | ppc405ep_cpc_t *cpc = opaque; | |
2818 | ||
2819 | cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ | |
2820 | cpc->epctl = 0x00000000; | |
2821 | cpc->pllmr[0] = 0x00011010; | |
2822 | cpc->pllmr[1] = 0x40000000; | |
2823 | cpc->ucr = 0x00000000; | |
2824 | cpc->srr = 0x00040000; | |
2825 | cpc->pci = 0x00000000; | |
2826 | cpc->er = 0x00000000; | |
2827 | cpc->fr = 0x00000000; | |
2828 | cpc->sr = 0x00000000; | |
2829 | ppc405ep_compute_clocks(cpc); | |
2830 | } | |
2831 | ||
2832 | /* XXX: sysclk should be between 25 and 100 MHz */ | |
2833 | static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], | |
2834 | uint32_t sysclk) | |
2835 | { | |
2836 | ppc405ep_cpc_t *cpc; | |
2837 | ||
2838 | cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t)); | |
2839 | if (cpc != NULL) { | |
2840 | memcpy(cpc->clk_setup, clk_setup, | |
2841 | PPC405EP_CLK_NB * sizeof(clk_setup_t)); | |
2842 | cpc->jtagid = 0x20267049; | |
2843 | cpc->sysclk = sysclk; | |
2844 | ppc405ep_cpc_reset(cpc); | |
2845 | qemu_register_reset(&ppc405ep_cpc_reset, cpc); | |
2846 | ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, | |
2847 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2848 | ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, | |
2849 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2850 | ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, | |
2851 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2852 | ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, | |
2853 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2854 | ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, | |
2855 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2856 | ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, | |
2857 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2858 | ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, | |
2859 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2860 | ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, | |
2861 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2862 | #if 0 | |
2863 | ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc, | |
2864 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2865 | ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc, | |
2866 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2867 | ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc, | |
2868 | &dcr_read_epcpc, &dcr_write_epcpc); | |
2869 | #endif | |
2870 | } | |
2871 | } | |
2872 | ||
2873 | CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], | |
2874 | target_phys_addr_t ram_sizes[2], | |
2875 | uint32_t sysclk, qemu_irq **picp, | |
2876 | ram_addr_t *offsetp, int do_init) | |
2877 | { | |
2878 | clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; | |
2879 | qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; | |
2880 | CPUState *env; | |
2881 | ppc4xx_mmio_t *mmio; | |
2882 | qemu_irq *pic, *irqs; | |
2883 | ram_addr_t offset; | |
2884 | int i; | |
2885 | ||
2886 | memset(clk_setup, 0, sizeof(clk_setup)); | |
2887 | /* init CPUs */ | |
2888 | env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK], | |
2889 | &tlb_clk_setup, sysclk); | |
2890 | clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; | |
2891 | clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; | |
2892 | /* Internal devices init */ | |
2893 | /* Memory mapped devices registers */ | |
2894 | mmio = ppc4xx_mmio_init(env, 0xEF600000); | |
2895 | /* PLB arbitrer */ | |
2896 | ppc4xx_plb_init(env); | |
2897 | /* PLB to OPB bridge */ | |
2898 | ppc4xx_pob_init(env); | |
2899 | /* OBP arbitrer */ | |
2900 | ppc4xx_opba_init(env, mmio, 0x600); | |
2901 | /* Universal interrupt controller */ | |
2902 | irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); | |
2903 | irqs[PPCUIC_OUTPUT_INT] = | |
2904 | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; | |
2905 | irqs[PPCUIC_OUTPUT_CINT] = | |
2906 | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; | |
2907 | pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); | |
2908 | *picp = pic; | |
2909 | /* SDRAM controller */ | |
2910 | ppc405_sdram_init(env, pic[14], 2, ram_bases, ram_sizes, do_init); | |
2911 | offset = 0; | |
2912 | for (i = 0; i < 2; i++) | |
2913 | offset += ram_sizes[i]; | |
2914 | /* External bus controller */ | |
2915 | ppc405_ebc_init(env); | |
2916 | /* DMA controller */ | |
2917 | dma_irqs[0] = pic[26]; | |
2918 | dma_irqs[1] = pic[25]; | |
2919 | dma_irqs[2] = pic[24]; | |
2920 | dma_irqs[3] = pic[23]; | |
2921 | ppc405_dma_init(env, dma_irqs); | |
2922 | /* IIC controller */ | |
2923 | ppc405_i2c_init(env, mmio, 0x500, pic[29]); | |
2924 | /* GPIO */ | |
2925 | ppc405_gpio_init(env, mmio, 0x700); | |
2926 | /* Serial ports */ | |
2927 | if (serial_hds[0] != NULL) { | |
2928 | ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]); | |
2929 | } | |
2930 | if (serial_hds[1] != NULL) { | |
2931 | ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]); | |
2932 | } | |
2933 | /* OCM */ | |
2934 | ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]); | |
2935 | offset += 4096; | |
2936 | /* GPT */ | |
2937 | gpt_irqs[0] = pic[12]; | |
2938 | gpt_irqs[1] = pic[11]; | |
2939 | gpt_irqs[2] = pic[10]; | |
2940 | gpt_irqs[3] = pic[9]; | |
2941 | gpt_irqs[4] = pic[8]; | |
2942 | ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs); | |
2943 | /* PCI */ | |
2944 | /* Uses pic[28], pic[15], pic[13] */ | |
2945 | /* MAL */ | |
2946 | mal_irqs[0] = pic[20]; | |
2947 | mal_irqs[1] = pic[19]; | |
2948 | mal_irqs[2] = pic[18]; | |
2949 | mal_irqs[3] = pic[17]; | |
2950 | ppc405_mal_init(env, mal_irqs); | |
2951 | /* Ethernet */ | |
2952 | /* Uses pic[22], pic[16], pic[14] */ | |
2953 | /* CPU control */ | |
2954 | ppc405ep_cpc_init(env, clk_setup, sysclk); | |
2955 | *offsetp = offset; | |
2956 | ||
2957 | return env; | |
2958 | } |