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1 | /* | |
2 | * ARM RealView Baseboard System emulation. | |
3 | * | |
4 | * Copyright (c) 2006-2007 CodeSourcery. | |
5 | * Written by Paul Brook | |
6 | * | |
7 | * This code is licenced under the GPL. | |
8 | */ | |
9 | ||
10 | #include "sysbus.h" | |
11 | #include "arm-misc.h" | |
12 | #include "primecell.h" | |
13 | #include "devices.h" | |
14 | #include "pci.h" | |
15 | #include "usb-ohci.h" | |
16 | #include "net.h" | |
17 | #include "sysemu.h" | |
18 | #include "boards.h" | |
19 | #include "bitbang_i2c.h" | |
20 | #include "blockdev.h" | |
21 | ||
22 | #define SMP_BOOT_ADDR 0xe0000000 | |
23 | ||
24 | typedef struct { | |
25 | SysBusDevice busdev; | |
26 | bitbang_i2c_interface *bitbang; | |
27 | int out; | |
28 | int in; | |
29 | } RealViewI2CState; | |
30 | ||
31 | static uint32_t realview_i2c_read(void *opaque, target_phys_addr_t offset) | |
32 | { | |
33 | RealViewI2CState *s = (RealViewI2CState *)opaque; | |
34 | ||
35 | if (offset == 0) { | |
36 | return (s->out & 1) | (s->in << 1); | |
37 | } else { | |
38 | hw_error("realview_i2c_read: Bad offset 0x%x\n", (int)offset); | |
39 | return -1; | |
40 | } | |
41 | } | |
42 | ||
43 | static void realview_i2c_write(void *opaque, target_phys_addr_t offset, | |
44 | uint32_t value) | |
45 | { | |
46 | RealViewI2CState *s = (RealViewI2CState *)opaque; | |
47 | ||
48 | switch (offset) { | |
49 | case 0: | |
50 | s->out |= value & 3; | |
51 | break; | |
52 | case 4: | |
53 | s->out &= ~value; | |
54 | break; | |
55 | default: | |
56 | hw_error("realview_i2c_write: Bad offset 0x%x\n", (int)offset); | |
57 | } | |
58 | bitbang_i2c_set(s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0); | |
59 | s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0); | |
60 | } | |
61 | ||
62 | static CPUReadMemoryFunc * const realview_i2c_readfn[] = { | |
63 | realview_i2c_read, | |
64 | realview_i2c_read, | |
65 | realview_i2c_read | |
66 | }; | |
67 | ||
68 | static CPUWriteMemoryFunc * const realview_i2c_writefn[] = { | |
69 | realview_i2c_write, | |
70 | realview_i2c_write, | |
71 | realview_i2c_write | |
72 | }; | |
73 | ||
74 | static int realview_i2c_init(SysBusDevice *dev) | |
75 | { | |
76 | RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev); | |
77 | i2c_bus *bus; | |
78 | int iomemtype; | |
79 | ||
80 | bus = i2c_init_bus(&dev->qdev, "i2c"); | |
81 | s->bitbang = bitbang_i2c_init(bus); | |
82 | iomemtype = cpu_register_io_memory(realview_i2c_readfn, | |
83 | realview_i2c_writefn, s, | |
84 | DEVICE_NATIVE_ENDIAN); | |
85 | sysbus_init_mmio(dev, 0x1000, iomemtype); | |
86 | return 0; | |
87 | } | |
88 | ||
89 | static SysBusDeviceInfo realview_i2c_info = { | |
90 | .init = realview_i2c_init, | |
91 | .qdev.name = "realview_i2c", | |
92 | .qdev.size = sizeof(RealViewI2CState), | |
93 | }; | |
94 | ||
95 | static void realview_register_devices(void) | |
96 | { | |
97 | sysbus_register_withprop(&realview_i2c_info); | |
98 | } | |
99 | ||
100 | /* Board init. */ | |
101 | ||
102 | static struct arm_boot_info realview_binfo = { | |
103 | .smp_loader_start = SMP_BOOT_ADDR, | |
104 | }; | |
105 | ||
106 | /* The following two lists must be consistent. */ | |
107 | enum realview_board_type { | |
108 | BOARD_EB, | |
109 | BOARD_EB_MPCORE, | |
110 | BOARD_PB_A8, | |
111 | BOARD_PBX_A9, | |
112 | }; | |
113 | ||
114 | static const int realview_board_id[] = { | |
115 | 0x33b, | |
116 | 0x33b, | |
117 | 0x769, | |
118 | 0x76d | |
119 | }; | |
120 | ||
121 | static void realview_init(ram_addr_t ram_size, | |
122 | const char *boot_device, | |
123 | const char *kernel_filename, const char *kernel_cmdline, | |
124 | const char *initrd_filename, const char *cpu_model, | |
125 | enum realview_board_type board_type) | |
126 | { | |
127 | CPUState *env = NULL; | |
128 | ram_addr_t ram_offset; | |
129 | DeviceState *dev, *sysctl, *gpio2; | |
130 | SysBusDevice *busdev; | |
131 | qemu_irq *irqp; | |
132 | qemu_irq pic[64]; | |
133 | qemu_irq mmc_irq[2]; | |
134 | PCIBus *pci_bus; | |
135 | NICInfo *nd; | |
136 | i2c_bus *i2c; | |
137 | int n; | |
138 | int done_nic = 0; | |
139 | qemu_irq cpu_irq[4]; | |
140 | int is_mpcore = 0; | |
141 | int is_pb = 0; | |
142 | uint32_t proc_id = 0; | |
143 | uint32_t sys_id; | |
144 | ram_addr_t low_ram_size; | |
145 | ||
146 | switch (board_type) { | |
147 | case BOARD_EB: | |
148 | break; | |
149 | case BOARD_EB_MPCORE: | |
150 | is_mpcore = 1; | |
151 | break; | |
152 | case BOARD_PB_A8: | |
153 | is_pb = 1; | |
154 | break; | |
155 | case BOARD_PBX_A9: | |
156 | is_mpcore = 1; | |
157 | is_pb = 1; | |
158 | break; | |
159 | } | |
160 | for (n = 0; n < smp_cpus; n++) { | |
161 | env = cpu_init(cpu_model); | |
162 | if (!env) { | |
163 | fprintf(stderr, "Unable to find CPU definition\n"); | |
164 | exit(1); | |
165 | } | |
166 | irqp = arm_pic_init_cpu(env); | |
167 | cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; | |
168 | } | |
169 | if (arm_feature(env, ARM_FEATURE_V7)) { | |
170 | if (is_mpcore) { | |
171 | proc_id = 0x0c000000; | |
172 | } else { | |
173 | proc_id = 0x0e000000; | |
174 | } | |
175 | } else if (arm_feature(env, ARM_FEATURE_V6K)) { | |
176 | proc_id = 0x06000000; | |
177 | } else if (arm_feature(env, ARM_FEATURE_V6)) { | |
178 | proc_id = 0x04000000; | |
179 | } else { | |
180 | proc_id = 0x02000000; | |
181 | } | |
182 | ||
183 | if (is_pb && ram_size > 0x20000000) { | |
184 | /* Core tile RAM. */ | |
185 | low_ram_size = ram_size - 0x20000000; | |
186 | ram_size = 0x20000000; | |
187 | ram_offset = qemu_ram_alloc(NULL, "realview.lowmem", low_ram_size); | |
188 | cpu_register_physical_memory(0x20000000, low_ram_size, | |
189 | ram_offset | IO_MEM_RAM); | |
190 | } | |
191 | ||
192 | ram_offset = qemu_ram_alloc(NULL, "realview.highmem", ram_size); | |
193 | low_ram_size = ram_size; | |
194 | if (low_ram_size > 0x10000000) | |
195 | low_ram_size = 0x10000000; | |
196 | /* SDRAM at address zero. */ | |
197 | cpu_register_physical_memory(0, low_ram_size, ram_offset | IO_MEM_RAM); | |
198 | if (is_pb) { | |
199 | /* And again at a high address. */ | |
200 | cpu_register_physical_memory(0x70000000, ram_size, | |
201 | ram_offset | IO_MEM_RAM); | |
202 | } else { | |
203 | ram_size = low_ram_size; | |
204 | } | |
205 | ||
206 | sys_id = is_pb ? 0x01780500 : 0xc1400400; | |
207 | sysctl = qdev_create(NULL, "realview_sysctl"); | |
208 | qdev_prop_set_uint32(sysctl, "sys_id", sys_id); | |
209 | qdev_init_nofail(sysctl); | |
210 | qdev_prop_set_uint32(sysctl, "proc_id", proc_id); | |
211 | sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000); | |
212 | ||
213 | if (is_mpcore) { | |
214 | dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore"); | |
215 | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); | |
216 | qdev_init_nofail(dev); | |
217 | busdev = sysbus_from_qdev(dev); | |
218 | if (is_pb) { | |
219 | realview_binfo.smp_priv_base = 0x1f000000; | |
220 | } else { | |
221 | realview_binfo.smp_priv_base = 0x10100000; | |
222 | } | |
223 | sysbus_mmio_map(busdev, 0, realview_binfo.smp_priv_base); | |
224 | for (n = 0; n < smp_cpus; n++) { | |
225 | sysbus_connect_irq(busdev, n, cpu_irq[n]); | |
226 | } | |
227 | } else { | |
228 | uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; | |
229 | /* For now just create the nIRQ GIC, and ignore the others. */ | |
230 | dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]); | |
231 | } | |
232 | for (n = 0; n < 64; n++) { | |
233 | pic[n] = qdev_get_gpio_in(dev, n); | |
234 | } | |
235 | ||
236 | sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]); | |
237 | sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]); | |
238 | ||
239 | sysbus_create_simple("pl011", 0x10009000, pic[12]); | |
240 | sysbus_create_simple("pl011", 0x1000a000, pic[13]); | |
241 | sysbus_create_simple("pl011", 0x1000b000, pic[14]); | |
242 | sysbus_create_simple("pl011", 0x1000c000, pic[15]); | |
243 | ||
244 | /* DMA controller is optional, apparently. */ | |
245 | sysbus_create_simple("pl081", 0x10030000, pic[24]); | |
246 | ||
247 | sysbus_create_simple("sp804", 0x10011000, pic[4]); | |
248 | sysbus_create_simple("sp804", 0x10012000, pic[5]); | |
249 | ||
250 | sysbus_create_simple("pl061", 0x10013000, pic[6]); | |
251 | sysbus_create_simple("pl061", 0x10014000, pic[7]); | |
252 | gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]); | |
253 | ||
254 | sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]); | |
255 | ||
256 | dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL); | |
257 | /* Wire up MMC card detect and read-only signals. These have | |
258 | * to go to both the PL061 GPIO and the sysctl register. | |
259 | * Note that the PL181 orders these lines (readonly,inserted) | |
260 | * and the PL061 has them the other way about. Also the card | |
261 | * detect line is inverted. | |
262 | */ | |
263 | mmc_irq[0] = qemu_irq_split( | |
264 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), | |
265 | qdev_get_gpio_in(gpio2, 1)); | |
266 | mmc_irq[1] = qemu_irq_split( | |
267 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), | |
268 | qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); | |
269 | qdev_connect_gpio_out(dev, 0, mmc_irq[0]); | |
270 | qdev_connect_gpio_out(dev, 1, mmc_irq[1]); | |
271 | ||
272 | sysbus_create_simple("pl031", 0x10017000, pic[10]); | |
273 | ||
274 | if (!is_pb) { | |
275 | dev = sysbus_create_varargs("realview_pci", 0x60000000, | |
276 | pic[48], pic[49], pic[50], pic[51], NULL); | |
277 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); | |
278 | if (usb_enabled) { | |
279 | usb_ohci_init_pci(pci_bus, -1); | |
280 | } | |
281 | n = drive_get_max_bus(IF_SCSI); | |
282 | while (n >= 0) { | |
283 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
284 | n--; | |
285 | } | |
286 | } | |
287 | for(n = 0; n < nb_nics; n++) { | |
288 | nd = &nd_table[n]; | |
289 | ||
290 | if (!done_nic && (!nd->model || | |
291 | strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) { | |
292 | if (is_pb) { | |
293 | lan9118_init(nd, 0x4e000000, pic[28]); | |
294 | } else { | |
295 | smc91c111_init(nd, 0x4e000000, pic[28]); | |
296 | } | |
297 | done_nic = 1; | |
298 | } else { | |
299 | pci_nic_init_nofail(nd, "rtl8139", NULL); | |
300 | } | |
301 | } | |
302 | ||
303 | dev = sysbus_create_simple("realview_i2c", 0x10002000, NULL); | |
304 | i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c"); | |
305 | i2c_create_slave(i2c, "ds1338", 0x68); | |
306 | ||
307 | /* Memory map for RealView Emulation Baseboard: */ | |
308 | /* 0x10000000 System registers. */ | |
309 | /* 0x10001000 System controller. */ | |
310 | /* 0x10002000 Two-Wire Serial Bus. */ | |
311 | /* 0x10003000 Reserved. */ | |
312 | /* 0x10004000 AACI. */ | |
313 | /* 0x10005000 MCI. */ | |
314 | /* 0x10006000 KMI0. */ | |
315 | /* 0x10007000 KMI1. */ | |
316 | /* 0x10008000 Character LCD. (EB) */ | |
317 | /* 0x10009000 UART0. */ | |
318 | /* 0x1000a000 UART1. */ | |
319 | /* 0x1000b000 UART2. */ | |
320 | /* 0x1000c000 UART3. */ | |
321 | /* 0x1000d000 SSPI. */ | |
322 | /* 0x1000e000 SCI. */ | |
323 | /* 0x1000f000 Reserved. */ | |
324 | /* 0x10010000 Watchdog. */ | |
325 | /* 0x10011000 Timer 0+1. */ | |
326 | /* 0x10012000 Timer 2+3. */ | |
327 | /* 0x10013000 GPIO 0. */ | |
328 | /* 0x10014000 GPIO 1. */ | |
329 | /* 0x10015000 GPIO 2. */ | |
330 | /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */ | |
331 | /* 0x10017000 RTC. */ | |
332 | /* 0x10018000 DMC. */ | |
333 | /* 0x10019000 PCI controller config. */ | |
334 | /* 0x10020000 CLCD. */ | |
335 | /* 0x10030000 DMA Controller. */ | |
336 | /* 0x10040000 GIC1. (EB) */ | |
337 | /* 0x10050000 GIC2. (EB) */ | |
338 | /* 0x10060000 GIC3. (EB) */ | |
339 | /* 0x10070000 GIC4. (EB) */ | |
340 | /* 0x10080000 SMC. */ | |
341 | /* 0x1e000000 GIC1. (PB) */ | |
342 | /* 0x1e001000 GIC2. (PB) */ | |
343 | /* 0x1e002000 GIC3. (PB) */ | |
344 | /* 0x1e003000 GIC4. (PB) */ | |
345 | /* 0x40000000 NOR flash. */ | |
346 | /* 0x44000000 DoC flash. */ | |
347 | /* 0x48000000 SRAM. */ | |
348 | /* 0x4c000000 Configuration flash. */ | |
349 | /* 0x4e000000 Ethernet. */ | |
350 | /* 0x4f000000 USB. */ | |
351 | /* 0x50000000 PISMO. */ | |
352 | /* 0x54000000 PISMO. */ | |
353 | /* 0x58000000 PISMO. */ | |
354 | /* 0x5c000000 PISMO. */ | |
355 | /* 0x60000000 PCI. */ | |
356 | /* 0x61000000 PCI Self Config. */ | |
357 | /* 0x62000000 PCI Config. */ | |
358 | /* 0x63000000 PCI IO. */ | |
359 | /* 0x64000000 PCI mem 0. */ | |
360 | /* 0x68000000 PCI mem 1. */ | |
361 | /* 0x6c000000 PCI mem 2. */ | |
362 | ||
363 | /* ??? Hack to map an additional page of ram for the secondary CPU | |
364 | startup code. I guess this works on real hardware because the | |
365 | BootROM happens to be in ROM/flash or in memory that isn't clobbered | |
366 | until after Linux boots the secondary CPUs. */ | |
367 | ram_offset = qemu_ram_alloc(NULL, "realview.hack", 0x1000); | |
368 | cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000, | |
369 | ram_offset | IO_MEM_RAM); | |
370 | ||
371 | realview_binfo.ram_size = ram_size; | |
372 | realview_binfo.kernel_filename = kernel_filename; | |
373 | realview_binfo.kernel_cmdline = kernel_cmdline; | |
374 | realview_binfo.initrd_filename = initrd_filename; | |
375 | realview_binfo.nb_cpus = smp_cpus; | |
376 | realview_binfo.board_id = realview_board_id[board_type]; | |
377 | realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0); | |
378 | arm_load_kernel(first_cpu, &realview_binfo); | |
379 | } | |
380 | ||
381 | static void realview_eb_init(ram_addr_t ram_size, | |
382 | const char *boot_device, | |
383 | const char *kernel_filename, const char *kernel_cmdline, | |
384 | const char *initrd_filename, const char *cpu_model) | |
385 | { | |
386 | if (!cpu_model) { | |
387 | cpu_model = "arm926"; | |
388 | } | |
389 | realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, | |
390 | initrd_filename, cpu_model, BOARD_EB); | |
391 | } | |
392 | ||
393 | static void realview_eb_mpcore_init(ram_addr_t ram_size, | |
394 | const char *boot_device, | |
395 | const char *kernel_filename, const char *kernel_cmdline, | |
396 | const char *initrd_filename, const char *cpu_model) | |
397 | { | |
398 | if (!cpu_model) { | |
399 | cpu_model = "arm11mpcore"; | |
400 | } | |
401 | realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, | |
402 | initrd_filename, cpu_model, BOARD_EB_MPCORE); | |
403 | } | |
404 | ||
405 | static void realview_pb_a8_init(ram_addr_t ram_size, | |
406 | const char *boot_device, | |
407 | const char *kernel_filename, const char *kernel_cmdline, | |
408 | const char *initrd_filename, const char *cpu_model) | |
409 | { | |
410 | if (!cpu_model) { | |
411 | cpu_model = "cortex-a8"; | |
412 | } | |
413 | realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, | |
414 | initrd_filename, cpu_model, BOARD_PB_A8); | |
415 | } | |
416 | ||
417 | static void realview_pbx_a9_init(ram_addr_t ram_size, | |
418 | const char *boot_device, | |
419 | const char *kernel_filename, const char *kernel_cmdline, | |
420 | const char *initrd_filename, const char *cpu_model) | |
421 | { | |
422 | if (!cpu_model) { | |
423 | cpu_model = "cortex-a9"; | |
424 | } | |
425 | realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, | |
426 | initrd_filename, cpu_model, BOARD_PBX_A9); | |
427 | } | |
428 | ||
429 | static QEMUMachine realview_eb_machine = { | |
430 | .name = "realview-eb", | |
431 | .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)", | |
432 | .init = realview_eb_init, | |
433 | .use_scsi = 1, | |
434 | }; | |
435 | ||
436 | static QEMUMachine realview_eb_mpcore_machine = { | |
437 | .name = "realview-eb-mpcore", | |
438 | .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)", | |
439 | .init = realview_eb_mpcore_init, | |
440 | .use_scsi = 1, | |
441 | .max_cpus = 4, | |
442 | }; | |
443 | ||
444 | static QEMUMachine realview_pb_a8_machine = { | |
445 | .name = "realview-pb-a8", | |
446 | .desc = "ARM RealView Platform Baseboard for Cortex-A8", | |
447 | .init = realview_pb_a8_init, | |
448 | }; | |
449 | ||
450 | static QEMUMachine realview_pbx_a9_machine = { | |
451 | .name = "realview-pbx-a9", | |
452 | .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9", | |
453 | .init = realview_pbx_a9_init, | |
454 | .use_scsi = 1, | |
455 | .max_cpus = 4, | |
456 | }; | |
457 | ||
458 | static void realview_machine_init(void) | |
459 | { | |
460 | qemu_register_machine(&realview_eb_machine); | |
461 | qemu_register_machine(&realview_eb_mpcore_machine); | |
462 | qemu_register_machine(&realview_pb_a8_machine); | |
463 | qemu_register_machine(&realview_pbx_a9_machine); | |
464 | } | |
465 | ||
466 | machine_init(realview_machine_init); | |
467 | device_init(realview_register_devices) |