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1 | /* | |
2 | * QEMU Sparc SBI interrupt controller emulation | |
3 | * | |
4 | * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "sysbus.h" | |
26 | ||
27 | //#define DEBUG_IRQ | |
28 | ||
29 | #ifdef DEBUG_IRQ | |
30 | #define DPRINTF(fmt, ...) \ | |
31 | do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0) | |
32 | #else | |
33 | #define DPRINTF(fmt, ...) | |
34 | #endif | |
35 | ||
36 | #define MAX_CPUS 16 | |
37 | ||
38 | #define SBI_NREGS 16 | |
39 | ||
40 | typedef struct SBIState { | |
41 | SysBusDevice busdev; | |
42 | uint32_t regs[SBI_NREGS]; | |
43 | uint32_t intreg_pending[MAX_CPUS]; | |
44 | qemu_irq cpu_irqs[MAX_CPUS]; | |
45 | uint32_t pil_out[MAX_CPUS]; | |
46 | } SBIState; | |
47 | ||
48 | #define SBI_SIZE (SBI_NREGS * 4) | |
49 | ||
50 | static void sbi_set_irq(void *opaque, int irq, int level) | |
51 | { | |
52 | } | |
53 | ||
54 | static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr) | |
55 | { | |
56 | SBIState *s = opaque; | |
57 | uint32_t saddr, ret; | |
58 | ||
59 | saddr = addr >> 2; | |
60 | switch (saddr) { | |
61 | default: | |
62 | ret = s->regs[saddr]; | |
63 | break; | |
64 | } | |
65 | DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret); | |
66 | ||
67 | return ret; | |
68 | } | |
69 | ||
70 | static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) | |
71 | { | |
72 | SBIState *s = opaque; | |
73 | uint32_t saddr; | |
74 | ||
75 | saddr = addr >> 2; | |
76 | DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val); | |
77 | switch (saddr) { | |
78 | default: | |
79 | s->regs[saddr] = val; | |
80 | break; | |
81 | } | |
82 | } | |
83 | ||
84 | static CPUReadMemoryFunc * const sbi_mem_read[3] = { | |
85 | NULL, | |
86 | NULL, | |
87 | sbi_mem_readl, | |
88 | }; | |
89 | ||
90 | static CPUWriteMemoryFunc * const sbi_mem_write[3] = { | |
91 | NULL, | |
92 | NULL, | |
93 | sbi_mem_writel, | |
94 | }; | |
95 | ||
96 | static const VMStateDescription vmstate_sbi = { | |
97 | .name ="sbi", | |
98 | .version_id = 1, | |
99 | .minimum_version_id = 1, | |
100 | .minimum_version_id_old = 1, | |
101 | .fields = (VMStateField []) { | |
102 | VMSTATE_UINT32_ARRAY(intreg_pending, SBIState, MAX_CPUS), | |
103 | VMSTATE_END_OF_LIST() | |
104 | } | |
105 | }; | |
106 | ||
107 | static void sbi_reset(DeviceState *d) | |
108 | { | |
109 | SBIState *s = container_of(d, SBIState, busdev.qdev); | |
110 | unsigned int i; | |
111 | ||
112 | for (i = 0; i < MAX_CPUS; i++) { | |
113 | s->intreg_pending[i] = 0; | |
114 | } | |
115 | } | |
116 | ||
117 | static int sbi_init1(SysBusDevice *dev) | |
118 | { | |
119 | SBIState *s = FROM_SYSBUS(SBIState, dev); | |
120 | int sbi_io_memory; | |
121 | unsigned int i; | |
122 | ||
123 | qdev_init_gpio_in(&dev->qdev, sbi_set_irq, 32 + MAX_CPUS); | |
124 | for (i = 0; i < MAX_CPUS; i++) { | |
125 | sysbus_init_irq(dev, &s->cpu_irqs[i]); | |
126 | } | |
127 | ||
128 | sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s, | |
129 | DEVICE_NATIVE_ENDIAN); | |
130 | sysbus_init_mmio(dev, SBI_SIZE, sbi_io_memory); | |
131 | ||
132 | return 0; | |
133 | } | |
134 | ||
135 | static SysBusDeviceInfo sbi_info = { | |
136 | .init = sbi_init1, | |
137 | .qdev.name = "sbi", | |
138 | .qdev.size = sizeof(SBIState), | |
139 | .qdev.vmsd = &vmstate_sbi, | |
140 | .qdev.reset = sbi_reset, | |
141 | }; | |
142 | ||
143 | static void sbi_register_devices(void) | |
144 | { | |
145 | sysbus_register_withprop(&sbi_info); | |
146 | } | |
147 | ||
148 | device_init(sbi_register_devices) |