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1 | /* | |
2 | * USB UHCI controller emulation | |
3 | * | |
4 | * Copyright (c) 2005 Fabrice Bellard | |
5 | * | |
6 | * Copyright (c) 2008 Max Krasnyansky | |
7 | * Magor rewrite of the UHCI data structures parser and frame processor | |
8 | * Support for fully async operation and multiple outstanding transactions | |
9 | * | |
10 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
11 | * of this software and associated documentation files (the "Software"), to deal | |
12 | * in the Software without restriction, including without limitation the rights | |
13 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
14 | * copies of the Software, and to permit persons to whom the Software is | |
15 | * furnished to do so, subject to the following conditions: | |
16 | * | |
17 | * The above copyright notice and this permission notice shall be included in | |
18 | * all copies or substantial portions of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
21 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
22 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
23 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
24 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
25 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
26 | * THE SOFTWARE. | |
27 | */ | |
28 | #include "hw/hw.h" | |
29 | #include "hw/usb.h" | |
30 | #include "hw/pci.h" | |
31 | #include "qemu-timer.h" | |
32 | #include "iov.h" | |
33 | #include "dma.h" | |
34 | #include "trace.h" | |
35 | ||
36 | //#define DEBUG | |
37 | //#define DEBUG_DUMP_DATA | |
38 | ||
39 | #define UHCI_CMD_FGR (1 << 4) | |
40 | #define UHCI_CMD_EGSM (1 << 3) | |
41 | #define UHCI_CMD_GRESET (1 << 2) | |
42 | #define UHCI_CMD_HCRESET (1 << 1) | |
43 | #define UHCI_CMD_RS (1 << 0) | |
44 | ||
45 | #define UHCI_STS_HCHALTED (1 << 5) | |
46 | #define UHCI_STS_HCPERR (1 << 4) | |
47 | #define UHCI_STS_HSERR (1 << 3) | |
48 | #define UHCI_STS_RD (1 << 2) | |
49 | #define UHCI_STS_USBERR (1 << 1) | |
50 | #define UHCI_STS_USBINT (1 << 0) | |
51 | ||
52 | #define TD_CTRL_SPD (1 << 29) | |
53 | #define TD_CTRL_ERROR_SHIFT 27 | |
54 | #define TD_CTRL_IOS (1 << 25) | |
55 | #define TD_CTRL_IOC (1 << 24) | |
56 | #define TD_CTRL_ACTIVE (1 << 23) | |
57 | #define TD_CTRL_STALL (1 << 22) | |
58 | #define TD_CTRL_BABBLE (1 << 20) | |
59 | #define TD_CTRL_NAK (1 << 19) | |
60 | #define TD_CTRL_TIMEOUT (1 << 18) | |
61 | ||
62 | #define UHCI_PORT_SUSPEND (1 << 12) | |
63 | #define UHCI_PORT_RESET (1 << 9) | |
64 | #define UHCI_PORT_LSDA (1 << 8) | |
65 | #define UHCI_PORT_RD (1 << 6) | |
66 | #define UHCI_PORT_ENC (1 << 3) | |
67 | #define UHCI_PORT_EN (1 << 2) | |
68 | #define UHCI_PORT_CSC (1 << 1) | |
69 | #define UHCI_PORT_CCS (1 << 0) | |
70 | ||
71 | #define UHCI_PORT_READ_ONLY (0x1bb) | |
72 | #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC) | |
73 | ||
74 | #define FRAME_TIMER_FREQ 1000 | |
75 | ||
76 | #define FRAME_MAX_LOOPS 256 | |
77 | ||
78 | #define NB_PORTS 2 | |
79 | ||
80 | enum { | |
81 | TD_RESULT_STOP_FRAME = 10, | |
82 | TD_RESULT_COMPLETE, | |
83 | TD_RESULT_NEXT_QH, | |
84 | TD_RESULT_ASYNC_START, | |
85 | TD_RESULT_ASYNC_CONT, | |
86 | }; | |
87 | ||
88 | typedef struct UHCIState UHCIState; | |
89 | typedef struct UHCIAsync UHCIAsync; | |
90 | typedef struct UHCIQueue UHCIQueue; | |
91 | ||
92 | /* | |
93 | * Pending async transaction. | |
94 | * 'packet' must be the first field because completion | |
95 | * handler does "(UHCIAsync *) pkt" cast. | |
96 | */ | |
97 | ||
98 | struct UHCIAsync { | |
99 | USBPacket packet; | |
100 | QEMUSGList sgl; | |
101 | UHCIQueue *queue; | |
102 | QTAILQ_ENTRY(UHCIAsync) next; | |
103 | uint32_t td; | |
104 | uint8_t isoc; | |
105 | uint8_t done; | |
106 | }; | |
107 | ||
108 | struct UHCIQueue { | |
109 | uint32_t token; | |
110 | UHCIState *uhci; | |
111 | QTAILQ_ENTRY(UHCIQueue) next; | |
112 | QTAILQ_HEAD(, UHCIAsync) asyncs; | |
113 | int8_t valid; | |
114 | }; | |
115 | ||
116 | typedef struct UHCIPort { | |
117 | USBPort port; | |
118 | uint16_t ctrl; | |
119 | } UHCIPort; | |
120 | ||
121 | struct UHCIState { | |
122 | PCIDevice dev; | |
123 | MemoryRegion io_bar; | |
124 | USBBus bus; /* Note unused when we're a companion controller */ | |
125 | uint16_t cmd; /* cmd register */ | |
126 | uint16_t status; | |
127 | uint16_t intr; /* interrupt enable register */ | |
128 | uint16_t frnum; /* frame number */ | |
129 | uint32_t fl_base_addr; /* frame list base address */ | |
130 | uint8_t sof_timing; | |
131 | uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ | |
132 | int64_t expire_time; | |
133 | QEMUTimer *frame_timer; | |
134 | QEMUBH *bh; | |
135 | uint32_t frame_bytes; | |
136 | uint32_t frame_bandwidth; | |
137 | UHCIPort ports[NB_PORTS]; | |
138 | ||
139 | /* Interrupts that should be raised at the end of the current frame. */ | |
140 | uint32_t pending_int_mask; | |
141 | int irq_pin; | |
142 | ||
143 | /* Active packets */ | |
144 | QTAILQ_HEAD(, UHCIQueue) queues; | |
145 | uint8_t num_ports_vmstate; | |
146 | ||
147 | /* Properties */ | |
148 | char *masterbus; | |
149 | uint32_t firstport; | |
150 | }; | |
151 | ||
152 | typedef struct UHCI_TD { | |
153 | uint32_t link; | |
154 | uint32_t ctrl; /* see TD_CTRL_xxx */ | |
155 | uint32_t token; | |
156 | uint32_t buffer; | |
157 | } UHCI_TD; | |
158 | ||
159 | typedef struct UHCI_QH { | |
160 | uint32_t link; | |
161 | uint32_t el_link; | |
162 | } UHCI_QH; | |
163 | ||
164 | static inline int32_t uhci_queue_token(UHCI_TD *td) | |
165 | { | |
166 | /* covers ep, dev, pid -> identifies the endpoint */ | |
167 | return td->token & 0x7ffff; | |
168 | } | |
169 | ||
170 | static UHCIQueue *uhci_queue_get(UHCIState *s, UHCI_TD *td) | |
171 | { | |
172 | uint32_t token = uhci_queue_token(td); | |
173 | UHCIQueue *queue; | |
174 | ||
175 | QTAILQ_FOREACH(queue, &s->queues, next) { | |
176 | if (queue->token == token) { | |
177 | return queue; | |
178 | } | |
179 | } | |
180 | ||
181 | queue = g_new0(UHCIQueue, 1); | |
182 | queue->uhci = s; | |
183 | queue->token = token; | |
184 | QTAILQ_INIT(&queue->asyncs); | |
185 | QTAILQ_INSERT_HEAD(&s->queues, queue, next); | |
186 | trace_usb_uhci_queue_add(queue->token); | |
187 | return queue; | |
188 | } | |
189 | ||
190 | static void uhci_queue_free(UHCIQueue *queue) | |
191 | { | |
192 | UHCIState *s = queue->uhci; | |
193 | ||
194 | trace_usb_uhci_queue_del(queue->token); | |
195 | QTAILQ_REMOVE(&s->queues, queue, next); | |
196 | g_free(queue); | |
197 | } | |
198 | ||
199 | static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t addr) | |
200 | { | |
201 | UHCIAsync *async = g_new0(UHCIAsync, 1); | |
202 | ||
203 | async->queue = queue; | |
204 | async->td = addr; | |
205 | usb_packet_init(&async->packet); | |
206 | pci_dma_sglist_init(&async->sgl, &queue->uhci->dev, 1); | |
207 | trace_usb_uhci_packet_add(async->queue->token, async->td); | |
208 | ||
209 | return async; | |
210 | } | |
211 | ||
212 | static void uhci_async_free(UHCIAsync *async) | |
213 | { | |
214 | trace_usb_uhci_packet_del(async->queue->token, async->td); | |
215 | usb_packet_cleanup(&async->packet); | |
216 | qemu_sglist_destroy(&async->sgl); | |
217 | g_free(async); | |
218 | } | |
219 | ||
220 | static void uhci_async_link(UHCIAsync *async) | |
221 | { | |
222 | UHCIQueue *queue = async->queue; | |
223 | QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); | |
224 | trace_usb_uhci_packet_link_async(async->queue->token, async->td); | |
225 | } | |
226 | ||
227 | static void uhci_async_unlink(UHCIAsync *async) | |
228 | { | |
229 | UHCIQueue *queue = async->queue; | |
230 | QTAILQ_REMOVE(&queue->asyncs, async, next); | |
231 | trace_usb_uhci_packet_unlink_async(async->queue->token, async->td); | |
232 | } | |
233 | ||
234 | static void uhci_async_cancel(UHCIAsync *async) | |
235 | { | |
236 | trace_usb_uhci_packet_cancel(async->queue->token, async->td, async->done); | |
237 | if (!async->done) | |
238 | usb_cancel_packet(&async->packet); | |
239 | uhci_async_free(async); | |
240 | } | |
241 | ||
242 | /* | |
243 | * Mark all outstanding async packets as invalid. | |
244 | * This is used for canceling them when TDs are removed by the HCD. | |
245 | */ | |
246 | static void uhci_async_validate_begin(UHCIState *s) | |
247 | { | |
248 | UHCIQueue *queue; | |
249 | ||
250 | QTAILQ_FOREACH(queue, &s->queues, next) { | |
251 | queue->valid--; | |
252 | } | |
253 | } | |
254 | ||
255 | /* | |
256 | * Cancel async packets that are no longer valid | |
257 | */ | |
258 | static void uhci_async_validate_end(UHCIState *s) | |
259 | { | |
260 | UHCIQueue *queue, *n; | |
261 | UHCIAsync *async; | |
262 | ||
263 | QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { | |
264 | if (queue->valid > 0) { | |
265 | continue; | |
266 | } | |
267 | while (!QTAILQ_EMPTY(&queue->asyncs)) { | |
268 | async = QTAILQ_FIRST(&queue->asyncs); | |
269 | uhci_async_unlink(async); | |
270 | uhci_async_cancel(async); | |
271 | } | |
272 | uhci_queue_free(queue); | |
273 | } | |
274 | } | |
275 | ||
276 | static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) | |
277 | { | |
278 | UHCIQueue *queue; | |
279 | UHCIAsync *curr, *n; | |
280 | ||
281 | QTAILQ_FOREACH(queue, &s->queues, next) { | |
282 | QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) { | |
283 | if (!usb_packet_is_inflight(&curr->packet) || | |
284 | curr->packet.ep->dev != dev) { | |
285 | continue; | |
286 | } | |
287 | uhci_async_unlink(curr); | |
288 | uhci_async_cancel(curr); | |
289 | } | |
290 | } | |
291 | } | |
292 | ||
293 | static void uhci_async_cancel_all(UHCIState *s) | |
294 | { | |
295 | UHCIQueue *queue, *nq; | |
296 | UHCIAsync *curr, *n; | |
297 | ||
298 | QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { | |
299 | QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) { | |
300 | uhci_async_unlink(curr); | |
301 | uhci_async_cancel(curr); | |
302 | } | |
303 | uhci_queue_free(queue); | |
304 | } | |
305 | } | |
306 | ||
307 | static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, UHCI_TD *td) | |
308 | { | |
309 | uint32_t token = uhci_queue_token(td); | |
310 | UHCIQueue *queue; | |
311 | UHCIAsync *async; | |
312 | ||
313 | QTAILQ_FOREACH(queue, &s->queues, next) { | |
314 | if (queue->token == token) { | |
315 | break; | |
316 | } | |
317 | } | |
318 | if (queue == NULL) { | |
319 | return NULL; | |
320 | } | |
321 | ||
322 | QTAILQ_FOREACH(async, &queue->asyncs, next) { | |
323 | if (async->td == addr) { | |
324 | return async; | |
325 | } | |
326 | } | |
327 | ||
328 | return NULL; | |
329 | } | |
330 | ||
331 | static void uhci_update_irq(UHCIState *s) | |
332 | { | |
333 | int level; | |
334 | if (((s->status2 & 1) && (s->intr & (1 << 2))) || | |
335 | ((s->status2 & 2) && (s->intr & (1 << 3))) || | |
336 | ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || | |
337 | ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || | |
338 | (s->status & UHCI_STS_HSERR) || | |
339 | (s->status & UHCI_STS_HCPERR)) { | |
340 | level = 1; | |
341 | } else { | |
342 | level = 0; | |
343 | } | |
344 | qemu_set_irq(s->dev.irq[s->irq_pin], level); | |
345 | } | |
346 | ||
347 | static void uhci_reset(void *opaque) | |
348 | { | |
349 | UHCIState *s = opaque; | |
350 | uint8_t *pci_conf; | |
351 | int i; | |
352 | UHCIPort *port; | |
353 | ||
354 | trace_usb_uhci_reset(); | |
355 | ||
356 | pci_conf = s->dev.config; | |
357 | ||
358 | pci_conf[0x6a] = 0x01; /* usb clock */ | |
359 | pci_conf[0x6b] = 0x00; | |
360 | s->cmd = 0; | |
361 | s->status = 0; | |
362 | s->status2 = 0; | |
363 | s->intr = 0; | |
364 | s->fl_base_addr = 0; | |
365 | s->sof_timing = 64; | |
366 | ||
367 | for(i = 0; i < NB_PORTS; i++) { | |
368 | port = &s->ports[i]; | |
369 | port->ctrl = 0x0080; | |
370 | if (port->port.dev && port->port.dev->attached) { | |
371 | usb_port_reset(&port->port); | |
372 | } | |
373 | } | |
374 | ||
375 | uhci_async_cancel_all(s); | |
376 | qemu_bh_cancel(s->bh); | |
377 | uhci_update_irq(s); | |
378 | } | |
379 | ||
380 | static const VMStateDescription vmstate_uhci_port = { | |
381 | .name = "uhci port", | |
382 | .version_id = 1, | |
383 | .minimum_version_id = 1, | |
384 | .minimum_version_id_old = 1, | |
385 | .fields = (VMStateField []) { | |
386 | VMSTATE_UINT16(ctrl, UHCIPort), | |
387 | VMSTATE_END_OF_LIST() | |
388 | } | |
389 | }; | |
390 | ||
391 | static int uhci_post_load(void *opaque, int version_id) | |
392 | { | |
393 | UHCIState *s = opaque; | |
394 | ||
395 | if (version_id < 2) { | |
396 | s->expire_time = qemu_get_clock_ns(vm_clock) + | |
397 | (get_ticks_per_sec() / FRAME_TIMER_FREQ); | |
398 | } | |
399 | return 0; | |
400 | } | |
401 | ||
402 | static const VMStateDescription vmstate_uhci = { | |
403 | .name = "uhci", | |
404 | .version_id = 2, | |
405 | .minimum_version_id = 1, | |
406 | .minimum_version_id_old = 1, | |
407 | .post_load = uhci_post_load, | |
408 | .fields = (VMStateField []) { | |
409 | VMSTATE_PCI_DEVICE(dev, UHCIState), | |
410 | VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), | |
411 | VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, | |
412 | vmstate_uhci_port, UHCIPort), | |
413 | VMSTATE_UINT16(cmd, UHCIState), | |
414 | VMSTATE_UINT16(status, UHCIState), | |
415 | VMSTATE_UINT16(intr, UHCIState), | |
416 | VMSTATE_UINT16(frnum, UHCIState), | |
417 | VMSTATE_UINT32(fl_base_addr, UHCIState), | |
418 | VMSTATE_UINT8(sof_timing, UHCIState), | |
419 | VMSTATE_UINT8(status2, UHCIState), | |
420 | VMSTATE_TIMER(frame_timer, UHCIState), | |
421 | VMSTATE_INT64_V(expire_time, UHCIState, 2), | |
422 | VMSTATE_END_OF_LIST() | |
423 | } | |
424 | }; | |
425 | ||
426 | static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) | |
427 | { | |
428 | UHCIState *s = opaque; | |
429 | ||
430 | addr &= 0x1f; | |
431 | switch(addr) { | |
432 | case 0x0c: | |
433 | s->sof_timing = val; | |
434 | break; | |
435 | } | |
436 | } | |
437 | ||
438 | static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) | |
439 | { | |
440 | UHCIState *s = opaque; | |
441 | uint32_t val; | |
442 | ||
443 | addr &= 0x1f; | |
444 | switch(addr) { | |
445 | case 0x0c: | |
446 | val = s->sof_timing; | |
447 | break; | |
448 | default: | |
449 | val = 0xff; | |
450 | break; | |
451 | } | |
452 | return val; | |
453 | } | |
454 | ||
455 | static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) | |
456 | { | |
457 | UHCIState *s = opaque; | |
458 | ||
459 | addr &= 0x1f; | |
460 | trace_usb_uhci_mmio_writew(addr, val); | |
461 | ||
462 | switch(addr) { | |
463 | case 0x00: | |
464 | if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { | |
465 | /* start frame processing */ | |
466 | trace_usb_uhci_schedule_start(); | |
467 | s->expire_time = qemu_get_clock_ns(vm_clock) + | |
468 | (get_ticks_per_sec() / FRAME_TIMER_FREQ); | |
469 | qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); | |
470 | s->status &= ~UHCI_STS_HCHALTED; | |
471 | } else if (!(val & UHCI_CMD_RS)) { | |
472 | s->status |= UHCI_STS_HCHALTED; | |
473 | } | |
474 | if (val & UHCI_CMD_GRESET) { | |
475 | UHCIPort *port; | |
476 | int i; | |
477 | ||
478 | /* send reset on the USB bus */ | |
479 | for(i = 0; i < NB_PORTS; i++) { | |
480 | port = &s->ports[i]; | |
481 | usb_device_reset(port->port.dev); | |
482 | } | |
483 | uhci_reset(s); | |
484 | return; | |
485 | } | |
486 | if (val & UHCI_CMD_HCRESET) { | |
487 | uhci_reset(s); | |
488 | return; | |
489 | } | |
490 | s->cmd = val; | |
491 | break; | |
492 | case 0x02: | |
493 | s->status &= ~val; | |
494 | /* XXX: the chip spec is not coherent, so we add a hidden | |
495 | register to distinguish between IOC and SPD */ | |
496 | if (val & UHCI_STS_USBINT) | |
497 | s->status2 = 0; | |
498 | uhci_update_irq(s); | |
499 | break; | |
500 | case 0x04: | |
501 | s->intr = val; | |
502 | uhci_update_irq(s); | |
503 | break; | |
504 | case 0x06: | |
505 | if (s->status & UHCI_STS_HCHALTED) | |
506 | s->frnum = val & 0x7ff; | |
507 | break; | |
508 | case 0x10 ... 0x1f: | |
509 | { | |
510 | UHCIPort *port; | |
511 | USBDevice *dev; | |
512 | int n; | |
513 | ||
514 | n = (addr >> 1) & 7; | |
515 | if (n >= NB_PORTS) | |
516 | return; | |
517 | port = &s->ports[n]; | |
518 | dev = port->port.dev; | |
519 | if (dev && dev->attached) { | |
520 | /* port reset */ | |
521 | if ( (val & UHCI_PORT_RESET) && | |
522 | !(port->ctrl & UHCI_PORT_RESET) ) { | |
523 | usb_device_reset(dev); | |
524 | } | |
525 | } | |
526 | port->ctrl &= UHCI_PORT_READ_ONLY; | |
527 | port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); | |
528 | /* some bits are reset when a '1' is written to them */ | |
529 | port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); | |
530 | } | |
531 | break; | |
532 | } | |
533 | } | |
534 | ||
535 | static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) | |
536 | { | |
537 | UHCIState *s = opaque; | |
538 | uint32_t val; | |
539 | ||
540 | addr &= 0x1f; | |
541 | switch(addr) { | |
542 | case 0x00: | |
543 | val = s->cmd; | |
544 | break; | |
545 | case 0x02: | |
546 | val = s->status; | |
547 | break; | |
548 | case 0x04: | |
549 | val = s->intr; | |
550 | break; | |
551 | case 0x06: | |
552 | val = s->frnum; | |
553 | break; | |
554 | case 0x10 ... 0x1f: | |
555 | { | |
556 | UHCIPort *port; | |
557 | int n; | |
558 | n = (addr >> 1) & 7; | |
559 | if (n >= NB_PORTS) | |
560 | goto read_default; | |
561 | port = &s->ports[n]; | |
562 | val = port->ctrl; | |
563 | } | |
564 | break; | |
565 | default: | |
566 | read_default: | |
567 | val = 0xff7f; /* disabled port */ | |
568 | break; | |
569 | } | |
570 | ||
571 | trace_usb_uhci_mmio_readw(addr, val); | |
572 | ||
573 | return val; | |
574 | } | |
575 | ||
576 | static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) | |
577 | { | |
578 | UHCIState *s = opaque; | |
579 | ||
580 | addr &= 0x1f; | |
581 | trace_usb_uhci_mmio_writel(addr, val); | |
582 | ||
583 | switch(addr) { | |
584 | case 0x08: | |
585 | s->fl_base_addr = val & ~0xfff; | |
586 | break; | |
587 | } | |
588 | } | |
589 | ||
590 | static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) | |
591 | { | |
592 | UHCIState *s = opaque; | |
593 | uint32_t val; | |
594 | ||
595 | addr &= 0x1f; | |
596 | switch(addr) { | |
597 | case 0x08: | |
598 | val = s->fl_base_addr; | |
599 | break; | |
600 | default: | |
601 | val = 0xffffffff; | |
602 | break; | |
603 | } | |
604 | trace_usb_uhci_mmio_readl(addr, val); | |
605 | return val; | |
606 | } | |
607 | ||
608 | /* signal resume if controller suspended */ | |
609 | static void uhci_resume (void *opaque) | |
610 | { | |
611 | UHCIState *s = (UHCIState *)opaque; | |
612 | ||
613 | if (!s) | |
614 | return; | |
615 | ||
616 | if (s->cmd & UHCI_CMD_EGSM) { | |
617 | s->cmd |= UHCI_CMD_FGR; | |
618 | s->status |= UHCI_STS_RD; | |
619 | uhci_update_irq(s); | |
620 | } | |
621 | } | |
622 | ||
623 | static void uhci_attach(USBPort *port1) | |
624 | { | |
625 | UHCIState *s = port1->opaque; | |
626 | UHCIPort *port = &s->ports[port1->index]; | |
627 | ||
628 | /* set connect status */ | |
629 | port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; | |
630 | ||
631 | /* update speed */ | |
632 | if (port->port.dev->speed == USB_SPEED_LOW) { | |
633 | port->ctrl |= UHCI_PORT_LSDA; | |
634 | } else { | |
635 | port->ctrl &= ~UHCI_PORT_LSDA; | |
636 | } | |
637 | ||
638 | uhci_resume(s); | |
639 | } | |
640 | ||
641 | static void uhci_detach(USBPort *port1) | |
642 | { | |
643 | UHCIState *s = port1->opaque; | |
644 | UHCIPort *port = &s->ports[port1->index]; | |
645 | ||
646 | uhci_async_cancel_device(s, port1->dev); | |
647 | ||
648 | /* set connect status */ | |
649 | if (port->ctrl & UHCI_PORT_CCS) { | |
650 | port->ctrl &= ~UHCI_PORT_CCS; | |
651 | port->ctrl |= UHCI_PORT_CSC; | |
652 | } | |
653 | /* disable port */ | |
654 | if (port->ctrl & UHCI_PORT_EN) { | |
655 | port->ctrl &= ~UHCI_PORT_EN; | |
656 | port->ctrl |= UHCI_PORT_ENC; | |
657 | } | |
658 | ||
659 | uhci_resume(s); | |
660 | } | |
661 | ||
662 | static void uhci_child_detach(USBPort *port1, USBDevice *child) | |
663 | { | |
664 | UHCIState *s = port1->opaque; | |
665 | ||
666 | uhci_async_cancel_device(s, child); | |
667 | } | |
668 | ||
669 | static void uhci_wakeup(USBPort *port1) | |
670 | { | |
671 | UHCIState *s = port1->opaque; | |
672 | UHCIPort *port = &s->ports[port1->index]; | |
673 | ||
674 | if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { | |
675 | port->ctrl |= UHCI_PORT_RD; | |
676 | uhci_resume(s); | |
677 | } | |
678 | } | |
679 | ||
680 | static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) | |
681 | { | |
682 | USBDevice *dev; | |
683 | int i; | |
684 | ||
685 | for (i = 0; i < NB_PORTS; i++) { | |
686 | UHCIPort *port = &s->ports[i]; | |
687 | if (!(port->ctrl & UHCI_PORT_EN)) { | |
688 | continue; | |
689 | } | |
690 | dev = usb_find_device(&port->port, addr); | |
691 | if (dev != NULL) { | |
692 | return dev; | |
693 | } | |
694 | } | |
695 | return NULL; | |
696 | } | |
697 | ||
698 | static void uhci_async_complete(USBPort *port, USBPacket *packet); | |
699 | static void uhci_process_frame(UHCIState *s); | |
700 | ||
701 | /* return -1 if fatal error (frame must be stopped) | |
702 | 0 if TD successful | |
703 | 1 if TD unsuccessful or inactive | |
704 | */ | |
705 | static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) | |
706 | { | |
707 | int len = 0, max_len, err, ret; | |
708 | uint8_t pid; | |
709 | ||
710 | max_len = ((td->token >> 21) + 1) & 0x7ff; | |
711 | pid = td->token & 0xff; | |
712 | ||
713 | ret = async->packet.result; | |
714 | ||
715 | if (td->ctrl & TD_CTRL_IOS) | |
716 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
717 | ||
718 | if (ret < 0) | |
719 | goto out; | |
720 | ||
721 | len = async->packet.result; | |
722 | td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); | |
723 | ||
724 | /* The NAK bit may have been set by a previous frame, so clear it | |
725 | here. The docs are somewhat unclear, but win2k relies on this | |
726 | behavior. */ | |
727 | td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); | |
728 | if (td->ctrl & TD_CTRL_IOC) | |
729 | *int_mask |= 0x01; | |
730 | ||
731 | if (pid == USB_TOKEN_IN) { | |
732 | if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { | |
733 | *int_mask |= 0x02; | |
734 | /* short packet: do not update QH */ | |
735 | trace_usb_uhci_packet_complete_shortxfer(async->queue->token, | |
736 | async->td); | |
737 | return TD_RESULT_NEXT_QH; | |
738 | } | |
739 | } | |
740 | ||
741 | /* success */ | |
742 | trace_usb_uhci_packet_complete_success(async->queue->token, async->td); | |
743 | return TD_RESULT_COMPLETE; | |
744 | ||
745 | out: | |
746 | /* | |
747 | * We should not do any further processing on a queue with errors! | |
748 | * This is esp. important for bulk endpoints with pipelining enabled | |
749 | * (redirection to a real USB device), where we must cancel all the | |
750 | * transfers after this one so that: | |
751 | * 1) If they've completed already, they are not processed further | |
752 | * causing more stalls, originating from the same failed transfer | |
753 | * 2) If still in flight, they are cancelled before the guest does | |
754 | * a clear stall, otherwise the guest and device can loose sync! | |
755 | */ | |
756 | while (!QTAILQ_EMPTY(&async->queue->asyncs)) { | |
757 | UHCIAsync *as = QTAILQ_FIRST(&async->queue->asyncs); | |
758 | uhci_async_unlink(as); | |
759 | uhci_async_cancel(as); | |
760 | } | |
761 | ||
762 | switch(ret) { | |
763 | case USB_RET_STALL: | |
764 | td->ctrl |= TD_CTRL_STALL; | |
765 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
766 | s->status |= UHCI_STS_USBERR; | |
767 | if (td->ctrl & TD_CTRL_IOC) { | |
768 | *int_mask |= 0x01; | |
769 | } | |
770 | uhci_update_irq(s); | |
771 | trace_usb_uhci_packet_complete_stall(async->queue->token, async->td); | |
772 | return TD_RESULT_NEXT_QH; | |
773 | ||
774 | case USB_RET_BABBLE: | |
775 | td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; | |
776 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
777 | s->status |= UHCI_STS_USBERR; | |
778 | if (td->ctrl & TD_CTRL_IOC) { | |
779 | *int_mask |= 0x01; | |
780 | } | |
781 | uhci_update_irq(s); | |
782 | /* frame interrupted */ | |
783 | trace_usb_uhci_packet_complete_babble(async->queue->token, async->td); | |
784 | return TD_RESULT_STOP_FRAME; | |
785 | ||
786 | case USB_RET_NAK: | |
787 | td->ctrl |= TD_CTRL_NAK; | |
788 | if (pid == USB_TOKEN_SETUP) | |
789 | break; | |
790 | return TD_RESULT_NEXT_QH; | |
791 | ||
792 | case USB_RET_IOERROR: | |
793 | case USB_RET_NODEV: | |
794 | default: | |
795 | break; | |
796 | } | |
797 | ||
798 | /* Retry the TD if error count is not zero */ | |
799 | ||
800 | td->ctrl |= TD_CTRL_TIMEOUT; | |
801 | err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3; | |
802 | if (err != 0) { | |
803 | err--; | |
804 | if (err == 0) { | |
805 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
806 | s->status |= UHCI_STS_USBERR; | |
807 | if (td->ctrl & TD_CTRL_IOC) | |
808 | *int_mask |= 0x01; | |
809 | uhci_update_irq(s); | |
810 | trace_usb_uhci_packet_complete_error(async->queue->token, | |
811 | async->td); | |
812 | } | |
813 | } | |
814 | td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) | | |
815 | (err << TD_CTRL_ERROR_SHIFT); | |
816 | return TD_RESULT_NEXT_QH; | |
817 | } | |
818 | ||
819 | static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, | |
820 | uint32_t *int_mask, bool queuing) | |
821 | { | |
822 | UHCIAsync *async; | |
823 | int len = 0, max_len; | |
824 | uint8_t pid; | |
825 | USBDevice *dev; | |
826 | USBEndpoint *ep; | |
827 | ||
828 | /* Is active ? */ | |
829 | if (!(td->ctrl & TD_CTRL_ACTIVE)) { | |
830 | /* | |
831 | * ehci11d spec page 22: "Even if the Active bit in the TD is already | |
832 | * cleared when the TD is fetched ... an IOC interrupt is generated" | |
833 | */ | |
834 | if (td->ctrl & TD_CTRL_IOC) { | |
835 | *int_mask |= 0x01; | |
836 | } | |
837 | return TD_RESULT_NEXT_QH; | |
838 | } | |
839 | ||
840 | async = uhci_async_find_td(s, addr, td); | |
841 | if (async) { | |
842 | /* Already submitted */ | |
843 | async->queue->valid = 32; | |
844 | ||
845 | if (!async->done) | |
846 | return TD_RESULT_ASYNC_CONT; | |
847 | if (queuing) { | |
848 | /* we are busy filling the queue, we are not prepared | |
849 | to consume completed packages then, just leave them | |
850 | in async state */ | |
851 | return TD_RESULT_ASYNC_CONT; | |
852 | } | |
853 | ||
854 | uhci_async_unlink(async); | |
855 | goto done; | |
856 | } | |
857 | ||
858 | /* Allocate new packet */ | |
859 | async = uhci_async_alloc(uhci_queue_get(s, td), addr); | |
860 | ||
861 | /* valid needs to be large enough to handle 10 frame delay | |
862 | * for initial isochronous requests | |
863 | */ | |
864 | async->queue->valid = 32; | |
865 | async->isoc = td->ctrl & TD_CTRL_IOS; | |
866 | ||
867 | max_len = ((td->token >> 21) + 1) & 0x7ff; | |
868 | pid = td->token & 0xff; | |
869 | ||
870 | dev = uhci_find_device(s, (td->token >> 8) & 0x7f); | |
871 | ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); | |
872 | usb_packet_setup(&async->packet, pid, ep, addr); | |
873 | qemu_sglist_add(&async->sgl, td->buffer, max_len); | |
874 | usb_packet_map(&async->packet, &async->sgl); | |
875 | ||
876 | switch(pid) { | |
877 | case USB_TOKEN_OUT: | |
878 | case USB_TOKEN_SETUP: | |
879 | len = usb_handle_packet(dev, &async->packet); | |
880 | if (len >= 0) | |
881 | len = max_len; | |
882 | break; | |
883 | ||
884 | case USB_TOKEN_IN: | |
885 | len = usb_handle_packet(dev, &async->packet); | |
886 | break; | |
887 | ||
888 | default: | |
889 | /* invalid pid : frame interrupted */ | |
890 | uhci_async_free(async); | |
891 | s->status |= UHCI_STS_HCPERR; | |
892 | uhci_update_irq(s); | |
893 | return TD_RESULT_STOP_FRAME; | |
894 | } | |
895 | ||
896 | if (len == USB_RET_ASYNC) { | |
897 | uhci_async_link(async); | |
898 | return TD_RESULT_ASYNC_START; | |
899 | } | |
900 | ||
901 | async->packet.result = len; | |
902 | ||
903 | done: | |
904 | len = uhci_complete_td(s, td, async, int_mask); | |
905 | usb_packet_unmap(&async->packet, &async->sgl); | |
906 | uhci_async_free(async); | |
907 | return len; | |
908 | } | |
909 | ||
910 | static void uhci_async_complete(USBPort *port, USBPacket *packet) | |
911 | { | |
912 | UHCIAsync *async = container_of(packet, UHCIAsync, packet); | |
913 | UHCIState *s = async->queue->uhci; | |
914 | ||
915 | if (async->isoc) { | |
916 | UHCI_TD td; | |
917 | uint32_t link = async->td; | |
918 | uint32_t int_mask = 0, val; | |
919 | ||
920 | pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); | |
921 | le32_to_cpus(&td.link); | |
922 | le32_to_cpus(&td.ctrl); | |
923 | le32_to_cpus(&td.token); | |
924 | le32_to_cpus(&td.buffer); | |
925 | ||
926 | uhci_async_unlink(async); | |
927 | uhci_complete_td(s, &td, async, &int_mask); | |
928 | s->pending_int_mask |= int_mask; | |
929 | ||
930 | /* update the status bits of the TD */ | |
931 | val = cpu_to_le32(td.ctrl); | |
932 | pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); | |
933 | uhci_async_free(async); | |
934 | } else { | |
935 | async->done = 1; | |
936 | if (s->frame_bytes < s->frame_bandwidth) { | |
937 | qemu_bh_schedule(s->bh); | |
938 | } | |
939 | } | |
940 | } | |
941 | ||
942 | static int is_valid(uint32_t link) | |
943 | { | |
944 | return (link & 1) == 0; | |
945 | } | |
946 | ||
947 | static int is_qh(uint32_t link) | |
948 | { | |
949 | return (link & 2) != 0; | |
950 | } | |
951 | ||
952 | static int depth_first(uint32_t link) | |
953 | { | |
954 | return (link & 4) != 0; | |
955 | } | |
956 | ||
957 | /* QH DB used for detecting QH loops */ | |
958 | #define UHCI_MAX_QUEUES 128 | |
959 | typedef struct { | |
960 | uint32_t addr[UHCI_MAX_QUEUES]; | |
961 | int count; | |
962 | } QhDb; | |
963 | ||
964 | static void qhdb_reset(QhDb *db) | |
965 | { | |
966 | db->count = 0; | |
967 | } | |
968 | ||
969 | /* Add QH to DB. Returns 1 if already present or DB is full. */ | |
970 | static int qhdb_insert(QhDb *db, uint32_t addr) | |
971 | { | |
972 | int i; | |
973 | for (i = 0; i < db->count; i++) | |
974 | if (db->addr[i] == addr) | |
975 | return 1; | |
976 | ||
977 | if (db->count >= UHCI_MAX_QUEUES) | |
978 | return 1; | |
979 | ||
980 | db->addr[db->count++] = addr; | |
981 | return 0; | |
982 | } | |
983 | ||
984 | static void uhci_fill_queue(UHCIState *s, UHCI_TD *td) | |
985 | { | |
986 | uint32_t int_mask = 0; | |
987 | uint32_t plink = td->link; | |
988 | uint32_t token = uhci_queue_token(td); | |
989 | UHCI_TD ptd; | |
990 | int ret; | |
991 | ||
992 | while (is_valid(plink)) { | |
993 | pci_dma_read(&s->dev, plink & ~0xf, &ptd, sizeof(ptd)); | |
994 | le32_to_cpus(&ptd.link); | |
995 | le32_to_cpus(&ptd.ctrl); | |
996 | le32_to_cpus(&ptd.token); | |
997 | le32_to_cpus(&ptd.buffer); | |
998 | if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { | |
999 | break; | |
1000 | } | |
1001 | if (uhci_queue_token(&ptd) != token) { | |
1002 | break; | |
1003 | } | |
1004 | trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); | |
1005 | ret = uhci_handle_td(s, plink, &ptd, &int_mask, true); | |
1006 | if (ret == TD_RESULT_ASYNC_CONT) { | |
1007 | break; | |
1008 | } | |
1009 | assert(ret == TD_RESULT_ASYNC_START); | |
1010 | assert(int_mask == 0); | |
1011 | if (ptd.ctrl & TD_CTRL_SPD) { | |
1012 | break; | |
1013 | } | |
1014 | plink = ptd.link; | |
1015 | } | |
1016 | } | |
1017 | ||
1018 | static void uhci_process_frame(UHCIState *s) | |
1019 | { | |
1020 | uint32_t frame_addr, link, old_td_ctrl, val, int_mask; | |
1021 | uint32_t curr_qh, td_count = 0; | |
1022 | int cnt, ret; | |
1023 | UHCI_TD td; | |
1024 | UHCI_QH qh; | |
1025 | QhDb qhdb; | |
1026 | ||
1027 | frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); | |
1028 | ||
1029 | pci_dma_read(&s->dev, frame_addr, &link, 4); | |
1030 | le32_to_cpus(&link); | |
1031 | ||
1032 | int_mask = 0; | |
1033 | curr_qh = 0; | |
1034 | ||
1035 | qhdb_reset(&qhdb); | |
1036 | ||
1037 | for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { | |
1038 | if (s->frame_bytes >= s->frame_bandwidth) { | |
1039 | /* We've reached the usb 1.1 bandwidth, which is | |
1040 | 1280 bytes/frame, stop processing */ | |
1041 | trace_usb_uhci_frame_stop_bandwidth(); | |
1042 | break; | |
1043 | } | |
1044 | if (is_qh(link)) { | |
1045 | /* QH */ | |
1046 | trace_usb_uhci_qh_load(link & ~0xf); | |
1047 | ||
1048 | if (qhdb_insert(&qhdb, link)) { | |
1049 | /* | |
1050 | * We're going in circles. Which is not a bug because | |
1051 | * HCD is allowed to do that as part of the BW management. | |
1052 | * | |
1053 | * Stop processing here if no transaction has been done | |
1054 | * since we've been here last time. | |
1055 | */ | |
1056 | if (td_count == 0) { | |
1057 | trace_usb_uhci_frame_loop_stop_idle(); | |
1058 | break; | |
1059 | } else { | |
1060 | trace_usb_uhci_frame_loop_continue(); | |
1061 | td_count = 0; | |
1062 | qhdb_reset(&qhdb); | |
1063 | qhdb_insert(&qhdb, link); | |
1064 | } | |
1065 | } | |
1066 | ||
1067 | pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); | |
1068 | le32_to_cpus(&qh.link); | |
1069 | le32_to_cpus(&qh.el_link); | |
1070 | ||
1071 | if (!is_valid(qh.el_link)) { | |
1072 | /* QH w/o elements */ | |
1073 | curr_qh = 0; | |
1074 | link = qh.link; | |
1075 | } else { | |
1076 | /* QH with elements */ | |
1077 | curr_qh = link; | |
1078 | link = qh.el_link; | |
1079 | } | |
1080 | continue; | |
1081 | } | |
1082 | ||
1083 | /* TD */ | |
1084 | pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); | |
1085 | le32_to_cpus(&td.link); | |
1086 | le32_to_cpus(&td.ctrl); | |
1087 | le32_to_cpus(&td.token); | |
1088 | le32_to_cpus(&td.buffer); | |
1089 | trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); | |
1090 | ||
1091 | old_td_ctrl = td.ctrl; | |
1092 | ret = uhci_handle_td(s, link, &td, &int_mask, false); | |
1093 | if (old_td_ctrl != td.ctrl) { | |
1094 | /* update the status bits of the TD */ | |
1095 | val = cpu_to_le32(td.ctrl); | |
1096 | pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); | |
1097 | } | |
1098 | ||
1099 | switch (ret) { | |
1100 | case TD_RESULT_STOP_FRAME: /* interrupted frame */ | |
1101 | goto out; | |
1102 | ||
1103 | case TD_RESULT_NEXT_QH: | |
1104 | case TD_RESULT_ASYNC_CONT: | |
1105 | trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); | |
1106 | link = curr_qh ? qh.link : td.link; | |
1107 | continue; | |
1108 | ||
1109 | case TD_RESULT_ASYNC_START: | |
1110 | trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); | |
1111 | if (is_valid(td.link) && !(td.ctrl & TD_CTRL_SPD)) { | |
1112 | uhci_fill_queue(s, &td); | |
1113 | } | |
1114 | link = curr_qh ? qh.link : td.link; | |
1115 | continue; | |
1116 | ||
1117 | case TD_RESULT_COMPLETE: | |
1118 | trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); | |
1119 | link = td.link; | |
1120 | td_count++; | |
1121 | s->frame_bytes += (td.ctrl & 0x7ff) + 1; | |
1122 | ||
1123 | if (curr_qh) { | |
1124 | /* update QH element link */ | |
1125 | qh.el_link = link; | |
1126 | val = cpu_to_le32(qh.el_link); | |
1127 | pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); | |
1128 | ||
1129 | if (!depth_first(link)) { | |
1130 | /* done with this QH */ | |
1131 | curr_qh = 0; | |
1132 | link = qh.link; | |
1133 | } | |
1134 | } | |
1135 | break; | |
1136 | ||
1137 | default: | |
1138 | assert(!"unknown return code"); | |
1139 | } | |
1140 | ||
1141 | /* go to the next entry */ | |
1142 | } | |
1143 | ||
1144 | out: | |
1145 | s->pending_int_mask |= int_mask; | |
1146 | } | |
1147 | ||
1148 | static void uhci_bh(void *opaque) | |
1149 | { | |
1150 | UHCIState *s = opaque; | |
1151 | uhci_process_frame(s); | |
1152 | } | |
1153 | ||
1154 | static void uhci_frame_timer(void *opaque) | |
1155 | { | |
1156 | UHCIState *s = opaque; | |
1157 | ||
1158 | /* prepare the timer for the next frame */ | |
1159 | s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ); | |
1160 | s->frame_bytes = 0; | |
1161 | qemu_bh_cancel(s->bh); | |
1162 | ||
1163 | if (!(s->cmd & UHCI_CMD_RS)) { | |
1164 | /* Full stop */ | |
1165 | trace_usb_uhci_schedule_stop(); | |
1166 | qemu_del_timer(s->frame_timer); | |
1167 | uhci_async_cancel_all(s); | |
1168 | /* set hchalted bit in status - UHCI11D 2.1.2 */ | |
1169 | s->status |= UHCI_STS_HCHALTED; | |
1170 | return; | |
1171 | } | |
1172 | ||
1173 | /* Complete the previous frame */ | |
1174 | if (s->pending_int_mask) { | |
1175 | s->status2 |= s->pending_int_mask; | |
1176 | s->status |= UHCI_STS_USBINT; | |
1177 | uhci_update_irq(s); | |
1178 | } | |
1179 | s->pending_int_mask = 0; | |
1180 | ||
1181 | /* Start new frame */ | |
1182 | s->frnum = (s->frnum + 1) & 0x7ff; | |
1183 | ||
1184 | trace_usb_uhci_frame_start(s->frnum); | |
1185 | ||
1186 | uhci_async_validate_begin(s); | |
1187 | ||
1188 | uhci_process_frame(s); | |
1189 | ||
1190 | uhci_async_validate_end(s); | |
1191 | ||
1192 | qemu_mod_timer(s->frame_timer, s->expire_time); | |
1193 | } | |
1194 | ||
1195 | static const MemoryRegionPortio uhci_portio[] = { | |
1196 | { 0, 32, 2, .write = uhci_ioport_writew, }, | |
1197 | { 0, 32, 2, .read = uhci_ioport_readw, }, | |
1198 | { 0, 32, 4, .write = uhci_ioport_writel, }, | |
1199 | { 0, 32, 4, .read = uhci_ioport_readl, }, | |
1200 | { 0, 32, 1, .write = uhci_ioport_writeb, }, | |
1201 | { 0, 32, 1, .read = uhci_ioport_readb, }, | |
1202 | PORTIO_END_OF_LIST() | |
1203 | }; | |
1204 | ||
1205 | static const MemoryRegionOps uhci_ioport_ops = { | |
1206 | .old_portio = uhci_portio, | |
1207 | }; | |
1208 | ||
1209 | static USBPortOps uhci_port_ops = { | |
1210 | .attach = uhci_attach, | |
1211 | .detach = uhci_detach, | |
1212 | .child_detach = uhci_child_detach, | |
1213 | .wakeup = uhci_wakeup, | |
1214 | .complete = uhci_async_complete, | |
1215 | }; | |
1216 | ||
1217 | static USBBusOps uhci_bus_ops = { | |
1218 | }; | |
1219 | ||
1220 | static int usb_uhci_common_initfn(PCIDevice *dev) | |
1221 | { | |
1222 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); | |
1223 | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); | |
1224 | uint8_t *pci_conf = s->dev.config; | |
1225 | int i; | |
1226 | ||
1227 | pci_conf[PCI_CLASS_PROG] = 0x00; | |
1228 | /* TODO: reset value should be 0. */ | |
1229 | pci_conf[USB_SBRN] = USB_RELEASE_1; // release number | |
1230 | ||
1231 | switch (pc->device_id) { | |
1232 | case PCI_DEVICE_ID_INTEL_82801I_UHCI1: | |
1233 | s->irq_pin = 0; /* A */ | |
1234 | break; | |
1235 | case PCI_DEVICE_ID_INTEL_82801I_UHCI2: | |
1236 | s->irq_pin = 1; /* B */ | |
1237 | break; | |
1238 | case PCI_DEVICE_ID_INTEL_82801I_UHCI3: | |
1239 | s->irq_pin = 2; /* C */ | |
1240 | break; | |
1241 | default: | |
1242 | s->irq_pin = 3; /* D */ | |
1243 | break; | |
1244 | } | |
1245 | pci_config_set_interrupt_pin(pci_conf, s->irq_pin + 1); | |
1246 | ||
1247 | if (s->masterbus) { | |
1248 | USBPort *ports[NB_PORTS]; | |
1249 | for(i = 0; i < NB_PORTS; i++) { | |
1250 | ports[i] = &s->ports[i].port; | |
1251 | } | |
1252 | if (usb_register_companion(s->masterbus, ports, NB_PORTS, | |
1253 | s->firstport, s, &uhci_port_ops, | |
1254 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) { | |
1255 | return -1; | |
1256 | } | |
1257 | } else { | |
1258 | usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev); | |
1259 | for (i = 0; i < NB_PORTS; i++) { | |
1260 | usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, | |
1261 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); | |
1262 | } | |
1263 | } | |
1264 | s->bh = qemu_bh_new(uhci_bh, s); | |
1265 | s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s); | |
1266 | s->num_ports_vmstate = NB_PORTS; | |
1267 | QTAILQ_INIT(&s->queues); | |
1268 | ||
1269 | qemu_register_reset(uhci_reset, s); | |
1270 | ||
1271 | memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20); | |
1272 | /* Use region 4 for consistency with real hardware. BSD guests seem | |
1273 | to rely on this. */ | |
1274 | pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); | |
1275 | ||
1276 | return 0; | |
1277 | } | |
1278 | ||
1279 | static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) | |
1280 | { | |
1281 | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); | |
1282 | uint8_t *pci_conf = s->dev.config; | |
1283 | ||
1284 | /* USB misc control 1/2 */ | |
1285 | pci_set_long(pci_conf + 0x40,0x00001000); | |
1286 | /* PM capability */ | |
1287 | pci_set_long(pci_conf + 0x80,0x00020001); | |
1288 | /* USB legacy support */ | |
1289 | pci_set_long(pci_conf + 0xc0,0x00002000); | |
1290 | ||
1291 | return usb_uhci_common_initfn(dev); | |
1292 | } | |
1293 | ||
1294 | static void usb_uhci_exit(PCIDevice *dev) | |
1295 | { | |
1296 | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); | |
1297 | ||
1298 | memory_region_destroy(&s->io_bar); | |
1299 | } | |
1300 | ||
1301 | static Property uhci_properties[] = { | |
1302 | DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), | |
1303 | DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), | |
1304 | DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), | |
1305 | DEFINE_PROP_END_OF_LIST(), | |
1306 | }; | |
1307 | ||
1308 | static void piix3_uhci_class_init(ObjectClass *klass, void *data) | |
1309 | { | |
1310 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1311 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
1312 | ||
1313 | k->init = usb_uhci_common_initfn; | |
1314 | k->exit = usb_uhci_exit; | |
1315 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
1316 | k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2; | |
1317 | k->revision = 0x01; | |
1318 | k->class_id = PCI_CLASS_SERIAL_USB; | |
1319 | dc->vmsd = &vmstate_uhci; | |
1320 | dc->props = uhci_properties; | |
1321 | } | |
1322 | ||
1323 | static TypeInfo piix3_uhci_info = { | |
1324 | .name = "piix3-usb-uhci", | |
1325 | .parent = TYPE_PCI_DEVICE, | |
1326 | .instance_size = sizeof(UHCIState), | |
1327 | .class_init = piix3_uhci_class_init, | |
1328 | }; | |
1329 | ||
1330 | static void piix4_uhci_class_init(ObjectClass *klass, void *data) | |
1331 | { | |
1332 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1333 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
1334 | ||
1335 | k->init = usb_uhci_common_initfn; | |
1336 | k->exit = usb_uhci_exit; | |
1337 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
1338 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2; | |
1339 | k->revision = 0x01; | |
1340 | k->class_id = PCI_CLASS_SERIAL_USB; | |
1341 | dc->vmsd = &vmstate_uhci; | |
1342 | dc->props = uhci_properties; | |
1343 | } | |
1344 | ||
1345 | static TypeInfo piix4_uhci_info = { | |
1346 | .name = "piix4-usb-uhci", | |
1347 | .parent = TYPE_PCI_DEVICE, | |
1348 | .instance_size = sizeof(UHCIState), | |
1349 | .class_init = piix4_uhci_class_init, | |
1350 | }; | |
1351 | ||
1352 | static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data) | |
1353 | { | |
1354 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1355 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
1356 | ||
1357 | k->init = usb_uhci_vt82c686b_initfn; | |
1358 | k->exit = usb_uhci_exit; | |
1359 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
1360 | k->device_id = PCI_DEVICE_ID_VIA_UHCI; | |
1361 | k->revision = 0x01; | |
1362 | k->class_id = PCI_CLASS_SERIAL_USB; | |
1363 | dc->vmsd = &vmstate_uhci; | |
1364 | dc->props = uhci_properties; | |
1365 | } | |
1366 | ||
1367 | static TypeInfo vt82c686b_uhci_info = { | |
1368 | .name = "vt82c686b-usb-uhci", | |
1369 | .parent = TYPE_PCI_DEVICE, | |
1370 | .instance_size = sizeof(UHCIState), | |
1371 | .class_init = vt82c686b_uhci_class_init, | |
1372 | }; | |
1373 | ||
1374 | static void ich9_uhci1_class_init(ObjectClass *klass, void *data) | |
1375 | { | |
1376 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1377 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
1378 | ||
1379 | k->init = usb_uhci_common_initfn; | |
1380 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
1381 | k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1; | |
1382 | k->revision = 0x03; | |
1383 | k->class_id = PCI_CLASS_SERIAL_USB; | |
1384 | dc->vmsd = &vmstate_uhci; | |
1385 | dc->props = uhci_properties; | |
1386 | } | |
1387 | ||
1388 | static TypeInfo ich9_uhci1_info = { | |
1389 | .name = "ich9-usb-uhci1", | |
1390 | .parent = TYPE_PCI_DEVICE, | |
1391 | .instance_size = sizeof(UHCIState), | |
1392 | .class_init = ich9_uhci1_class_init, | |
1393 | }; | |
1394 | ||
1395 | static void ich9_uhci2_class_init(ObjectClass *klass, void *data) | |
1396 | { | |
1397 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1398 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
1399 | ||
1400 | k->init = usb_uhci_common_initfn; | |
1401 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
1402 | k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2; | |
1403 | k->revision = 0x03; | |
1404 | k->class_id = PCI_CLASS_SERIAL_USB; | |
1405 | dc->vmsd = &vmstate_uhci; | |
1406 | dc->props = uhci_properties; | |
1407 | } | |
1408 | ||
1409 | static TypeInfo ich9_uhci2_info = { | |
1410 | .name = "ich9-usb-uhci2", | |
1411 | .parent = TYPE_PCI_DEVICE, | |
1412 | .instance_size = sizeof(UHCIState), | |
1413 | .class_init = ich9_uhci2_class_init, | |
1414 | }; | |
1415 | ||
1416 | static void ich9_uhci3_class_init(ObjectClass *klass, void *data) | |
1417 | { | |
1418 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1419 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
1420 | ||
1421 | k->init = usb_uhci_common_initfn; | |
1422 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
1423 | k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3; | |
1424 | k->revision = 0x03; | |
1425 | k->class_id = PCI_CLASS_SERIAL_USB; | |
1426 | dc->vmsd = &vmstate_uhci; | |
1427 | dc->props = uhci_properties; | |
1428 | } | |
1429 | ||
1430 | static TypeInfo ich9_uhci3_info = { | |
1431 | .name = "ich9-usb-uhci3", | |
1432 | .parent = TYPE_PCI_DEVICE, | |
1433 | .instance_size = sizeof(UHCIState), | |
1434 | .class_init = ich9_uhci3_class_init, | |
1435 | }; | |
1436 | ||
1437 | static void uhci_register_types(void) | |
1438 | { | |
1439 | type_register_static(&piix3_uhci_info); | |
1440 | type_register_static(&piix4_uhci_info); | |
1441 | type_register_static(&vt82c686b_uhci_info); | |
1442 | type_register_static(&ich9_uhci1_info); | |
1443 | type_register_static(&ich9_uhci2_info); | |
1444 | type_register_static(&ich9_uhci3_info); | |
1445 | } | |
1446 | ||
1447 | type_init(uhci_register_types) |