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1 | /* | |
2 | * QEMU USB EHCI Emulation | |
3 | * | |
4 | * Copyright(c) 2008 Emutex Ltd. (address@hidden) | |
5 | * | |
6 | * EHCI project was started by Mark Burkley, with contributions by | |
7 | * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf, | |
8 | * Jan Kiszka and Vincent Palatin contributed bugfixes. | |
9 | * | |
10 | * | |
11 | * This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU Lesser General Public | |
13 | * License as published by the Free Software Foundation; either | |
14 | * version 2 of the License, or(at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * Lesser General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
23 | */ | |
24 | ||
25 | #include "hw.h" | |
26 | #include "qemu-timer.h" | |
27 | #include "usb.h" | |
28 | #include "pci.h" | |
29 | #include "monitor.h" | |
30 | #include "trace.h" | |
31 | ||
32 | #define EHCI_DEBUG 0 | |
33 | ||
34 | #if EHCI_DEBUG | |
35 | #define DPRINTF printf | |
36 | #else | |
37 | #define DPRINTF(...) | |
38 | #endif | |
39 | ||
40 | /* internal processing - reset HC to try and recover */ | |
41 | #define USB_RET_PROCERR (-99) | |
42 | ||
43 | #define MMIO_SIZE 0x1000 | |
44 | ||
45 | /* Capability Registers Base Address - section 2.2 */ | |
46 | #define CAPREGBASE 0x0000 | |
47 | #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved | |
48 | #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version # | |
49 | #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params | |
50 | #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params | |
51 | #define EECP HCCPARAMS + 1 | |
52 | #define HCSPPORTROUTE1 CAPREGBASE + 0x000c | |
53 | #define HCSPPORTROUTE2 CAPREGBASE + 0x0010 | |
54 | ||
55 | #define OPREGBASE 0x0020 // Operational Registers Base Address | |
56 | ||
57 | #define USBCMD OPREGBASE + 0x0000 | |
58 | #define USBCMD_RUNSTOP (1 << 0) // run / Stop | |
59 | #define USBCMD_HCRESET (1 << 1) // HC Reset | |
60 | #define USBCMD_FLS (3 << 2) // Frame List Size | |
61 | #define USBCMD_FLS_SH 2 // Frame List Size Shift | |
62 | #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable | |
63 | #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable | |
64 | #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell | |
65 | #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset | |
66 | #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count | |
67 | #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable | |
68 | #define USBCMD_ITC (0x7f << 16) // Int Threshold Control | |
69 | #define USBCMD_ITC_SH 16 // Int Threshold Control Shift | |
70 | ||
71 | #define USBSTS OPREGBASE + 0x0004 | |
72 | #define USBSTS_RO_MASK 0x0000003f | |
73 | #define USBSTS_INT (1 << 0) // USB Interrupt | |
74 | #define USBSTS_ERRINT (1 << 1) // Error Interrupt | |
75 | #define USBSTS_PCD (1 << 2) // Port Change Detect | |
76 | #define USBSTS_FLR (1 << 3) // Frame List Rollover | |
77 | #define USBSTS_HSE (1 << 4) // Host System Error | |
78 | #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance | |
79 | #define USBSTS_HALT (1 << 12) // HC Halted | |
80 | #define USBSTS_REC (1 << 13) // Reclamation | |
81 | #define USBSTS_PSS (1 << 14) // Periodic Schedule Status | |
82 | #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status | |
83 | ||
84 | /* | |
85 | * Interrupt enable bits correspond to the interrupt active bits in USBSTS | |
86 | * so no need to redefine here. | |
87 | */ | |
88 | #define USBINTR OPREGBASE + 0x0008 | |
89 | #define USBINTR_MASK 0x0000003f | |
90 | ||
91 | #define FRINDEX OPREGBASE + 0x000c | |
92 | #define CTRLDSSEGMENT OPREGBASE + 0x0010 | |
93 | #define PERIODICLISTBASE OPREGBASE + 0x0014 | |
94 | #define ASYNCLISTADDR OPREGBASE + 0x0018 | |
95 | #define ASYNCLISTADDR_MASK 0xffffffe0 | |
96 | ||
97 | #define CONFIGFLAG OPREGBASE + 0x0040 | |
98 | ||
99 | #define PORTSC (OPREGBASE + 0x0044) | |
100 | #define PORTSC_BEGIN PORTSC | |
101 | #define PORTSC_END (PORTSC + 4 * NB_PORTS) | |
102 | /* | |
103 | * Bits that are reserved or are read-only are masked out of values | |
104 | * written to us by software | |
105 | */ | |
106 | #define PORTSC_RO_MASK 0x007001c0 | |
107 | #define PORTSC_RWC_MASK 0x0000002a | |
108 | #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable | |
109 | #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable | |
110 | #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable | |
111 | #define PORTSC_PTC (15 << 16) // Port Test Control | |
112 | #define PORTSC_PTC_SH 16 // Port Test Control shift | |
113 | #define PORTSC_PIC (3 << 14) // Port Indicator Control | |
114 | #define PORTSC_PIC_SH 14 // Port Indicator Control Shift | |
115 | #define PORTSC_POWNER (1 << 13) // Port Owner | |
116 | #define PORTSC_PPOWER (1 << 12) // Port Power | |
117 | #define PORTSC_LINESTAT (3 << 10) // Port Line Status | |
118 | #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift | |
119 | #define PORTSC_PRESET (1 << 8) // Port Reset | |
120 | #define PORTSC_SUSPEND (1 << 7) // Port Suspend | |
121 | #define PORTSC_FPRES (1 << 6) // Force Port Resume | |
122 | #define PORTSC_OCC (1 << 5) // Over Current Change | |
123 | #define PORTSC_OCA (1 << 4) // Over Current Active | |
124 | #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change | |
125 | #define PORTSC_PED (1 << 2) // Port Enable/Disable | |
126 | #define PORTSC_CSC (1 << 1) // Connect Status Change | |
127 | #define PORTSC_CONNECT (1 << 0) // Current Connect Status | |
128 | ||
129 | #define FRAME_TIMER_FREQ 1000 | |
130 | #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) | |
131 | ||
132 | #define NB_MAXINTRATE 8 // Max rate at which controller issues ints | |
133 | #define NB_PORTS 6 // Number of downstream ports | |
134 | #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction | |
135 | #define MAX_ITERATIONS 20 // Max number of QH before we break the loop | |
136 | #define MAX_QH 100 // Max allowable queue heads in a chain | |
137 | ||
138 | /* Internal periodic / asynchronous schedule state machine states | |
139 | */ | |
140 | typedef enum { | |
141 | EST_INACTIVE = 1000, | |
142 | EST_ACTIVE, | |
143 | EST_EXECUTING, | |
144 | EST_SLEEPING, | |
145 | /* The following states are internal to the state machine function | |
146 | */ | |
147 | EST_WAITLISTHEAD, | |
148 | EST_FETCHENTRY, | |
149 | EST_FETCHQH, | |
150 | EST_FETCHITD, | |
151 | EST_ADVANCEQUEUE, | |
152 | EST_FETCHQTD, | |
153 | EST_EXECUTE, | |
154 | EST_WRITEBACK, | |
155 | EST_HORIZONTALQH | |
156 | } EHCI_STATES; | |
157 | ||
158 | /* macros for accessing fields within next link pointer entry */ | |
159 | #define NLPTR_GET(x) ((x) & 0xffffffe0) | |
160 | #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) | |
161 | #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid | |
162 | ||
163 | /* link pointer types */ | |
164 | #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor | |
165 | #define NLPTR_TYPE_QH 1 // queue head | |
166 | #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor | |
167 | #define NLPTR_TYPE_FSTN 3 // frame span traversal node | |
168 | ||
169 | ||
170 | /* EHCI spec version 1.0 Section 3.3 | |
171 | */ | |
172 | typedef struct EHCIitd { | |
173 | uint32_t next; | |
174 | ||
175 | uint32_t transact[8]; | |
176 | #define ITD_XACT_ACTIVE (1 << 31) | |
177 | #define ITD_XACT_DBERROR (1 << 30) | |
178 | #define ITD_XACT_BABBLE (1 << 29) | |
179 | #define ITD_XACT_XACTERR (1 << 28) | |
180 | #define ITD_XACT_LENGTH_MASK 0x0fff0000 | |
181 | #define ITD_XACT_LENGTH_SH 16 | |
182 | #define ITD_XACT_IOC (1 << 15) | |
183 | #define ITD_XACT_PGSEL_MASK 0x00007000 | |
184 | #define ITD_XACT_PGSEL_SH 12 | |
185 | #define ITD_XACT_OFFSET_MASK 0x00000fff | |
186 | ||
187 | uint32_t bufptr[7]; | |
188 | #define ITD_BUFPTR_MASK 0xfffff000 | |
189 | #define ITD_BUFPTR_SH 12 | |
190 | #define ITD_BUFPTR_EP_MASK 0x00000f00 | |
191 | #define ITD_BUFPTR_EP_SH 8 | |
192 | #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f | |
193 | #define ITD_BUFPTR_DEVADDR_SH 0 | |
194 | #define ITD_BUFPTR_DIRECTION (1 << 11) | |
195 | #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff | |
196 | #define ITD_BUFPTR_MAXPKT_SH 0 | |
197 | #define ITD_BUFPTR_MULT_MASK 0x00000003 | |
198 | #define ITD_BUFPTR_MULT_SH 0 | |
199 | } EHCIitd; | |
200 | ||
201 | /* EHCI spec version 1.0 Section 3.4 | |
202 | */ | |
203 | typedef struct EHCIsitd { | |
204 | uint32_t next; // Standard next link pointer | |
205 | uint32_t epchar; | |
206 | #define SITD_EPCHAR_IO (1 << 31) | |
207 | #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000 | |
208 | #define SITD_EPCHAR_PORTNUM_SH 24 | |
209 | #define SITD_EPCHAR_HUBADD_MASK 0x007f0000 | |
210 | #define SITD_EPCHAR_HUBADDR_SH 16 | |
211 | #define SITD_EPCHAR_EPNUM_MASK 0x00000f00 | |
212 | #define SITD_EPCHAR_EPNUM_SH 8 | |
213 | #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f | |
214 | ||
215 | uint32_t uframe; | |
216 | #define SITD_UFRAME_CMASK_MASK 0x0000ff00 | |
217 | #define SITD_UFRAME_CMASK_SH 8 | |
218 | #define SITD_UFRAME_SMASK_MASK 0x000000ff | |
219 | ||
220 | uint32_t results; | |
221 | #define SITD_RESULTS_IOC (1 << 31) | |
222 | #define SITD_RESULTS_PGSEL (1 << 30) | |
223 | #define SITD_RESULTS_TBYTES_MASK 0x03ff0000 | |
224 | #define SITD_RESULTS_TYBYTES_SH 16 | |
225 | #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00 | |
226 | #define SITD_RESULTS_CPROGMASK_SH 8 | |
227 | #define SITD_RESULTS_ACTIVE (1 << 7) | |
228 | #define SITD_RESULTS_ERR (1 << 6) | |
229 | #define SITD_RESULTS_DBERR (1 << 5) | |
230 | #define SITD_RESULTS_BABBLE (1 << 4) | |
231 | #define SITD_RESULTS_XACTERR (1 << 3) | |
232 | #define SITD_RESULTS_MISSEDUF (1 << 2) | |
233 | #define SITD_RESULTS_SPLITXSTATE (1 << 1) | |
234 | ||
235 | uint32_t bufptr[2]; | |
236 | #define SITD_BUFPTR_MASK 0xfffff000 | |
237 | #define SITD_BUFPTR_CURROFF_MASK 0x00000fff | |
238 | #define SITD_BUFPTR_TPOS_MASK 0x00000018 | |
239 | #define SITD_BUFPTR_TPOS_SH 3 | |
240 | #define SITD_BUFPTR_TCNT_MASK 0x00000007 | |
241 | ||
242 | uint32_t backptr; // Standard next link pointer | |
243 | } EHCIsitd; | |
244 | ||
245 | /* EHCI spec version 1.0 Section 3.5 | |
246 | */ | |
247 | typedef struct EHCIqtd { | |
248 | uint32_t next; // Standard next link pointer | |
249 | uint32_t altnext; // Standard next link pointer | |
250 | uint32_t token; | |
251 | #define QTD_TOKEN_DTOGGLE (1 << 31) | |
252 | #define QTD_TOKEN_TBYTES_MASK 0x7fff0000 | |
253 | #define QTD_TOKEN_TBYTES_SH 16 | |
254 | #define QTD_TOKEN_IOC (1 << 15) | |
255 | #define QTD_TOKEN_CPAGE_MASK 0x00007000 | |
256 | #define QTD_TOKEN_CPAGE_SH 12 | |
257 | #define QTD_TOKEN_CERR_MASK 0x00000c00 | |
258 | #define QTD_TOKEN_CERR_SH 10 | |
259 | #define QTD_TOKEN_PID_MASK 0x00000300 | |
260 | #define QTD_TOKEN_PID_SH 8 | |
261 | #define QTD_TOKEN_ACTIVE (1 << 7) | |
262 | #define QTD_TOKEN_HALT (1 << 6) | |
263 | #define QTD_TOKEN_DBERR (1 << 5) | |
264 | #define QTD_TOKEN_BABBLE (1 << 4) | |
265 | #define QTD_TOKEN_XACTERR (1 << 3) | |
266 | #define QTD_TOKEN_MISSEDUF (1 << 2) | |
267 | #define QTD_TOKEN_SPLITXSTATE (1 << 1) | |
268 | #define QTD_TOKEN_PING (1 << 0) | |
269 | ||
270 | uint32_t bufptr[5]; // Standard buffer pointer | |
271 | #define QTD_BUFPTR_MASK 0xfffff000 | |
272 | } EHCIqtd; | |
273 | ||
274 | /* EHCI spec version 1.0 Section 3.6 | |
275 | */ | |
276 | typedef struct EHCIqh { | |
277 | uint32_t next; // Standard next link pointer | |
278 | ||
279 | /* endpoint characteristics */ | |
280 | uint32_t epchar; | |
281 | #define QH_EPCHAR_RL_MASK 0xf0000000 | |
282 | #define QH_EPCHAR_RL_SH 28 | |
283 | #define QH_EPCHAR_C (1 << 27) | |
284 | #define QH_EPCHAR_MPLEN_MASK 0x07FF0000 | |
285 | #define QH_EPCHAR_MPLEN_SH 16 | |
286 | #define QH_EPCHAR_H (1 << 15) | |
287 | #define QH_EPCHAR_DTC (1 << 14) | |
288 | #define QH_EPCHAR_EPS_MASK 0x00003000 | |
289 | #define QH_EPCHAR_EPS_SH 12 | |
290 | #define EHCI_QH_EPS_FULL 0 | |
291 | #define EHCI_QH_EPS_LOW 1 | |
292 | #define EHCI_QH_EPS_HIGH 2 | |
293 | #define EHCI_QH_EPS_RESERVED 3 | |
294 | ||
295 | #define QH_EPCHAR_EP_MASK 0x00000f00 | |
296 | #define QH_EPCHAR_EP_SH 8 | |
297 | #define QH_EPCHAR_I (1 << 7) | |
298 | #define QH_EPCHAR_DEVADDR_MASK 0x0000007f | |
299 | #define QH_EPCHAR_DEVADDR_SH 0 | |
300 | ||
301 | /* endpoint capabilities */ | |
302 | uint32_t epcap; | |
303 | #define QH_EPCAP_MULT_MASK 0xc0000000 | |
304 | #define QH_EPCAP_MULT_SH 30 | |
305 | #define QH_EPCAP_PORTNUM_MASK 0x3f800000 | |
306 | #define QH_EPCAP_PORTNUM_SH 23 | |
307 | #define QH_EPCAP_HUBADDR_MASK 0x007f0000 | |
308 | #define QH_EPCAP_HUBADDR_SH 16 | |
309 | #define QH_EPCAP_CMASK_MASK 0x0000ff00 | |
310 | #define QH_EPCAP_CMASK_SH 8 | |
311 | #define QH_EPCAP_SMASK_MASK 0x000000ff | |
312 | #define QH_EPCAP_SMASK_SH 0 | |
313 | ||
314 | uint32_t current_qtd; // Standard next link pointer | |
315 | uint32_t next_qtd; // Standard next link pointer | |
316 | uint32_t altnext_qtd; | |
317 | #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e | |
318 | #define QH_ALTNEXT_NAKCNT_SH 1 | |
319 | ||
320 | uint32_t token; // Same as QTD token | |
321 | uint32_t bufptr[5]; // Standard buffer pointer | |
322 | #define BUFPTR_CPROGMASK_MASK 0x000000ff | |
323 | #define BUFPTR_FRAMETAG_MASK 0x0000001f | |
324 | #define BUFPTR_SBYTES_MASK 0x00000fe0 | |
325 | #define BUFPTR_SBYTES_SH 5 | |
326 | } EHCIqh; | |
327 | ||
328 | /* EHCI spec version 1.0 Section 3.7 | |
329 | */ | |
330 | typedef struct EHCIfstn { | |
331 | uint32_t next; // Standard next link pointer | |
332 | uint32_t backptr; // Standard next link pointer | |
333 | } EHCIfstn; | |
334 | ||
335 | typedef struct EHCIQueue EHCIQueue; | |
336 | typedef struct EHCIState EHCIState; | |
337 | ||
338 | enum async_state { | |
339 | EHCI_ASYNC_NONE = 0, | |
340 | EHCI_ASYNC_INFLIGHT, | |
341 | EHCI_ASYNC_FINISHED, | |
342 | }; | |
343 | ||
344 | struct EHCIQueue { | |
345 | EHCIState *ehci; | |
346 | QTAILQ_ENTRY(EHCIQueue) next; | |
347 | bool async_schedule; | |
348 | uint32_t seen; | |
349 | uint64_t ts; | |
350 | ||
351 | /* cached data from guest - needs to be flushed | |
352 | * when guest removes an entry (doorbell, handshake sequence) | |
353 | */ | |
354 | EHCIqh qh; // copy of current QH (being worked on) | |
355 | uint32_t qhaddr; // address QH read from | |
356 | EHCIqtd qtd; // copy of current QTD (being worked on) | |
357 | uint32_t qtdaddr; // address QTD read from | |
358 | ||
359 | USBPacket packet; | |
360 | uint8_t buffer[BUFF_SIZE]; | |
361 | int pid; | |
362 | uint32_t tbytes; | |
363 | enum async_state async; | |
364 | int usb_status; | |
365 | }; | |
366 | ||
367 | struct EHCIState { | |
368 | PCIDevice dev; | |
369 | USBBus bus; | |
370 | qemu_irq irq; | |
371 | target_phys_addr_t mem_base; | |
372 | int mem; | |
373 | int companion_count; | |
374 | ||
375 | /* properties */ | |
376 | uint32_t freq; | |
377 | uint32_t maxframes; | |
378 | ||
379 | /* | |
380 | * EHCI spec version 1.0 Section 2.3 | |
381 | * Host Controller Operational Registers | |
382 | */ | |
383 | union { | |
384 | uint8_t mmio[MMIO_SIZE]; | |
385 | struct { | |
386 | uint8_t cap[OPREGBASE]; | |
387 | uint32_t usbcmd; | |
388 | uint32_t usbsts; | |
389 | uint32_t usbintr; | |
390 | uint32_t frindex; | |
391 | uint32_t ctrldssegment; | |
392 | uint32_t periodiclistbase; | |
393 | uint32_t asynclistaddr; | |
394 | uint32_t notused[9]; | |
395 | uint32_t configflag; | |
396 | uint32_t portsc[NB_PORTS]; | |
397 | }; | |
398 | }; | |
399 | ||
400 | /* | |
401 | * Internal states, shadow registers, etc | |
402 | */ | |
403 | uint32_t sofv; | |
404 | QEMUTimer *frame_timer; | |
405 | int attach_poll_counter; | |
406 | int astate; // Current state in asynchronous schedule | |
407 | int pstate; // Current state in periodic schedule | |
408 | USBPort ports[NB_PORTS]; | |
409 | USBPort *companion_ports[NB_PORTS]; | |
410 | uint32_t usbsts_pending; | |
411 | QTAILQ_HEAD(, EHCIQueue) queues; | |
412 | ||
413 | uint32_t a_fetch_addr; // which address to look at next | |
414 | uint32_t p_fetch_addr; // which address to look at next | |
415 | ||
416 | USBPacket ipacket; | |
417 | uint8_t ibuffer[BUFF_SIZE]; | |
418 | int isoch_pause; | |
419 | ||
420 | uint64_t last_run_ns; | |
421 | }; | |
422 | ||
423 | #define SET_LAST_RUN_CLOCK(s) \ | |
424 | (s)->last_run_ns = qemu_get_clock_ns(vm_clock); | |
425 | ||
426 | /* nifty macros from Arnon's EHCI version */ | |
427 | #define get_field(data, field) \ | |
428 | (((data) & field##_MASK) >> field##_SH) | |
429 | ||
430 | #define set_field(data, newval, field) do { \ | |
431 | uint32_t val = *data; \ | |
432 | val &= ~ field##_MASK; \ | |
433 | val |= ((newval) << field##_SH) & field##_MASK; \ | |
434 | *data = val; \ | |
435 | } while(0) | |
436 | ||
437 | static const char *ehci_state_names[] = { | |
438 | [ EST_INACTIVE ] = "INACTIVE", | |
439 | [ EST_ACTIVE ] = "ACTIVE", | |
440 | [ EST_EXECUTING ] = "EXECUTING", | |
441 | [ EST_SLEEPING ] = "SLEEPING", | |
442 | [ EST_WAITLISTHEAD ] = "WAITLISTHEAD", | |
443 | [ EST_FETCHENTRY ] = "FETCH ENTRY", | |
444 | [ EST_FETCHQH ] = "FETCH QH", | |
445 | [ EST_FETCHITD ] = "FETCH ITD", | |
446 | [ EST_ADVANCEQUEUE ] = "ADVANCEQUEUE", | |
447 | [ EST_FETCHQTD ] = "FETCH QTD", | |
448 | [ EST_EXECUTE ] = "EXECUTE", | |
449 | [ EST_WRITEBACK ] = "WRITEBACK", | |
450 | [ EST_HORIZONTALQH ] = "HORIZONTALQH", | |
451 | }; | |
452 | ||
453 | static const char *ehci_mmio_names[] = { | |
454 | [ CAPLENGTH ] = "CAPLENGTH", | |
455 | [ HCIVERSION ] = "HCIVERSION", | |
456 | [ HCSPARAMS ] = "HCSPARAMS", | |
457 | [ HCCPARAMS ] = "HCCPARAMS", | |
458 | [ USBCMD ] = "USBCMD", | |
459 | [ USBSTS ] = "USBSTS", | |
460 | [ USBINTR ] = "USBINTR", | |
461 | [ FRINDEX ] = "FRINDEX", | |
462 | [ PERIODICLISTBASE ] = "P-LIST BASE", | |
463 | [ ASYNCLISTADDR ] = "A-LIST ADDR", | |
464 | [ PORTSC_BEGIN ] = "PORTSC #0", | |
465 | [ PORTSC_BEGIN + 4] = "PORTSC #1", | |
466 | [ PORTSC_BEGIN + 8] = "PORTSC #2", | |
467 | [ PORTSC_BEGIN + 12] = "PORTSC #3", | |
468 | [ CONFIGFLAG ] = "CONFIGFLAG", | |
469 | }; | |
470 | ||
471 | static const char *nr2str(const char **n, size_t len, uint32_t nr) | |
472 | { | |
473 | if (nr < len && n[nr] != NULL) { | |
474 | return n[nr]; | |
475 | } else { | |
476 | return "unknown"; | |
477 | } | |
478 | } | |
479 | ||
480 | static const char *state2str(uint32_t state) | |
481 | { | |
482 | return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state); | |
483 | } | |
484 | ||
485 | static const char *addr2str(target_phys_addr_t addr) | |
486 | { | |
487 | return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr); | |
488 | } | |
489 | ||
490 | static void ehci_trace_usbsts(uint32_t mask, int state) | |
491 | { | |
492 | /* interrupts */ | |
493 | if (mask & USBSTS_INT) { | |
494 | trace_usb_ehci_usbsts("INT", state); | |
495 | } | |
496 | if (mask & USBSTS_ERRINT) { | |
497 | trace_usb_ehci_usbsts("ERRINT", state); | |
498 | } | |
499 | if (mask & USBSTS_PCD) { | |
500 | trace_usb_ehci_usbsts("PCD", state); | |
501 | } | |
502 | if (mask & USBSTS_FLR) { | |
503 | trace_usb_ehci_usbsts("FLR", state); | |
504 | } | |
505 | if (mask & USBSTS_HSE) { | |
506 | trace_usb_ehci_usbsts("HSE", state); | |
507 | } | |
508 | if (mask & USBSTS_IAA) { | |
509 | trace_usb_ehci_usbsts("IAA", state); | |
510 | } | |
511 | ||
512 | /* status */ | |
513 | if (mask & USBSTS_HALT) { | |
514 | trace_usb_ehci_usbsts("HALT", state); | |
515 | } | |
516 | if (mask & USBSTS_REC) { | |
517 | trace_usb_ehci_usbsts("REC", state); | |
518 | } | |
519 | if (mask & USBSTS_PSS) { | |
520 | trace_usb_ehci_usbsts("PSS", state); | |
521 | } | |
522 | if (mask & USBSTS_ASS) { | |
523 | trace_usb_ehci_usbsts("ASS", state); | |
524 | } | |
525 | } | |
526 | ||
527 | static inline void ehci_set_usbsts(EHCIState *s, int mask) | |
528 | { | |
529 | if ((s->usbsts & mask) == mask) { | |
530 | return; | |
531 | } | |
532 | ehci_trace_usbsts(mask, 1); | |
533 | s->usbsts |= mask; | |
534 | } | |
535 | ||
536 | static inline void ehci_clear_usbsts(EHCIState *s, int mask) | |
537 | { | |
538 | if ((s->usbsts & mask) == 0) { | |
539 | return; | |
540 | } | |
541 | ehci_trace_usbsts(mask, 0); | |
542 | s->usbsts &= ~mask; | |
543 | } | |
544 | ||
545 | static inline void ehci_set_interrupt(EHCIState *s, int intr) | |
546 | { | |
547 | int level = 0; | |
548 | ||
549 | // TODO honour interrupt threshold requests | |
550 | ||
551 | ehci_set_usbsts(s, intr); | |
552 | ||
553 | if ((s->usbsts & USBINTR_MASK) & s->usbintr) { | |
554 | level = 1; | |
555 | } | |
556 | ||
557 | qemu_set_irq(s->irq, level); | |
558 | } | |
559 | ||
560 | static inline void ehci_record_interrupt(EHCIState *s, int intr) | |
561 | { | |
562 | s->usbsts_pending |= intr; | |
563 | } | |
564 | ||
565 | static inline void ehci_commit_interrupt(EHCIState *s) | |
566 | { | |
567 | if (!s->usbsts_pending) { | |
568 | return; | |
569 | } | |
570 | ehci_set_interrupt(s, s->usbsts_pending); | |
571 | s->usbsts_pending = 0; | |
572 | } | |
573 | ||
574 | static void ehci_set_state(EHCIState *s, int async, int state) | |
575 | { | |
576 | if (async) { | |
577 | trace_usb_ehci_state("async", state2str(state)); | |
578 | s->astate = state; | |
579 | } else { | |
580 | trace_usb_ehci_state("periodic", state2str(state)); | |
581 | s->pstate = state; | |
582 | } | |
583 | } | |
584 | ||
585 | static int ehci_get_state(EHCIState *s, int async) | |
586 | { | |
587 | return async ? s->astate : s->pstate; | |
588 | } | |
589 | ||
590 | static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) | |
591 | { | |
592 | if (async) { | |
593 | s->a_fetch_addr = addr; | |
594 | } else { | |
595 | s->p_fetch_addr = addr; | |
596 | } | |
597 | } | |
598 | ||
599 | static int ehci_get_fetch_addr(EHCIState *s, int async) | |
600 | { | |
601 | return async ? s->a_fetch_addr : s->p_fetch_addr; | |
602 | } | |
603 | ||
604 | static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh) | |
605 | { | |
606 | /* need three here due to argument count limits */ | |
607 | trace_usb_ehci_qh_ptrs(q, addr, qh->next, | |
608 | qh->current_qtd, qh->next_qtd, qh->altnext_qtd); | |
609 | trace_usb_ehci_qh_fields(addr, | |
610 | get_field(qh->epchar, QH_EPCHAR_RL), | |
611 | get_field(qh->epchar, QH_EPCHAR_MPLEN), | |
612 | get_field(qh->epchar, QH_EPCHAR_EPS), | |
613 | get_field(qh->epchar, QH_EPCHAR_EP), | |
614 | get_field(qh->epchar, QH_EPCHAR_DEVADDR)); | |
615 | trace_usb_ehci_qh_bits(addr, | |
616 | (bool)(qh->epchar & QH_EPCHAR_C), | |
617 | (bool)(qh->epchar & QH_EPCHAR_H), | |
618 | (bool)(qh->epchar & QH_EPCHAR_DTC), | |
619 | (bool)(qh->epchar & QH_EPCHAR_I)); | |
620 | } | |
621 | ||
622 | static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd) | |
623 | { | |
624 | /* need three here due to argument count limits */ | |
625 | trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); | |
626 | trace_usb_ehci_qtd_fields(addr, | |
627 | get_field(qtd->token, QTD_TOKEN_TBYTES), | |
628 | get_field(qtd->token, QTD_TOKEN_CPAGE), | |
629 | get_field(qtd->token, QTD_TOKEN_CERR), | |
630 | get_field(qtd->token, QTD_TOKEN_PID)); | |
631 | trace_usb_ehci_qtd_bits(addr, | |
632 | (bool)(qtd->token & QTD_TOKEN_IOC), | |
633 | (bool)(qtd->token & QTD_TOKEN_ACTIVE), | |
634 | (bool)(qtd->token & QTD_TOKEN_HALT), | |
635 | (bool)(qtd->token & QTD_TOKEN_BABBLE), | |
636 | (bool)(qtd->token & QTD_TOKEN_XACTERR)); | |
637 | } | |
638 | ||
639 | static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd) | |
640 | { | |
641 | trace_usb_ehci_itd(addr, itd->next, | |
642 | get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT), | |
643 | get_field(itd->bufptr[2], ITD_BUFPTR_MULT), | |
644 | get_field(itd->bufptr[0], ITD_BUFPTR_EP), | |
645 | get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR)); | |
646 | } | |
647 | ||
648 | /* queue management */ | |
649 | ||
650 | static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async) | |
651 | { | |
652 | EHCIQueue *q; | |
653 | ||
654 | q = qemu_mallocz(sizeof(*q)); | |
655 | q->ehci = ehci; | |
656 | q->async_schedule = async; | |
657 | QTAILQ_INSERT_HEAD(&ehci->queues, q, next); | |
658 | trace_usb_ehci_queue_action(q, "alloc"); | |
659 | return q; | |
660 | } | |
661 | ||
662 | static void ehci_free_queue(EHCIQueue *q) | |
663 | { | |
664 | trace_usb_ehci_queue_action(q, "free"); | |
665 | if (q->async == EHCI_ASYNC_INFLIGHT) { | |
666 | usb_cancel_packet(&q->packet); | |
667 | } | |
668 | QTAILQ_REMOVE(&q->ehci->queues, q, next); | |
669 | qemu_free(q); | |
670 | } | |
671 | ||
672 | static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr) | |
673 | { | |
674 | EHCIQueue *q; | |
675 | ||
676 | QTAILQ_FOREACH(q, &ehci->queues, next) { | |
677 | if (addr == q->qhaddr) { | |
678 | return q; | |
679 | } | |
680 | } | |
681 | return NULL; | |
682 | } | |
683 | ||
684 | static void ehci_queues_rip_unused(EHCIState *ehci) | |
685 | { | |
686 | EHCIQueue *q, *tmp; | |
687 | ||
688 | QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) { | |
689 | if (q->seen) { | |
690 | q->seen = 0; | |
691 | q->ts = ehci->last_run_ns; | |
692 | continue; | |
693 | } | |
694 | if (ehci->last_run_ns < q->ts + 250000000) { | |
695 | /* allow 0.25 sec idle */ | |
696 | continue; | |
697 | } | |
698 | ehci_free_queue(q); | |
699 | } | |
700 | } | |
701 | ||
702 | static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev) | |
703 | { | |
704 | EHCIQueue *q, *tmp; | |
705 | ||
706 | QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) { | |
707 | if (q->packet.owner != dev) { | |
708 | continue; | |
709 | } | |
710 | ehci_free_queue(q); | |
711 | } | |
712 | } | |
713 | ||
714 | static void ehci_queues_rip_all(EHCIState *ehci) | |
715 | { | |
716 | EHCIQueue *q, *tmp; | |
717 | ||
718 | QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) { | |
719 | ehci_free_queue(q); | |
720 | } | |
721 | } | |
722 | ||
723 | /* Attach or detach a device on root hub */ | |
724 | ||
725 | static void ehci_attach(USBPort *port) | |
726 | { | |
727 | EHCIState *s = port->opaque; | |
728 | uint32_t *portsc = &s->portsc[port->index]; | |
729 | ||
730 | trace_usb_ehci_port_attach(port->index, port->dev->product_desc); | |
731 | ||
732 | if (*portsc & PORTSC_POWNER) { | |
733 | USBPort *companion = s->companion_ports[port->index]; | |
734 | companion->dev = port->dev; | |
735 | companion->ops->attach(companion); | |
736 | return; | |
737 | } | |
738 | ||
739 | *portsc |= PORTSC_CONNECT; | |
740 | *portsc |= PORTSC_CSC; | |
741 | ||
742 | ehci_set_interrupt(s, USBSTS_PCD); | |
743 | } | |
744 | ||
745 | static void ehci_detach(USBPort *port) | |
746 | { | |
747 | EHCIState *s = port->opaque; | |
748 | uint32_t *portsc = &s->portsc[port->index]; | |
749 | ||
750 | trace_usb_ehci_port_detach(port->index); | |
751 | ||
752 | if (*portsc & PORTSC_POWNER) { | |
753 | USBPort *companion = s->companion_ports[port->index]; | |
754 | companion->ops->detach(companion); | |
755 | companion->dev = NULL; | |
756 | return; | |
757 | } | |
758 | ||
759 | ehci_queues_rip_device(s, port->dev); | |
760 | ||
761 | *portsc &= ~(PORTSC_CONNECT|PORTSC_PED); | |
762 | *portsc |= PORTSC_CSC; | |
763 | ||
764 | ehci_set_interrupt(s, USBSTS_PCD); | |
765 | } | |
766 | ||
767 | static void ehci_child_detach(USBPort *port, USBDevice *child) | |
768 | { | |
769 | EHCIState *s = port->opaque; | |
770 | uint32_t portsc = s->portsc[port->index]; | |
771 | ||
772 | if (portsc & PORTSC_POWNER) { | |
773 | USBPort *companion = s->companion_ports[port->index]; | |
774 | companion->ops->child_detach(companion, child); | |
775 | companion->dev = NULL; | |
776 | return; | |
777 | } | |
778 | ||
779 | ehci_queues_rip_device(s, child); | |
780 | } | |
781 | ||
782 | static void ehci_wakeup(USBPort *port) | |
783 | { | |
784 | EHCIState *s = port->opaque; | |
785 | uint32_t portsc = s->portsc[port->index]; | |
786 | ||
787 | if (portsc & PORTSC_POWNER) { | |
788 | USBPort *companion = s->companion_ports[port->index]; | |
789 | if (companion->ops->wakeup) { | |
790 | companion->ops->wakeup(companion); | |
791 | } | |
792 | } | |
793 | } | |
794 | ||
795 | static int ehci_register_companion(USBBus *bus, USBPort *ports[], | |
796 | uint32_t portcount, uint32_t firstport) | |
797 | { | |
798 | EHCIState *s = container_of(bus, EHCIState, bus); | |
799 | uint32_t i; | |
800 | ||
801 | if (firstport + portcount > NB_PORTS) { | |
802 | qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport", | |
803 | "firstport on masterbus"); | |
804 | error_printf_unless_qmp( | |
805 | "firstport value of %u makes companion take ports %u - %u, which " | |
806 | "is outside of the valid range of 0 - %u\n", firstport, firstport, | |
807 | firstport + portcount - 1, NB_PORTS - 1); | |
808 | return -1; | |
809 | } | |
810 | ||
811 | for (i = 0; i < portcount; i++) { | |
812 | if (s->companion_ports[firstport + i]) { | |
813 | qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus", | |
814 | "an USB masterbus"); | |
815 | error_printf_unless_qmp( | |
816 | "port %u on masterbus %s already has a companion assigned\n", | |
817 | firstport + i, bus->qbus.name); | |
818 | return -1; | |
819 | } | |
820 | } | |
821 | ||
822 | for (i = 0; i < portcount; i++) { | |
823 | s->companion_ports[firstport + i] = ports[i]; | |
824 | s->ports[firstport + i].speedmask |= | |
825 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL; | |
826 | /* Ensure devs attached before the initial reset go to the companion */ | |
827 | s->portsc[firstport + i] = PORTSC_POWNER; | |
828 | } | |
829 | ||
830 | s->companion_count++; | |
831 | s->mmio[0x05] = (s->companion_count << 4) | portcount; | |
832 | ||
833 | return 0; | |
834 | } | |
835 | ||
836 | /* 4.1 host controller initialization */ | |
837 | static void ehci_reset(void *opaque) | |
838 | { | |
839 | EHCIState *s = opaque; | |
840 | int i; | |
841 | USBDevice *devs[NB_PORTS]; | |
842 | ||
843 | trace_usb_ehci_reset(); | |
844 | ||
845 | /* | |
846 | * Do the detach before touching portsc, so that it correctly gets send to | |
847 | * us or to our companion based on PORTSC_POWNER before the reset. | |
848 | */ | |
849 | for(i = 0; i < NB_PORTS; i++) { | |
850 | devs[i] = s->ports[i].dev; | |
851 | if (devs[i]) { | |
852 | usb_attach(&s->ports[i], NULL); | |
853 | } | |
854 | } | |
855 | ||
856 | memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE); | |
857 | ||
858 | s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; | |
859 | s->usbsts = USBSTS_HALT; | |
860 | ||
861 | s->astate = EST_INACTIVE; | |
862 | s->pstate = EST_INACTIVE; | |
863 | s->isoch_pause = -1; | |
864 | s->attach_poll_counter = 0; | |
865 | ||
866 | for(i = 0; i < NB_PORTS; i++) { | |
867 | if (s->companion_ports[i]) { | |
868 | s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; | |
869 | } else { | |
870 | s->portsc[i] = PORTSC_PPOWER; | |
871 | } | |
872 | if (devs[i]) { | |
873 | usb_attach(&s->ports[i], devs[i]); | |
874 | } | |
875 | } | |
876 | ehci_queues_rip_all(s); | |
877 | } | |
878 | ||
879 | static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr) | |
880 | { | |
881 | EHCIState *s = ptr; | |
882 | uint32_t val; | |
883 | ||
884 | val = s->mmio[addr]; | |
885 | ||
886 | return val; | |
887 | } | |
888 | ||
889 | static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr) | |
890 | { | |
891 | EHCIState *s = ptr; | |
892 | uint32_t val; | |
893 | ||
894 | val = s->mmio[addr] | (s->mmio[addr+1] << 8); | |
895 | ||
896 | return val; | |
897 | } | |
898 | ||
899 | static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr) | |
900 | { | |
901 | EHCIState *s = ptr; | |
902 | uint32_t val; | |
903 | ||
904 | val = s->mmio[addr] | (s->mmio[addr+1] << 8) | | |
905 | (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24); | |
906 | ||
907 | trace_usb_ehci_mmio_readl(addr, addr2str(addr), val); | |
908 | return val; | |
909 | } | |
910 | ||
911 | static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val) | |
912 | { | |
913 | fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n"); | |
914 | exit(1); | |
915 | } | |
916 | ||
917 | static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val) | |
918 | { | |
919 | fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n"); | |
920 | exit(1); | |
921 | } | |
922 | ||
923 | static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner) | |
924 | { | |
925 | USBDevice *dev = s->ports[port].dev; | |
926 | uint32_t *portsc = &s->portsc[port]; | |
927 | uint32_t orig; | |
928 | ||
929 | if (s->companion_ports[port] == NULL) | |
930 | return; | |
931 | ||
932 | owner = owner & PORTSC_POWNER; | |
933 | orig = *portsc & PORTSC_POWNER; | |
934 | ||
935 | if (!(owner ^ orig)) { | |
936 | return; | |
937 | } | |
938 | ||
939 | if (dev) { | |
940 | usb_attach(&s->ports[port], NULL); | |
941 | } | |
942 | ||
943 | *portsc &= ~PORTSC_POWNER; | |
944 | *portsc |= owner; | |
945 | ||
946 | if (dev) { | |
947 | usb_attach(&s->ports[port], dev); | |
948 | } | |
949 | } | |
950 | ||
951 | static void handle_port_status_write(EHCIState *s, int port, uint32_t val) | |
952 | { | |
953 | uint32_t *portsc = &s->portsc[port]; | |
954 | USBDevice *dev = s->ports[port].dev; | |
955 | ||
956 | /* Clear rwc bits */ | |
957 | *portsc &= ~(val & PORTSC_RWC_MASK); | |
958 | /* The guest may clear, but not set the PED bit */ | |
959 | *portsc &= val | ~PORTSC_PED; | |
960 | /* POWNER is masked out by RO_MASK as it is RO when we've no companion */ | |
961 | handle_port_owner_write(s, port, val); | |
962 | /* And finally apply RO_MASK */ | |
963 | val &= PORTSC_RO_MASK; | |
964 | ||
965 | if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) { | |
966 | trace_usb_ehci_port_reset(port, 1); | |
967 | } | |
968 | ||
969 | if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) { | |
970 | trace_usb_ehci_port_reset(port, 0); | |
971 | if (dev) { | |
972 | usb_attach(&s->ports[port], dev); | |
973 | usb_send_msg(dev, USB_MSG_RESET); | |
974 | *portsc &= ~PORTSC_CSC; | |
975 | } | |
976 | ||
977 | /* | |
978 | * Table 2.16 Set the enable bit(and enable bit change) to indicate | |
979 | * to SW that this port has a high speed device attached | |
980 | */ | |
981 | if (dev && (dev->speedmask & USB_SPEED_MASK_HIGH)) { | |
982 | val |= PORTSC_PED; | |
983 | } | |
984 | } | |
985 | ||
986 | *portsc &= ~PORTSC_RO_MASK; | |
987 | *portsc |= val; | |
988 | } | |
989 | ||
990 | static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val) | |
991 | { | |
992 | EHCIState *s = ptr; | |
993 | uint32_t *mmio = (uint32_t *)(&s->mmio[addr]); | |
994 | uint32_t old = *mmio; | |
995 | int i; | |
996 | ||
997 | trace_usb_ehci_mmio_writel(addr, addr2str(addr), val); | |
998 | ||
999 | /* Only aligned reads are allowed on OHCI */ | |
1000 | if (addr & 3) { | |
1001 | fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x" | |
1002 | TARGET_FMT_plx "\n", addr); | |
1003 | return; | |
1004 | } | |
1005 | ||
1006 | if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) { | |
1007 | handle_port_status_write(s, (addr-PORTSC)/4, val); | |
1008 | trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); | |
1009 | return; | |
1010 | } | |
1011 | ||
1012 | if (addr < OPREGBASE) { | |
1013 | fprintf(stderr, "usb-ehci: write attempt to read-only register" | |
1014 | TARGET_FMT_plx "\n", addr); | |
1015 | return; | |
1016 | } | |
1017 | ||
1018 | ||
1019 | /* Do any register specific pre-write processing here. */ | |
1020 | switch(addr) { | |
1021 | case USBCMD: | |
1022 | if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) { | |
1023 | qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); | |
1024 | SET_LAST_RUN_CLOCK(s); | |
1025 | ehci_clear_usbsts(s, USBSTS_HALT); | |
1026 | } | |
1027 | ||
1028 | if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
1029 | qemu_del_timer(s->frame_timer); | |
1030 | // TODO - should finish out some stuff before setting halt | |
1031 | ehci_set_usbsts(s, USBSTS_HALT); | |
1032 | } | |
1033 | ||
1034 | if (val & USBCMD_HCRESET) { | |
1035 | ehci_reset(s); | |
1036 | val &= ~USBCMD_HCRESET; | |
1037 | } | |
1038 | ||
1039 | /* not supporting dynamic frame list size at the moment */ | |
1040 | if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) { | |
1041 | fprintf(stderr, "attempt to set frame list size -- value %d\n", | |
1042 | val & USBCMD_FLS); | |
1043 | val &= ~USBCMD_FLS; | |
1044 | } | |
1045 | break; | |
1046 | ||
1047 | case USBSTS: | |
1048 | val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO | |
1049 | ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC | |
1050 | val = s->usbsts; | |
1051 | ehci_set_interrupt(s, 0); | |
1052 | break; | |
1053 | ||
1054 | case USBINTR: | |
1055 | val &= USBINTR_MASK; | |
1056 | break; | |
1057 | ||
1058 | case FRINDEX: | |
1059 | s->sofv = val >> 3; | |
1060 | break; | |
1061 | ||
1062 | case CONFIGFLAG: | |
1063 | val &= 0x1; | |
1064 | if (val) { | |
1065 | for(i = 0; i < NB_PORTS; i++) | |
1066 | handle_port_owner_write(s, i, 0); | |
1067 | } | |
1068 | break; | |
1069 | ||
1070 | case PERIODICLISTBASE: | |
1071 | if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
1072 | fprintf(stderr, | |
1073 | "ehci: PERIODIC list base register set while periodic schedule\n" | |
1074 | " is enabled and HC is enabled\n"); | |
1075 | } | |
1076 | break; | |
1077 | ||
1078 | case ASYNCLISTADDR: | |
1079 | if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
1080 | fprintf(stderr, | |
1081 | "ehci: ASYNC list address register set while async schedule\n" | |
1082 | " is enabled and HC is enabled\n"); | |
1083 | } | |
1084 | break; | |
1085 | } | |
1086 | ||
1087 | *mmio = val; | |
1088 | trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); | |
1089 | } | |
1090 | ||
1091 | ||
1092 | // TODO : Put in common header file, duplication from usb-ohci.c | |
1093 | ||
1094 | /* Get an array of dwords from main memory */ | |
1095 | static inline int get_dwords(uint32_t addr, uint32_t *buf, int num) | |
1096 | { | |
1097 | int i; | |
1098 | ||
1099 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
1100 | cpu_physical_memory_rw(addr,(uint8_t *)buf, sizeof(*buf), 0); | |
1101 | *buf = le32_to_cpu(*buf); | |
1102 | } | |
1103 | ||
1104 | return 1; | |
1105 | } | |
1106 | ||
1107 | /* Put an array of dwords in to main memory */ | |
1108 | static inline int put_dwords(uint32_t addr, uint32_t *buf, int num) | |
1109 | { | |
1110 | int i; | |
1111 | ||
1112 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
1113 | uint32_t tmp = cpu_to_le32(*buf); | |
1114 | cpu_physical_memory_rw(addr,(uint8_t *)&tmp, sizeof(tmp), 1); | |
1115 | } | |
1116 | ||
1117 | return 1; | |
1118 | } | |
1119 | ||
1120 | // 4.10.2 | |
1121 | ||
1122 | static int ehci_qh_do_overlay(EHCIQueue *q) | |
1123 | { | |
1124 | int i; | |
1125 | int dtoggle; | |
1126 | int ping; | |
1127 | int eps; | |
1128 | int reload; | |
1129 | ||
1130 | // remember values in fields to preserve in qh after overlay | |
1131 | ||
1132 | dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; | |
1133 | ping = q->qh.token & QTD_TOKEN_PING; | |
1134 | ||
1135 | q->qh.current_qtd = q->qtdaddr; | |
1136 | q->qh.next_qtd = q->qtd.next; | |
1137 | q->qh.altnext_qtd = q->qtd.altnext; | |
1138 | q->qh.token = q->qtd.token; | |
1139 | ||
1140 | ||
1141 | eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); | |
1142 | if (eps == EHCI_QH_EPS_HIGH) { | |
1143 | q->qh.token &= ~QTD_TOKEN_PING; | |
1144 | q->qh.token |= ping; | |
1145 | } | |
1146 | ||
1147 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); | |
1148 | set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); | |
1149 | ||
1150 | for (i = 0; i < 5; i++) { | |
1151 | q->qh.bufptr[i] = q->qtd.bufptr[i]; | |
1152 | } | |
1153 | ||
1154 | if (!(q->qh.epchar & QH_EPCHAR_DTC)) { | |
1155 | // preserve QH DT bit | |
1156 | q->qh.token &= ~QTD_TOKEN_DTOGGLE; | |
1157 | q->qh.token |= dtoggle; | |
1158 | } | |
1159 | ||
1160 | q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK; | |
1161 | q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK; | |
1162 | ||
1163 | put_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2); | |
1164 | ||
1165 | return 0; | |
1166 | } | |
1167 | ||
1168 | static int ehci_buffer_rw(EHCIQueue *q, int bytes, int rw) | |
1169 | { | |
1170 | int bufpos = 0; | |
1171 | int cpage, offset; | |
1172 | uint32_t head; | |
1173 | uint32_t tail; | |
1174 | ||
1175 | ||
1176 | if (!bytes) { | |
1177 | return 0; | |
1178 | } | |
1179 | ||
1180 | cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); | |
1181 | if (cpage > 4) { | |
1182 | fprintf(stderr, "cpage out of range (%d)\n", cpage); | |
1183 | return USB_RET_PROCERR; | |
1184 | } | |
1185 | ||
1186 | offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK; | |
1187 | ||
1188 | do { | |
1189 | /* start and end of this page */ | |
1190 | head = q->qh.bufptr[cpage] & QTD_BUFPTR_MASK; | |
1191 | tail = head + ~QTD_BUFPTR_MASK + 1; | |
1192 | /* add offset into page */ | |
1193 | head |= offset; | |
1194 | ||
1195 | if (bytes <= (tail - head)) { | |
1196 | tail = head + bytes; | |
1197 | } | |
1198 | ||
1199 | trace_usb_ehci_data(rw, cpage, offset, head, tail-head, bufpos); | |
1200 | cpu_physical_memory_rw(head, q->buffer + bufpos, tail - head, rw); | |
1201 | ||
1202 | bufpos += (tail - head); | |
1203 | offset += (tail - head); | |
1204 | bytes -= (tail - head); | |
1205 | ||
1206 | if (bytes > 0) { | |
1207 | cpage++; | |
1208 | offset = 0; | |
1209 | } | |
1210 | } while (bytes > 0); | |
1211 | ||
1212 | /* save cpage */ | |
1213 | set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); | |
1214 | ||
1215 | /* save offset into cpage */ | |
1216 | q->qh.bufptr[0] &= QTD_BUFPTR_MASK; | |
1217 | q->qh.bufptr[0] |= offset; | |
1218 | ||
1219 | return 0; | |
1220 | } | |
1221 | ||
1222 | static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) | |
1223 | { | |
1224 | EHCIQueue *q; | |
1225 | EHCIState *s = port->opaque; | |
1226 | uint32_t portsc = s->portsc[port->index]; | |
1227 | ||
1228 | if (portsc & PORTSC_POWNER) { | |
1229 | USBPort *companion = s->companion_ports[port->index]; | |
1230 | companion->ops->complete(companion, packet); | |
1231 | return; | |
1232 | } | |
1233 | ||
1234 | q = container_of(packet, EHCIQueue, packet); | |
1235 | trace_usb_ehci_queue_action(q, "wakeup"); | |
1236 | assert(q->async == EHCI_ASYNC_INFLIGHT); | |
1237 | q->async = EHCI_ASYNC_FINISHED; | |
1238 | q->usb_status = packet->len; | |
1239 | } | |
1240 | ||
1241 | static void ehci_execute_complete(EHCIQueue *q) | |
1242 | { | |
1243 | int c_err, reload; | |
1244 | ||
1245 | assert(q->async != EHCI_ASYNC_INFLIGHT); | |
1246 | q->async = EHCI_ASYNC_NONE; | |
1247 | ||
1248 | DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n", | |
1249 | q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status); | |
1250 | ||
1251 | if (q->usb_status < 0) { | |
1252 | err: | |
1253 | /* TO-DO: put this is in a function that can be invoked below as well */ | |
1254 | c_err = get_field(q->qh.token, QTD_TOKEN_CERR); | |
1255 | c_err--; | |
1256 | set_field(&q->qh.token, c_err, QTD_TOKEN_CERR); | |
1257 | ||
1258 | switch(q->usb_status) { | |
1259 | case USB_RET_NODEV: | |
1260 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); | |
1261 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); | |
1262 | break; | |
1263 | case USB_RET_STALL: | |
1264 | q->qh.token |= QTD_TOKEN_HALT; | |
1265 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); | |
1266 | break; | |
1267 | case USB_RET_NAK: | |
1268 | /* 4.10.3 */ | |
1269 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); | |
1270 | if ((q->pid == USB_TOKEN_IN) && reload) { | |
1271 | int nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT); | |
1272 | nakcnt--; | |
1273 | set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT); | |
1274 | } else if (!reload) { | |
1275 | return; | |
1276 | } | |
1277 | break; | |
1278 | case USB_RET_BABBLE: | |
1279 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); | |
1280 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); | |
1281 | break; | |
1282 | default: | |
1283 | /* should not be triggerable */ | |
1284 | fprintf(stderr, "USB invalid response %d to handle\n", q->usb_status); | |
1285 | assert(0); | |
1286 | break; | |
1287 | } | |
1288 | } else { | |
1289 | // DPRINTF("Short packet condition\n"); | |
1290 | // TODO check 4.12 for splits | |
1291 | ||
1292 | if ((q->usb_status > q->tbytes) && (q->pid == USB_TOKEN_IN)) { | |
1293 | q->usb_status = USB_RET_BABBLE; | |
1294 | goto err; | |
1295 | } | |
1296 | ||
1297 | if (q->tbytes && q->pid == USB_TOKEN_IN) { | |
1298 | if (ehci_buffer_rw(q, q->usb_status, 1) != 0) { | |
1299 | q->usb_status = USB_RET_PROCERR; | |
1300 | return; | |
1301 | } | |
1302 | q->tbytes -= q->usb_status; | |
1303 | } else { | |
1304 | q->tbytes = 0; | |
1305 | } | |
1306 | ||
1307 | DPRINTF("updating tbytes to %d\n", q->tbytes); | |
1308 | set_field(&q->qh.token, q->tbytes, QTD_TOKEN_TBYTES); | |
1309 | } | |
1310 | ||
1311 | q->qh.token ^= QTD_TOKEN_DTOGGLE; | |
1312 | q->qh.token &= ~QTD_TOKEN_ACTIVE; | |
1313 | ||
1314 | if ((q->usb_status >= 0) && (q->qh.token & QTD_TOKEN_IOC)) { | |
1315 | ehci_record_interrupt(q->ehci, USBSTS_INT); | |
1316 | } | |
1317 | } | |
1318 | ||
1319 | // 4.10.3 | |
1320 | ||
1321 | static int ehci_execute(EHCIQueue *q) | |
1322 | { | |
1323 | USBPort *port; | |
1324 | USBDevice *dev; | |
1325 | int ret; | |
1326 | int i; | |
1327 | int endp; | |
1328 | int devadr; | |
1329 | ||
1330 | if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) { | |
1331 | fprintf(stderr, "Attempting to execute inactive QH\n"); | |
1332 | return USB_RET_PROCERR; | |
1333 | } | |
1334 | ||
1335 | q->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH; | |
1336 | if (q->tbytes > BUFF_SIZE) { | |
1337 | fprintf(stderr, "Request for more bytes than allowed\n"); | |
1338 | return USB_RET_PROCERR; | |
1339 | } | |
1340 | ||
1341 | q->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH; | |
1342 | switch(q->pid) { | |
1343 | case 0: q->pid = USB_TOKEN_OUT; break; | |
1344 | case 1: q->pid = USB_TOKEN_IN; break; | |
1345 | case 2: q->pid = USB_TOKEN_SETUP; break; | |
1346 | default: fprintf(stderr, "bad token\n"); break; | |
1347 | } | |
1348 | ||
1349 | if ((q->tbytes && q->pid != USB_TOKEN_IN) && | |
1350 | (ehci_buffer_rw(q, q->tbytes, 0) != 0)) { | |
1351 | return USB_RET_PROCERR; | |
1352 | } | |
1353 | ||
1354 | endp = get_field(q->qh.epchar, QH_EPCHAR_EP); | |
1355 | devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR); | |
1356 | ||
1357 | ret = USB_RET_NODEV; | |
1358 | ||
1359 | // TO-DO: associating device with ehci port | |
1360 | for(i = 0; i < NB_PORTS; i++) { | |
1361 | port = &q->ehci->ports[i]; | |
1362 | dev = port->dev; | |
1363 | ||
1364 | if (!(q->ehci->portsc[i] &(PORTSC_CONNECT))) { | |
1365 | DPRINTF("Port %d, no exec, not connected(%08X)\n", | |
1366 | i, q->ehci->portsc[i]); | |
1367 | continue; | |
1368 | } | |
1369 | ||
1370 | q->packet.pid = q->pid; | |
1371 | q->packet.devaddr = devadr; | |
1372 | q->packet.devep = endp; | |
1373 | q->packet.data = q->buffer; | |
1374 | q->packet.len = q->tbytes; | |
1375 | ||
1376 | ret = usb_handle_packet(dev, &q->packet); | |
1377 | ||
1378 | DPRINTF("submit: qh %x next %x qtd %x pid %x len %d (total %d) endp %x ret %d\n", | |
1379 | q->qhaddr, q->qh.next, q->qtdaddr, q->pid, | |
1380 | q->packet.len, q->tbytes, endp, ret); | |
1381 | ||
1382 | if (ret != USB_RET_NODEV) { | |
1383 | break; | |
1384 | } | |
1385 | } | |
1386 | ||
1387 | if (ret > BUFF_SIZE) { | |
1388 | fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n"); | |
1389 | return USB_RET_PROCERR; | |
1390 | } | |
1391 | ||
1392 | return ret; | |
1393 | } | |
1394 | ||
1395 | /* 4.7.2 | |
1396 | */ | |
1397 | ||
1398 | static int ehci_process_itd(EHCIState *ehci, | |
1399 | EHCIitd *itd) | |
1400 | { | |
1401 | USBPort *port; | |
1402 | USBDevice *dev; | |
1403 | int ret; | |
1404 | uint32_t i, j, len, len1, len2, pid, dir, devaddr, endp; | |
1405 | uint32_t pg, off, ptr1, ptr2, max, mult; | |
1406 | ||
1407 | dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION); | |
1408 | devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR); | |
1409 | endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP); | |
1410 | max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT); | |
1411 | mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT); | |
1412 | ||
1413 | for(i = 0; i < 8; i++) { | |
1414 | if (itd->transact[i] & ITD_XACT_ACTIVE) { | |
1415 | pg = get_field(itd->transact[i], ITD_XACT_PGSEL); | |
1416 | off = itd->transact[i] & ITD_XACT_OFFSET_MASK; | |
1417 | ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); | |
1418 | ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK); | |
1419 | len = get_field(itd->transact[i], ITD_XACT_LENGTH); | |
1420 | ||
1421 | if (len > max * mult) { | |
1422 | len = max * mult; | |
1423 | } | |
1424 | ||
1425 | if (len > BUFF_SIZE) { | |
1426 | return USB_RET_PROCERR; | |
1427 | } | |
1428 | ||
1429 | if (off + len > 4096) { | |
1430 | /* transfer crosses page border */ | |
1431 | len2 = off + len - 4096; | |
1432 | len1 = len - len2; | |
1433 | } else { | |
1434 | len1 = len; | |
1435 | len2 = 0; | |
1436 | } | |
1437 | ||
1438 | if (!dir) { | |
1439 | pid = USB_TOKEN_OUT; | |
1440 | trace_usb_ehci_data(0, pg, off, ptr1 + off, len1, 0); | |
1441 | cpu_physical_memory_rw(ptr1 + off, &ehci->ibuffer[0], len1, 0); | |
1442 | if (len2) { | |
1443 | trace_usb_ehci_data(0, pg+1, 0, ptr2, len2, len1); | |
1444 | cpu_physical_memory_rw(ptr2, &ehci->ibuffer[len1], len2, 0); | |
1445 | } | |
1446 | } else { | |
1447 | pid = USB_TOKEN_IN; | |
1448 | } | |
1449 | ||
1450 | ret = USB_RET_NODEV; | |
1451 | ||
1452 | for (j = 0; j < NB_PORTS; j++) { | |
1453 | port = &ehci->ports[j]; | |
1454 | dev = port->dev; | |
1455 | ||
1456 | if (!(ehci->portsc[j] &(PORTSC_CONNECT))) { | |
1457 | continue; | |
1458 | } | |
1459 | ||
1460 | ehci->ipacket.pid = pid; | |
1461 | ehci->ipacket.devaddr = devaddr; | |
1462 | ehci->ipacket.devep = endp; | |
1463 | ehci->ipacket.data = ehci->ibuffer; | |
1464 | ehci->ipacket.len = len; | |
1465 | ||
1466 | ret = usb_handle_packet(dev, &ehci->ipacket); | |
1467 | ||
1468 | if (ret != USB_RET_NODEV) { | |
1469 | break; | |
1470 | } | |
1471 | } | |
1472 | ||
1473 | #if 0 | |
1474 | /* In isoch, there is no facility to indicate a NAK so let's | |
1475 | * instead just complete a zero-byte transaction. Setting | |
1476 | * DBERR seems too draconian. | |
1477 | */ | |
1478 | ||
1479 | if (ret == USB_RET_NAK) { | |
1480 | if (ehci->isoch_pause > 0) { | |
1481 | DPRINTF("ISOCH: received a NAK but paused so returning\n"); | |
1482 | ehci->isoch_pause--; | |
1483 | return 0; | |
1484 | } else if (ehci->isoch_pause == -1) { | |
1485 | DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n"); | |
1486 | // Pause frindex for up to 50 msec waiting for data from | |
1487 | // remote | |
1488 | ehci->isoch_pause = 50; | |
1489 | return 0; | |
1490 | } else { | |
1491 | DPRINTF("ISOCH: isoch pause timeout! return 0\n"); | |
1492 | ret = 0; | |
1493 | } | |
1494 | } else { | |
1495 | DPRINTF("ISOCH: received ACK, clearing pause\n"); | |
1496 | ehci->isoch_pause = -1; | |
1497 | } | |
1498 | #else | |
1499 | if (ret == USB_RET_NAK) { | |
1500 | ret = 0; | |
1501 | } | |
1502 | #endif | |
1503 | ||
1504 | if (ret >= 0) { | |
1505 | if (!dir) { | |
1506 | /* OUT */ | |
1507 | set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH); | |
1508 | } else { | |
1509 | /* IN */ | |
1510 | if (len1 > ret) { | |
1511 | len1 = ret; | |
1512 | } | |
1513 | if (len2 > ret - len1) { | |
1514 | len2 = ret - len1; | |
1515 | } | |
1516 | if (len1) { | |
1517 | trace_usb_ehci_data(1, pg, off, ptr1 + off, len1, 0); | |
1518 | cpu_physical_memory_rw(ptr1 + off, &ehci->ibuffer[0], len1, 1); | |
1519 | } | |
1520 | if (len2) { | |
1521 | trace_usb_ehci_data(1, pg+1, 0, ptr2, len2, len1); | |
1522 | cpu_physical_memory_rw(ptr2, &ehci->ibuffer[len1], len2, 1); | |
1523 | } | |
1524 | set_field(&itd->transact[i], ret, ITD_XACT_LENGTH); | |
1525 | } | |
1526 | ||
1527 | if (itd->transact[i] & ITD_XACT_IOC) { | |
1528 | ehci_record_interrupt(ehci, USBSTS_INT); | |
1529 | } | |
1530 | } | |
1531 | itd->transact[i] &= ~ITD_XACT_ACTIVE; | |
1532 | } | |
1533 | } | |
1534 | return 0; | |
1535 | } | |
1536 | ||
1537 | /* This state is the entry point for asynchronous schedule | |
1538 | * processing. Entry here consitutes a EHCI start event state (4.8.5) | |
1539 | */ | |
1540 | static int ehci_state_waitlisthead(EHCIState *ehci, int async) | |
1541 | { | |
1542 | EHCIqh qh; | |
1543 | int i = 0; | |
1544 | int again = 0; | |
1545 | uint32_t entry = ehci->asynclistaddr; | |
1546 | ||
1547 | /* set reclamation flag at start event (4.8.6) */ | |
1548 | if (async) { | |
1549 | ehci_set_usbsts(ehci, USBSTS_REC); | |
1550 | } | |
1551 | ||
1552 | ehci_queues_rip_unused(ehci); | |
1553 | ||
1554 | /* Find the head of the list (4.9.1.1) */ | |
1555 | for(i = 0; i < MAX_QH; i++) { | |
1556 | get_dwords(NLPTR_GET(entry), (uint32_t *) &qh, sizeof(EHCIqh) >> 2); | |
1557 | ehci_trace_qh(NULL, NLPTR_GET(entry), &qh); | |
1558 | ||
1559 | if (qh.epchar & QH_EPCHAR_H) { | |
1560 | if (async) { | |
1561 | entry |= (NLPTR_TYPE_QH << 1); | |
1562 | } | |
1563 | ||
1564 | ehci_set_fetch_addr(ehci, async, entry); | |
1565 | ehci_set_state(ehci, async, EST_FETCHENTRY); | |
1566 | again = 1; | |
1567 | goto out; | |
1568 | } | |
1569 | ||
1570 | entry = qh.next; | |
1571 | if (entry == ehci->asynclistaddr) { | |
1572 | break; | |
1573 | } | |
1574 | } | |
1575 | ||
1576 | /* no head found for list. */ | |
1577 | ||
1578 | ehci_set_state(ehci, async, EST_ACTIVE); | |
1579 | ||
1580 | out: | |
1581 | return again; | |
1582 | } | |
1583 | ||
1584 | ||
1585 | /* This state is the entry point for periodic schedule processing as | |
1586 | * well as being a continuation state for async processing. | |
1587 | */ | |
1588 | static int ehci_state_fetchentry(EHCIState *ehci, int async) | |
1589 | { | |
1590 | int again = 0; | |
1591 | uint32_t entry = ehci_get_fetch_addr(ehci, async); | |
1592 | ||
1593 | if (entry < 0x1000) { | |
1594 | DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry); | |
1595 | ehci_set_state(ehci, async, EST_ACTIVE); | |
1596 | goto out; | |
1597 | } | |
1598 | ||
1599 | /* section 4.8, only QH in async schedule */ | |
1600 | if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) { | |
1601 | fprintf(stderr, "non queue head request in async schedule\n"); | |
1602 | return -1; | |
1603 | } | |
1604 | ||
1605 | switch (NLPTR_TYPE_GET(entry)) { | |
1606 | case NLPTR_TYPE_QH: | |
1607 | ehci_set_state(ehci, async, EST_FETCHQH); | |
1608 | again = 1; | |
1609 | break; | |
1610 | ||
1611 | case NLPTR_TYPE_ITD: | |
1612 | ehci_set_state(ehci, async, EST_FETCHITD); | |
1613 | again = 1; | |
1614 | break; | |
1615 | ||
1616 | default: | |
1617 | // TODO: handle siTD and FSTN types | |
1618 | fprintf(stderr, "FETCHENTRY: entry at %X is of type %d " | |
1619 | "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry)); | |
1620 | return -1; | |
1621 | } | |
1622 | ||
1623 | out: | |
1624 | return again; | |
1625 | } | |
1626 | ||
1627 | static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) | |
1628 | { | |
1629 | uint32_t entry; | |
1630 | EHCIQueue *q; | |
1631 | int reload; | |
1632 | ||
1633 | entry = ehci_get_fetch_addr(ehci, async); | |
1634 | q = ehci_find_queue_by_qh(ehci, entry); | |
1635 | if (NULL == q) { | |
1636 | q = ehci_alloc_queue(ehci, async); | |
1637 | } | |
1638 | q->qhaddr = entry; | |
1639 | q->seen++; | |
1640 | ||
1641 | if (q->seen > 1) { | |
1642 | /* we are going in circles -- stop processing */ | |
1643 | ehci_set_state(ehci, async, EST_ACTIVE); | |
1644 | q = NULL; | |
1645 | goto out; | |
1646 | } | |
1647 | ||
1648 | get_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2); | |
1649 | ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh); | |
1650 | ||
1651 | if (q->async == EHCI_ASYNC_INFLIGHT) { | |
1652 | /* I/O still in progress -- skip queue */ | |
1653 | ehci_set_state(ehci, async, EST_HORIZONTALQH); | |
1654 | goto out; | |
1655 | } | |
1656 | if (q->async == EHCI_ASYNC_FINISHED) { | |
1657 | /* I/O finished -- continue processing queue */ | |
1658 | trace_usb_ehci_queue_action(q, "resume"); | |
1659 | ehci_set_state(ehci, async, EST_EXECUTING); | |
1660 | goto out; | |
1661 | } | |
1662 | ||
1663 | if (async && (q->qh.epchar & QH_EPCHAR_H)) { | |
1664 | ||
1665 | /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */ | |
1666 | if (ehci->usbsts & USBSTS_REC) { | |
1667 | ehci_clear_usbsts(ehci, USBSTS_REC); | |
1668 | } else { | |
1669 | DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset" | |
1670 | " - done processing\n", q->qhaddr); | |
1671 | ehci_set_state(ehci, async, EST_ACTIVE); | |
1672 | q = NULL; | |
1673 | goto out; | |
1674 | } | |
1675 | } | |
1676 | ||
1677 | #if EHCI_DEBUG | |
1678 | if (q->qhaddr != q->qh.next) { | |
1679 | DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n", | |
1680 | q->qhaddr, | |
1681 | q->qh.epchar & QH_EPCHAR_H, | |
1682 | q->qh.token & QTD_TOKEN_HALT, | |
1683 | q->qh.token & QTD_TOKEN_ACTIVE, | |
1684 | q->qh.next); | |
1685 | } | |
1686 | #endif | |
1687 | ||
1688 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); | |
1689 | if (reload) { | |
1690 | set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); | |
1691 | } | |
1692 | ||
1693 | if (q->qh.token & QTD_TOKEN_HALT) { | |
1694 | ehci_set_state(ehci, async, EST_HORIZONTALQH); | |
1695 | ||
1696 | } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && (q->qh.current_qtd > 0x1000)) { | |
1697 | q->qtdaddr = q->qh.current_qtd; | |
1698 | ehci_set_state(ehci, async, EST_FETCHQTD); | |
1699 | ||
1700 | } else { | |
1701 | /* EHCI spec version 1.0 Section 4.10.2 */ | |
1702 | ehci_set_state(ehci, async, EST_ADVANCEQUEUE); | |
1703 | } | |
1704 | ||
1705 | out: | |
1706 | return q; | |
1707 | } | |
1708 | ||
1709 | static int ehci_state_fetchitd(EHCIState *ehci, int async) | |
1710 | { | |
1711 | uint32_t entry; | |
1712 | EHCIitd itd; | |
1713 | ||
1714 | assert(!async); | |
1715 | entry = ehci_get_fetch_addr(ehci, async); | |
1716 | ||
1717 | get_dwords(NLPTR_GET(entry),(uint32_t *) &itd, | |
1718 | sizeof(EHCIitd) >> 2); | |
1719 | ehci_trace_itd(ehci, entry, &itd); | |
1720 | ||
1721 | if (ehci_process_itd(ehci, &itd) != 0) { | |
1722 | return -1; | |
1723 | } | |
1724 | ||
1725 | put_dwords(NLPTR_GET(entry), (uint32_t *) &itd, | |
1726 | sizeof(EHCIitd) >> 2); | |
1727 | ehci_set_fetch_addr(ehci, async, itd.next); | |
1728 | ehci_set_state(ehci, async, EST_FETCHENTRY); | |
1729 | ||
1730 | return 1; | |
1731 | } | |
1732 | ||
1733 | /* Section 4.10.2 - paragraph 3 */ | |
1734 | static int ehci_state_advqueue(EHCIQueue *q, int async) | |
1735 | { | |
1736 | #if 0 | |
1737 | /* TO-DO: 4.10.2 - paragraph 2 | |
1738 | * if I-bit is set to 1 and QH is not active | |
1739 | * go to horizontal QH | |
1740 | */ | |
1741 | if (I-bit set) { | |
1742 | ehci_set_state(ehci, async, EST_HORIZONTALQH); | |
1743 | goto out; | |
1744 | } | |
1745 | #endif | |
1746 | ||
1747 | /* | |
1748 | * want data and alt-next qTD is valid | |
1749 | */ | |
1750 | if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && | |
1751 | (q->qh.altnext_qtd > 0x1000) && | |
1752 | (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) { | |
1753 | q->qtdaddr = q->qh.altnext_qtd; | |
1754 | ehci_set_state(q->ehci, async, EST_FETCHQTD); | |
1755 | ||
1756 | /* | |
1757 | * next qTD is valid | |
1758 | */ | |
1759 | } else if ((q->qh.next_qtd > 0x1000) && | |
1760 | (NLPTR_TBIT(q->qh.next_qtd) == 0)) { | |
1761 | q->qtdaddr = q->qh.next_qtd; | |
1762 | ehci_set_state(q->ehci, async, EST_FETCHQTD); | |
1763 | ||
1764 | /* | |
1765 | * no valid qTD, try next QH | |
1766 | */ | |
1767 | } else { | |
1768 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
1769 | } | |
1770 | ||
1771 | return 1; | |
1772 | } | |
1773 | ||
1774 | /* Section 4.10.2 - paragraph 4 */ | |
1775 | static int ehci_state_fetchqtd(EHCIQueue *q, int async) | |
1776 | { | |
1777 | int again = 0; | |
1778 | ||
1779 | get_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qtd, sizeof(EHCIqtd) >> 2); | |
1780 | ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &q->qtd); | |
1781 | ||
1782 | if (q->qtd.token & QTD_TOKEN_ACTIVE) { | |
1783 | ehci_set_state(q->ehci, async, EST_EXECUTE); | |
1784 | again = 1; | |
1785 | } else { | |
1786 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
1787 | again = 1; | |
1788 | } | |
1789 | ||
1790 | return again; | |
1791 | } | |
1792 | ||
1793 | static int ehci_state_horizqh(EHCIQueue *q, int async) | |
1794 | { | |
1795 | int again = 0; | |
1796 | ||
1797 | if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) { | |
1798 | ehci_set_fetch_addr(q->ehci, async, q->qh.next); | |
1799 | ehci_set_state(q->ehci, async, EST_FETCHENTRY); | |
1800 | again = 1; | |
1801 | } else { | |
1802 | ehci_set_state(q->ehci, async, EST_ACTIVE); | |
1803 | } | |
1804 | ||
1805 | return again; | |
1806 | } | |
1807 | ||
1808 | /* | |
1809 | * Write the qh back to guest physical memory. This step isn't | |
1810 | * in the EHCI spec but we need to do it since we don't share | |
1811 | * physical memory with our guest VM. | |
1812 | * | |
1813 | * The first three dwords are read-only for the EHCI, so skip them | |
1814 | * when writing back the qh. | |
1815 | */ | |
1816 | static void ehci_flush_qh(EHCIQueue *q) | |
1817 | { | |
1818 | uint32_t *qh = (uint32_t *) &q->qh; | |
1819 | uint32_t dwords = sizeof(EHCIqh) >> 2; | |
1820 | uint32_t addr = NLPTR_GET(q->qhaddr); | |
1821 | ||
1822 | put_dwords(addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); | |
1823 | } | |
1824 | ||
1825 | static int ehci_state_execute(EHCIQueue *q, int async) | |
1826 | { | |
1827 | int again = 0; | |
1828 | int reload, nakcnt; | |
1829 | int smask; | |
1830 | ||
1831 | if (ehci_qh_do_overlay(q) != 0) { | |
1832 | return -1; | |
1833 | } | |
1834 | ||
1835 | smask = get_field(q->qh.epcap, QH_EPCAP_SMASK); | |
1836 | ||
1837 | if (!smask) { | |
1838 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); | |
1839 | nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT); | |
1840 | if (reload && !nakcnt) { | |
1841 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
1842 | again = 1; | |
1843 | goto out; | |
1844 | } | |
1845 | } | |
1846 | ||
1847 | // TODO verify enough time remains in the uframe as in 4.4.1.1 | |
1848 | // TODO write back ptr to async list when done or out of time | |
1849 | // TODO Windows does not seem to ever set the MULT field | |
1850 | ||
1851 | if (!async) { | |
1852 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); | |
1853 | if (!transactCtr) { | |
1854 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
1855 | again = 1; | |
1856 | goto out; | |
1857 | } | |
1858 | } | |
1859 | ||
1860 | if (async) { | |
1861 | ehci_set_usbsts(q->ehci, USBSTS_REC); | |
1862 | } | |
1863 | ||
1864 | q->usb_status = ehci_execute(q); | |
1865 | if (q->usb_status == USB_RET_PROCERR) { | |
1866 | again = -1; | |
1867 | goto out; | |
1868 | } | |
1869 | if (q->usb_status == USB_RET_ASYNC) { | |
1870 | ehci_flush_qh(q); | |
1871 | trace_usb_ehci_queue_action(q, "suspend"); | |
1872 | q->async = EHCI_ASYNC_INFLIGHT; | |
1873 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
1874 | again = 1; | |
1875 | goto out; | |
1876 | } | |
1877 | ||
1878 | ehci_set_state(q->ehci, async, EST_EXECUTING); | |
1879 | again = 1; | |
1880 | ||
1881 | out: | |
1882 | return again; | |
1883 | } | |
1884 | ||
1885 | static int ehci_state_executing(EHCIQueue *q, int async) | |
1886 | { | |
1887 | int again = 0; | |
1888 | int reload, nakcnt; | |
1889 | ||
1890 | ehci_execute_complete(q); | |
1891 | if (q->usb_status == USB_RET_ASYNC) { | |
1892 | goto out; | |
1893 | } | |
1894 | if (q->usb_status == USB_RET_PROCERR) { | |
1895 | again = -1; | |
1896 | goto out; | |
1897 | } | |
1898 | ||
1899 | // 4.10.3 | |
1900 | if (!async) { | |
1901 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); | |
1902 | transactCtr--; | |
1903 | set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT); | |
1904 | // 4.10.3, bottom of page 82, should exit this state when transaction | |
1905 | // counter decrements to 0 | |
1906 | } | |
1907 | ||
1908 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); | |
1909 | if (reload) { | |
1910 | nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT); | |
1911 | if (q->usb_status == USB_RET_NAK) { | |
1912 | if (nakcnt) { | |
1913 | nakcnt--; | |
1914 | } | |
1915 | } else { | |
1916 | nakcnt = reload; | |
1917 | } | |
1918 | set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT); | |
1919 | } | |
1920 | ||
1921 | /* 4.10.5 */ | |
1922 | if ((q->usb_status == USB_RET_NAK) || (q->qh.token & QTD_TOKEN_ACTIVE)) { | |
1923 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
1924 | } else { | |
1925 | ehci_set_state(q->ehci, async, EST_WRITEBACK); | |
1926 | } | |
1927 | ||
1928 | again = 1; | |
1929 | ||
1930 | out: | |
1931 | ehci_flush_qh(q); | |
1932 | return again; | |
1933 | } | |
1934 | ||
1935 | ||
1936 | static int ehci_state_writeback(EHCIQueue *q, int async) | |
1937 | { | |
1938 | int again = 0; | |
1939 | ||
1940 | /* Write back the QTD from the QH area */ | |
1941 | ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), (EHCIqtd*) &q->qh.next_qtd); | |
1942 | put_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qh.next_qtd, | |
1943 | sizeof(EHCIqtd) >> 2); | |
1944 | ||
1945 | /* | |
1946 | * EHCI specs say go horizontal here. | |
1947 | * | |
1948 | * We can also advance the queue here for performance reasons. We | |
1949 | * need to take care to only take that shortcut in case we've | |
1950 | * processed the qtd just written back without errors, i.e. halt | |
1951 | * bit is clear. | |
1952 | */ | |
1953 | if (q->qh.token & QTD_TOKEN_HALT) { | |
1954 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
1955 | again = 1; | |
1956 | } else { | |
1957 | ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE); | |
1958 | again = 1; | |
1959 | } | |
1960 | return again; | |
1961 | } | |
1962 | ||
1963 | /* | |
1964 | * This is the state machine that is common to both async and periodic | |
1965 | */ | |
1966 | ||
1967 | static void ehci_advance_state(EHCIState *ehci, | |
1968 | int async) | |
1969 | { | |
1970 | EHCIQueue *q = NULL; | |
1971 | int again; | |
1972 | int iter = 0; | |
1973 | ||
1974 | do { | |
1975 | if (ehci_get_state(ehci, async) == EST_FETCHQH) { | |
1976 | iter++; | |
1977 | /* if we are roaming a lot of QH without executing a qTD | |
1978 | * something is wrong with the linked list. TO-DO: why is | |
1979 | * this hack needed? | |
1980 | */ | |
1981 | assert(iter < MAX_ITERATIONS); | |
1982 | #if 0 | |
1983 | if (iter > MAX_ITERATIONS) { | |
1984 | DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n"); | |
1985 | ehci_set_state(ehci, async, EST_ACTIVE); | |
1986 | break; | |
1987 | } | |
1988 | #endif | |
1989 | } | |
1990 | switch(ehci_get_state(ehci, async)) { | |
1991 | case EST_WAITLISTHEAD: | |
1992 | again = ehci_state_waitlisthead(ehci, async); | |
1993 | break; | |
1994 | ||
1995 | case EST_FETCHENTRY: | |
1996 | again = ehci_state_fetchentry(ehci, async); | |
1997 | break; | |
1998 | ||
1999 | case EST_FETCHQH: | |
2000 | q = ehci_state_fetchqh(ehci, async); | |
2001 | again = q ? 1 : 0; | |
2002 | break; | |
2003 | ||
2004 | case EST_FETCHITD: | |
2005 | again = ehci_state_fetchitd(ehci, async); | |
2006 | break; | |
2007 | ||
2008 | case EST_ADVANCEQUEUE: | |
2009 | again = ehci_state_advqueue(q, async); | |
2010 | break; | |
2011 | ||
2012 | case EST_FETCHQTD: | |
2013 | again = ehci_state_fetchqtd(q, async); | |
2014 | break; | |
2015 | ||
2016 | case EST_HORIZONTALQH: | |
2017 | again = ehci_state_horizqh(q, async); | |
2018 | break; | |
2019 | ||
2020 | case EST_EXECUTE: | |
2021 | iter = 0; | |
2022 | again = ehci_state_execute(q, async); | |
2023 | break; | |
2024 | ||
2025 | case EST_EXECUTING: | |
2026 | assert(q != NULL); | |
2027 | again = ehci_state_executing(q, async); | |
2028 | break; | |
2029 | ||
2030 | case EST_WRITEBACK: | |
2031 | again = ehci_state_writeback(q, async); | |
2032 | break; | |
2033 | ||
2034 | default: | |
2035 | fprintf(stderr, "Bad state!\n"); | |
2036 | again = -1; | |
2037 | assert(0); | |
2038 | break; | |
2039 | } | |
2040 | ||
2041 | if (again < 0) { | |
2042 | fprintf(stderr, "processing error - resetting ehci HC\n"); | |
2043 | ehci_reset(ehci); | |
2044 | again = 0; | |
2045 | assert(0); | |
2046 | } | |
2047 | } | |
2048 | while (again); | |
2049 | ||
2050 | ehci_commit_interrupt(ehci); | |
2051 | } | |
2052 | ||
2053 | static void ehci_advance_async_state(EHCIState *ehci) | |
2054 | { | |
2055 | int async = 1; | |
2056 | ||
2057 | switch(ehci_get_state(ehci, async)) { | |
2058 | case EST_INACTIVE: | |
2059 | if (!(ehci->usbcmd & USBCMD_ASE)) { | |
2060 | break; | |
2061 | } | |
2062 | ehci_set_usbsts(ehci, USBSTS_ASS); | |
2063 | ehci_set_state(ehci, async, EST_ACTIVE); | |
2064 | // No break, fall through to ACTIVE | |
2065 | ||
2066 | case EST_ACTIVE: | |
2067 | if ( !(ehci->usbcmd & USBCMD_ASE)) { | |
2068 | ehci_clear_usbsts(ehci, USBSTS_ASS); | |
2069 | ehci_set_state(ehci, async, EST_INACTIVE); | |
2070 | break; | |
2071 | } | |
2072 | ||
2073 | /* If the doorbell is set, the guest wants to make a change to the | |
2074 | * schedule. The host controller needs to release cached data. | |
2075 | * (section 4.8.2) | |
2076 | */ | |
2077 | if (ehci->usbcmd & USBCMD_IAAD) { | |
2078 | DPRINTF("ASYNC: doorbell request acknowledged\n"); | |
2079 | ehci->usbcmd &= ~USBCMD_IAAD; | |
2080 | ehci_set_interrupt(ehci, USBSTS_IAA); | |
2081 | break; | |
2082 | } | |
2083 | ||
2084 | /* make sure guest has acknowledged */ | |
2085 | /* TO-DO: is this really needed? */ | |
2086 | if (ehci->usbsts & USBSTS_IAA) { | |
2087 | DPRINTF("IAA status bit still set.\n"); | |
2088 | break; | |
2089 | } | |
2090 | ||
2091 | /* check that address register has been set */ | |
2092 | if (ehci->asynclistaddr == 0) { | |
2093 | break; | |
2094 | } | |
2095 | ||
2096 | ehci_set_state(ehci, async, EST_WAITLISTHEAD); | |
2097 | ehci_advance_state(ehci, async); | |
2098 | break; | |
2099 | ||
2100 | default: | |
2101 | /* this should only be due to a developer mistake */ | |
2102 | fprintf(stderr, "ehci: Bad asynchronous state %d. " | |
2103 | "Resetting to active\n", ehci->astate); | |
2104 | assert(0); | |
2105 | } | |
2106 | } | |
2107 | ||
2108 | static void ehci_advance_periodic_state(EHCIState *ehci) | |
2109 | { | |
2110 | uint32_t entry; | |
2111 | uint32_t list; | |
2112 | int async = 0; | |
2113 | ||
2114 | // 4.6 | |
2115 | ||
2116 | switch(ehci_get_state(ehci, async)) { | |
2117 | case EST_INACTIVE: | |
2118 | if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) { | |
2119 | ehci_set_usbsts(ehci, USBSTS_PSS); | |
2120 | ehci_set_state(ehci, async, EST_ACTIVE); | |
2121 | // No break, fall through to ACTIVE | |
2122 | } else | |
2123 | break; | |
2124 | ||
2125 | case EST_ACTIVE: | |
2126 | if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) { | |
2127 | ehci_clear_usbsts(ehci, USBSTS_PSS); | |
2128 | ehci_set_state(ehci, async, EST_INACTIVE); | |
2129 | break; | |
2130 | } | |
2131 | ||
2132 | list = ehci->periodiclistbase & 0xfffff000; | |
2133 | /* check that register has been set */ | |
2134 | if (list == 0) { | |
2135 | break; | |
2136 | } | |
2137 | list |= ((ehci->frindex & 0x1ff8) >> 1); | |
2138 | ||
2139 | cpu_physical_memory_rw(list, (uint8_t *) &entry, sizeof entry, 0); | |
2140 | entry = le32_to_cpu(entry); | |
2141 | ||
2142 | DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n", | |
2143 | ehci->frindex / 8, list, entry); | |
2144 | ehci_set_fetch_addr(ehci, async,entry); | |
2145 | ehci_set_state(ehci, async, EST_FETCHENTRY); | |
2146 | ehci_advance_state(ehci, async); | |
2147 | break; | |
2148 | ||
2149 | default: | |
2150 | /* this should only be due to a developer mistake */ | |
2151 | fprintf(stderr, "ehci: Bad periodic state %d. " | |
2152 | "Resetting to active\n", ehci->pstate); | |
2153 | assert(0); | |
2154 | } | |
2155 | } | |
2156 | ||
2157 | static void ehci_frame_timer(void *opaque) | |
2158 | { | |
2159 | EHCIState *ehci = opaque; | |
2160 | int64_t expire_time, t_now; | |
2161 | uint64_t ns_elapsed; | |
2162 | int frames; | |
2163 | int i; | |
2164 | int skipped_frames = 0; | |
2165 | ||
2166 | t_now = qemu_get_clock_ns(vm_clock); | |
2167 | expire_time = t_now + (get_ticks_per_sec() / ehci->freq); | |
2168 | ||
2169 | ns_elapsed = t_now - ehci->last_run_ns; | |
2170 | frames = ns_elapsed / FRAME_TIMER_NS; | |
2171 | ||
2172 | for (i = 0; i < frames; i++) { | |
2173 | if ( !(ehci->usbsts & USBSTS_HALT)) { | |
2174 | if (ehci->isoch_pause <= 0) { | |
2175 | ehci->frindex += 8; | |
2176 | } | |
2177 | ||
2178 | if (ehci->frindex > 0x00001fff) { | |
2179 | ehci->frindex = 0; | |
2180 | ehci_set_interrupt(ehci, USBSTS_FLR); | |
2181 | } | |
2182 | ||
2183 | ehci->sofv = (ehci->frindex - 1) >> 3; | |
2184 | ehci->sofv &= 0x000003ff; | |
2185 | } | |
2186 | ||
2187 | if (frames - i > ehci->maxframes) { | |
2188 | skipped_frames++; | |
2189 | } else { | |
2190 | ehci_advance_periodic_state(ehci); | |
2191 | } | |
2192 | ||
2193 | ehci->last_run_ns += FRAME_TIMER_NS; | |
2194 | } | |
2195 | ||
2196 | #if 0 | |
2197 | if (skipped_frames) { | |
2198 | DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames); | |
2199 | } | |
2200 | #endif | |
2201 | ||
2202 | /* Async is not inside loop since it executes everything it can once | |
2203 | * called | |
2204 | */ | |
2205 | ehci_advance_async_state(ehci); | |
2206 | ||
2207 | qemu_mod_timer(ehci->frame_timer, expire_time); | |
2208 | } | |
2209 | ||
2210 | static CPUReadMemoryFunc *ehci_readfn[3]={ | |
2211 | ehci_mem_readb, | |
2212 | ehci_mem_readw, | |
2213 | ehci_mem_readl | |
2214 | }; | |
2215 | ||
2216 | static CPUWriteMemoryFunc *ehci_writefn[3]={ | |
2217 | ehci_mem_writeb, | |
2218 | ehci_mem_writew, | |
2219 | ehci_mem_writel | |
2220 | }; | |
2221 | ||
2222 | static void ehci_map(PCIDevice *pci_dev, int region_num, | |
2223 | pcibus_t addr, pcibus_t size, int type) | |
2224 | { | |
2225 | EHCIState *s =(EHCIState *)pci_dev; | |
2226 | ||
2227 | DPRINTF("ehci_map: region %d, addr %08" PRIx64 ", size %" PRId64 ", s->mem %08X\n", | |
2228 | region_num, addr, size, s->mem); | |
2229 | s->mem_base = addr; | |
2230 | cpu_register_physical_memory(addr, size, s->mem); | |
2231 | } | |
2232 | ||
2233 | static int usb_ehci_initfn(PCIDevice *dev); | |
2234 | ||
2235 | static USBPortOps ehci_port_ops = { | |
2236 | .attach = ehci_attach, | |
2237 | .detach = ehci_detach, | |
2238 | .child_detach = ehci_child_detach, | |
2239 | .wakeup = ehci_wakeup, | |
2240 | .complete = ehci_async_complete_packet, | |
2241 | }; | |
2242 | ||
2243 | static USBBusOps ehci_bus_ops = { | |
2244 | .register_companion = ehci_register_companion, | |
2245 | }; | |
2246 | ||
2247 | static Property ehci_properties[] = { | |
2248 | DEFINE_PROP_UINT32("freq", EHCIState, freq, FRAME_TIMER_FREQ), | |
2249 | DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), | |
2250 | DEFINE_PROP_END_OF_LIST(), | |
2251 | }; | |
2252 | ||
2253 | static PCIDeviceInfo ehci_info[] = { | |
2254 | { | |
2255 | .qdev.name = "usb-ehci", | |
2256 | .qdev.size = sizeof(EHCIState), | |
2257 | .init = usb_ehci_initfn, | |
2258 | .vendor_id = PCI_VENDOR_ID_INTEL, | |
2259 | .device_id = PCI_DEVICE_ID_INTEL_82801D, /* ich4 */ | |
2260 | .revision = 0x10, | |
2261 | .class_id = PCI_CLASS_SERIAL_USB, | |
2262 | .qdev.props = ehci_properties, | |
2263 | },{ | |
2264 | .qdev.name = "ich9-usb-ehci1", | |
2265 | .qdev.size = sizeof(EHCIState), | |
2266 | .init = usb_ehci_initfn, | |
2267 | .vendor_id = PCI_VENDOR_ID_INTEL, | |
2268 | .device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1, | |
2269 | .revision = 0x03, | |
2270 | .class_id = PCI_CLASS_SERIAL_USB, | |
2271 | .qdev.props = ehci_properties, | |
2272 | },{ | |
2273 | /* end of list */ | |
2274 | } | |
2275 | }; | |
2276 | ||
2277 | static int usb_ehci_initfn(PCIDevice *dev) | |
2278 | { | |
2279 | EHCIState *s = DO_UPCAST(EHCIState, dev, dev); | |
2280 | uint8_t *pci_conf = s->dev.config; | |
2281 | int i; | |
2282 | ||
2283 | pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); | |
2284 | ||
2285 | /* capabilities pointer */ | |
2286 | pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); | |
2287 | //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); | |
2288 | ||
2289 | pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); // interrupt pin 3 | |
2290 | pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); | |
2291 | pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); | |
2292 | ||
2293 | // pci_conf[0x50] = 0x01; // power management caps | |
2294 | ||
2295 | pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4) | |
2296 | pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5) | |
2297 | pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6) | |
2298 | ||
2299 | pci_conf[0x64] = 0x00; | |
2300 | pci_conf[0x65] = 0x00; | |
2301 | pci_conf[0x66] = 0x00; | |
2302 | pci_conf[0x67] = 0x00; | |
2303 | pci_conf[0x68] = 0x01; | |
2304 | pci_conf[0x69] = 0x00; | |
2305 | pci_conf[0x6a] = 0x00; | |
2306 | pci_conf[0x6b] = 0x00; // USBLEGSUP | |
2307 | pci_conf[0x6c] = 0x00; | |
2308 | pci_conf[0x6d] = 0x00; | |
2309 | pci_conf[0x6e] = 0x00; | |
2310 | pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS | |
2311 | ||
2312 | // 2.2 host controller interface version | |
2313 | s->mmio[0x00] = (uint8_t) OPREGBASE; | |
2314 | s->mmio[0x01] = 0x00; | |
2315 | s->mmio[0x02] = 0x00; | |
2316 | s->mmio[0x03] = 0x01; // HC version | |
2317 | s->mmio[0x04] = NB_PORTS; // Number of downstream ports | |
2318 | s->mmio[0x05] = 0x00; // No companion ports at present | |
2319 | s->mmio[0x06] = 0x00; | |
2320 | s->mmio[0x07] = 0x00; | |
2321 | s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable | |
2322 | s->mmio[0x09] = 0x68; // EECP | |
2323 | s->mmio[0x0a] = 0x00; | |
2324 | s->mmio[0x0b] = 0x00; | |
2325 | ||
2326 | s->irq = s->dev.irq[3]; | |
2327 | ||
2328 | usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev); | |
2329 | for(i = 0; i < NB_PORTS; i++) { | |
2330 | usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, | |
2331 | USB_SPEED_MASK_HIGH); | |
2332 | s->ports[i].dev = 0; | |
2333 | } | |
2334 | ||
2335 | s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s); | |
2336 | QTAILQ_INIT(&s->queues); | |
2337 | ||
2338 | qemu_register_reset(ehci_reset, s); | |
2339 | ||
2340 | s->mem = cpu_register_io_memory(ehci_readfn, ehci_writefn, s, | |
2341 | DEVICE_LITTLE_ENDIAN); | |
2342 | ||
2343 | pci_register_bar(&s->dev, 0, MMIO_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY, | |
2344 | ehci_map); | |
2345 | ||
2346 | fprintf(stderr, "*** EHCI support is under development ***\n"); | |
2347 | ||
2348 | return 0; | |
2349 | } | |
2350 | ||
2351 | static void ehci_register(void) | |
2352 | { | |
2353 | pci_qdev_register_many(ehci_info); | |
2354 | } | |
2355 | device_init(ehci_register); | |
2356 | ||
2357 | /* | |
2358 | * vim: expandtab ts=4 | |
2359 | */ |