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1 | /** @file\r | |
2 | Copyright (c) 2006, Intel Corporation \r | |
3 | All rights reserved. This program and the accompanying materials \r | |
4 | are licensed and made available under the terms and conditions of the BSD License \r | |
5 | which accompanies this distribution. The full text of the license may be found at \r | |
6 | http://opensource.org/licenses/bsd-license.php \r | |
7 | \r | |
8 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
9 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
10 | \r | |
11 | **/\r | |
12 | \r | |
13 | #include "idebus.h"\r | |
14 | \r | |
15 | BOOLEAN SlaveDeviceExist = FALSE;\r | |
16 | BOOLEAN MasterDeviceExist = FALSE;\r | |
17 | \r | |
18 | /**\r | |
19 | TODO: Add function description\r | |
20 | \r | |
21 | @param PciIo TODO: add argument description\r | |
22 | @param Port TODO: add argument description\r | |
23 | \r | |
24 | TODO: add return values\r | |
25 | \r | |
26 | **/\r | |
27 | UINT8\r | |
28 | IDEReadPortB (\r | |
29 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
30 | IN UINT16 Port\r | |
31 | )\r | |
32 | {\r | |
33 | UINT8 Data;\r | |
34 | \r | |
35 | Data = 0;\r | |
36 | //\r | |
37 | // perform 1-byte data read from register\r | |
38 | //\r | |
39 | PciIo->Io.Read (\r | |
40 | PciIo,\r | |
41 | EfiPciIoWidthUint8,\r | |
42 | EFI_PCI_IO_PASS_THROUGH_BAR,\r | |
43 | (UINT64) Port,\r | |
44 | 1,\r | |
45 | &Data\r | |
46 | );\r | |
47 | return Data;\r | |
48 | }\r | |
49 | \r | |
50 | /**\r | |
51 | Reads multiple words of data from the IDE data port. \r | |
52 | Call the IO abstraction once to do the complete read,\r | |
53 | not one word at a time\r | |
54 | \r | |
55 | @param PciIo Pointer to the EFI_PCI_IO instance\r | |
56 | @param Port IO port to read\r | |
57 | @param Count No. of UINT16's to read\r | |
58 | @param Buffer Pointer to the data buffer for read\r | |
59 | \r | |
60 | **/\r | |
61 | VOID\r | |
62 | IDEReadPortWMultiple (\r | |
63 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
64 | IN UINT16 Port,\r | |
65 | IN UINTN Count,\r | |
66 | IN VOID *Buffer\r | |
67 | )\r | |
68 | {\r | |
69 | UINT16 *AlignedBuffer;\r | |
70 | UINT16 *WorkingBuffer;\r | |
71 | UINTN Size;\r | |
72 | \r | |
73 | //\r | |
74 | // Prepare an 16-bit alligned working buffer. CpuIo will return failure and\r | |
75 | // not perform actual I/O operations if buffer pointer passed in is not at\r | |
76 | // natural boundary. The "Buffer" argument is passed in by user and may not\r | |
77 | // at 16-bit natural boundary.\r | |
78 | //\r | |
79 | Size = sizeof (UINT16) * Count;\r | |
80 | \r | |
81 | gBS->AllocatePool (\r | |
82 | EfiBootServicesData,\r | |
83 | Size + 1,\r | |
84 | (VOID**)&WorkingBuffer\r | |
85 | );\r | |
86 | \r | |
87 | AlignedBuffer = (UINT16 *) ((UINTN)(((UINTN) WorkingBuffer + 0x1) & (~0x1)));\r | |
88 | \r | |
89 | //\r | |
90 | // Perform UINT16 data read from FIFO\r | |
91 | //\r | |
92 | PciIo->Io.Read (\r | |
93 | PciIo,\r | |
94 | EfiPciIoWidthFifoUint16,\r | |
95 | EFI_PCI_IO_PASS_THROUGH_BAR,\r | |
96 | (UINT64) Port,\r | |
97 | Count,\r | |
98 | (UINT16*)AlignedBuffer\r | |
99 | );\r | |
100 | \r | |
101 | //\r | |
102 | // Copy data to user buffer\r | |
103 | //\r | |
104 | CopyMem (Buffer, (UINT16*)AlignedBuffer, Size);\r | |
105 | gBS->FreePool (WorkingBuffer);\r | |
106 | }\r | |
107 | \r | |
108 | /**\r | |
109 | TODO: Add function description\r | |
110 | \r | |
111 | @param PciIo TODO: add argument description\r | |
112 | @param Port TODO: add argument description\r | |
113 | @param Data TODO: add argument description\r | |
114 | \r | |
115 | TODO: add return values\r | |
116 | \r | |
117 | **/\r | |
118 | VOID\r | |
119 | IDEWritePortB (\r | |
120 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
121 | IN UINT16 Port,\r | |
122 | IN UINT8 Data\r | |
123 | )\r | |
124 | {\r | |
125 | //\r | |
126 | // perform 1-byte data write to register\r | |
127 | //\r | |
128 | PciIo->Io.Write (\r | |
129 | PciIo,\r | |
130 | EfiPciIoWidthUint8,\r | |
131 | EFI_PCI_IO_PASS_THROUGH_BAR,\r | |
132 | (UINT64) Port,\r | |
133 | 1,\r | |
134 | &Data\r | |
135 | );\r | |
136 | \r | |
137 | }\r | |
138 | \r | |
139 | /**\r | |
140 | TODO: Add function description\r | |
141 | \r | |
142 | @param PciIo TODO: add argument description\r | |
143 | @param Port TODO: add argument description\r | |
144 | @param Data TODO: add argument description\r | |
145 | \r | |
146 | TODO: add return values\r | |
147 | \r | |
148 | **/\r | |
149 | VOID\r | |
150 | IDEWritePortW (\r | |
151 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
152 | IN UINT16 Port,\r | |
153 | IN UINT16 Data\r | |
154 | )\r | |
155 | {\r | |
156 | //\r | |
157 | // perform 1-word data write to register\r | |
158 | //\r | |
159 | PciIo->Io.Write (\r | |
160 | PciIo,\r | |
161 | EfiPciIoWidthUint16,\r | |
162 | EFI_PCI_IO_PASS_THROUGH_BAR,\r | |
163 | (UINT64) Port,\r | |
164 | 1,\r | |
165 | &Data\r | |
166 | );\r | |
167 | }\r | |
168 | \r | |
169 | /**\r | |
170 | Write multiple words of data to the IDE data port. \r | |
171 | Call the IO abstraction once to do the complete read,\r | |
172 | not one word at a time\r | |
173 | \r | |
174 | @param PciIo Pointer to the EFI_PCI_IO instance\r | |
175 | @param Port IO port to read\r | |
176 | @param Count No. of UINT16's to read\r | |
177 | @param Buffer Pointer to the data buffer for read\r | |
178 | \r | |
179 | **/\r | |
180 | VOID\r | |
181 | IDEWritePortWMultiple (\r | |
182 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
183 | IN UINT16 Port,\r | |
184 | IN UINTN Count,\r | |
185 | IN VOID *Buffer\r | |
186 | )\r | |
187 | {\r | |
188 | UINT16 *AlignedBuffer;\r | |
189 | UINT32 *WorkingBuffer;\r | |
190 | UINTN Size;\r | |
191 | \r | |
192 | //\r | |
193 | // Prepare an 16-bit alligned working buffer. CpuIo will return failure and\r | |
194 | // not perform actual I/O operations if buffer pointer passed in is not at\r | |
195 | // natural boundary. The "Buffer" argument is passed in by user and may not\r | |
196 | // at 16-bit natural boundary.\r | |
197 | //\r | |
198 | Size = sizeof (UINT16) * Count;\r | |
199 | \r | |
200 | gBS->AllocatePool (\r | |
201 | EfiBootServicesData,\r | |
202 | Size + 1,\r | |
203 | (VOID **) &WorkingBuffer\r | |
204 | );\r | |
205 | \r | |
206 | AlignedBuffer = (UINT16 *) ((UINTN)(((UINTN) WorkingBuffer + 0x1) & (~0x1)));\r | |
207 | \r | |
208 | //\r | |
209 | // Copy data from user buffer to working buffer\r | |
210 | //\r | |
211 | CopyMem ((UINT16 *) AlignedBuffer, Buffer, Size);\r | |
212 | \r | |
213 | //\r | |
214 | // perform UINT16 data write to the FIFO\r | |
215 | //\r | |
216 | PciIo->Io.Write (\r | |
217 | PciIo,\r | |
218 | EfiPciIoWidthFifoUint16,\r | |
219 | EFI_PCI_IO_PASS_THROUGH_BAR,\r | |
220 | (UINT64) Port,\r | |
221 | Count,\r | |
222 | (UINT16 *) AlignedBuffer\r | |
223 | );\r | |
224 | \r | |
225 | gBS->FreePool (WorkingBuffer);\r | |
226 | }\r | |
227 | \r | |
228 | /**\r | |
229 | TODO: Add function description\r | |
230 | \r | |
231 | @param IdeDev TODO: add argument description\r | |
232 | \r | |
233 | TODO: add return values\r | |
234 | \r | |
235 | **/\r | |
236 | BOOLEAN\r | |
237 | BadIdeDeviceCheck (\r | |
238 | IN IDE_BLK_IO_DEV *IdeDev\r | |
239 | )\r | |
240 | {\r | |
241 | //\r | |
242 | // check whether all registers return 0xff,\r | |
243 | // if so, deem the channel is disabled.\r | |
244 | //\r | |
245 | #ifdef EFI_DEBUG\r | |
246 | \r | |
247 | if (IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Data) != 0xff) {\r | |
248 | return FALSE;\r | |
249 | }\r | |
250 | \r | |
251 | if (IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Feature) != 0xff) {\r | |
252 | return FALSE;\r | |
253 | }\r | |
254 | \r | |
255 | if (IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->SectorCount) != 0xff) {\r | |
256 | return FALSE;\r | |
257 | }\r | |
258 | \r | |
259 | if (IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->SectorNumber) != 0xff) {\r | |
260 | return FALSE;\r | |
261 | }\r | |
262 | \r | |
263 | if (IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->CylinderLsb) != 0xff) {\r | |
264 | return FALSE;\r | |
265 | }\r | |
266 | \r | |
267 | if (IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->CylinderMsb) != 0xff) {\r | |
268 | return FALSE;\r | |
269 | }\r | |
270 | \r | |
271 | if (IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Head) != 0xff) {\r | |
272 | return FALSE;\r | |
273 | }\r | |
274 | \r | |
275 | if (IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Command) != 0xff) {\r | |
276 | return FALSE;\r | |
277 | }\r | |
278 | \r | |
279 | if (IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Alt.AltStatus) != 0xff) {\r | |
280 | return FALSE;\r | |
281 | }\r | |
282 | \r | |
283 | return TRUE;\r | |
284 | \r | |
285 | #else\r | |
286 | \r | |
287 | return FALSE;\r | |
288 | \r | |
289 | #endif\r | |
290 | }\r | |
291 | \r | |
292 | //\r | |
293 | // GetIdeRegistersBaseAddr\r | |
294 | //\r | |
295 | /**\r | |
296 | Get IDE IO port registers' base addresses by mode. In 'Compatibility' mode,\r | |
297 | use fixed addresses. In Native-PCI mode, get base addresses from BARs in\r | |
298 | the PCI IDE controller's Configuration Space.\r | |
299 | \r | |
300 | The steps to get IDE IO port registers' base addresses for each channel \r | |
301 | as follows:\r | |
302 | \r | |
303 | 1. Examine the Programming Interface byte of the Class Code fields in PCI IDE \r | |
304 | controller's Configuration Space to determine the operating mode.\r | |
305 | \r | |
306 | 2. a) In 'Compatibility' mode, use fixed addresses shown in the Table 1 below.\r | |
307 | <pre>\r | |
308 | ___________________________________________\r | |
309 | | | Command Block | Control Block |\r | |
310 | | Channel | Registers | Registers |\r | |
311 | |___________|_______________|_______________|\r | |
312 | | Primary | 1F0h - 1F7h | 3F6h - 3F7h |\r | |
313 | |___________|_______________|_______________|\r | |
314 | | Secondary | 170h - 177h | 376h - 377h |\r | |
315 | |___________|_______________|_______________|\r | |
316 | \r | |
317 | Table 1. Compatibility resource mappings\r | |
318 | </pre>\r | |
319 | \r | |
320 | b) In Native-PCI mode, IDE registers are mapped into IO space using the BARs\r | |
321 | in IDE controller's PCI Configuration Space, shown in the Table 2 below.\r | |
322 | <pre>\r | |
323 | ___________________________________________________\r | |
324 | | | Command Block | Control Block |\r | |
325 | | Channel | Registers | Registers |\r | |
326 | |___________|___________________|___________________|\r | |
327 | | Primary | BAR at offset 0x10| BAR at offset 0x14|\r | |
328 | |___________|___________________|___________________|\r | |
329 | | Secondary | BAR at offset 0x18| BAR at offset 0x1C|\r | |
330 | |___________|___________________|___________________|\r | |
331 | \r | |
332 | Table 2. BARs for Register Mapping\r | |
333 | </pre>\r | |
334 | @note Refer to Intel ICH4 datasheet, Control Block Offset: 03F4h for \r | |
335 | primary, 0374h for secondary. So 2 bytes extra offset should be \r | |
336 | added to the base addresses read from BARs.\r | |
337 | \r | |
338 | For more details, please refer to PCI IDE Controller Specification and Intel \r | |
339 | ICH4 Datasheet.\r | |
340 | \r | |
341 | @param PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance\r | |
342 | @param IdeRegsBaseAddr Pointer to IDE_REGISTERS_BASE_ADDR to\r | |
343 | receive IDE IO port registers' base addresses\r | |
344 | \r | |
345 | **/\r | |
346 | EFI_STATUS\r | |
347 | GetIdeRegistersBaseAddr (\r | |
348 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
349 | OUT IDE_REGISTERS_BASE_ADDR *IdeRegsBaseAddr\r | |
350 | )\r | |
351 | // TODO: EFI_UNSUPPORTED - add return value to function comment\r | |
352 | // TODO: EFI_UNSUPPORTED - add return value to function comment\r | |
353 | // TODO: EFI_SUCCESS - add return value to function comment\r | |
354 | {\r | |
355 | EFI_STATUS Status;\r | |
356 | PCI_TYPE00 PciData;\r | |
357 | \r | |
358 | Status = PciIo->Pci.Read (\r | |
359 | PciIo,\r | |
360 | EfiPciIoWidthUint8,\r | |
361 | 0,\r | |
362 | sizeof (PciData),\r | |
363 | &PciData\r | |
364 | );\r | |
365 | \r | |
366 | if (EFI_ERROR (Status)) {\r | |
367 | return Status;\r | |
368 | }\r | |
369 | \r | |
370 | if ((PciData.Hdr.ClassCode[0] & IDE_PRIMARY_OPERATING_MODE) == 0) {\r | |
371 | IdeRegsBaseAddr[IdePrimary].CommandBlockBaseAddr = 0x1f0;\r | |
372 | IdeRegsBaseAddr[IdePrimary].ControlBlockBaseAddr = 0x3f6;\r | |
373 | IdeRegsBaseAddr[IdePrimary].BusMasterBaseAddr = \r | |
374 | (UINT16)((PciData.Device.Bar[4] & 0x0000fff0));\r | |
375 | } else {\r | |
376 | //\r | |
377 | // The BARs should be of IO type\r | |
378 | //\r | |
379 | if ((PciData.Device.Bar[0] & bit0) == 0 || \r | |
380 | (PciData.Device.Bar[1] & bit0) == 0) {\r | |
381 | return EFI_UNSUPPORTED;\r | |
382 | }\r | |
383 | \r | |
384 | IdeRegsBaseAddr[IdePrimary].CommandBlockBaseAddr =\r | |
385 | (UINT16) (PciData.Device.Bar[0] & 0x0000fff8);\r | |
386 | IdeRegsBaseAddr[IdePrimary].ControlBlockBaseAddr =\r | |
387 | (UINT16) ((PciData.Device.Bar[1] & 0x0000fffc) + 2);\r | |
388 | IdeRegsBaseAddr[IdePrimary].BusMasterBaseAddr =\r | |
389 | (UINT16) ((PciData.Device.Bar[4] & 0x0000fff0));\r | |
390 | }\r | |
391 | \r | |
392 | if ((PciData.Hdr.ClassCode[0] & IDE_SECONDARY_OPERATING_MODE) == 0) {\r | |
393 | IdeRegsBaseAddr[IdeSecondary].CommandBlockBaseAddr = 0x170;\r | |
394 | IdeRegsBaseAddr[IdeSecondary].ControlBlockBaseAddr = 0x376;\r | |
395 | IdeRegsBaseAddr[IdeSecondary].BusMasterBaseAddr =\r | |
396 | (UINT16) ((PciData.Device.Bar[4] & 0x0000fff0));\r | |
397 | } else {\r | |
398 | //\r | |
399 | // The BARs should be of IO type\r | |
400 | //\r | |
401 | if ((PciData.Device.Bar[2] & bit0) == 0 ||\r | |
402 | (PciData.Device.Bar[3] & bit0) == 0) {\r | |
403 | return EFI_UNSUPPORTED;\r | |
404 | }\r | |
405 | \r | |
406 | IdeRegsBaseAddr[IdeSecondary].CommandBlockBaseAddr =\r | |
407 | (UINT16) (PciData.Device.Bar[2] & 0x0000fff8);\r | |
408 | IdeRegsBaseAddr[IdeSecondary].ControlBlockBaseAddr =\r | |
409 | (UINT16) ((PciData.Device.Bar[3] & 0x0000fffc) + 2);\r | |
410 | IdeRegsBaseAddr[IdeSecondary].BusMasterBaseAddr =\r | |
411 | (UINT16) ((PciData.Device.Bar[4] & 0x0000fff0));\r | |
412 | }\r | |
413 | \r | |
414 | return EFI_SUCCESS;\r | |
415 | }\r | |
416 | \r | |
417 | /**\r | |
418 | This function is used to requery IDE resources. The IDE controller will \r | |
419 | probably switch between native and legacy modes during the EFI->CSM->OS \r | |
420 | transfer. We do this everytime before an BlkIo operation to ensure its\r | |
421 | succeess.\r | |
422 | \r | |
423 | @param IdeDev The BLK_IO private data which specifies the IDE device\r | |
424 | \r | |
425 | **/\r | |
426 | EFI_STATUS\r | |
427 | ReassignIdeResources (\r | |
428 | IN IDE_BLK_IO_DEV *IdeDev\r | |
429 | )\r | |
430 | // TODO: EFI_SUCCESS - add return value to function comment\r | |
431 | {\r | |
432 | EFI_STATUS Status;\r | |
433 | IDE_REGISTERS_BASE_ADDR IdeRegsBaseAddr[IdeMaxChannel];\r | |
434 | UINT16 CommandBlockBaseAddr;\r | |
435 | UINT16 ControlBlockBaseAddr;\r | |
436 | \r | |
437 | //\r | |
438 | // Requery IDE IO port registers' base addresses in case of the switch of\r | |
439 | // native and legacy modes\r | |
440 | //\r | |
441 | Status = GetIdeRegistersBaseAddr (IdeDev->PciIo, IdeRegsBaseAddr);\r | |
442 | if (EFI_ERROR (Status)) {\r | |
443 | return Status;\r | |
444 | }\r | |
445 | \r | |
446 | ZeroMem (IdeDev->IoPort, sizeof (IDE_BASE_REGISTERS));\r | |
447 | CommandBlockBaseAddr = IdeRegsBaseAddr[IdeDev->Channel].CommandBlockBaseAddr;\r | |
448 | ControlBlockBaseAddr = IdeRegsBaseAddr[IdeDev->Channel].ControlBlockBaseAddr;\r | |
449 | \r | |
450 | IdeDev->IoPort->Data = CommandBlockBaseAddr;\r | |
451 | (*(UINT16 *) &IdeDev->IoPort->Reg1) = (UINT16) (CommandBlockBaseAddr + 0x01);\r | |
452 | IdeDev->IoPort->SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);\r | |
453 | IdeDev->IoPort->SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x03);\r | |
454 | IdeDev->IoPort->CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x04);\r | |
455 | IdeDev->IoPort->CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);\r | |
456 | IdeDev->IoPort->Head = (UINT16) (CommandBlockBaseAddr + 0x06);\r | |
457 | \r | |
458 | (*(UINT16 *) &IdeDev->IoPort->Reg) = (UINT16) (CommandBlockBaseAddr + 0x07);\r | |
459 | (*(UINT16 *) &IdeDev->IoPort->Alt) = ControlBlockBaseAddr;\r | |
460 | IdeDev->IoPort->DriveAddress = (UINT16) (ControlBlockBaseAddr + 0x01);\r | |
461 | IdeDev->IoPort->MasterSlave = (UINT16) ((IdeDev->Device == IdeMaster) ? 1 : 0);\r | |
462 | \r | |
463 | IdeDev->IoPort->BusMasterBaseAddr = IdeRegsBaseAddr[IdeDev->Channel].BusMasterBaseAddr;\r | |
464 | return EFI_SUCCESS;\r | |
465 | }\r | |
466 | \r | |
467 | /**\r | |
468 | Read SATA registers to detect SATA disks\r | |
469 | \r | |
470 | @param IdeDev The BLK_IO private data which specifies the IDE device\r | |
471 | \r | |
472 | **/\r | |
473 | EFI_STATUS\r | |
474 | CheckPowerMode (\r | |
475 | IDE_BLK_IO_DEV *IdeDev\r | |
476 | )\r | |
477 | // TODO: EFI_NOT_FOUND - add return value to function comment\r | |
478 | // TODO: EFI_SUCCESS - add return value to function comment\r | |
479 | // TODO: EFI_NOT_FOUND - add return value to function comment\r | |
480 | {\r | |
481 | UINT8 ErrorRegister;\r | |
482 | EFI_STATUS Status;\r | |
483 | \r | |
484 | IDEWritePortB (\r | |
485 | IdeDev->PciIo,\r | |
486 | IdeDev->IoPort->Head,\r | |
487 | (UINT8) ((IdeDev->Device << 4) | 0xe0)\r | |
488 | );\r | |
489 | \r | |
490 | //\r | |
491 | // Wait 31 seconds for BSY clear. BSY should be in clear state if there exists\r | |
492 | // a device (initial state). Normally, BSY is also in clear state if there is\r | |
493 | // no device\r | |
494 | //\r | |
495 | Status = WaitForBSYClear (IdeDev, 31000);\r | |
496 | if (EFI_ERROR (Status)) {\r | |
497 | return EFI_NOT_FOUND;\r | |
498 | }\r | |
499 | \r | |
500 | //\r | |
501 | // select device, read error register\r | |
502 | //\r | |
503 | IDEWritePortB (\r | |
504 | IdeDev->PciIo,\r | |
505 | IdeDev->IoPort->Head,\r | |
506 | (UINT8) ((IdeDev->Device << 4) | 0xe0)\r | |
507 | );\r | |
508 | Status = DRDYReady (IdeDev, 200);\r | |
509 | \r | |
510 | ErrorRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);\r | |
511 | if ((ErrorRegister == 0x01) || (ErrorRegister == 0x81)) {\r | |
512 | return EFI_SUCCESS;\r | |
513 | } else {\r | |
514 | return EFI_NOT_FOUND;\r | |
515 | }\r | |
516 | }\r | |
517 | \r | |
518 | //\r | |
519 | // DiscoverIdeDevice\r | |
520 | //\r | |
521 | /**\r | |
522 | Detect if there is disk connected to this port\r | |
523 | \r | |
524 | @param IdeDev The BLK_IO private data which specifies the IDE device\r | |
525 | \r | |
526 | **/\r | |
527 | EFI_STATUS\r | |
528 | DiscoverIdeDevice (\r | |
529 | IN IDE_BLK_IO_DEV *IdeDev\r | |
530 | )\r | |
531 | // TODO: EFI_NOT_FOUND - add return value to function comment\r | |
532 | // TODO: EFI_NOT_FOUND - add return value to function comment\r | |
533 | // TODO: EFI_SUCCESS - add return value to function comment\r | |
534 | {\r | |
535 | EFI_STATUS Status;\r | |
536 | BOOLEAN SataFlag;\r | |
537 | \r | |
538 | SataFlag = FALSE;\r | |
539 | //\r | |
540 | // This extra detection is for SATA disks\r | |
541 | //\r | |
542 | Status = CheckPowerMode (IdeDev);\r | |
543 | if (Status == EFI_SUCCESS) {\r | |
544 | SataFlag = TRUE;\r | |
545 | }\r | |
546 | \r | |
547 | //\r | |
548 | // If a channel has not been checked, check it now. Then set it to "checked" state\r | |
549 | // After this step, all devices in this channel have been checked.\r | |
550 | //\r | |
551 | Status = DetectIDEController (IdeDev);\r | |
552 | \r | |
553 | if ((EFI_ERROR (Status)) && !SataFlag) {\r | |
554 | return EFI_NOT_FOUND;\r | |
555 | }\r | |
556 | \r | |
557 | //\r | |
558 | // Device exists. test if it is an ATA device\r | |
559 | //\r | |
560 | Status = ATAIdentify (IdeDev);\r | |
561 | if (EFI_ERROR (Status)) {\r | |
562 | //\r | |
563 | // if not ATA device, test if it is an ATAPI device\r | |
564 | //\r | |
565 | Status = ATAPIIdentify (IdeDev);\r | |
566 | if (EFI_ERROR (Status)) {\r | |
567 | //\r | |
568 | // if not ATAPI device either, return error.\r | |
569 | //\r | |
570 | return EFI_NOT_FOUND;\r | |
571 | }\r | |
572 | }\r | |
573 | \r | |
574 | //\r | |
575 | // Init Block I/O interface\r | |
576 | //\r | |
577 | IdeDev->BlkIo.Revision = EFI_BLOCK_IO_PROTOCOL_REVISION;\r | |
578 | IdeDev->BlkIo.Reset = IDEBlkIoReset;\r | |
579 | IdeDev->BlkIo.ReadBlocks = IDEBlkIoReadBlocks;\r | |
580 | IdeDev->BlkIo.WriteBlocks = IDEBlkIoWriteBlocks;\r | |
581 | IdeDev->BlkIo.FlushBlocks = IDEBlkIoFlushBlocks;\r | |
582 | \r | |
583 | IdeDev->BlkMedia.LogicalPartition = FALSE;\r | |
584 | IdeDev->BlkMedia.WriteCaching = FALSE;\r | |
585 | \r | |
586 | //\r | |
587 | // Init Disk Info interface\r | |
588 | //\r | |
589 | gBS->CopyMem (&IdeDev->DiskInfo.Interface, &gEfiDiskInfoIdeInterfaceGuid, sizeof (EFI_GUID));\r | |
590 | IdeDev->DiskInfo.Inquiry = IDEDiskInfoInquiry;\r | |
591 | IdeDev->DiskInfo.Identify = IDEDiskInfoIdentify;\r | |
592 | IdeDev->DiskInfo.SenseData = IDEDiskInfoSenseData;\r | |
593 | IdeDev->DiskInfo.WhichIde = IDEDiskInfoWhichIde;\r | |
594 | \r | |
595 | return EFI_SUCCESS;\r | |
596 | }\r | |
597 | \r | |
598 | /**\r | |
599 | This function is called by DiscoverIdeDevice(). It is used for detect \r | |
600 | whether the IDE device exists in the specified Channel as the specified \r | |
601 | Device Number.\r | |
602 | \r | |
603 | There is two IDE channels: one is Primary Channel, the other is \r | |
604 | Secondary Channel.(Channel is the logical name for the physical "Cable".) \r | |
605 | Different channel has different register group.\r | |
606 | \r | |
607 | On each IDE channel, at most two IDE devices attach, \r | |
608 | one is called Device 0 (Master device), the other is called Device 1 \r | |
609 | (Slave device). The devices on the same channel co-use the same register \r | |
610 | group, so before sending out a command for a specified device via command \r | |
611 | register, it is a must to select the current device to accept the command \r | |
612 | by set the device number in the Head/Device Register.\r | |
613 | \r | |
614 | @param[in] *IdeDev\r | |
615 | pointer pointing to IDE_BLK_IO_DEV data structure, used\r | |
616 | to record all the information of the IDE device.\r | |
617 | \r | |
618 | @retval TRUE\r | |
619 | successfully detects device.\r | |
620 | \r | |
621 | @retval FALSE\r | |
622 | any failure during detection process will return this\r | |
623 | value.\r | |
624 | \r | |
625 | @note\r | |
626 | TODO: EFI_SUCCESS - add return value to function comment\r | |
627 | TODO: EFI_NOT_FOUND - add return value to function comment\r | |
628 | \r | |
629 | **/\r | |
630 | EFI_STATUS\r | |
631 | DetectIDEController (\r | |
632 | IN IDE_BLK_IO_DEV *IdeDev\r | |
633 | )\r | |
634 | {\r | |
635 | EFI_STATUS Status;\r | |
636 | UINT8 ErrorReg;\r | |
637 | UINT8 StatusReg;\r | |
638 | UINT8 InitStatusReg;\r | |
639 | EFI_STATUS DeviceStatus;\r | |
640 | \r | |
641 | //\r | |
642 | // Slave device has been detected with master device.\r | |
643 | //\r | |
644 | if ((IdeDev->Device) == 1) {\r | |
645 | if (SlaveDeviceExist) {\r | |
646 | //\r | |
647 | // If master not exists but slave exists, slave have to wait a while\r | |
648 | //\r | |
649 | if (!MasterDeviceExist) {\r | |
650 | //\r | |
651 | // if single slave can't be detected, add delay 4s here.\r | |
652 | //\r | |
653 | gBS->Stall (4000000);\r | |
654 | }\r | |
655 | \r | |
656 | return EFI_SUCCESS;\r | |
657 | } else {\r | |
658 | return EFI_NOT_FOUND;\r | |
659 | }\r | |
660 | }\r | |
661 | \r | |
662 | //\r | |
663 | // Select slave device\r | |
664 | //\r | |
665 | IDEWritePortB (\r | |
666 | IdeDev->PciIo,\r | |
667 | IdeDev->IoPort->Head,\r | |
668 | (UINT8) ((1 << 4) | 0xe0)\r | |
669 | );\r | |
670 | gBS->Stall (100);\r | |
671 | \r | |
672 | //\r | |
673 | // Save the init slave status register\r | |
674 | //\r | |
675 | InitStatusReg = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Status);\r | |
676 | \r | |
677 | //\r | |
678 | // Select master back\r | |
679 | //\r | |
680 | IDEWritePortB (\r | |
681 | IdeDev->PciIo,\r | |
682 | IdeDev->IoPort->Head,\r | |
683 | (UINT8) ((0 << 4) | 0xe0)\r | |
684 | );\r | |
685 | gBS->Stall (100);\r | |
686 | //\r | |
687 | // Send ATA Device Execut Diagnostic command.\r | |
688 | // This command should work no matter DRDY is ready or not\r | |
689 | //\r | |
690 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Command, 0x90);\r | |
691 | \r | |
692 | Status = WaitForBSYClear (IdeDev, 3500);\r | |
693 | \r | |
694 | ErrorReg = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);\r | |
695 | \r | |
696 | //\r | |
697 | // Master Error register is 0x01. D0 passed, D1 passed or not present.\r | |
698 | // Master Error register is 0x81. D0 passed, D1 failed. Return.\r | |
699 | // Master Error register is other value. D0 failed, D1 passed or not present..\r | |
700 | //\r | |
701 | if (ErrorReg == 0x01) {\r | |
702 | MasterDeviceExist = TRUE;\r | |
703 | DeviceStatus = EFI_SUCCESS;\r | |
704 | } else if (ErrorReg == 0x81) {\r | |
705 | \r | |
706 | MasterDeviceExist = TRUE;\r | |
707 | DeviceStatus = EFI_SUCCESS;\r | |
708 | SlaveDeviceExist = FALSE;\r | |
709 | \r | |
710 | return DeviceStatus;\r | |
711 | } else {\r | |
712 | MasterDeviceExist = FALSE;\r | |
713 | DeviceStatus = EFI_NOT_FOUND;\r | |
714 | }\r | |
715 | \r | |
716 | //\r | |
717 | // Master Error register is not 0x81, Go on check Slave\r | |
718 | //\r | |
719 | \r | |
720 | //\r | |
721 | // select slave\r | |
722 | //\r | |
723 | IDEWritePortB (\r | |
724 | IdeDev->PciIo,\r | |
725 | IdeDev->IoPort->Head,\r | |
726 | (UINT8) ((1 << 4) | 0xe0)\r | |
727 | );\r | |
728 | \r | |
729 | gBS->Stall (300);\r | |
730 | ErrorReg = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);\r | |
731 | \r | |
732 | //\r | |
733 | // Slave Error register is not 0x01, D1 failed. Return.\r | |
734 | //\r | |
735 | if (ErrorReg != 0x01) {\r | |
736 | SlaveDeviceExist = FALSE;\r | |
737 | return DeviceStatus;\r | |
738 | }\r | |
739 | \r | |
740 | StatusReg = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Status);\r | |
741 | \r | |
742 | //\r | |
743 | // Most ATAPI devices don't set DRDY bit, so test with a slow but accurate\r | |
744 | // "ATAPI TEST UNIT READY" command\r | |
745 | //\r | |
746 | if (((StatusReg & DRDY) == 0) && ((InitStatusReg & DRDY) == 0)) {\r | |
747 | Status = AtapiTestUnitReady (IdeDev);\r | |
748 | \r | |
749 | //\r | |
750 | // Still fail, Slave doesn't exist.\r | |
751 | //\r | |
752 | if (EFI_ERROR (Status)) {\r | |
753 | SlaveDeviceExist = FALSE;\r | |
754 | return DeviceStatus;\r | |
755 | }\r | |
756 | }\r | |
757 | \r | |
758 | //\r | |
759 | // Error reg is 0x01 and DRDY is ready,\r | |
760 | // or ATAPI test unit ready success,\r | |
761 | // or init Slave status DRDY is ready\r | |
762 | // Slave exists.\r | |
763 | //\r | |
764 | SlaveDeviceExist = TRUE;\r | |
765 | \r | |
766 | return DeviceStatus;\r | |
767 | \r | |
768 | }\r | |
769 | \r | |
770 | /**\r | |
771 | This function is used to poll for the DRQ bit clear in the Status \r | |
772 | Register. DRQ is cleared when the device is finished transferring data. \r | |
773 | So this function is called after data transfer is finished.\r | |
774 | \r | |
775 | @param[in] *IdeDev\r | |
776 | pointer pointing to IDE_BLK_IO_DEV data structure, used\r | |
777 | to record all the information of the IDE device.\r | |
778 | \r | |
779 | @param[in] TimeoutInMilliSeconds\r | |
780 | used to designate the timeout for the DRQ clear.\r | |
781 | \r | |
782 | @retval EFI_SUCCESS\r | |
783 | DRQ bit clear within the time out.\r | |
784 | \r | |
785 | @retval EFI_TIMEOUT\r | |
786 | DRQ bit not clear within the time out.\r | |
787 | \r | |
788 | @note\r | |
789 | Read Status Register will clear interrupt status.\r | |
790 | \r | |
791 | **/\r | |
792 | EFI_STATUS\r | |
793 | DRQClear (\r | |
794 | IN IDE_BLK_IO_DEV *IdeDev,\r | |
795 | IN UINTN TimeoutInMilliSeconds\r | |
796 | )\r | |
797 | // TODO: function comment is missing 'Routine Description:'\r | |
798 | // TODO: function comment is missing 'Arguments:'\r | |
799 | // TODO: IdeDev - add argument and description to function comment\r | |
800 | // TODO: TimeoutInMilliSeconds - add argument and description to function comment\r | |
801 | // TODO: EFI_ABORTED - add return value to function comment\r | |
802 | {\r | |
803 | UINT32 Delay;\r | |
804 | UINT8 StatusRegister;\r | |
805 | UINT8 ErrorRegister;\r | |
806 | \r | |
807 | Delay = (UINT32) (((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 30) + 1);\r | |
808 | do {\r | |
809 | \r | |
810 | StatusRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Status);\r | |
811 | \r | |
812 | //\r | |
813 | // wait for BSY == 0 and DRQ == 0\r | |
814 | //\r | |
815 | if ((StatusRegister & (DRQ | BSY)) == 0) {\r | |
816 | break;\r | |
817 | }\r | |
818 | \r | |
819 | if ((StatusRegister & (BSY | ERR)) == ERR) {\r | |
820 | \r | |
821 | ErrorRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);\r | |
822 | if ((ErrorRegister & ABRT_ERR) == ABRT_ERR) {\r | |
823 | return EFI_ABORTED;\r | |
824 | }\r | |
825 | }\r | |
826 | \r | |
827 | //\r | |
828 | // Stall for 30 us\r | |
829 | //\r | |
830 | gBS->Stall (30);\r | |
831 | \r | |
832 | Delay--;\r | |
833 | \r | |
834 | } while (Delay);\r | |
835 | \r | |
836 | if (Delay == 0) {\r | |
837 | return EFI_TIMEOUT;\r | |
838 | }\r | |
839 | \r | |
840 | return EFI_SUCCESS;\r | |
841 | }\r | |
842 | \r | |
843 | /**\r | |
844 | This function is used to poll for the DRQ bit clear in the Alternate \r | |
845 | Status Register. DRQ is cleared when the device is finished \r | |
846 | transferring data. So this function is called after data transfer\r | |
847 | is finished.\r | |
848 | \r | |
849 | @param[in] *IdeDev\r | |
850 | pointer pointing to IDE_BLK_IO_DEV data structure, used\r | |
851 | to record all the information of the IDE device.\r | |
852 | \r | |
853 | @param[in] TimeoutInMilliSeconds\r | |
854 | used to designate the timeout for the DRQ clear.\r | |
855 | \r | |
856 | @retval EFI_SUCCESS\r | |
857 | DRQ bit clear within the time out.\r | |
858 | \r | |
859 | @retval EFI_TIMEOUT\r | |
860 | DRQ bit not clear within the time out.\r | |
861 | \r | |
862 | @note\r | |
863 | Read Alternate Status Register will not clear interrupt status.\r | |
864 | \r | |
865 | **/\r | |
866 | EFI_STATUS\r | |
867 | DRQClear2 (\r | |
868 | IN IDE_BLK_IO_DEV *IdeDev,\r | |
869 | IN UINTN TimeoutInMilliSeconds\r | |
870 | )\r | |
871 | // TODO: function comment is missing 'Routine Description:'\r | |
872 | // TODO: function comment is missing 'Arguments:'\r | |
873 | // TODO: IdeDev - add argument and description to function comment\r | |
874 | // TODO: TimeoutInMilliSeconds - add argument and description to function comment\r | |
875 | // TODO: EFI_ABORTED - add return value to function comment\r | |
876 | {\r | |
877 | UINT32 Delay;\r | |
878 | UINT8 AltRegister;\r | |
879 | UINT8 ErrorRegister;\r | |
880 | \r | |
881 | Delay = (UINT32) (((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 30) + 1);\r | |
882 | do {\r | |
883 | \r | |
884 | AltRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Alt.AltStatus);\r | |
885 | \r | |
886 | //\r | |
887 | // wait for BSY == 0 and DRQ == 0\r | |
888 | //\r | |
889 | if ((AltRegister & (DRQ | BSY)) == 0) {\r | |
890 | break;\r | |
891 | }\r | |
892 | \r | |
893 | if ((AltRegister & (BSY | ERR)) == ERR) {\r | |
894 | \r | |
895 | ErrorRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);\r | |
896 | if ((ErrorRegister & ABRT_ERR) == ABRT_ERR) {\r | |
897 | return EFI_ABORTED;\r | |
898 | }\r | |
899 | }\r | |
900 | \r | |
901 | //\r | |
902 | // Stall for 30 us\r | |
903 | //\r | |
904 | gBS->Stall (30);\r | |
905 | \r | |
906 | Delay--;\r | |
907 | \r | |
908 | } while (Delay);\r | |
909 | \r | |
910 | if (Delay == 0) {\r | |
911 | return EFI_TIMEOUT;\r | |
912 | }\r | |
913 | \r | |
914 | return EFI_SUCCESS;\r | |
915 | }\r | |
916 | \r | |
917 | /**\r | |
918 | This function is used to poll for the DRQ bit set in the \r | |
919 | Status Register.\r | |
920 | DRQ is set when the device is ready to transfer data. So this function\r | |
921 | is called after the command is sent to the device and before required \r | |
922 | data is transferred.\r | |
923 | \r | |
924 | @param[in] IDE_BLK_IO_DEV IN *IdeDev\r | |
925 | pointer pointing to IDE_BLK_IO_DEV data structure,used\r | |
926 | to record all the information of the IDE device.\r | |
927 | \r | |
928 | @param[in] UINTN IN TimeoutInMilliSeconds\r | |
929 | used to designate the timeout for the DRQ ready.\r | |
930 | \r | |
931 | @retval EFI_SUCCESS\r | |
932 | DRQ bit set within the time out.\r | |
933 | \r | |
934 | @retval EFI_TIMEOUT\r | |
935 | DRQ bit not set within the time out.\r | |
936 | \r | |
937 | @retval EFI_ABORTED\r | |
938 | DRQ bit not set caused by the command abort.\r | |
939 | \r | |
940 | @note\r | |
941 | Read Status Register will clear interrupt status.\r | |
942 | \r | |
943 | **/\r | |
944 | EFI_STATUS\r | |
945 | DRQReady (\r | |
946 | IN IDE_BLK_IO_DEV *IdeDev,\r | |
947 | IN UINTN TimeoutInMilliSeconds\r | |
948 | )\r | |
949 | // TODO: function comment is missing 'Routine Description:'\r | |
950 | // TODO: function comment is missing 'Arguments:'\r | |
951 | // TODO: IdeDev - add argument and description to function comment\r | |
952 | // TODO: TimeoutInMilliSeconds - add argument and description to function comment\r | |
953 | {\r | |
954 | UINT32 Delay;\r | |
955 | UINT8 StatusRegister;\r | |
956 | UINT8 ErrorRegister;\r | |
957 | \r | |
958 | Delay = (UINT32) (((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 30) + 1);\r | |
959 | do {\r | |
960 | //\r | |
961 | // read Status Register will clear interrupt\r | |
962 | //\r | |
963 | StatusRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Status);\r | |
964 | \r | |
965 | //\r | |
966 | // BSY==0,DRQ==1\r | |
967 | //\r | |
968 | if ((StatusRegister & (BSY | DRQ)) == DRQ) {\r | |
969 | break;\r | |
970 | }\r | |
971 | \r | |
972 | if ((StatusRegister & (BSY | ERR)) == ERR) {\r | |
973 | \r | |
974 | ErrorRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);\r | |
975 | if ((ErrorRegister & ABRT_ERR) == ABRT_ERR) {\r | |
976 | return EFI_ABORTED;\r | |
977 | }\r | |
978 | }\r | |
979 | \r | |
980 | //\r | |
981 | // Stall for 30 us\r | |
982 | //\r | |
983 | gBS->Stall (30);\r | |
984 | \r | |
985 | Delay--;\r | |
986 | } while (Delay);\r | |
987 | \r | |
988 | if (Delay == 0) {\r | |
989 | return EFI_TIMEOUT;\r | |
990 | }\r | |
991 | \r | |
992 | return EFI_SUCCESS;\r | |
993 | }\r | |
994 | \r | |
995 | /**\r | |
996 | This function is used to poll for the DRQ bit set in the \r | |
997 | Alternate Status Register. DRQ is set when the device is ready to \r | |
998 | transfer data. So this function is called after the command \r | |
999 | is sent to the device and before required data is transferred.\r | |
1000 | \r | |
1001 | @param[in] IDE_BLK_IO_DEV IN *IdeDev\r | |
1002 | pointer pointing to IDE_BLK_IO_DEV data structure, used\r | |
1003 | to record all the information of the IDE device.\r | |
1004 | \r | |
1005 | @param[in] UINTN IN TimeoutInMilliSeconds\r | |
1006 | used to designate the timeout for the DRQ ready.\r | |
1007 | \r | |
1008 | @retval EFI_SUCCESS\r | |
1009 | DRQ bit set within the time out.\r | |
1010 | \r | |
1011 | @retval EFI_TIMEOUT\r | |
1012 | DRQ bit not set within the time out.\r | |
1013 | \r | |
1014 | @retval EFI_ABORTED\r | |
1015 | DRQ bit not set caused by the command abort.\r | |
1016 | \r | |
1017 | @note\r | |
1018 | Read Alternate Status Register will not clear interrupt status.\r | |
1019 | \r | |
1020 | **/\r | |
1021 | EFI_STATUS\r | |
1022 | DRQReady2 (\r | |
1023 | IN IDE_BLK_IO_DEV *IdeDev,\r | |
1024 | IN UINTN TimeoutInMilliSeconds\r | |
1025 | )\r | |
1026 | // TODO: function comment is missing 'Routine Description:'\r | |
1027 | // TODO: function comment is missing 'Arguments:'\r | |
1028 | // TODO: IdeDev - add argument and description to function comment\r | |
1029 | // TODO: TimeoutInMilliSeconds - add argument and description to function comment\r | |
1030 | {\r | |
1031 | UINT32 Delay;\r | |
1032 | UINT8 AltRegister;\r | |
1033 | UINT8 ErrorRegister;\r | |
1034 | \r | |
1035 | Delay = (UINT32) (((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 30) + 1);\r | |
1036 | \r | |
1037 | do {\r | |
1038 | //\r | |
1039 | // Read Alternate Status Register will not clear interrupt status\r | |
1040 | //\r | |
1041 | AltRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Alt.AltStatus);\r | |
1042 | //\r | |
1043 | // BSY == 0 , DRQ == 1\r | |
1044 | //\r | |
1045 | if ((AltRegister & (BSY | DRQ)) == DRQ) {\r | |
1046 | break;\r | |
1047 | }\r | |
1048 | \r | |
1049 | if ((AltRegister & (BSY | ERR)) == ERR) {\r | |
1050 | \r | |
1051 | ErrorRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);\r | |
1052 | if ((ErrorRegister & ABRT_ERR) == ABRT_ERR) {\r | |
1053 | return EFI_ABORTED;\r | |
1054 | }\r | |
1055 | }\r | |
1056 | \r | |
1057 | //\r | |
1058 | // Stall for 30 us\r | |
1059 | //\r | |
1060 | gBS->Stall (30);\r | |
1061 | \r | |
1062 | Delay--;\r | |
1063 | } while (Delay);\r | |
1064 | \r | |
1065 | if (Delay == 0) {\r | |
1066 | return EFI_TIMEOUT;\r | |
1067 | }\r | |
1068 | \r | |
1069 | return EFI_SUCCESS;\r | |
1070 | }\r | |
1071 | \r | |
1072 | /**\r | |
1073 | This function is used to poll for the BSY bit clear in the \r | |
1074 | Status Register. BSY is clear when the device is not busy.\r | |
1075 | Every command must be sent after device is not busy.\r | |
1076 | \r | |
1077 | @param[in] IDE_BLK_IO_DEV IN *IdeDev\r | |
1078 | pointer pointing to IDE_BLK_IO_DEV data structure, used\r | |
1079 | to record all the information of the IDE device.\r | |
1080 | \r | |
1081 | @param[in] UINTN IN TimeoutInMilliSeconds\r | |
1082 | used to designate the timeout for the DRQ ready.\r | |
1083 | \r | |
1084 | @retval EFI_SUCCESS\r | |
1085 | BSY bit clear within the time out.\r | |
1086 | \r | |
1087 | @retval EFI_TIMEOUT\r | |
1088 | BSY bit not clear within the time out.\r | |
1089 | \r | |
1090 | @note\r | |
1091 | Read Status Register will clear interrupt status.\r | |
1092 | \r | |
1093 | **/\r | |
1094 | EFI_STATUS\r | |
1095 | WaitForBSYClear (\r | |
1096 | IN IDE_BLK_IO_DEV *IdeDev,\r | |
1097 | IN UINTN TimeoutInMilliSeconds\r | |
1098 | )\r | |
1099 | // TODO: function comment is missing 'Routine Description:'\r | |
1100 | // TODO: function comment is missing 'Arguments:'\r | |
1101 | // TODO: IdeDev - add argument and description to function comment\r | |
1102 | // TODO: TimeoutInMilliSeconds - add argument and description to function comment\r | |
1103 | {\r | |
1104 | UINT32 Delay;\r | |
1105 | UINT8 StatusRegister;\r | |
1106 | \r | |
1107 | Delay = (UINT32) (((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 30) + 1);\r | |
1108 | do {\r | |
1109 | \r | |
1110 | StatusRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Status);\r | |
1111 | if ((StatusRegister & BSY) == 0x00) {\r | |
1112 | break;\r | |
1113 | }\r | |
1114 | \r | |
1115 | //\r | |
1116 | // Stall for 30 us\r | |
1117 | //\r | |
1118 | gBS->Stall (30);\r | |
1119 | \r | |
1120 | Delay--;\r | |
1121 | \r | |
1122 | } while (Delay);\r | |
1123 | \r | |
1124 | if (Delay == 0) {\r | |
1125 | return EFI_TIMEOUT;\r | |
1126 | }\r | |
1127 | \r | |
1128 | return EFI_SUCCESS;\r | |
1129 | }\r | |
1130 | //\r | |
1131 | // WaitForBSYClear2\r | |
1132 | //\r | |
1133 | /**\r | |
1134 | This function is used to poll for the BSY bit clear in the \r | |
1135 | Alternate Status Register. BSY is clear when the device is not busy.\r | |
1136 | Every command must be sent after device is not busy.\r | |
1137 | \r | |
1138 | @param[in] IDE_BLK_IO_DEV IN *IdeDev\r | |
1139 | pointer pointing to IDE_BLK_IO_DEV data structure, used\r | |
1140 | to record all the information of the IDE device.\r | |
1141 | \r | |
1142 | @param[in] UINTN IN TimeoutInMilliSeconds\r | |
1143 | used to designate the timeout for the DRQ ready.\r | |
1144 | \r | |
1145 | @retval EFI_SUCCESS\r | |
1146 | BSY bit clear within the time out.\r | |
1147 | \r | |
1148 | @retval EFI_TIMEOUT\r | |
1149 | BSY bit not clear within the time out.\r | |
1150 | \r | |
1151 | @note\r | |
1152 | Read Alternate Status Register will not clear interrupt status.\r | |
1153 | \r | |
1154 | **/\r | |
1155 | EFI_STATUS\r | |
1156 | WaitForBSYClear2 (\r | |
1157 | IN IDE_BLK_IO_DEV *IdeDev,\r | |
1158 | IN UINTN TimeoutInMilliSeconds\r | |
1159 | )\r | |
1160 | // TODO: function comment is missing 'Routine Description:'\r | |
1161 | // TODO: function comment is missing 'Arguments:'\r | |
1162 | // TODO: IdeDev - add argument and description to function comment\r | |
1163 | // TODO: TimeoutInMilliSeconds - add argument and description to function comment\r | |
1164 | {\r | |
1165 | UINT32 Delay;\r | |
1166 | UINT8 AltRegister;\r | |
1167 | \r | |
1168 | Delay = (UINT32) (((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 30) + 1);\r | |
1169 | do {\r | |
1170 | AltRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Alt.AltStatus);\r | |
1171 | if ((AltRegister & BSY) == 0x00) {\r | |
1172 | break;\r | |
1173 | }\r | |
1174 | \r | |
1175 | gBS->Stall (30);\r | |
1176 | \r | |
1177 | Delay--;\r | |
1178 | \r | |
1179 | } while (Delay);\r | |
1180 | \r | |
1181 | if (Delay == 0) {\r | |
1182 | return EFI_TIMEOUT;\r | |
1183 | }\r | |
1184 | \r | |
1185 | return EFI_SUCCESS;\r | |
1186 | }\r | |
1187 | \r | |
1188 | //\r | |
1189 | // DRDYReady\r | |
1190 | //\r | |
1191 | /**\r | |
1192 | This function is used to poll for the DRDY bit set in the \r | |
1193 | Status Register. DRDY bit is set when the device is ready \r | |
1194 | to accept command. Most ATA commands must be sent after \r | |
1195 | DRDY set except the ATAPI Packet Command.\r | |
1196 | \r | |
1197 | @param[in] IDE_BLK_IO_DEV IN *IdeDev\r | |
1198 | pointer pointing to IDE_BLK_IO_DEV data structure, used\r | |
1199 | to record all the information of the IDE device.\r | |
1200 | \r | |
1201 | @param[in] UINTN IN TimeoutInMilliSeconds\r | |
1202 | used to designate the timeout for the DRQ ready.\r | |
1203 | \r | |
1204 | @retval EFI_SUCCESS\r | |
1205 | DRDY bit set within the time out.\r | |
1206 | \r | |
1207 | @retval EFI_TIMEOUT\r | |
1208 | DRDY bit not set within the time out.\r | |
1209 | \r | |
1210 | @note\r | |
1211 | Read Status Register will clear interrupt status.\r | |
1212 | \r | |
1213 | **/\r | |
1214 | EFI_STATUS\r | |
1215 | DRDYReady (\r | |
1216 | IN IDE_BLK_IO_DEV *IdeDev,\r | |
1217 | IN UINTN DelayInMilliSeconds\r | |
1218 | )\r | |
1219 | // TODO: function comment is missing 'Routine Description:'\r | |
1220 | // TODO: function comment is missing 'Arguments:'\r | |
1221 | // TODO: IdeDev - add argument and description to function comment\r | |
1222 | // TODO: DelayInMilliSeconds - add argument and description to function comment\r | |
1223 | // TODO: EFI_ABORTED - add return value to function comment\r | |
1224 | {\r | |
1225 | UINT32 Delay;\r | |
1226 | UINT8 StatusRegister;\r | |
1227 | UINT8 ErrorRegister;\r | |
1228 | \r | |
1229 | Delay = (UINT32) (((DelayInMilliSeconds * STALL_1_MILLI_SECOND) / 30) + 1);\r | |
1230 | do {\r | |
1231 | StatusRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Status);\r | |
1232 | //\r | |
1233 | // BSY == 0 , DRDY == 1\r | |
1234 | //\r | |
1235 | if ((StatusRegister & (DRDY | BSY)) == DRDY) {\r | |
1236 | break;\r | |
1237 | }\r | |
1238 | \r | |
1239 | if ((StatusRegister & (BSY | ERR)) == ERR) {\r | |
1240 | \r | |
1241 | ErrorRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);\r | |
1242 | if ((ErrorRegister & ABRT_ERR) == ABRT_ERR) {\r | |
1243 | return EFI_ABORTED;\r | |
1244 | }\r | |
1245 | }\r | |
1246 | \r | |
1247 | gBS->Stall (15);\r | |
1248 | \r | |
1249 | Delay--;\r | |
1250 | } while (Delay);\r | |
1251 | \r | |
1252 | if (Delay == 0) {\r | |
1253 | return EFI_TIMEOUT;\r | |
1254 | }\r | |
1255 | \r | |
1256 | return EFI_SUCCESS;\r | |
1257 | }\r | |
1258 | \r | |
1259 | //\r | |
1260 | // DRDYReady2\r | |
1261 | //\r | |
1262 | /**\r | |
1263 | This function is used to poll for the DRDY bit set in the \r | |
1264 | Alternate Status Register. DRDY bit is set when the device is ready \r | |
1265 | to accept command. Most ATA commands must be sent after \r | |
1266 | DRDY set except the ATAPI Packet Command.\r | |
1267 | \r | |
1268 | @param[in] IDE_BLK_IO_DEV IN *IdeDev\r | |
1269 | pointer pointing to IDE_BLK_IO_DEV data structure, used\r | |
1270 | to record all the information of the IDE device.\r | |
1271 | \r | |
1272 | @param[in] UINTN IN TimeoutInMilliSeconds\r | |
1273 | used to designate the timeout for the DRQ ready.\r | |
1274 | \r | |
1275 | @retval EFI_SUCCESS\r | |
1276 | DRDY bit set within the time out.\r | |
1277 | \r | |
1278 | @retval EFI_TIMEOUT\r | |
1279 | DRDY bit not set within the time out.\r | |
1280 | \r | |
1281 | @note\r | |
1282 | Read Alternate Status Register will clear interrupt status.\r | |
1283 | \r | |
1284 | **/\r | |
1285 | EFI_STATUS\r | |
1286 | DRDYReady2 (\r | |
1287 | IN IDE_BLK_IO_DEV *IdeDev,\r | |
1288 | IN UINTN DelayInMilliSeconds\r | |
1289 | )\r | |
1290 | // TODO: function comment is missing 'Routine Description:'\r | |
1291 | // TODO: function comment is missing 'Arguments:'\r | |
1292 | // TODO: IdeDev - add argument and description to function comment\r | |
1293 | // TODO: DelayInMilliSeconds - add argument and description to function comment\r | |
1294 | // TODO: EFI_ABORTED - add return value to function comment\r | |
1295 | {\r | |
1296 | UINT32 Delay;\r | |
1297 | UINT8 AltRegister;\r | |
1298 | UINT8 ErrorRegister;\r | |
1299 | \r | |
1300 | Delay = (UINT32) (((DelayInMilliSeconds * STALL_1_MILLI_SECOND) / 30) + 1);\r | |
1301 | do {\r | |
1302 | AltRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Alt.AltStatus);\r | |
1303 | //\r | |
1304 | // BSY == 0 , DRDY == 1\r | |
1305 | //\r | |
1306 | if ((AltRegister & (DRDY | BSY)) == DRDY) {\r | |
1307 | break;\r | |
1308 | }\r | |
1309 | \r | |
1310 | if ((AltRegister & (BSY | ERR)) == ERR) {\r | |
1311 | \r | |
1312 | ErrorRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);\r | |
1313 | if ((ErrorRegister & ABRT_ERR) == ABRT_ERR) {\r | |
1314 | return EFI_ABORTED;\r | |
1315 | }\r | |
1316 | }\r | |
1317 | \r | |
1318 | gBS->Stall (30);\r | |
1319 | \r | |
1320 | Delay--;\r | |
1321 | } while (Delay);\r | |
1322 | \r | |
1323 | if (Delay == 0) {\r | |
1324 | return EFI_TIMEOUT;\r | |
1325 | }\r | |
1326 | \r | |
1327 | return EFI_SUCCESS;\r | |
1328 | }\r | |
1329 | \r | |
1330 | //\r | |
1331 | // SwapStringChars\r | |
1332 | //\r | |
1333 | /**\r | |
1334 | This function is a helper function used to change the char order in a \r | |
1335 | string. It is designed specially for the PrintAtaModuleName() function.\r | |
1336 | After the IDE device is detected, the IDE driver gets the device module\r | |
1337 | name by sending ATA command called ATA Identify Command or ATAPI \r | |
1338 | Identify Command to the specified IDE device. The module name returned \r | |
1339 | is a string of ASCII characters: the first character is bit8--bit15 \r | |
1340 | of the first word, the second character is bit0--bit7 of the first word \r | |
1341 | and so on. Thus the string can not be print directly before it is \r | |
1342 | preprocessed by this func to change the order of characters in \r | |
1343 | each word in the string.\r | |
1344 | \r | |
1345 | @param[in] CHAR8 IN *Destination\r | |
1346 | Indicates the destination string.\r | |
1347 | \r | |
1348 | @param[in] CHAR8 IN *Source\r | |
1349 | Indicates the source string.\r | |
1350 | \r | |
1351 | @param[in] UINT8 IN Size\r | |
1352 | the length of the string\r | |
1353 | \r | |
1354 | **/\r | |
1355 | VOID\r | |
1356 | SwapStringChars (\r | |
1357 | IN CHAR8 *Destination,\r | |
1358 | IN CHAR8 *Source,\r | |
1359 | IN UINT32 Size\r | |
1360 | )\r | |
1361 | {\r | |
1362 | UINT32 Index;\r | |
1363 | CHAR8 Temp;\r | |
1364 | \r | |
1365 | for (Index = 0; Index < Size; Index += 2) {\r | |
1366 | \r | |
1367 | Temp = Source[Index + 1];\r | |
1368 | Destination[Index + 1] = Source[Index];\r | |
1369 | Destination[Index] = Temp;\r | |
1370 | }\r | |
1371 | }\r | |
1372 | \r | |
1373 | //\r | |
1374 | // ReleaseIdeResources\r | |
1375 | //\r | |
1376 | /**\r | |
1377 | Release resources of an IDE device before stopping it.\r | |
1378 | \r | |
1379 | @param[in] *IdeBlkIoDevice Standard IDE device private data structure\r | |
1380 | \r | |
1381 | **/\r | |
1382 | VOID\r | |
1383 | ReleaseIdeResources (\r | |
1384 | IN IDE_BLK_IO_DEV *IdeBlkIoDevice\r | |
1385 | )\r | |
1386 | {\r | |
1387 | if (IdeBlkIoDevice == NULL) {\r | |
1388 | return ;\r | |
1389 | }\r | |
1390 | \r | |
1391 | //\r | |
1392 | // Release all the resourses occupied by the IDE_BLK_IO_DEV\r | |
1393 | //\r | |
1394 | \r | |
1395 | if (IdeBlkIoDevice->SenseData != NULL) {\r | |
1396 | gBS->FreePool (IdeBlkIoDevice->SenseData);\r | |
1397 | IdeBlkIoDevice->SenseData = NULL;\r | |
1398 | }\r | |
1399 | \r | |
1400 | if (IdeBlkIoDevice->Cache != NULL) {\r | |
1401 | gBS->FreePool (IdeBlkIoDevice->Cache);\r | |
1402 | IdeBlkIoDevice->Cache = NULL;\r | |
1403 | }\r | |
1404 | \r | |
1405 | if (IdeBlkIoDevice->pIdData != NULL) {\r | |
1406 | gBS->FreePool (IdeBlkIoDevice->pIdData);\r | |
1407 | IdeBlkIoDevice->pIdData = NULL;\r | |
1408 | }\r | |
1409 | \r | |
1410 | if (IdeBlkIoDevice->pInquiryData != NULL) {\r | |
1411 | gBS->FreePool (IdeBlkIoDevice->pInquiryData);\r | |
1412 | IdeBlkIoDevice->pInquiryData = NULL;\r | |
1413 | }\r | |
1414 | \r | |
1415 | if (IdeBlkIoDevice->ControllerNameTable != NULL) {\r | |
1416 | FreeUnicodeStringTable (IdeBlkIoDevice->ControllerNameTable);\r | |
1417 | IdeBlkIoDevice->ControllerNameTable = NULL;\r | |
1418 | }\r | |
1419 | \r | |
1420 | if (IdeBlkIoDevice->IoPort != NULL) {\r | |
1421 | gBS->FreePool (IdeBlkIoDevice->IoPort);\r | |
1422 | }\r | |
1423 | \r | |
1424 | if (IdeBlkIoDevice->DevicePath != NULL) {\r | |
1425 | gBS->FreePool (IdeBlkIoDevice->DevicePath);\r | |
1426 | }\r | |
1427 | \r | |
1428 | gBS->FreePool (IdeBlkIoDevice);\r | |
1429 | IdeBlkIoDevice = NULL;\r | |
1430 | \r | |
1431 | return ;\r | |
1432 | }\r | |
1433 | \r | |
1434 | //\r | |
1435 | // SetDeviceTransferMode\r | |
1436 | //\r | |
1437 | /**\r | |
1438 | Set the calculated Best transfer mode to a detected device\r | |
1439 | \r | |
1440 | @param[in] *IdeDev Standard IDE device private data structure\r | |
1441 | @param[in] *TransferMode The device transfer mode to be set\r | |
1442 | \r | |
1443 | @return Set transfer mode Command execute status\r | |
1444 | \r | |
1445 | **/\r | |
1446 | EFI_STATUS\r | |
1447 | SetDeviceTransferMode (\r | |
1448 | IN IDE_BLK_IO_DEV *IdeDev,\r | |
1449 | IN ATA_TRANSFER_MODE *TransferMode\r | |
1450 | )\r | |
1451 | // TODO: function comment is missing 'Routine Description:'\r | |
1452 | {\r | |
1453 | EFI_STATUS Status;\r | |
1454 | UINT8 DeviceSelect;\r | |
1455 | UINT8 SectorCount;\r | |
1456 | \r | |
1457 | DeviceSelect = 0;\r | |
1458 | DeviceSelect = (UINT8) ((IdeDev->Device) << 4);\r | |
1459 | SectorCount = *((UINT8 *) TransferMode);\r | |
1460 | \r | |
1461 | //\r | |
1462 | // Send SET FEATURE command (sub command 0x03) to set pio mode.\r | |
1463 | //\r | |
1464 | Status = AtaNonDataCommandIn (\r | |
1465 | IdeDev,\r | |
1466 | SET_FEATURES_CMD,\r | |
1467 | DeviceSelect,\r | |
1468 | 0x03,\r | |
1469 | SectorCount,\r | |
1470 | 0,\r | |
1471 | 0,\r | |
1472 | 0\r | |
1473 | );\r | |
1474 | \r | |
1475 | return Status;\r | |
1476 | }\r | |
1477 | \r | |
1478 | /**\r | |
1479 | Send ATA command into device with NON_DATA protocol\r | |
1480 | \r | |
1481 | @param IdeDev Standard IDE device private data structure\r | |
1482 | @param AtaCommand The ATA command to be sent\r | |
1483 | @param Device The value in Device register\r | |
1484 | @param Feature The value in Feature register\r | |
1485 | @param SectorCount The value in SectorCount register\r | |
1486 | @param LbaLow The value in LBA_LOW register\r | |
1487 | @param LbaMiddle The value in LBA_MIDDLE register\r | |
1488 | @param LbaHigh The value in LBA_HIGH register\r | |
1489 | \r | |
1490 | @retval EFI_SUCCESS Reading succeed\r | |
1491 | @retval EFI_ABORTED Command failed\r | |
1492 | @retval EFI_DEVICE_ERROR Device status error\r | |
1493 | \r | |
1494 | **/\r | |
1495 | EFI_STATUS\r | |
1496 | AtaNonDataCommandIn (\r | |
1497 | IN IDE_BLK_IO_DEV *IdeDev,\r | |
1498 | IN UINT8 AtaCommand,\r | |
1499 | IN UINT8 Device,\r | |
1500 | IN UINT8 Feature,\r | |
1501 | IN UINT8 SectorCount,\r | |
1502 | IN UINT8 LbaLow,\r | |
1503 | IN UINT8 LbaMiddle,\r | |
1504 | IN UINT8 LbaHigh\r | |
1505 | )\r | |
1506 | {\r | |
1507 | EFI_STATUS Status;\r | |
1508 | UINT8 StatusRegister;\r | |
1509 | \r | |
1510 | Status = WaitForBSYClear (IdeDev, ATATIMEOUT);\r | |
1511 | if (EFI_ERROR (Status)) {\r | |
1512 | return EFI_DEVICE_ERROR;\r | |
1513 | }\r | |
1514 | \r | |
1515 | //\r | |
1516 | // Select device (bit4), set LBA mode(bit6) (use 0xe0 for compatibility)\r | |
1517 | //\r | |
1518 | IDEWritePortB (\r | |
1519 | IdeDev->PciIo,\r | |
1520 | IdeDev->IoPort->Head,\r | |
1521 | (UINT8) ((IdeDev->Device << 4) | 0xe0)\r | |
1522 | );\r | |
1523 | \r | |
1524 | //\r | |
1525 | // ATA commands for ATA device must be issued when DRDY is set\r | |
1526 | //\r | |
1527 | Status = DRDYReady (IdeDev, ATATIMEOUT);\r | |
1528 | if (EFI_ERROR (Status)) {\r | |
1529 | return EFI_DEVICE_ERROR;\r | |
1530 | }\r | |
1531 | \r | |
1532 | //\r | |
1533 | // Pass parameter into device register block\r | |
1534 | //\r | |
1535 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Head, Device);\r | |
1536 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Feature, Feature);\r | |
1537 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorCount, SectorCount);\r | |
1538 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorNumber, LbaLow);\r | |
1539 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderLsb, LbaMiddle);\r | |
1540 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderMsb, LbaHigh);\r | |
1541 | \r | |
1542 | //\r | |
1543 | // Send command via Command Register\r | |
1544 | //\r | |
1545 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Command, AtaCommand);\r | |
1546 | \r | |
1547 | //\r | |
1548 | // Wait for command completion\r | |
1549 | //\r | |
1550 | Status = WaitForBSYClear (IdeDev, ATATIMEOUT);\r | |
1551 | if (EFI_ERROR (Status)) {\r | |
1552 | return EFI_DEVICE_ERROR;\r | |
1553 | }\r | |
1554 | \r | |
1555 | StatusRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Status);\r | |
1556 | if ((StatusRegister & ERR) == ERR) {\r | |
1557 | //\r | |
1558 | // Failed to execute command, abort operation\r | |
1559 | //\r | |
1560 | return EFI_ABORTED;\r | |
1561 | }\r | |
1562 | \r | |
1563 | return EFI_SUCCESS;\r | |
1564 | }\r | |
1565 | \r | |
1566 | /**\r | |
1567 | Send ATA Ext command into device with NON_DATA protocol\r | |
1568 | \r | |
1569 | @param IdeDev Standard IDE device private data structure\r | |
1570 | @param AtaCommand The ATA command to be sent\r | |
1571 | @param Device The value in Device register\r | |
1572 | @param Feature The value in Feature register\r | |
1573 | @param SectorCount The value in SectorCount register\r | |
1574 | @param LbaAddress The LBA address in 48-bit mode\r | |
1575 | \r | |
1576 | @retval EFI_SUCCESS Reading succeed\r | |
1577 | @retval EFI_ABORTED Command failed\r | |
1578 | @retval EFI_DEVICE_ERROR Device status error\r | |
1579 | \r | |
1580 | **/\r | |
1581 | EFI_STATUS\r | |
1582 | AtaNonDataCommandInExt (\r | |
1583 | IN IDE_BLK_IO_DEV *IdeDev,\r | |
1584 | IN UINT8 AtaCommand,\r | |
1585 | IN UINT8 Device,\r | |
1586 | IN UINT16 Feature,\r | |
1587 | IN UINT16 SectorCount,\r | |
1588 | IN EFI_LBA LbaAddress\r | |
1589 | )\r | |
1590 | {\r | |
1591 | EFI_STATUS Status;\r | |
1592 | UINT8 StatusRegister;\r | |
1593 | UINT8 SectorCount8;\r | |
1594 | UINT8 Feature8;\r | |
1595 | UINT8 LbaLow;\r | |
1596 | UINT8 LbaMid;\r | |
1597 | UINT8 LbaHigh;\r | |
1598 | \r | |
1599 | Status = WaitForBSYClear (IdeDev, ATATIMEOUT);\r | |
1600 | if (EFI_ERROR (Status)) {\r | |
1601 | return EFI_DEVICE_ERROR;\r | |
1602 | }\r | |
1603 | \r | |
1604 | //\r | |
1605 | // Select device (bit4), set LBA mode(bit6) (use 0xe0 for compatibility)\r | |
1606 | //\r | |
1607 | IDEWritePortB (\r | |
1608 | IdeDev->PciIo,\r | |
1609 | IdeDev->IoPort->Head,\r | |
1610 | (UINT8) ((IdeDev->Device << 4) | 0xe0)\r | |
1611 | );\r | |
1612 | \r | |
1613 | //\r | |
1614 | // ATA commands for ATA device must be issued when DRDY is set\r | |
1615 | //\r | |
1616 | Status = DRDYReady (IdeDev, ATATIMEOUT);\r | |
1617 | if (EFI_ERROR (Status)) {\r | |
1618 | return EFI_DEVICE_ERROR;\r | |
1619 | }\r | |
1620 | \r | |
1621 | //\r | |
1622 | // Pass parameter into device register block\r | |
1623 | //\r | |
1624 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Head, Device);\r | |
1625 | \r | |
1626 | //\r | |
1627 | // Fill the feature register, which is a two-byte FIFO. Need write twice.\r | |
1628 | //\r | |
1629 | Feature8 = (UINT8) (Feature >> 8);\r | |
1630 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Feature, Feature8);\r | |
1631 | \r | |
1632 | Feature8 = (UINT8) Feature;\r | |
1633 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Feature, Feature8);\r | |
1634 | \r | |
1635 | //\r | |
1636 | // Fill the sector count register, which is a two-byte FIFO. Need write twice.\r | |
1637 | //\r | |
1638 | SectorCount8 = (UINT8) (SectorCount >> 8);\r | |
1639 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorCount, SectorCount8);\r | |
1640 | \r | |
1641 | SectorCount8 = (UINT8) SectorCount;\r | |
1642 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorCount, SectorCount8);\r | |
1643 | \r | |
1644 | //\r | |
1645 | // Fill the start LBA registers, which are also two-byte FIFO\r | |
1646 | //\r | |
1647 | LbaLow = (UINT8) RShiftU64 (LbaAddress, 24);\r | |
1648 | LbaMid = (UINT8) RShiftU64 (LbaAddress, 32);\r | |
1649 | LbaHigh = (UINT8) RShiftU64 (LbaAddress, 40);\r | |
1650 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorNumber, LbaLow);\r | |
1651 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderLsb, LbaMid);\r | |
1652 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderMsb, LbaHigh);\r | |
1653 | \r | |
1654 | LbaLow = (UINT8) LbaAddress;\r | |
1655 | LbaMid = (UINT8) RShiftU64 (LbaAddress, 8);\r | |
1656 | LbaHigh = (UINT8) RShiftU64 (LbaAddress, 16);\r | |
1657 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorNumber, LbaLow);\r | |
1658 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderLsb, LbaMid);\r | |
1659 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderMsb, LbaHigh);\r | |
1660 | \r | |
1661 | //\r | |
1662 | // Send command via Command Register\r | |
1663 | //\r | |
1664 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Command, AtaCommand);\r | |
1665 | \r | |
1666 | //\r | |
1667 | // Wait for command completion\r | |
1668 | //\r | |
1669 | Status = WaitForBSYClear (IdeDev, ATATIMEOUT);\r | |
1670 | if (EFI_ERROR (Status)) {\r | |
1671 | return EFI_DEVICE_ERROR;\r | |
1672 | }\r | |
1673 | \r | |
1674 | StatusRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Status);\r | |
1675 | if ((StatusRegister & ERR) == ERR) {\r | |
1676 | //\r | |
1677 | // Failed to execute command, abort operation\r | |
1678 | //\r | |
1679 | return EFI_ABORTED;\r | |
1680 | }\r | |
1681 | \r | |
1682 | return EFI_SUCCESS;\r | |
1683 | }\r | |
1684 | \r | |
1685 | //\r | |
1686 | // SetDriveParameters\r | |
1687 | //\r | |
1688 | /**\r | |
1689 | Set drive parameters for devices not support PACKETS command\r | |
1690 | \r | |
1691 | @param[in] IdeDev Standard IDE device private data structure\r | |
1692 | @param[in] DriveParameters The device parameters to be set into the disk\r | |
1693 | \r | |
1694 | @return SetParameters Command execute status\r | |
1695 | \r | |
1696 | **/\r | |
1697 | EFI_STATUS\r | |
1698 | SetDriveParameters (\r | |
1699 | IN IDE_BLK_IO_DEV *IdeDev,\r | |
1700 | IN ATA_DRIVE_PARMS *DriveParameters\r | |
1701 | )\r | |
1702 | {\r | |
1703 | EFI_STATUS Status;\r | |
1704 | UINT8 DeviceSelect;\r | |
1705 | \r | |
1706 | DeviceSelect = 0;\r | |
1707 | DeviceSelect = (UINT8) ((IdeDev->Device) << 4);\r | |
1708 | \r | |
1709 | //\r | |
1710 | // Send Init drive parameters\r | |
1711 | //\r | |
1712 | Status = AtaPioDataIn (\r | |
1713 | IdeDev,\r | |
1714 | NULL,\r | |
1715 | 0,\r | |
1716 | INIT_DRIVE_PARAM_CMD,\r | |
1717 | (UINT8) (DeviceSelect + DriveParameters->Heads),\r | |
1718 | DriveParameters->Sector,\r | |
1719 | 0,\r | |
1720 | 0,\r | |
1721 | 0\r | |
1722 | );\r | |
1723 | \r | |
1724 | //\r | |
1725 | // Send Set Multiple parameters\r | |
1726 | //\r | |
1727 | Status = AtaPioDataIn (\r | |
1728 | IdeDev,\r | |
1729 | NULL,\r | |
1730 | 0,\r | |
1731 | SET_MULTIPLE_MODE_CMD,\r | |
1732 | DeviceSelect,\r | |
1733 | DriveParameters->MultipleSector,\r | |
1734 | 0,\r | |
1735 | 0,\r | |
1736 | 0\r | |
1737 | );\r | |
1738 | \r | |
1739 | return Status;\r | |
1740 | }\r | |
1741 | \r | |
1742 | /**\r | |
1743 | TODO: Add function description\r | |
1744 | \r | |
1745 | @param IdeDev TODO: add argument description\r | |
1746 | \r | |
1747 | @retval EFI_SUCCESS TODO: Add description for return value\r | |
1748 | \r | |
1749 | **/\r | |
1750 | EFI_STATUS\r | |
1751 | EnableInterrupt (\r | |
1752 | IN IDE_BLK_IO_DEV *IdeDev\r | |
1753 | )\r | |
1754 | {\r | |
1755 | UINT8 DeviceControl;\r | |
1756 | \r | |
1757 | //\r | |
1758 | // Enable interrupt for DMA operation\r | |
1759 | //\r | |
1760 | DeviceControl = 0;\r | |
1761 | IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl, DeviceControl);\r | |
1762 | \r | |
1763 | return EFI_SUCCESS;\r | |
1764 | }\r |