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1 | /* | |
2 | * qemu user main | |
3 | * | |
4 | * Copyright (c) 2003-2008 Fabrice Bellard | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #include <stdlib.h> | |
20 | #include <stdio.h> | |
21 | #include <stdarg.h> | |
22 | #include <string.h> | |
23 | #include <errno.h> | |
24 | #include <unistd.h> | |
25 | #include <sys/mman.h> | |
26 | #include <sys/syscall.h> | |
27 | #include <sys/resource.h> | |
28 | ||
29 | #include "qemu.h" | |
30 | #include "qemu-common.h" | |
31 | #include "qemu/cache-utils.h" | |
32 | #include "cpu.h" | |
33 | #include "tcg.h" | |
34 | #include "qemu/timer.h" | |
35 | #include "qemu/envlist.h" | |
36 | #include "elf.h" | |
37 | ||
38 | char *exec_path; | |
39 | ||
40 | int singlestep; | |
41 | const char *filename; | |
42 | const char *argv0; | |
43 | int gdbstub_port; | |
44 | envlist_t *envlist; | |
45 | const char *cpu_model; | |
46 | unsigned long mmap_min_addr; | |
47 | #if defined(CONFIG_USE_GUEST_BASE) | |
48 | unsigned long guest_base; | |
49 | int have_guest_base; | |
50 | #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64) | |
51 | /* | |
52 | * When running 32-on-64 we should make sure we can fit all of the possible | |
53 | * guest address space into a contiguous chunk of virtual host memory. | |
54 | * | |
55 | * This way we will never overlap with our own libraries or binaries or stack | |
56 | * or anything else that QEMU maps. | |
57 | */ | |
58 | # ifdef TARGET_MIPS | |
59 | /* MIPS only supports 31 bits of virtual address space for user space */ | |
60 | unsigned long reserved_va = 0x77000000; | |
61 | # else | |
62 | unsigned long reserved_va = 0xf7000000; | |
63 | # endif | |
64 | #else | |
65 | unsigned long reserved_va; | |
66 | #endif | |
67 | #endif | |
68 | ||
69 | static void usage(void); | |
70 | ||
71 | static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX; | |
72 | const char *qemu_uname_release = CONFIG_UNAME_RELEASE; | |
73 | ||
74 | /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so | |
75 | we allocate a bigger stack. Need a better solution, for example | |
76 | by remapping the process stack directly at the right place */ | |
77 | unsigned long guest_stack_size = 8 * 1024 * 1024UL; | |
78 | ||
79 | void gemu_log(const char *fmt, ...) | |
80 | { | |
81 | va_list ap; | |
82 | ||
83 | va_start(ap, fmt); | |
84 | vfprintf(stderr, fmt, ap); | |
85 | va_end(ap); | |
86 | } | |
87 | ||
88 | #if defined(TARGET_I386) | |
89 | int cpu_get_pic_interrupt(CPUX86State *env) | |
90 | { | |
91 | return -1; | |
92 | } | |
93 | #endif | |
94 | ||
95 | /***********************************************************/ | |
96 | /* Helper routines for implementing atomic operations. */ | |
97 | ||
98 | /* To implement exclusive operations we force all cpus to syncronise. | |
99 | We don't require a full sync, only that no cpus are executing guest code. | |
100 | The alternative is to map target atomic ops onto host equivalents, | |
101 | which requires quite a lot of per host/target work. */ | |
102 | static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER; | |
103 | static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER; | |
104 | static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER; | |
105 | static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER; | |
106 | static int pending_cpus; | |
107 | ||
108 | /* Make sure everything is in a consistent state for calling fork(). */ | |
109 | void fork_start(void) | |
110 | { | |
111 | pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); | |
112 | pthread_mutex_lock(&exclusive_lock); | |
113 | mmap_fork_start(); | |
114 | } | |
115 | ||
116 | void fork_end(int child) | |
117 | { | |
118 | mmap_fork_end(child); | |
119 | if (child) { | |
120 | /* Child processes created by fork() only have a single thread. | |
121 | Discard information about the parent threads. */ | |
122 | first_cpu = thread_cpu; | |
123 | first_cpu->next_cpu = NULL; | |
124 | pending_cpus = 0; | |
125 | pthread_mutex_init(&exclusive_lock, NULL); | |
126 | pthread_mutex_init(&cpu_list_mutex, NULL); | |
127 | pthread_cond_init(&exclusive_cond, NULL); | |
128 | pthread_cond_init(&exclusive_resume, NULL); | |
129 | pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL); | |
130 | gdbserver_fork((CPUArchState *)thread_cpu->env_ptr); | |
131 | } else { | |
132 | pthread_mutex_unlock(&exclusive_lock); | |
133 | pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); | |
134 | } | |
135 | } | |
136 | ||
137 | /* Wait for pending exclusive operations to complete. The exclusive lock | |
138 | must be held. */ | |
139 | static inline void exclusive_idle(void) | |
140 | { | |
141 | while (pending_cpus) { | |
142 | pthread_cond_wait(&exclusive_resume, &exclusive_lock); | |
143 | } | |
144 | } | |
145 | ||
146 | /* Start an exclusive operation. | |
147 | Must only be called from outside cpu_arm_exec. */ | |
148 | static inline void start_exclusive(void) | |
149 | { | |
150 | CPUState *other_cpu; | |
151 | ||
152 | pthread_mutex_lock(&exclusive_lock); | |
153 | exclusive_idle(); | |
154 | ||
155 | pending_cpus = 1; | |
156 | /* Make all other cpus stop executing. */ | |
157 | for (other_cpu = first_cpu; other_cpu; other_cpu = other_cpu->next_cpu) { | |
158 | if (other_cpu->running) { | |
159 | pending_cpus++; | |
160 | cpu_exit(other_cpu); | |
161 | } | |
162 | } | |
163 | if (pending_cpus > 1) { | |
164 | pthread_cond_wait(&exclusive_cond, &exclusive_lock); | |
165 | } | |
166 | } | |
167 | ||
168 | /* Finish an exclusive operation. */ | |
169 | static inline void end_exclusive(void) | |
170 | { | |
171 | pending_cpus = 0; | |
172 | pthread_cond_broadcast(&exclusive_resume); | |
173 | pthread_mutex_unlock(&exclusive_lock); | |
174 | } | |
175 | ||
176 | /* Wait for exclusive ops to finish, and begin cpu execution. */ | |
177 | static inline void cpu_exec_start(CPUState *cpu) | |
178 | { | |
179 | pthread_mutex_lock(&exclusive_lock); | |
180 | exclusive_idle(); | |
181 | cpu->running = true; | |
182 | pthread_mutex_unlock(&exclusive_lock); | |
183 | } | |
184 | ||
185 | /* Mark cpu as not executing, and release pending exclusive ops. */ | |
186 | static inline void cpu_exec_end(CPUState *cpu) | |
187 | { | |
188 | pthread_mutex_lock(&exclusive_lock); | |
189 | cpu->running = false; | |
190 | if (pending_cpus > 1) { | |
191 | pending_cpus--; | |
192 | if (pending_cpus == 1) { | |
193 | pthread_cond_signal(&exclusive_cond); | |
194 | } | |
195 | } | |
196 | exclusive_idle(); | |
197 | pthread_mutex_unlock(&exclusive_lock); | |
198 | } | |
199 | ||
200 | void cpu_list_lock(void) | |
201 | { | |
202 | pthread_mutex_lock(&cpu_list_mutex); | |
203 | } | |
204 | ||
205 | void cpu_list_unlock(void) | |
206 | { | |
207 | pthread_mutex_unlock(&cpu_list_mutex); | |
208 | } | |
209 | ||
210 | ||
211 | #ifdef TARGET_I386 | |
212 | /***********************************************************/ | |
213 | /* CPUX86 core interface */ | |
214 | ||
215 | void cpu_smm_update(CPUX86State *env) | |
216 | { | |
217 | } | |
218 | ||
219 | uint64_t cpu_get_tsc(CPUX86State *env) | |
220 | { | |
221 | return cpu_get_real_ticks(); | |
222 | } | |
223 | ||
224 | static void write_dt(void *ptr, unsigned long addr, unsigned long limit, | |
225 | int flags) | |
226 | { | |
227 | unsigned int e1, e2; | |
228 | uint32_t *p; | |
229 | e1 = (addr << 16) | (limit & 0xffff); | |
230 | e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); | |
231 | e2 |= flags; | |
232 | p = ptr; | |
233 | p[0] = tswap32(e1); | |
234 | p[1] = tswap32(e2); | |
235 | } | |
236 | ||
237 | static uint64_t *idt_table; | |
238 | #ifdef TARGET_X86_64 | |
239 | static void set_gate64(void *ptr, unsigned int type, unsigned int dpl, | |
240 | uint64_t addr, unsigned int sel) | |
241 | { | |
242 | uint32_t *p, e1, e2; | |
243 | e1 = (addr & 0xffff) | (sel << 16); | |
244 | e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); | |
245 | p = ptr; | |
246 | p[0] = tswap32(e1); | |
247 | p[1] = tswap32(e2); | |
248 | p[2] = tswap32(addr >> 32); | |
249 | p[3] = 0; | |
250 | } | |
251 | /* only dpl matters as we do only user space emulation */ | |
252 | static void set_idt(int n, unsigned int dpl) | |
253 | { | |
254 | set_gate64(idt_table + n * 2, 0, dpl, 0, 0); | |
255 | } | |
256 | #else | |
257 | static void set_gate(void *ptr, unsigned int type, unsigned int dpl, | |
258 | uint32_t addr, unsigned int sel) | |
259 | { | |
260 | uint32_t *p, e1, e2; | |
261 | e1 = (addr & 0xffff) | (sel << 16); | |
262 | e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); | |
263 | p = ptr; | |
264 | p[0] = tswap32(e1); | |
265 | p[1] = tswap32(e2); | |
266 | } | |
267 | ||
268 | /* only dpl matters as we do only user space emulation */ | |
269 | static void set_idt(int n, unsigned int dpl) | |
270 | { | |
271 | set_gate(idt_table + n, 0, dpl, 0, 0); | |
272 | } | |
273 | #endif | |
274 | ||
275 | void cpu_loop(CPUX86State *env) | |
276 | { | |
277 | int trapnr; | |
278 | abi_ulong pc; | |
279 | target_siginfo_t info; | |
280 | ||
281 | for(;;) { | |
282 | trapnr = cpu_x86_exec(env); | |
283 | switch(trapnr) { | |
284 | case 0x80: | |
285 | /* linux syscall from int $0x80 */ | |
286 | env->regs[R_EAX] = do_syscall(env, | |
287 | env->regs[R_EAX], | |
288 | env->regs[R_EBX], | |
289 | env->regs[R_ECX], | |
290 | env->regs[R_EDX], | |
291 | env->regs[R_ESI], | |
292 | env->regs[R_EDI], | |
293 | env->regs[R_EBP], | |
294 | 0, 0); | |
295 | break; | |
296 | #ifndef TARGET_ABI32 | |
297 | case EXCP_SYSCALL: | |
298 | /* linux syscall from syscall instruction */ | |
299 | env->regs[R_EAX] = do_syscall(env, | |
300 | env->regs[R_EAX], | |
301 | env->regs[R_EDI], | |
302 | env->regs[R_ESI], | |
303 | env->regs[R_EDX], | |
304 | env->regs[10], | |
305 | env->regs[8], | |
306 | env->regs[9], | |
307 | 0, 0); | |
308 | env->eip = env->exception_next_eip; | |
309 | break; | |
310 | #endif | |
311 | case EXCP0B_NOSEG: | |
312 | case EXCP0C_STACK: | |
313 | info.si_signo = SIGBUS; | |
314 | info.si_errno = 0; | |
315 | info.si_code = TARGET_SI_KERNEL; | |
316 | info._sifields._sigfault._addr = 0; | |
317 | queue_signal(env, info.si_signo, &info); | |
318 | break; | |
319 | case EXCP0D_GPF: | |
320 | /* XXX: potential problem if ABI32 */ | |
321 | #ifndef TARGET_X86_64 | |
322 | if (env->eflags & VM_MASK) { | |
323 | handle_vm86_fault(env); | |
324 | } else | |
325 | #endif | |
326 | { | |
327 | info.si_signo = SIGSEGV; | |
328 | info.si_errno = 0; | |
329 | info.si_code = TARGET_SI_KERNEL; | |
330 | info._sifields._sigfault._addr = 0; | |
331 | queue_signal(env, info.si_signo, &info); | |
332 | } | |
333 | break; | |
334 | case EXCP0E_PAGE: | |
335 | info.si_signo = SIGSEGV; | |
336 | info.si_errno = 0; | |
337 | if (!(env->error_code & 1)) | |
338 | info.si_code = TARGET_SEGV_MAPERR; | |
339 | else | |
340 | info.si_code = TARGET_SEGV_ACCERR; | |
341 | info._sifields._sigfault._addr = env->cr[2]; | |
342 | queue_signal(env, info.si_signo, &info); | |
343 | break; | |
344 | case EXCP00_DIVZ: | |
345 | #ifndef TARGET_X86_64 | |
346 | if (env->eflags & VM_MASK) { | |
347 | handle_vm86_trap(env, trapnr); | |
348 | } else | |
349 | #endif | |
350 | { | |
351 | /* division by zero */ | |
352 | info.si_signo = SIGFPE; | |
353 | info.si_errno = 0; | |
354 | info.si_code = TARGET_FPE_INTDIV; | |
355 | info._sifields._sigfault._addr = env->eip; | |
356 | queue_signal(env, info.si_signo, &info); | |
357 | } | |
358 | break; | |
359 | case EXCP01_DB: | |
360 | case EXCP03_INT3: | |
361 | #ifndef TARGET_X86_64 | |
362 | if (env->eflags & VM_MASK) { | |
363 | handle_vm86_trap(env, trapnr); | |
364 | } else | |
365 | #endif | |
366 | { | |
367 | info.si_signo = SIGTRAP; | |
368 | info.si_errno = 0; | |
369 | if (trapnr == EXCP01_DB) { | |
370 | info.si_code = TARGET_TRAP_BRKPT; | |
371 | info._sifields._sigfault._addr = env->eip; | |
372 | } else { | |
373 | info.si_code = TARGET_SI_KERNEL; | |
374 | info._sifields._sigfault._addr = 0; | |
375 | } | |
376 | queue_signal(env, info.si_signo, &info); | |
377 | } | |
378 | break; | |
379 | case EXCP04_INTO: | |
380 | case EXCP05_BOUND: | |
381 | #ifndef TARGET_X86_64 | |
382 | if (env->eflags & VM_MASK) { | |
383 | handle_vm86_trap(env, trapnr); | |
384 | } else | |
385 | #endif | |
386 | { | |
387 | info.si_signo = SIGSEGV; | |
388 | info.si_errno = 0; | |
389 | info.si_code = TARGET_SI_KERNEL; | |
390 | info._sifields._sigfault._addr = 0; | |
391 | queue_signal(env, info.si_signo, &info); | |
392 | } | |
393 | break; | |
394 | case EXCP06_ILLOP: | |
395 | info.si_signo = SIGILL; | |
396 | info.si_errno = 0; | |
397 | info.si_code = TARGET_ILL_ILLOPN; | |
398 | info._sifields._sigfault._addr = env->eip; | |
399 | queue_signal(env, info.si_signo, &info); | |
400 | break; | |
401 | case EXCP_INTERRUPT: | |
402 | /* just indicate that signals should be handled asap */ | |
403 | break; | |
404 | case EXCP_DEBUG: | |
405 | { | |
406 | int sig; | |
407 | ||
408 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
409 | if (sig) | |
410 | { | |
411 | info.si_signo = sig; | |
412 | info.si_errno = 0; | |
413 | info.si_code = TARGET_TRAP_BRKPT; | |
414 | queue_signal(env, info.si_signo, &info); | |
415 | } | |
416 | } | |
417 | break; | |
418 | default: | |
419 | pc = env->segs[R_CS].base + env->eip; | |
420 | fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n", | |
421 | (long)pc, trapnr); | |
422 | abort(); | |
423 | } | |
424 | process_pending_signals(env); | |
425 | } | |
426 | } | |
427 | #endif | |
428 | ||
429 | #ifdef TARGET_ARM | |
430 | ||
431 | #define get_user_code_u32(x, gaddr, doswap) \ | |
432 | ({ abi_long __r = get_user_u32((x), (gaddr)); \ | |
433 | if (!__r && (doswap)) { \ | |
434 | (x) = bswap32(x); \ | |
435 | } \ | |
436 | __r; \ | |
437 | }) | |
438 | ||
439 | #define get_user_code_u16(x, gaddr, doswap) \ | |
440 | ({ abi_long __r = get_user_u16((x), (gaddr)); \ | |
441 | if (!__r && (doswap)) { \ | |
442 | (x) = bswap16(x); \ | |
443 | } \ | |
444 | __r; \ | |
445 | }) | |
446 | ||
447 | /* | |
448 | * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt | |
449 | * Input: | |
450 | * r0 = pointer to oldval | |
451 | * r1 = pointer to newval | |
452 | * r2 = pointer to target value | |
453 | * | |
454 | * Output: | |
455 | * r0 = 0 if *ptr was changed, non-0 if no exchange happened | |
456 | * C set if *ptr was changed, clear if no exchange happened | |
457 | * | |
458 | * Note segv's in kernel helpers are a bit tricky, we can set the | |
459 | * data address sensibly but the PC address is just the entry point. | |
460 | */ | |
461 | static void arm_kernel_cmpxchg64_helper(CPUARMState *env) | |
462 | { | |
463 | uint64_t oldval, newval, val; | |
464 | uint32_t addr, cpsr; | |
465 | target_siginfo_t info; | |
466 | ||
467 | /* Based on the 32 bit code in do_kernel_trap */ | |
468 | ||
469 | /* XXX: This only works between threads, not between processes. | |
470 | It's probably possible to implement this with native host | |
471 | operations. However things like ldrex/strex are much harder so | |
472 | there's not much point trying. */ | |
473 | start_exclusive(); | |
474 | cpsr = cpsr_read(env); | |
475 | addr = env->regs[2]; | |
476 | ||
477 | if (get_user_u64(oldval, env->regs[0])) { | |
478 | env->cp15.c6_data = env->regs[0]; | |
479 | goto segv; | |
480 | }; | |
481 | ||
482 | if (get_user_u64(newval, env->regs[1])) { | |
483 | env->cp15.c6_data = env->regs[1]; | |
484 | goto segv; | |
485 | }; | |
486 | ||
487 | if (get_user_u64(val, addr)) { | |
488 | env->cp15.c6_data = addr; | |
489 | goto segv; | |
490 | } | |
491 | ||
492 | if (val == oldval) { | |
493 | val = newval; | |
494 | ||
495 | if (put_user_u64(val, addr)) { | |
496 | env->cp15.c6_data = addr; | |
497 | goto segv; | |
498 | }; | |
499 | ||
500 | env->regs[0] = 0; | |
501 | cpsr |= CPSR_C; | |
502 | } else { | |
503 | env->regs[0] = -1; | |
504 | cpsr &= ~CPSR_C; | |
505 | } | |
506 | cpsr_write(env, cpsr, CPSR_C); | |
507 | end_exclusive(); | |
508 | return; | |
509 | ||
510 | segv: | |
511 | end_exclusive(); | |
512 | /* We get the PC of the entry address - which is as good as anything, | |
513 | on a real kernel what you get depends on which mode it uses. */ | |
514 | info.si_signo = SIGSEGV; | |
515 | info.si_errno = 0; | |
516 | /* XXX: check env->error_code */ | |
517 | info.si_code = TARGET_SEGV_MAPERR; | |
518 | info._sifields._sigfault._addr = env->cp15.c6_data; | |
519 | queue_signal(env, info.si_signo, &info); | |
520 | ||
521 | end_exclusive(); | |
522 | } | |
523 | ||
524 | /* Handle a jump to the kernel code page. */ | |
525 | static int | |
526 | do_kernel_trap(CPUARMState *env) | |
527 | { | |
528 | uint32_t addr; | |
529 | uint32_t cpsr; | |
530 | uint32_t val; | |
531 | ||
532 | switch (env->regs[15]) { | |
533 | case 0xffff0fa0: /* __kernel_memory_barrier */ | |
534 | /* ??? No-op. Will need to do better for SMP. */ | |
535 | break; | |
536 | case 0xffff0fc0: /* __kernel_cmpxchg */ | |
537 | /* XXX: This only works between threads, not between processes. | |
538 | It's probably possible to implement this with native host | |
539 | operations. However things like ldrex/strex are much harder so | |
540 | there's not much point trying. */ | |
541 | start_exclusive(); | |
542 | cpsr = cpsr_read(env); | |
543 | addr = env->regs[2]; | |
544 | /* FIXME: This should SEGV if the access fails. */ | |
545 | if (get_user_u32(val, addr)) | |
546 | val = ~env->regs[0]; | |
547 | if (val == env->regs[0]) { | |
548 | val = env->regs[1]; | |
549 | /* FIXME: Check for segfaults. */ | |
550 | put_user_u32(val, addr); | |
551 | env->regs[0] = 0; | |
552 | cpsr |= CPSR_C; | |
553 | } else { | |
554 | env->regs[0] = -1; | |
555 | cpsr &= ~CPSR_C; | |
556 | } | |
557 | cpsr_write(env, cpsr, CPSR_C); | |
558 | end_exclusive(); | |
559 | break; | |
560 | case 0xffff0fe0: /* __kernel_get_tls */ | |
561 | env->regs[0] = env->cp15.c13_tls2; | |
562 | break; | |
563 | case 0xffff0f60: /* __kernel_cmpxchg64 */ | |
564 | arm_kernel_cmpxchg64_helper(env); | |
565 | break; | |
566 | ||
567 | default: | |
568 | return 1; | |
569 | } | |
570 | /* Jump back to the caller. */ | |
571 | addr = env->regs[14]; | |
572 | if (addr & 1) { | |
573 | env->thumb = 1; | |
574 | addr &= ~1; | |
575 | } | |
576 | env->regs[15] = addr; | |
577 | ||
578 | return 0; | |
579 | } | |
580 | ||
581 | static int do_strex(CPUARMState *env) | |
582 | { | |
583 | uint32_t val; | |
584 | int size; | |
585 | int rc = 1; | |
586 | int segv = 0; | |
587 | uint32_t addr; | |
588 | start_exclusive(); | |
589 | addr = env->exclusive_addr; | |
590 | if (addr != env->exclusive_test) { | |
591 | goto fail; | |
592 | } | |
593 | size = env->exclusive_info & 0xf; | |
594 | switch (size) { | |
595 | case 0: | |
596 | segv = get_user_u8(val, addr); | |
597 | break; | |
598 | case 1: | |
599 | segv = get_user_u16(val, addr); | |
600 | break; | |
601 | case 2: | |
602 | case 3: | |
603 | segv = get_user_u32(val, addr); | |
604 | break; | |
605 | default: | |
606 | abort(); | |
607 | } | |
608 | if (segv) { | |
609 | env->cp15.c6_data = addr; | |
610 | goto done; | |
611 | } | |
612 | if (val != env->exclusive_val) { | |
613 | goto fail; | |
614 | } | |
615 | if (size == 3) { | |
616 | segv = get_user_u32(val, addr + 4); | |
617 | if (segv) { | |
618 | env->cp15.c6_data = addr + 4; | |
619 | goto done; | |
620 | } | |
621 | if (val != env->exclusive_high) { | |
622 | goto fail; | |
623 | } | |
624 | } | |
625 | val = env->regs[(env->exclusive_info >> 8) & 0xf]; | |
626 | switch (size) { | |
627 | case 0: | |
628 | segv = put_user_u8(val, addr); | |
629 | break; | |
630 | case 1: | |
631 | segv = put_user_u16(val, addr); | |
632 | break; | |
633 | case 2: | |
634 | case 3: | |
635 | segv = put_user_u32(val, addr); | |
636 | break; | |
637 | } | |
638 | if (segv) { | |
639 | env->cp15.c6_data = addr; | |
640 | goto done; | |
641 | } | |
642 | if (size == 3) { | |
643 | val = env->regs[(env->exclusive_info >> 12) & 0xf]; | |
644 | segv = put_user_u32(val, addr + 4); | |
645 | if (segv) { | |
646 | env->cp15.c6_data = addr + 4; | |
647 | goto done; | |
648 | } | |
649 | } | |
650 | rc = 0; | |
651 | fail: | |
652 | env->regs[15] += 4; | |
653 | env->regs[(env->exclusive_info >> 4) & 0xf] = rc; | |
654 | done: | |
655 | end_exclusive(); | |
656 | return segv; | |
657 | } | |
658 | ||
659 | void cpu_loop(CPUARMState *env) | |
660 | { | |
661 | CPUState *cs = CPU(arm_env_get_cpu(env)); | |
662 | int trapnr; | |
663 | unsigned int n, insn; | |
664 | target_siginfo_t info; | |
665 | uint32_t addr; | |
666 | ||
667 | for(;;) { | |
668 | cpu_exec_start(cs); | |
669 | trapnr = cpu_arm_exec(env); | |
670 | cpu_exec_end(cs); | |
671 | switch(trapnr) { | |
672 | case EXCP_UDEF: | |
673 | { | |
674 | TaskState *ts = env->opaque; | |
675 | uint32_t opcode; | |
676 | int rc; | |
677 | ||
678 | /* we handle the FPU emulation here, as Linux */ | |
679 | /* we get the opcode */ | |
680 | /* FIXME - what to do if get_user() fails? */ | |
681 | get_user_code_u32(opcode, env->regs[15], env->bswap_code); | |
682 | ||
683 | rc = EmulateAll(opcode, &ts->fpa, env); | |
684 | if (rc == 0) { /* illegal instruction */ | |
685 | info.si_signo = SIGILL; | |
686 | info.si_errno = 0; | |
687 | info.si_code = TARGET_ILL_ILLOPN; | |
688 | info._sifields._sigfault._addr = env->regs[15]; | |
689 | queue_signal(env, info.si_signo, &info); | |
690 | } else if (rc < 0) { /* FP exception */ | |
691 | int arm_fpe=0; | |
692 | ||
693 | /* translate softfloat flags to FPSR flags */ | |
694 | if (-rc & float_flag_invalid) | |
695 | arm_fpe |= BIT_IOC; | |
696 | if (-rc & float_flag_divbyzero) | |
697 | arm_fpe |= BIT_DZC; | |
698 | if (-rc & float_flag_overflow) | |
699 | arm_fpe |= BIT_OFC; | |
700 | if (-rc & float_flag_underflow) | |
701 | arm_fpe |= BIT_UFC; | |
702 | if (-rc & float_flag_inexact) | |
703 | arm_fpe |= BIT_IXC; | |
704 | ||
705 | FPSR fpsr = ts->fpa.fpsr; | |
706 | //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); | |
707 | ||
708 | if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ | |
709 | info.si_signo = SIGFPE; | |
710 | info.si_errno = 0; | |
711 | ||
712 | /* ordered by priority, least first */ | |
713 | if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES; | |
714 | if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND; | |
715 | if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF; | |
716 | if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV; | |
717 | if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV; | |
718 | ||
719 | info._sifields._sigfault._addr = env->regs[15]; | |
720 | queue_signal(env, info.si_signo, &info); | |
721 | } else { | |
722 | env->regs[15] += 4; | |
723 | } | |
724 | ||
725 | /* accumulate unenabled exceptions */ | |
726 | if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) | |
727 | fpsr |= BIT_IXC; | |
728 | if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) | |
729 | fpsr |= BIT_UFC; | |
730 | if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) | |
731 | fpsr |= BIT_OFC; | |
732 | if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) | |
733 | fpsr |= BIT_DZC; | |
734 | if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) | |
735 | fpsr |= BIT_IOC; | |
736 | ts->fpa.fpsr=fpsr; | |
737 | } else { /* everything OK */ | |
738 | /* increment PC */ | |
739 | env->regs[15] += 4; | |
740 | } | |
741 | } | |
742 | break; | |
743 | case EXCP_SWI: | |
744 | case EXCP_BKPT: | |
745 | { | |
746 | env->eabi = 1; | |
747 | /* system call */ | |
748 | if (trapnr == EXCP_BKPT) { | |
749 | if (env->thumb) { | |
750 | /* FIXME - what to do if get_user() fails? */ | |
751 | get_user_code_u16(insn, env->regs[15], env->bswap_code); | |
752 | n = insn & 0xff; | |
753 | env->regs[15] += 2; | |
754 | } else { | |
755 | /* FIXME - what to do if get_user() fails? */ | |
756 | get_user_code_u32(insn, env->regs[15], env->bswap_code); | |
757 | n = (insn & 0xf) | ((insn >> 4) & 0xff0); | |
758 | env->regs[15] += 4; | |
759 | } | |
760 | } else { | |
761 | if (env->thumb) { | |
762 | /* FIXME - what to do if get_user() fails? */ | |
763 | get_user_code_u16(insn, env->regs[15] - 2, | |
764 | env->bswap_code); | |
765 | n = insn & 0xff; | |
766 | } else { | |
767 | /* FIXME - what to do if get_user() fails? */ | |
768 | get_user_code_u32(insn, env->regs[15] - 4, | |
769 | env->bswap_code); | |
770 | n = insn & 0xffffff; | |
771 | } | |
772 | } | |
773 | ||
774 | if (n == ARM_NR_cacheflush) { | |
775 | /* nop */ | |
776 | } else if (n == ARM_NR_semihosting | |
777 | || n == ARM_NR_thumb_semihosting) { | |
778 | env->regs[0] = do_arm_semihosting (env); | |
779 | } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) { | |
780 | /* linux syscall */ | |
781 | if (env->thumb || n == 0) { | |
782 | n = env->regs[7]; | |
783 | } else { | |
784 | n -= ARM_SYSCALL_BASE; | |
785 | env->eabi = 0; | |
786 | } | |
787 | if ( n > ARM_NR_BASE) { | |
788 | switch (n) { | |
789 | case ARM_NR_cacheflush: | |
790 | /* nop */ | |
791 | break; | |
792 | case ARM_NR_set_tls: | |
793 | cpu_set_tls(env, env->regs[0]); | |
794 | env->regs[0] = 0; | |
795 | break; | |
796 | default: | |
797 | gemu_log("qemu: Unsupported ARM syscall: 0x%x\n", | |
798 | n); | |
799 | env->regs[0] = -TARGET_ENOSYS; | |
800 | break; | |
801 | } | |
802 | } else { | |
803 | env->regs[0] = do_syscall(env, | |
804 | n, | |
805 | env->regs[0], | |
806 | env->regs[1], | |
807 | env->regs[2], | |
808 | env->regs[3], | |
809 | env->regs[4], | |
810 | env->regs[5], | |
811 | 0, 0); | |
812 | } | |
813 | } else { | |
814 | goto error; | |
815 | } | |
816 | } | |
817 | break; | |
818 | case EXCP_INTERRUPT: | |
819 | /* just indicate that signals should be handled asap */ | |
820 | break; | |
821 | case EXCP_PREFETCH_ABORT: | |
822 | addr = env->cp15.c6_insn; | |
823 | goto do_segv; | |
824 | case EXCP_DATA_ABORT: | |
825 | addr = env->cp15.c6_data; | |
826 | do_segv: | |
827 | { | |
828 | info.si_signo = SIGSEGV; | |
829 | info.si_errno = 0; | |
830 | /* XXX: check env->error_code */ | |
831 | info.si_code = TARGET_SEGV_MAPERR; | |
832 | info._sifields._sigfault._addr = addr; | |
833 | queue_signal(env, info.si_signo, &info); | |
834 | } | |
835 | break; | |
836 | case EXCP_DEBUG: | |
837 | { | |
838 | int sig; | |
839 | ||
840 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
841 | if (sig) | |
842 | { | |
843 | info.si_signo = sig; | |
844 | info.si_errno = 0; | |
845 | info.si_code = TARGET_TRAP_BRKPT; | |
846 | queue_signal(env, info.si_signo, &info); | |
847 | } | |
848 | } | |
849 | break; | |
850 | case EXCP_KERNEL_TRAP: | |
851 | if (do_kernel_trap(env)) | |
852 | goto error; | |
853 | break; | |
854 | case EXCP_STREX: | |
855 | if (do_strex(env)) { | |
856 | addr = env->cp15.c6_data; | |
857 | goto do_segv; | |
858 | } | |
859 | break; | |
860 | default: | |
861 | error: | |
862 | fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", | |
863 | trapnr); | |
864 | cpu_dump_state(cs, stderr, fprintf, 0); | |
865 | abort(); | |
866 | } | |
867 | process_pending_signals(env); | |
868 | } | |
869 | } | |
870 | ||
871 | #endif | |
872 | ||
873 | #ifdef TARGET_UNICORE32 | |
874 | ||
875 | void cpu_loop(CPUUniCore32State *env) | |
876 | { | |
877 | CPUState *cs = CPU(uc32_env_get_cpu(env)); | |
878 | int trapnr; | |
879 | unsigned int n, insn; | |
880 | target_siginfo_t info; | |
881 | ||
882 | for (;;) { | |
883 | cpu_exec_start(cs); | |
884 | trapnr = uc32_cpu_exec(env); | |
885 | cpu_exec_end(cs); | |
886 | switch (trapnr) { | |
887 | case UC32_EXCP_PRIV: | |
888 | { | |
889 | /* system call */ | |
890 | get_user_u32(insn, env->regs[31] - 4); | |
891 | n = insn & 0xffffff; | |
892 | ||
893 | if (n >= UC32_SYSCALL_BASE) { | |
894 | /* linux syscall */ | |
895 | n -= UC32_SYSCALL_BASE; | |
896 | if (n == UC32_SYSCALL_NR_set_tls) { | |
897 | cpu_set_tls(env, env->regs[0]); | |
898 | env->regs[0] = 0; | |
899 | } else { | |
900 | env->regs[0] = do_syscall(env, | |
901 | n, | |
902 | env->regs[0], | |
903 | env->regs[1], | |
904 | env->regs[2], | |
905 | env->regs[3], | |
906 | env->regs[4], | |
907 | env->regs[5], | |
908 | 0, 0); | |
909 | } | |
910 | } else { | |
911 | goto error; | |
912 | } | |
913 | } | |
914 | break; | |
915 | case UC32_EXCP_DTRAP: | |
916 | case UC32_EXCP_ITRAP: | |
917 | info.si_signo = SIGSEGV; | |
918 | info.si_errno = 0; | |
919 | /* XXX: check env->error_code */ | |
920 | info.si_code = TARGET_SEGV_MAPERR; | |
921 | info._sifields._sigfault._addr = env->cp0.c4_faultaddr; | |
922 | queue_signal(env, info.si_signo, &info); | |
923 | break; | |
924 | case EXCP_INTERRUPT: | |
925 | /* just indicate that signals should be handled asap */ | |
926 | break; | |
927 | case EXCP_DEBUG: | |
928 | { | |
929 | int sig; | |
930 | ||
931 | sig = gdb_handlesig(env, TARGET_SIGTRAP); | |
932 | if (sig) { | |
933 | info.si_signo = sig; | |
934 | info.si_errno = 0; | |
935 | info.si_code = TARGET_TRAP_BRKPT; | |
936 | queue_signal(env, info.si_signo, &info); | |
937 | } | |
938 | } | |
939 | break; | |
940 | default: | |
941 | goto error; | |
942 | } | |
943 | process_pending_signals(env); | |
944 | } | |
945 | ||
946 | error: | |
947 | fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); | |
948 | cpu_dump_state(cs, stderr, fprintf, 0); | |
949 | abort(); | |
950 | } | |
951 | #endif | |
952 | ||
953 | #ifdef TARGET_SPARC | |
954 | #define SPARC64_STACK_BIAS 2047 | |
955 | ||
956 | //#define DEBUG_WIN | |
957 | ||
958 | /* WARNING: dealing with register windows _is_ complicated. More info | |
959 | can be found at http://www.sics.se/~psm/sparcstack.html */ | |
960 | static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) | |
961 | { | |
962 | index = (index + cwp * 16) % (16 * env->nwindows); | |
963 | /* wrap handling : if cwp is on the last window, then we use the | |
964 | registers 'after' the end */ | |
965 | if (index < 8 && env->cwp == env->nwindows - 1) | |
966 | index += 16 * env->nwindows; | |
967 | return index; | |
968 | } | |
969 | ||
970 | /* save the register window 'cwp1' */ | |
971 | static inline void save_window_offset(CPUSPARCState *env, int cwp1) | |
972 | { | |
973 | unsigned int i; | |
974 | abi_ulong sp_ptr; | |
975 | ||
976 | sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; | |
977 | #ifdef TARGET_SPARC64 | |
978 | if (sp_ptr & 3) | |
979 | sp_ptr += SPARC64_STACK_BIAS; | |
980 | #endif | |
981 | #if defined(DEBUG_WIN) | |
982 | printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n", | |
983 | sp_ptr, cwp1); | |
984 | #endif | |
985 | for(i = 0; i < 16; i++) { | |
986 | /* FIXME - what to do if put_user() fails? */ | |
987 | put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); | |
988 | sp_ptr += sizeof(abi_ulong); | |
989 | } | |
990 | } | |
991 | ||
992 | static void save_window(CPUSPARCState *env) | |
993 | { | |
994 | #ifndef TARGET_SPARC64 | |
995 | unsigned int new_wim; | |
996 | new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & | |
997 | ((1LL << env->nwindows) - 1); | |
998 | save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); | |
999 | env->wim = new_wim; | |
1000 | #else | |
1001 | save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); | |
1002 | env->cansave++; | |
1003 | env->canrestore--; | |
1004 | #endif | |
1005 | } | |
1006 | ||
1007 | static void restore_window(CPUSPARCState *env) | |
1008 | { | |
1009 | #ifndef TARGET_SPARC64 | |
1010 | unsigned int new_wim; | |
1011 | #endif | |
1012 | unsigned int i, cwp1; | |
1013 | abi_ulong sp_ptr; | |
1014 | ||
1015 | #ifndef TARGET_SPARC64 | |
1016 | new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & | |
1017 | ((1LL << env->nwindows) - 1); | |
1018 | #endif | |
1019 | ||
1020 | /* restore the invalid window */ | |
1021 | cwp1 = cpu_cwp_inc(env, env->cwp + 1); | |
1022 | sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; | |
1023 | #ifdef TARGET_SPARC64 | |
1024 | if (sp_ptr & 3) | |
1025 | sp_ptr += SPARC64_STACK_BIAS; | |
1026 | #endif | |
1027 | #if defined(DEBUG_WIN) | |
1028 | printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n", | |
1029 | sp_ptr, cwp1); | |
1030 | #endif | |
1031 | for(i = 0; i < 16; i++) { | |
1032 | /* FIXME - what to do if get_user() fails? */ | |
1033 | get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); | |
1034 | sp_ptr += sizeof(abi_ulong); | |
1035 | } | |
1036 | #ifdef TARGET_SPARC64 | |
1037 | env->canrestore++; | |
1038 | if (env->cleanwin < env->nwindows - 1) | |
1039 | env->cleanwin++; | |
1040 | env->cansave--; | |
1041 | #else | |
1042 | env->wim = new_wim; | |
1043 | #endif | |
1044 | } | |
1045 | ||
1046 | static void flush_windows(CPUSPARCState *env) | |
1047 | { | |
1048 | int offset, cwp1; | |
1049 | ||
1050 | offset = 1; | |
1051 | for(;;) { | |
1052 | /* if restore would invoke restore_window(), then we can stop */ | |
1053 | cwp1 = cpu_cwp_inc(env, env->cwp + offset); | |
1054 | #ifndef TARGET_SPARC64 | |
1055 | if (env->wim & (1 << cwp1)) | |
1056 | break; | |
1057 | #else | |
1058 | if (env->canrestore == 0) | |
1059 | break; | |
1060 | env->cansave++; | |
1061 | env->canrestore--; | |
1062 | #endif | |
1063 | save_window_offset(env, cwp1); | |
1064 | offset++; | |
1065 | } | |
1066 | cwp1 = cpu_cwp_inc(env, env->cwp + 1); | |
1067 | #ifndef TARGET_SPARC64 | |
1068 | /* set wim so that restore will reload the registers */ | |
1069 | env->wim = 1 << cwp1; | |
1070 | #endif | |
1071 | #if defined(DEBUG_WIN) | |
1072 | printf("flush_windows: nb=%d\n", offset - 1); | |
1073 | #endif | |
1074 | } | |
1075 | ||
1076 | void cpu_loop (CPUSPARCState *env) | |
1077 | { | |
1078 | CPUState *cs = CPU(sparc_env_get_cpu(env)); | |
1079 | int trapnr; | |
1080 | abi_long ret; | |
1081 | target_siginfo_t info; | |
1082 | ||
1083 | while (1) { | |
1084 | trapnr = cpu_sparc_exec (env); | |
1085 | ||
1086 | /* Compute PSR before exposing state. */ | |
1087 | if (env->cc_op != CC_OP_FLAGS) { | |
1088 | cpu_get_psr(env); | |
1089 | } | |
1090 | ||
1091 | switch (trapnr) { | |
1092 | #ifndef TARGET_SPARC64 | |
1093 | case 0x88: | |
1094 | case 0x90: | |
1095 | #else | |
1096 | case 0x110: | |
1097 | case 0x16d: | |
1098 | #endif | |
1099 | ret = do_syscall (env, env->gregs[1], | |
1100 | env->regwptr[0], env->regwptr[1], | |
1101 | env->regwptr[2], env->regwptr[3], | |
1102 | env->regwptr[4], env->regwptr[5], | |
1103 | 0, 0); | |
1104 | if ((abi_ulong)ret >= (abi_ulong)(-515)) { | |
1105 | #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) | |
1106 | env->xcc |= PSR_CARRY; | |
1107 | #else | |
1108 | env->psr |= PSR_CARRY; | |
1109 | #endif | |
1110 | ret = -ret; | |
1111 | } else { | |
1112 | #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) | |
1113 | env->xcc &= ~PSR_CARRY; | |
1114 | #else | |
1115 | env->psr &= ~PSR_CARRY; | |
1116 | #endif | |
1117 | } | |
1118 | env->regwptr[0] = ret; | |
1119 | /* next instruction */ | |
1120 | env->pc = env->npc; | |
1121 | env->npc = env->npc + 4; | |
1122 | break; | |
1123 | case 0x83: /* flush windows */ | |
1124 | #ifdef TARGET_ABI32 | |
1125 | case 0x103: | |
1126 | #endif | |
1127 | flush_windows(env); | |
1128 | /* next instruction */ | |
1129 | env->pc = env->npc; | |
1130 | env->npc = env->npc + 4; | |
1131 | break; | |
1132 | #ifndef TARGET_SPARC64 | |
1133 | case TT_WIN_OVF: /* window overflow */ | |
1134 | save_window(env); | |
1135 | break; | |
1136 | case TT_WIN_UNF: /* window underflow */ | |
1137 | restore_window(env); | |
1138 | break; | |
1139 | case TT_TFAULT: | |
1140 | case TT_DFAULT: | |
1141 | { | |
1142 | info.si_signo = TARGET_SIGSEGV; | |
1143 | info.si_errno = 0; | |
1144 | /* XXX: check env->error_code */ | |
1145 | info.si_code = TARGET_SEGV_MAPERR; | |
1146 | info._sifields._sigfault._addr = env->mmuregs[4]; | |
1147 | queue_signal(env, info.si_signo, &info); | |
1148 | } | |
1149 | break; | |
1150 | #else | |
1151 | case TT_SPILL: /* window overflow */ | |
1152 | save_window(env); | |
1153 | break; | |
1154 | case TT_FILL: /* window underflow */ | |
1155 | restore_window(env); | |
1156 | break; | |
1157 | case TT_TFAULT: | |
1158 | case TT_DFAULT: | |
1159 | { | |
1160 | info.si_signo = TARGET_SIGSEGV; | |
1161 | info.si_errno = 0; | |
1162 | /* XXX: check env->error_code */ | |
1163 | info.si_code = TARGET_SEGV_MAPERR; | |
1164 | if (trapnr == TT_DFAULT) | |
1165 | info._sifields._sigfault._addr = env->dmmuregs[4]; | |
1166 | else | |
1167 | info._sifields._sigfault._addr = cpu_tsptr(env)->tpc; | |
1168 | queue_signal(env, info.si_signo, &info); | |
1169 | } | |
1170 | break; | |
1171 | #ifndef TARGET_ABI32 | |
1172 | case 0x16e: | |
1173 | flush_windows(env); | |
1174 | sparc64_get_context(env); | |
1175 | break; | |
1176 | case 0x16f: | |
1177 | flush_windows(env); | |
1178 | sparc64_set_context(env); | |
1179 | break; | |
1180 | #endif | |
1181 | #endif | |
1182 | case EXCP_INTERRUPT: | |
1183 | /* just indicate that signals should be handled asap */ | |
1184 | break; | |
1185 | case TT_ILL_INSN: | |
1186 | { | |
1187 | info.si_signo = TARGET_SIGILL; | |
1188 | info.si_errno = 0; | |
1189 | info.si_code = TARGET_ILL_ILLOPC; | |
1190 | info._sifields._sigfault._addr = env->pc; | |
1191 | queue_signal(env, info.si_signo, &info); | |
1192 | } | |
1193 | break; | |
1194 | case EXCP_DEBUG: | |
1195 | { | |
1196 | int sig; | |
1197 | ||
1198 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
1199 | if (sig) | |
1200 | { | |
1201 | info.si_signo = sig; | |
1202 | info.si_errno = 0; | |
1203 | info.si_code = TARGET_TRAP_BRKPT; | |
1204 | queue_signal(env, info.si_signo, &info); | |
1205 | } | |
1206 | } | |
1207 | break; | |
1208 | default: | |
1209 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
1210 | cpu_dump_state(cs, stderr, fprintf, 0); | |
1211 | exit (1); | |
1212 | } | |
1213 | process_pending_signals (env); | |
1214 | } | |
1215 | } | |
1216 | ||
1217 | #endif | |
1218 | ||
1219 | #ifdef TARGET_PPC | |
1220 | static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env) | |
1221 | { | |
1222 | /* TO FIX */ | |
1223 | return 0; | |
1224 | } | |
1225 | ||
1226 | uint64_t cpu_ppc_load_tbl(CPUPPCState *env) | |
1227 | { | |
1228 | return cpu_ppc_get_tb(env); | |
1229 | } | |
1230 | ||
1231 | uint32_t cpu_ppc_load_tbu(CPUPPCState *env) | |
1232 | { | |
1233 | return cpu_ppc_get_tb(env) >> 32; | |
1234 | } | |
1235 | ||
1236 | uint64_t cpu_ppc_load_atbl(CPUPPCState *env) | |
1237 | { | |
1238 | return cpu_ppc_get_tb(env); | |
1239 | } | |
1240 | ||
1241 | uint32_t cpu_ppc_load_atbu(CPUPPCState *env) | |
1242 | { | |
1243 | return cpu_ppc_get_tb(env) >> 32; | |
1244 | } | |
1245 | ||
1246 | uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env) | |
1247 | __attribute__ (( alias ("cpu_ppc_load_tbu") )); | |
1248 | ||
1249 | uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env) | |
1250 | { | |
1251 | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; | |
1252 | } | |
1253 | ||
1254 | /* XXX: to be fixed */ | |
1255 | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) | |
1256 | { | |
1257 | return -1; | |
1258 | } | |
1259 | ||
1260 | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) | |
1261 | { | |
1262 | return -1; | |
1263 | } | |
1264 | ||
1265 | #define EXCP_DUMP(env, fmt, ...) \ | |
1266 | do { \ | |
1267 | CPUState *cs = ENV_GET_CPU(env); \ | |
1268 | fprintf(stderr, fmt , ## __VA_ARGS__); \ | |
1269 | cpu_dump_state(cs, stderr, fprintf, 0); \ | |
1270 | qemu_log(fmt, ## __VA_ARGS__); \ | |
1271 | if (qemu_log_enabled()) { \ | |
1272 | log_cpu_state(cs, 0); \ | |
1273 | } \ | |
1274 | } while (0) | |
1275 | ||
1276 | static int do_store_exclusive(CPUPPCState *env) | |
1277 | { | |
1278 | target_ulong addr; | |
1279 | target_ulong page_addr; | |
1280 | target_ulong val; | |
1281 | int flags; | |
1282 | int segv = 0; | |
1283 | ||
1284 | addr = env->reserve_ea; | |
1285 | page_addr = addr & TARGET_PAGE_MASK; | |
1286 | start_exclusive(); | |
1287 | mmap_lock(); | |
1288 | flags = page_get_flags(page_addr); | |
1289 | if ((flags & PAGE_READ) == 0) { | |
1290 | segv = 1; | |
1291 | } else { | |
1292 | int reg = env->reserve_info & 0x1f; | |
1293 | int size = (env->reserve_info >> 5) & 0xf; | |
1294 | int stored = 0; | |
1295 | ||
1296 | if (addr == env->reserve_addr) { | |
1297 | switch (size) { | |
1298 | case 1: segv = get_user_u8(val, addr); break; | |
1299 | case 2: segv = get_user_u16(val, addr); break; | |
1300 | case 4: segv = get_user_u32(val, addr); break; | |
1301 | #if defined(TARGET_PPC64) | |
1302 | case 8: segv = get_user_u64(val, addr); break; | |
1303 | #endif | |
1304 | default: abort(); | |
1305 | } | |
1306 | if (!segv && val == env->reserve_val) { | |
1307 | val = env->gpr[reg]; | |
1308 | switch (size) { | |
1309 | case 1: segv = put_user_u8(val, addr); break; | |
1310 | case 2: segv = put_user_u16(val, addr); break; | |
1311 | case 4: segv = put_user_u32(val, addr); break; | |
1312 | #if defined(TARGET_PPC64) | |
1313 | case 8: segv = put_user_u64(val, addr); break; | |
1314 | #endif | |
1315 | default: abort(); | |
1316 | } | |
1317 | if (!segv) { | |
1318 | stored = 1; | |
1319 | } | |
1320 | } | |
1321 | } | |
1322 | env->crf[0] = (stored << 1) | xer_so; | |
1323 | env->reserve_addr = (target_ulong)-1; | |
1324 | } | |
1325 | if (!segv) { | |
1326 | env->nip += 4; | |
1327 | } | |
1328 | mmap_unlock(); | |
1329 | end_exclusive(); | |
1330 | return segv; | |
1331 | } | |
1332 | ||
1333 | void cpu_loop(CPUPPCState *env) | |
1334 | { | |
1335 | CPUState *cs = CPU(ppc_env_get_cpu(env)); | |
1336 | target_siginfo_t info; | |
1337 | int trapnr; | |
1338 | target_ulong ret; | |
1339 | ||
1340 | for(;;) { | |
1341 | cpu_exec_start(cs); | |
1342 | trapnr = cpu_ppc_exec(env); | |
1343 | cpu_exec_end(cs); | |
1344 | switch(trapnr) { | |
1345 | case POWERPC_EXCP_NONE: | |
1346 | /* Just go on */ | |
1347 | break; | |
1348 | case POWERPC_EXCP_CRITICAL: /* Critical input */ | |
1349 | cpu_abort(env, "Critical interrupt while in user mode. " | |
1350 | "Aborting\n"); | |
1351 | break; | |
1352 | case POWERPC_EXCP_MCHECK: /* Machine check exception */ | |
1353 | cpu_abort(env, "Machine check exception while in user mode. " | |
1354 | "Aborting\n"); | |
1355 | break; | |
1356 | case POWERPC_EXCP_DSI: /* Data storage exception */ | |
1357 | EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n", | |
1358 | env->spr[SPR_DAR]); | |
1359 | /* XXX: check this. Seems bugged */ | |
1360 | switch (env->error_code & 0xFF000000) { | |
1361 | case 0x40000000: | |
1362 | info.si_signo = TARGET_SIGSEGV; | |
1363 | info.si_errno = 0; | |
1364 | info.si_code = TARGET_SEGV_MAPERR; | |
1365 | break; | |
1366 | case 0x04000000: | |
1367 | info.si_signo = TARGET_SIGILL; | |
1368 | info.si_errno = 0; | |
1369 | info.si_code = TARGET_ILL_ILLADR; | |
1370 | break; | |
1371 | case 0x08000000: | |
1372 | info.si_signo = TARGET_SIGSEGV; | |
1373 | info.si_errno = 0; | |
1374 | info.si_code = TARGET_SEGV_ACCERR; | |
1375 | break; | |
1376 | default: | |
1377 | /* Let's send a regular segfault... */ | |
1378 | EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", | |
1379 | env->error_code); | |
1380 | info.si_signo = TARGET_SIGSEGV; | |
1381 | info.si_errno = 0; | |
1382 | info.si_code = TARGET_SEGV_MAPERR; | |
1383 | break; | |
1384 | } | |
1385 | info._sifields._sigfault._addr = env->nip; | |
1386 | queue_signal(env, info.si_signo, &info); | |
1387 | break; | |
1388 | case POWERPC_EXCP_ISI: /* Instruction storage exception */ | |
1389 | EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx | |
1390 | "\n", env->spr[SPR_SRR0]); | |
1391 | /* XXX: check this */ | |
1392 | switch (env->error_code & 0xFF000000) { | |
1393 | case 0x40000000: | |
1394 | info.si_signo = TARGET_SIGSEGV; | |
1395 | info.si_errno = 0; | |
1396 | info.si_code = TARGET_SEGV_MAPERR; | |
1397 | break; | |
1398 | case 0x10000000: | |
1399 | case 0x08000000: | |
1400 | info.si_signo = TARGET_SIGSEGV; | |
1401 | info.si_errno = 0; | |
1402 | info.si_code = TARGET_SEGV_ACCERR; | |
1403 | break; | |
1404 | default: | |
1405 | /* Let's send a regular segfault... */ | |
1406 | EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", | |
1407 | env->error_code); | |
1408 | info.si_signo = TARGET_SIGSEGV; | |
1409 | info.si_errno = 0; | |
1410 | info.si_code = TARGET_SEGV_MAPERR; | |
1411 | break; | |
1412 | } | |
1413 | info._sifields._sigfault._addr = env->nip - 4; | |
1414 | queue_signal(env, info.si_signo, &info); | |
1415 | break; | |
1416 | case POWERPC_EXCP_EXTERNAL: /* External input */ | |
1417 | cpu_abort(env, "External interrupt while in user mode. " | |
1418 | "Aborting\n"); | |
1419 | break; | |
1420 | case POWERPC_EXCP_ALIGN: /* Alignment exception */ | |
1421 | EXCP_DUMP(env, "Unaligned memory access\n"); | |
1422 | /* XXX: check this */ | |
1423 | info.si_signo = TARGET_SIGBUS; | |
1424 | info.si_errno = 0; | |
1425 | info.si_code = TARGET_BUS_ADRALN; | |
1426 | info._sifields._sigfault._addr = env->nip - 4; | |
1427 | queue_signal(env, info.si_signo, &info); | |
1428 | break; | |
1429 | case POWERPC_EXCP_PROGRAM: /* Program exception */ | |
1430 | /* XXX: check this */ | |
1431 | switch (env->error_code & ~0xF) { | |
1432 | case POWERPC_EXCP_FP: | |
1433 | EXCP_DUMP(env, "Floating point program exception\n"); | |
1434 | info.si_signo = TARGET_SIGFPE; | |
1435 | info.si_errno = 0; | |
1436 | switch (env->error_code & 0xF) { | |
1437 | case POWERPC_EXCP_FP_OX: | |
1438 | info.si_code = TARGET_FPE_FLTOVF; | |
1439 | break; | |
1440 | case POWERPC_EXCP_FP_UX: | |
1441 | info.si_code = TARGET_FPE_FLTUND; | |
1442 | break; | |
1443 | case POWERPC_EXCP_FP_ZX: | |
1444 | case POWERPC_EXCP_FP_VXZDZ: | |
1445 | info.si_code = TARGET_FPE_FLTDIV; | |
1446 | break; | |
1447 | case POWERPC_EXCP_FP_XX: | |
1448 | info.si_code = TARGET_FPE_FLTRES; | |
1449 | break; | |
1450 | case POWERPC_EXCP_FP_VXSOFT: | |
1451 | info.si_code = TARGET_FPE_FLTINV; | |
1452 | break; | |
1453 | case POWERPC_EXCP_FP_VXSNAN: | |
1454 | case POWERPC_EXCP_FP_VXISI: | |
1455 | case POWERPC_EXCP_FP_VXIDI: | |
1456 | case POWERPC_EXCP_FP_VXIMZ: | |
1457 | case POWERPC_EXCP_FP_VXVC: | |
1458 | case POWERPC_EXCP_FP_VXSQRT: | |
1459 | case POWERPC_EXCP_FP_VXCVI: | |
1460 | info.si_code = TARGET_FPE_FLTSUB; | |
1461 | break; | |
1462 | default: | |
1463 | EXCP_DUMP(env, "Unknown floating point exception (%02x)\n", | |
1464 | env->error_code); | |
1465 | break; | |
1466 | } | |
1467 | break; | |
1468 | case POWERPC_EXCP_INVAL: | |
1469 | EXCP_DUMP(env, "Invalid instruction\n"); | |
1470 | info.si_signo = TARGET_SIGILL; | |
1471 | info.si_errno = 0; | |
1472 | switch (env->error_code & 0xF) { | |
1473 | case POWERPC_EXCP_INVAL_INVAL: | |
1474 | info.si_code = TARGET_ILL_ILLOPC; | |
1475 | break; | |
1476 | case POWERPC_EXCP_INVAL_LSWX: | |
1477 | info.si_code = TARGET_ILL_ILLOPN; | |
1478 | break; | |
1479 | case POWERPC_EXCP_INVAL_SPR: | |
1480 | info.si_code = TARGET_ILL_PRVREG; | |
1481 | break; | |
1482 | case POWERPC_EXCP_INVAL_FP: | |
1483 | info.si_code = TARGET_ILL_COPROC; | |
1484 | break; | |
1485 | default: | |
1486 | EXCP_DUMP(env, "Unknown invalid operation (%02x)\n", | |
1487 | env->error_code & 0xF); | |
1488 | info.si_code = TARGET_ILL_ILLADR; | |
1489 | break; | |
1490 | } | |
1491 | break; | |
1492 | case POWERPC_EXCP_PRIV: | |
1493 | EXCP_DUMP(env, "Privilege violation\n"); | |
1494 | info.si_signo = TARGET_SIGILL; | |
1495 | info.si_errno = 0; | |
1496 | switch (env->error_code & 0xF) { | |
1497 | case POWERPC_EXCP_PRIV_OPC: | |
1498 | info.si_code = TARGET_ILL_PRVOPC; | |
1499 | break; | |
1500 | case POWERPC_EXCP_PRIV_REG: | |
1501 | info.si_code = TARGET_ILL_PRVREG; | |
1502 | break; | |
1503 | default: | |
1504 | EXCP_DUMP(env, "Unknown privilege violation (%02x)\n", | |
1505 | env->error_code & 0xF); | |
1506 | info.si_code = TARGET_ILL_PRVOPC; | |
1507 | break; | |
1508 | } | |
1509 | break; | |
1510 | case POWERPC_EXCP_TRAP: | |
1511 | cpu_abort(env, "Tried to call a TRAP\n"); | |
1512 | break; | |
1513 | default: | |
1514 | /* Should not happen ! */ | |
1515 | cpu_abort(env, "Unknown program exception (%02x)\n", | |
1516 | env->error_code); | |
1517 | break; | |
1518 | } | |
1519 | info._sifields._sigfault._addr = env->nip - 4; | |
1520 | queue_signal(env, info.si_signo, &info); | |
1521 | break; | |
1522 | case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ | |
1523 | EXCP_DUMP(env, "No floating point allowed\n"); | |
1524 | info.si_signo = TARGET_SIGILL; | |
1525 | info.si_errno = 0; | |
1526 | info.si_code = TARGET_ILL_COPROC; | |
1527 | info._sifields._sigfault._addr = env->nip - 4; | |
1528 | queue_signal(env, info.si_signo, &info); | |
1529 | break; | |
1530 | case POWERPC_EXCP_SYSCALL: /* System call exception */ | |
1531 | cpu_abort(env, "Syscall exception while in user mode. " | |
1532 | "Aborting\n"); | |
1533 | break; | |
1534 | case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ | |
1535 | EXCP_DUMP(env, "No APU instruction allowed\n"); | |
1536 | info.si_signo = TARGET_SIGILL; | |
1537 | info.si_errno = 0; | |
1538 | info.si_code = TARGET_ILL_COPROC; | |
1539 | info._sifields._sigfault._addr = env->nip - 4; | |
1540 | queue_signal(env, info.si_signo, &info); | |
1541 | break; | |
1542 | case POWERPC_EXCP_DECR: /* Decrementer exception */ | |
1543 | cpu_abort(env, "Decrementer interrupt while in user mode. " | |
1544 | "Aborting\n"); | |
1545 | break; | |
1546 | case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ | |
1547 | cpu_abort(env, "Fix interval timer interrupt while in user mode. " | |
1548 | "Aborting\n"); | |
1549 | break; | |
1550 | case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ | |
1551 | cpu_abort(env, "Watchdog timer interrupt while in user mode. " | |
1552 | "Aborting\n"); | |
1553 | break; | |
1554 | case POWERPC_EXCP_DTLB: /* Data TLB error */ | |
1555 | cpu_abort(env, "Data TLB exception while in user mode. " | |
1556 | "Aborting\n"); | |
1557 | break; | |
1558 | case POWERPC_EXCP_ITLB: /* Instruction TLB error */ | |
1559 | cpu_abort(env, "Instruction TLB exception while in user mode. " | |
1560 | "Aborting\n"); | |
1561 | break; | |
1562 | case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ | |
1563 | EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n"); | |
1564 | info.si_signo = TARGET_SIGILL; | |
1565 | info.si_errno = 0; | |
1566 | info.si_code = TARGET_ILL_COPROC; | |
1567 | info._sifields._sigfault._addr = env->nip - 4; | |
1568 | queue_signal(env, info.si_signo, &info); | |
1569 | break; | |
1570 | case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ | |
1571 | cpu_abort(env, "Embedded floating-point data IRQ not handled\n"); | |
1572 | break; | |
1573 | case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ | |
1574 | cpu_abort(env, "Embedded floating-point round IRQ not handled\n"); | |
1575 | break; | |
1576 | case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ | |
1577 | cpu_abort(env, "Performance monitor exception not handled\n"); | |
1578 | break; | |
1579 | case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ | |
1580 | cpu_abort(env, "Doorbell interrupt while in user mode. " | |
1581 | "Aborting\n"); | |
1582 | break; | |
1583 | case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ | |
1584 | cpu_abort(env, "Doorbell critical interrupt while in user mode. " | |
1585 | "Aborting\n"); | |
1586 | break; | |
1587 | case POWERPC_EXCP_RESET: /* System reset exception */ | |
1588 | cpu_abort(env, "Reset interrupt while in user mode. " | |
1589 | "Aborting\n"); | |
1590 | break; | |
1591 | case POWERPC_EXCP_DSEG: /* Data segment exception */ | |
1592 | cpu_abort(env, "Data segment exception while in user mode. " | |
1593 | "Aborting\n"); | |
1594 | break; | |
1595 | case POWERPC_EXCP_ISEG: /* Instruction segment exception */ | |
1596 | cpu_abort(env, "Instruction segment exception " | |
1597 | "while in user mode. Aborting\n"); | |
1598 | break; | |
1599 | /* PowerPC 64 with hypervisor mode support */ | |
1600 | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ | |
1601 | cpu_abort(env, "Hypervisor decrementer interrupt " | |
1602 | "while in user mode. Aborting\n"); | |
1603 | break; | |
1604 | case POWERPC_EXCP_TRACE: /* Trace exception */ | |
1605 | /* Nothing to do: | |
1606 | * we use this exception to emulate step-by-step execution mode. | |
1607 | */ | |
1608 | break; | |
1609 | /* PowerPC 64 with hypervisor mode support */ | |
1610 | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ | |
1611 | cpu_abort(env, "Hypervisor data storage exception " | |
1612 | "while in user mode. Aborting\n"); | |
1613 | break; | |
1614 | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ | |
1615 | cpu_abort(env, "Hypervisor instruction storage exception " | |
1616 | "while in user mode. Aborting\n"); | |
1617 | break; | |
1618 | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ | |
1619 | cpu_abort(env, "Hypervisor data segment exception " | |
1620 | "while in user mode. Aborting\n"); | |
1621 | break; | |
1622 | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ | |
1623 | cpu_abort(env, "Hypervisor instruction segment exception " | |
1624 | "while in user mode. Aborting\n"); | |
1625 | break; | |
1626 | case POWERPC_EXCP_VPU: /* Vector unavailable exception */ | |
1627 | EXCP_DUMP(env, "No Altivec instructions allowed\n"); | |
1628 | info.si_signo = TARGET_SIGILL; | |
1629 | info.si_errno = 0; | |
1630 | info.si_code = TARGET_ILL_COPROC; | |
1631 | info._sifields._sigfault._addr = env->nip - 4; | |
1632 | queue_signal(env, info.si_signo, &info); | |
1633 | break; | |
1634 | case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ | |
1635 | cpu_abort(env, "Programmable interval timer interrupt " | |
1636 | "while in user mode. Aborting\n"); | |
1637 | break; | |
1638 | case POWERPC_EXCP_IO: /* IO error exception */ | |
1639 | cpu_abort(env, "IO error exception while in user mode. " | |
1640 | "Aborting\n"); | |
1641 | break; | |
1642 | case POWERPC_EXCP_RUNM: /* Run mode exception */ | |
1643 | cpu_abort(env, "Run mode exception while in user mode. " | |
1644 | "Aborting\n"); | |
1645 | break; | |
1646 | case POWERPC_EXCP_EMUL: /* Emulation trap exception */ | |
1647 | cpu_abort(env, "Emulation trap exception not handled\n"); | |
1648 | break; | |
1649 | case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ | |
1650 | cpu_abort(env, "Instruction fetch TLB exception " | |
1651 | "while in user-mode. Aborting"); | |
1652 | break; | |
1653 | case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ | |
1654 | cpu_abort(env, "Data load TLB exception while in user-mode. " | |
1655 | "Aborting"); | |
1656 | break; | |
1657 | case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ | |
1658 | cpu_abort(env, "Data store TLB exception while in user-mode. " | |
1659 | "Aborting"); | |
1660 | break; | |
1661 | case POWERPC_EXCP_FPA: /* Floating-point assist exception */ | |
1662 | cpu_abort(env, "Floating-point assist exception not handled\n"); | |
1663 | break; | |
1664 | case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ | |
1665 | cpu_abort(env, "Instruction address breakpoint exception " | |
1666 | "not handled\n"); | |
1667 | break; | |
1668 | case POWERPC_EXCP_SMI: /* System management interrupt */ | |
1669 | cpu_abort(env, "System management interrupt while in user mode. " | |
1670 | "Aborting\n"); | |
1671 | break; | |
1672 | case POWERPC_EXCP_THERM: /* Thermal interrupt */ | |
1673 | cpu_abort(env, "Thermal interrupt interrupt while in user mode. " | |
1674 | "Aborting\n"); | |
1675 | break; | |
1676 | case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ | |
1677 | cpu_abort(env, "Performance monitor exception not handled\n"); | |
1678 | break; | |
1679 | case POWERPC_EXCP_VPUA: /* Vector assist exception */ | |
1680 | cpu_abort(env, "Vector assist exception not handled\n"); | |
1681 | break; | |
1682 | case POWERPC_EXCP_SOFTP: /* Soft patch exception */ | |
1683 | cpu_abort(env, "Soft patch exception not handled\n"); | |
1684 | break; | |
1685 | case POWERPC_EXCP_MAINT: /* Maintenance exception */ | |
1686 | cpu_abort(env, "Maintenance exception while in user mode. " | |
1687 | "Aborting\n"); | |
1688 | break; | |
1689 | case POWERPC_EXCP_STOP: /* stop translation */ | |
1690 | /* We did invalidate the instruction cache. Go on */ | |
1691 | break; | |
1692 | case POWERPC_EXCP_BRANCH: /* branch instruction: */ | |
1693 | /* We just stopped because of a branch. Go on */ | |
1694 | break; | |
1695 | case POWERPC_EXCP_SYSCALL_USER: | |
1696 | /* system call in user-mode emulation */ | |
1697 | /* WARNING: | |
1698 | * PPC ABI uses overflow flag in cr0 to signal an error | |
1699 | * in syscalls. | |
1700 | */ | |
1701 | env->crf[0] &= ~0x1; | |
1702 | ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], | |
1703 | env->gpr[5], env->gpr[6], env->gpr[7], | |
1704 | env->gpr[8], 0, 0); | |
1705 | if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) { | |
1706 | /* Returning from a successful sigreturn syscall. | |
1707 | Avoid corrupting register state. */ | |
1708 | break; | |
1709 | } | |
1710 | if (ret > (target_ulong)(-515)) { | |
1711 | env->crf[0] |= 0x1; | |
1712 | ret = -ret; | |
1713 | } | |
1714 | env->gpr[3] = ret; | |
1715 | break; | |
1716 | case POWERPC_EXCP_STCX: | |
1717 | if (do_store_exclusive(env)) { | |
1718 | info.si_signo = TARGET_SIGSEGV; | |
1719 | info.si_errno = 0; | |
1720 | info.si_code = TARGET_SEGV_MAPERR; | |
1721 | info._sifields._sigfault._addr = env->nip; | |
1722 | queue_signal(env, info.si_signo, &info); | |
1723 | } | |
1724 | break; | |
1725 | case EXCP_DEBUG: | |
1726 | { | |
1727 | int sig; | |
1728 | ||
1729 | sig = gdb_handlesig(env, TARGET_SIGTRAP); | |
1730 | if (sig) { | |
1731 | info.si_signo = sig; | |
1732 | info.si_errno = 0; | |
1733 | info.si_code = TARGET_TRAP_BRKPT; | |
1734 | queue_signal(env, info.si_signo, &info); | |
1735 | } | |
1736 | } | |
1737 | break; | |
1738 | case EXCP_INTERRUPT: | |
1739 | /* just indicate that signals should be handled asap */ | |
1740 | break; | |
1741 | default: | |
1742 | cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr); | |
1743 | break; | |
1744 | } | |
1745 | process_pending_signals(env); | |
1746 | } | |
1747 | } | |
1748 | #endif | |
1749 | ||
1750 | #ifdef TARGET_MIPS | |
1751 | ||
1752 | # ifdef TARGET_ABI_MIPSO32 | |
1753 | # define MIPS_SYS(name, args) args, | |
1754 | static const uint8_t mips_syscall_args[] = { | |
1755 | MIPS_SYS(sys_syscall , 8) /* 4000 */ | |
1756 | MIPS_SYS(sys_exit , 1) | |
1757 | MIPS_SYS(sys_fork , 0) | |
1758 | MIPS_SYS(sys_read , 3) | |
1759 | MIPS_SYS(sys_write , 3) | |
1760 | MIPS_SYS(sys_open , 3) /* 4005 */ | |
1761 | MIPS_SYS(sys_close , 1) | |
1762 | MIPS_SYS(sys_waitpid , 3) | |
1763 | MIPS_SYS(sys_creat , 2) | |
1764 | MIPS_SYS(sys_link , 2) | |
1765 | MIPS_SYS(sys_unlink , 1) /* 4010 */ | |
1766 | MIPS_SYS(sys_execve , 0) | |
1767 | MIPS_SYS(sys_chdir , 1) | |
1768 | MIPS_SYS(sys_time , 1) | |
1769 | MIPS_SYS(sys_mknod , 3) | |
1770 | MIPS_SYS(sys_chmod , 2) /* 4015 */ | |
1771 | MIPS_SYS(sys_lchown , 3) | |
1772 | MIPS_SYS(sys_ni_syscall , 0) | |
1773 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */ | |
1774 | MIPS_SYS(sys_lseek , 3) | |
1775 | MIPS_SYS(sys_getpid , 0) /* 4020 */ | |
1776 | MIPS_SYS(sys_mount , 5) | |
1777 | MIPS_SYS(sys_oldumount , 1) | |
1778 | MIPS_SYS(sys_setuid , 1) | |
1779 | MIPS_SYS(sys_getuid , 0) | |
1780 | MIPS_SYS(sys_stime , 1) /* 4025 */ | |
1781 | MIPS_SYS(sys_ptrace , 4) | |
1782 | MIPS_SYS(sys_alarm , 1) | |
1783 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */ | |
1784 | MIPS_SYS(sys_pause , 0) | |
1785 | MIPS_SYS(sys_utime , 2) /* 4030 */ | |
1786 | MIPS_SYS(sys_ni_syscall , 0) | |
1787 | MIPS_SYS(sys_ni_syscall , 0) | |
1788 | MIPS_SYS(sys_access , 2) | |
1789 | MIPS_SYS(sys_nice , 1) | |
1790 | MIPS_SYS(sys_ni_syscall , 0) /* 4035 */ | |
1791 | MIPS_SYS(sys_sync , 0) | |
1792 | MIPS_SYS(sys_kill , 2) | |
1793 | MIPS_SYS(sys_rename , 2) | |
1794 | MIPS_SYS(sys_mkdir , 2) | |
1795 | MIPS_SYS(sys_rmdir , 1) /* 4040 */ | |
1796 | MIPS_SYS(sys_dup , 1) | |
1797 | MIPS_SYS(sys_pipe , 0) | |
1798 | MIPS_SYS(sys_times , 1) | |
1799 | MIPS_SYS(sys_ni_syscall , 0) | |
1800 | MIPS_SYS(sys_brk , 1) /* 4045 */ | |
1801 | MIPS_SYS(sys_setgid , 1) | |
1802 | MIPS_SYS(sys_getgid , 0) | |
1803 | MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */ | |
1804 | MIPS_SYS(sys_geteuid , 0) | |
1805 | MIPS_SYS(sys_getegid , 0) /* 4050 */ | |
1806 | MIPS_SYS(sys_acct , 0) | |
1807 | MIPS_SYS(sys_umount , 2) | |
1808 | MIPS_SYS(sys_ni_syscall , 0) | |
1809 | MIPS_SYS(sys_ioctl , 3) | |
1810 | MIPS_SYS(sys_fcntl , 3) /* 4055 */ | |
1811 | MIPS_SYS(sys_ni_syscall , 2) | |
1812 | MIPS_SYS(sys_setpgid , 2) | |
1813 | MIPS_SYS(sys_ni_syscall , 0) | |
1814 | MIPS_SYS(sys_olduname , 1) | |
1815 | MIPS_SYS(sys_umask , 1) /* 4060 */ | |
1816 | MIPS_SYS(sys_chroot , 1) | |
1817 | MIPS_SYS(sys_ustat , 2) | |
1818 | MIPS_SYS(sys_dup2 , 2) | |
1819 | MIPS_SYS(sys_getppid , 0) | |
1820 | MIPS_SYS(sys_getpgrp , 0) /* 4065 */ | |
1821 | MIPS_SYS(sys_setsid , 0) | |
1822 | MIPS_SYS(sys_sigaction , 3) | |
1823 | MIPS_SYS(sys_sgetmask , 0) | |
1824 | MIPS_SYS(sys_ssetmask , 1) | |
1825 | MIPS_SYS(sys_setreuid , 2) /* 4070 */ | |
1826 | MIPS_SYS(sys_setregid , 2) | |
1827 | MIPS_SYS(sys_sigsuspend , 0) | |
1828 | MIPS_SYS(sys_sigpending , 1) | |
1829 | MIPS_SYS(sys_sethostname , 2) | |
1830 | MIPS_SYS(sys_setrlimit , 2) /* 4075 */ | |
1831 | MIPS_SYS(sys_getrlimit , 2) | |
1832 | MIPS_SYS(sys_getrusage , 2) | |
1833 | MIPS_SYS(sys_gettimeofday, 2) | |
1834 | MIPS_SYS(sys_settimeofday, 2) | |
1835 | MIPS_SYS(sys_getgroups , 2) /* 4080 */ | |
1836 | MIPS_SYS(sys_setgroups , 2) | |
1837 | MIPS_SYS(sys_ni_syscall , 0) /* old_select */ | |
1838 | MIPS_SYS(sys_symlink , 2) | |
1839 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */ | |
1840 | MIPS_SYS(sys_readlink , 3) /* 4085 */ | |
1841 | MIPS_SYS(sys_uselib , 1) | |
1842 | MIPS_SYS(sys_swapon , 2) | |
1843 | MIPS_SYS(sys_reboot , 3) | |
1844 | MIPS_SYS(old_readdir , 3) | |
1845 | MIPS_SYS(old_mmap , 6) /* 4090 */ | |
1846 | MIPS_SYS(sys_munmap , 2) | |
1847 | MIPS_SYS(sys_truncate , 2) | |
1848 | MIPS_SYS(sys_ftruncate , 2) | |
1849 | MIPS_SYS(sys_fchmod , 2) | |
1850 | MIPS_SYS(sys_fchown , 3) /* 4095 */ | |
1851 | MIPS_SYS(sys_getpriority , 2) | |
1852 | MIPS_SYS(sys_setpriority , 3) | |
1853 | MIPS_SYS(sys_ni_syscall , 0) | |
1854 | MIPS_SYS(sys_statfs , 2) | |
1855 | MIPS_SYS(sys_fstatfs , 2) /* 4100 */ | |
1856 | MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */ | |
1857 | MIPS_SYS(sys_socketcall , 2) | |
1858 | MIPS_SYS(sys_syslog , 3) | |
1859 | MIPS_SYS(sys_setitimer , 3) | |
1860 | MIPS_SYS(sys_getitimer , 2) /* 4105 */ | |
1861 | MIPS_SYS(sys_newstat , 2) | |
1862 | MIPS_SYS(sys_newlstat , 2) | |
1863 | MIPS_SYS(sys_newfstat , 2) | |
1864 | MIPS_SYS(sys_uname , 1) | |
1865 | MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */ | |
1866 | MIPS_SYS(sys_vhangup , 0) | |
1867 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */ | |
1868 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */ | |
1869 | MIPS_SYS(sys_wait4 , 4) | |
1870 | MIPS_SYS(sys_swapoff , 1) /* 4115 */ | |
1871 | MIPS_SYS(sys_sysinfo , 1) | |
1872 | MIPS_SYS(sys_ipc , 6) | |
1873 | MIPS_SYS(sys_fsync , 1) | |
1874 | MIPS_SYS(sys_sigreturn , 0) | |
1875 | MIPS_SYS(sys_clone , 6) /* 4120 */ | |
1876 | MIPS_SYS(sys_setdomainname, 2) | |
1877 | MIPS_SYS(sys_newuname , 1) | |
1878 | MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */ | |
1879 | MIPS_SYS(sys_adjtimex , 1) | |
1880 | MIPS_SYS(sys_mprotect , 3) /* 4125 */ | |
1881 | MIPS_SYS(sys_sigprocmask , 3) | |
1882 | MIPS_SYS(sys_ni_syscall , 0) /* was create_module */ | |
1883 | MIPS_SYS(sys_init_module , 5) | |
1884 | MIPS_SYS(sys_delete_module, 1) | |
1885 | MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */ | |
1886 | MIPS_SYS(sys_quotactl , 0) | |
1887 | MIPS_SYS(sys_getpgid , 1) | |
1888 | MIPS_SYS(sys_fchdir , 1) | |
1889 | MIPS_SYS(sys_bdflush , 2) | |
1890 | MIPS_SYS(sys_sysfs , 3) /* 4135 */ | |
1891 | MIPS_SYS(sys_personality , 1) | |
1892 | MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */ | |
1893 | MIPS_SYS(sys_setfsuid , 1) | |
1894 | MIPS_SYS(sys_setfsgid , 1) | |
1895 | MIPS_SYS(sys_llseek , 5) /* 4140 */ | |
1896 | MIPS_SYS(sys_getdents , 3) | |
1897 | MIPS_SYS(sys_select , 5) | |
1898 | MIPS_SYS(sys_flock , 2) | |
1899 | MIPS_SYS(sys_msync , 3) | |
1900 | MIPS_SYS(sys_readv , 3) /* 4145 */ | |
1901 | MIPS_SYS(sys_writev , 3) | |
1902 | MIPS_SYS(sys_cacheflush , 3) | |
1903 | MIPS_SYS(sys_cachectl , 3) | |
1904 | MIPS_SYS(sys_sysmips , 4) | |
1905 | MIPS_SYS(sys_ni_syscall , 0) /* 4150 */ | |
1906 | MIPS_SYS(sys_getsid , 1) | |
1907 | MIPS_SYS(sys_fdatasync , 0) | |
1908 | MIPS_SYS(sys_sysctl , 1) | |
1909 | MIPS_SYS(sys_mlock , 2) | |
1910 | MIPS_SYS(sys_munlock , 2) /* 4155 */ | |
1911 | MIPS_SYS(sys_mlockall , 1) | |
1912 | MIPS_SYS(sys_munlockall , 0) | |
1913 | MIPS_SYS(sys_sched_setparam, 2) | |
1914 | MIPS_SYS(sys_sched_getparam, 2) | |
1915 | MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */ | |
1916 | MIPS_SYS(sys_sched_getscheduler, 1) | |
1917 | MIPS_SYS(sys_sched_yield , 0) | |
1918 | MIPS_SYS(sys_sched_get_priority_max, 1) | |
1919 | MIPS_SYS(sys_sched_get_priority_min, 1) | |
1920 | MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ | |
1921 | MIPS_SYS(sys_nanosleep, 2) | |
1922 | MIPS_SYS(sys_mremap , 4) | |
1923 | MIPS_SYS(sys_accept , 3) | |
1924 | MIPS_SYS(sys_bind , 3) | |
1925 | MIPS_SYS(sys_connect , 3) /* 4170 */ | |
1926 | MIPS_SYS(sys_getpeername , 3) | |
1927 | MIPS_SYS(sys_getsockname , 3) | |
1928 | MIPS_SYS(sys_getsockopt , 5) | |
1929 | MIPS_SYS(sys_listen , 2) | |
1930 | MIPS_SYS(sys_recv , 4) /* 4175 */ | |
1931 | MIPS_SYS(sys_recvfrom , 6) | |
1932 | MIPS_SYS(sys_recvmsg , 3) | |
1933 | MIPS_SYS(sys_send , 4) | |
1934 | MIPS_SYS(sys_sendmsg , 3) | |
1935 | MIPS_SYS(sys_sendto , 6) /* 4180 */ | |
1936 | MIPS_SYS(sys_setsockopt , 5) | |
1937 | MIPS_SYS(sys_shutdown , 2) | |
1938 | MIPS_SYS(sys_socket , 3) | |
1939 | MIPS_SYS(sys_socketpair , 4) | |
1940 | MIPS_SYS(sys_setresuid , 3) /* 4185 */ | |
1941 | MIPS_SYS(sys_getresuid , 3) | |
1942 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */ | |
1943 | MIPS_SYS(sys_poll , 3) | |
1944 | MIPS_SYS(sys_nfsservctl , 3) | |
1945 | MIPS_SYS(sys_setresgid , 3) /* 4190 */ | |
1946 | MIPS_SYS(sys_getresgid , 3) | |
1947 | MIPS_SYS(sys_prctl , 5) | |
1948 | MIPS_SYS(sys_rt_sigreturn, 0) | |
1949 | MIPS_SYS(sys_rt_sigaction, 4) | |
1950 | MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */ | |
1951 | MIPS_SYS(sys_rt_sigpending, 2) | |
1952 | MIPS_SYS(sys_rt_sigtimedwait, 4) | |
1953 | MIPS_SYS(sys_rt_sigqueueinfo, 3) | |
1954 | MIPS_SYS(sys_rt_sigsuspend, 0) | |
1955 | MIPS_SYS(sys_pread64 , 6) /* 4200 */ | |
1956 | MIPS_SYS(sys_pwrite64 , 6) | |
1957 | MIPS_SYS(sys_chown , 3) | |
1958 | MIPS_SYS(sys_getcwd , 2) | |
1959 | MIPS_SYS(sys_capget , 2) | |
1960 | MIPS_SYS(sys_capset , 2) /* 4205 */ | |
1961 | MIPS_SYS(sys_sigaltstack , 2) | |
1962 | MIPS_SYS(sys_sendfile , 4) | |
1963 | MIPS_SYS(sys_ni_syscall , 0) | |
1964 | MIPS_SYS(sys_ni_syscall , 0) | |
1965 | MIPS_SYS(sys_mmap2 , 6) /* 4210 */ | |
1966 | MIPS_SYS(sys_truncate64 , 4) | |
1967 | MIPS_SYS(sys_ftruncate64 , 4) | |
1968 | MIPS_SYS(sys_stat64 , 2) | |
1969 | MIPS_SYS(sys_lstat64 , 2) | |
1970 | MIPS_SYS(sys_fstat64 , 2) /* 4215 */ | |
1971 | MIPS_SYS(sys_pivot_root , 2) | |
1972 | MIPS_SYS(sys_mincore , 3) | |
1973 | MIPS_SYS(sys_madvise , 3) | |
1974 | MIPS_SYS(sys_getdents64 , 3) | |
1975 | MIPS_SYS(sys_fcntl64 , 3) /* 4220 */ | |
1976 | MIPS_SYS(sys_ni_syscall , 0) | |
1977 | MIPS_SYS(sys_gettid , 0) | |
1978 | MIPS_SYS(sys_readahead , 5) | |
1979 | MIPS_SYS(sys_setxattr , 5) | |
1980 | MIPS_SYS(sys_lsetxattr , 5) /* 4225 */ | |
1981 | MIPS_SYS(sys_fsetxattr , 5) | |
1982 | MIPS_SYS(sys_getxattr , 4) | |
1983 | MIPS_SYS(sys_lgetxattr , 4) | |
1984 | MIPS_SYS(sys_fgetxattr , 4) | |
1985 | MIPS_SYS(sys_listxattr , 3) /* 4230 */ | |
1986 | MIPS_SYS(sys_llistxattr , 3) | |
1987 | MIPS_SYS(sys_flistxattr , 3) | |
1988 | MIPS_SYS(sys_removexattr , 2) | |
1989 | MIPS_SYS(sys_lremovexattr, 2) | |
1990 | MIPS_SYS(sys_fremovexattr, 2) /* 4235 */ | |
1991 | MIPS_SYS(sys_tkill , 2) | |
1992 | MIPS_SYS(sys_sendfile64 , 5) | |
1993 | MIPS_SYS(sys_futex , 6) | |
1994 | MIPS_SYS(sys_sched_setaffinity, 3) | |
1995 | MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */ | |
1996 | MIPS_SYS(sys_io_setup , 2) | |
1997 | MIPS_SYS(sys_io_destroy , 1) | |
1998 | MIPS_SYS(sys_io_getevents, 5) | |
1999 | MIPS_SYS(sys_io_submit , 3) | |
2000 | MIPS_SYS(sys_io_cancel , 3) /* 4245 */ | |
2001 | MIPS_SYS(sys_exit_group , 1) | |
2002 | MIPS_SYS(sys_lookup_dcookie, 3) | |
2003 | MIPS_SYS(sys_epoll_create, 1) | |
2004 | MIPS_SYS(sys_epoll_ctl , 4) | |
2005 | MIPS_SYS(sys_epoll_wait , 3) /* 4250 */ | |
2006 | MIPS_SYS(sys_remap_file_pages, 5) | |
2007 | MIPS_SYS(sys_set_tid_address, 1) | |
2008 | MIPS_SYS(sys_restart_syscall, 0) | |
2009 | MIPS_SYS(sys_fadvise64_64, 7) | |
2010 | MIPS_SYS(sys_statfs64 , 3) /* 4255 */ | |
2011 | MIPS_SYS(sys_fstatfs64 , 2) | |
2012 | MIPS_SYS(sys_timer_create, 3) | |
2013 | MIPS_SYS(sys_timer_settime, 4) | |
2014 | MIPS_SYS(sys_timer_gettime, 2) | |
2015 | MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */ | |
2016 | MIPS_SYS(sys_timer_delete, 1) | |
2017 | MIPS_SYS(sys_clock_settime, 2) | |
2018 | MIPS_SYS(sys_clock_gettime, 2) | |
2019 | MIPS_SYS(sys_clock_getres, 2) | |
2020 | MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */ | |
2021 | MIPS_SYS(sys_tgkill , 3) | |
2022 | MIPS_SYS(sys_utimes , 2) | |
2023 | MIPS_SYS(sys_mbind , 4) | |
2024 | MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */ | |
2025 | MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */ | |
2026 | MIPS_SYS(sys_mq_open , 4) | |
2027 | MIPS_SYS(sys_mq_unlink , 1) | |
2028 | MIPS_SYS(sys_mq_timedsend, 5) | |
2029 | MIPS_SYS(sys_mq_timedreceive, 5) | |
2030 | MIPS_SYS(sys_mq_notify , 2) /* 4275 */ | |
2031 | MIPS_SYS(sys_mq_getsetattr, 3) | |
2032 | MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */ | |
2033 | MIPS_SYS(sys_waitid , 4) | |
2034 | MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */ | |
2035 | MIPS_SYS(sys_add_key , 5) | |
2036 | MIPS_SYS(sys_request_key, 4) | |
2037 | MIPS_SYS(sys_keyctl , 5) | |
2038 | MIPS_SYS(sys_set_thread_area, 1) | |
2039 | MIPS_SYS(sys_inotify_init, 0) | |
2040 | MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */ | |
2041 | MIPS_SYS(sys_inotify_rm_watch, 2) | |
2042 | MIPS_SYS(sys_migrate_pages, 4) | |
2043 | MIPS_SYS(sys_openat, 4) | |
2044 | MIPS_SYS(sys_mkdirat, 3) | |
2045 | MIPS_SYS(sys_mknodat, 4) /* 4290 */ | |
2046 | MIPS_SYS(sys_fchownat, 5) | |
2047 | MIPS_SYS(sys_futimesat, 3) | |
2048 | MIPS_SYS(sys_fstatat64, 4) | |
2049 | MIPS_SYS(sys_unlinkat, 3) | |
2050 | MIPS_SYS(sys_renameat, 4) /* 4295 */ | |
2051 | MIPS_SYS(sys_linkat, 5) | |
2052 | MIPS_SYS(sys_symlinkat, 3) | |
2053 | MIPS_SYS(sys_readlinkat, 4) | |
2054 | MIPS_SYS(sys_fchmodat, 3) | |
2055 | MIPS_SYS(sys_faccessat, 3) /* 4300 */ | |
2056 | MIPS_SYS(sys_pselect6, 6) | |
2057 | MIPS_SYS(sys_ppoll, 5) | |
2058 | MIPS_SYS(sys_unshare, 1) | |
2059 | MIPS_SYS(sys_splice, 4) | |
2060 | MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ | |
2061 | MIPS_SYS(sys_tee, 4) | |
2062 | MIPS_SYS(sys_vmsplice, 4) | |
2063 | MIPS_SYS(sys_move_pages, 6) | |
2064 | MIPS_SYS(sys_set_robust_list, 2) | |
2065 | MIPS_SYS(sys_get_robust_list, 3) /* 4310 */ | |
2066 | MIPS_SYS(sys_kexec_load, 4) | |
2067 | MIPS_SYS(sys_getcpu, 3) | |
2068 | MIPS_SYS(sys_epoll_pwait, 6) | |
2069 | MIPS_SYS(sys_ioprio_set, 3) | |
2070 | MIPS_SYS(sys_ioprio_get, 2) | |
2071 | MIPS_SYS(sys_utimensat, 4) | |
2072 | MIPS_SYS(sys_signalfd, 3) | |
2073 | MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */ | |
2074 | MIPS_SYS(sys_eventfd, 1) | |
2075 | MIPS_SYS(sys_fallocate, 6) /* 4320 */ | |
2076 | MIPS_SYS(sys_timerfd_create, 2) | |
2077 | MIPS_SYS(sys_timerfd_gettime, 2) | |
2078 | MIPS_SYS(sys_timerfd_settime, 4) | |
2079 | MIPS_SYS(sys_signalfd4, 4) | |
2080 | MIPS_SYS(sys_eventfd2, 2) /* 4325 */ | |
2081 | MIPS_SYS(sys_epoll_create1, 1) | |
2082 | MIPS_SYS(sys_dup3, 3) | |
2083 | MIPS_SYS(sys_pipe2, 2) | |
2084 | MIPS_SYS(sys_inotify_init1, 1) | |
2085 | MIPS_SYS(sys_preadv, 6) /* 4330 */ | |
2086 | MIPS_SYS(sys_pwritev, 6) | |
2087 | MIPS_SYS(sys_rt_tgsigqueueinfo, 4) | |
2088 | MIPS_SYS(sys_perf_event_open, 5) | |
2089 | MIPS_SYS(sys_accept4, 4) | |
2090 | MIPS_SYS(sys_recvmmsg, 5) /* 4335 */ | |
2091 | MIPS_SYS(sys_fanotify_init, 2) | |
2092 | MIPS_SYS(sys_fanotify_mark, 6) | |
2093 | MIPS_SYS(sys_prlimit64, 4) | |
2094 | MIPS_SYS(sys_name_to_handle_at, 5) | |
2095 | MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */ | |
2096 | MIPS_SYS(sys_clock_adjtime, 2) | |
2097 | MIPS_SYS(sys_syncfs, 1) | |
2098 | }; | |
2099 | # undef MIPS_SYS | |
2100 | # endif /* O32 */ | |
2101 | ||
2102 | static int do_store_exclusive(CPUMIPSState *env) | |
2103 | { | |
2104 | target_ulong addr; | |
2105 | target_ulong page_addr; | |
2106 | target_ulong val; | |
2107 | int flags; | |
2108 | int segv = 0; | |
2109 | int reg; | |
2110 | int d; | |
2111 | ||
2112 | addr = env->lladdr; | |
2113 | page_addr = addr & TARGET_PAGE_MASK; | |
2114 | start_exclusive(); | |
2115 | mmap_lock(); | |
2116 | flags = page_get_flags(page_addr); | |
2117 | if ((flags & PAGE_READ) == 0) { | |
2118 | segv = 1; | |
2119 | } else { | |
2120 | reg = env->llreg & 0x1f; | |
2121 | d = (env->llreg & 0x20) != 0; | |
2122 | if (d) { | |
2123 | segv = get_user_s64(val, addr); | |
2124 | } else { | |
2125 | segv = get_user_s32(val, addr); | |
2126 | } | |
2127 | if (!segv) { | |
2128 | if (val != env->llval) { | |
2129 | env->active_tc.gpr[reg] = 0; | |
2130 | } else { | |
2131 | if (d) { | |
2132 | segv = put_user_u64(env->llnewval, addr); | |
2133 | } else { | |
2134 | segv = put_user_u32(env->llnewval, addr); | |
2135 | } | |
2136 | if (!segv) { | |
2137 | env->active_tc.gpr[reg] = 1; | |
2138 | } | |
2139 | } | |
2140 | } | |
2141 | } | |
2142 | env->lladdr = -1; | |
2143 | if (!segv) { | |
2144 | env->active_tc.PC += 4; | |
2145 | } | |
2146 | mmap_unlock(); | |
2147 | end_exclusive(); | |
2148 | return segv; | |
2149 | } | |
2150 | ||
2151 | /* Break codes */ | |
2152 | enum { | |
2153 | BRK_OVERFLOW = 6, | |
2154 | BRK_DIVZERO = 7 | |
2155 | }; | |
2156 | ||
2157 | static int do_break(CPUMIPSState *env, target_siginfo_t *info, | |
2158 | unsigned int code) | |
2159 | { | |
2160 | int ret = -1; | |
2161 | ||
2162 | switch (code) { | |
2163 | case BRK_OVERFLOW: | |
2164 | case BRK_DIVZERO: | |
2165 | info->si_signo = TARGET_SIGFPE; | |
2166 | info->si_errno = 0; | |
2167 | info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV; | |
2168 | queue_signal(env, info->si_signo, &*info); | |
2169 | ret = 0; | |
2170 | break; | |
2171 | default: | |
2172 | break; | |
2173 | } | |
2174 | ||
2175 | return ret; | |
2176 | } | |
2177 | ||
2178 | void cpu_loop(CPUMIPSState *env) | |
2179 | { | |
2180 | CPUState *cs = CPU(mips_env_get_cpu(env)); | |
2181 | target_siginfo_t info; | |
2182 | int trapnr; | |
2183 | abi_long ret; | |
2184 | # ifdef TARGET_ABI_MIPSO32 | |
2185 | unsigned int syscall_num; | |
2186 | # endif | |
2187 | ||
2188 | for(;;) { | |
2189 | cpu_exec_start(cs); | |
2190 | trapnr = cpu_mips_exec(env); | |
2191 | cpu_exec_end(cs); | |
2192 | switch(trapnr) { | |
2193 | case EXCP_SYSCALL: | |
2194 | env->active_tc.PC += 4; | |
2195 | # ifdef TARGET_ABI_MIPSO32 | |
2196 | syscall_num = env->active_tc.gpr[2] - 4000; | |
2197 | if (syscall_num >= sizeof(mips_syscall_args)) { | |
2198 | ret = -TARGET_ENOSYS; | |
2199 | } else { | |
2200 | int nb_args; | |
2201 | abi_ulong sp_reg; | |
2202 | abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; | |
2203 | ||
2204 | nb_args = mips_syscall_args[syscall_num]; | |
2205 | sp_reg = env->active_tc.gpr[29]; | |
2206 | switch (nb_args) { | |
2207 | /* these arguments are taken from the stack */ | |
2208 | case 8: | |
2209 | if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) { | |
2210 | goto done_syscall; | |
2211 | } | |
2212 | case 7: | |
2213 | if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) { | |
2214 | goto done_syscall; | |
2215 | } | |
2216 | case 6: | |
2217 | if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) { | |
2218 | goto done_syscall; | |
2219 | } | |
2220 | case 5: | |
2221 | if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) { | |
2222 | goto done_syscall; | |
2223 | } | |
2224 | default: | |
2225 | break; | |
2226 | } | |
2227 | ret = do_syscall(env, env->active_tc.gpr[2], | |
2228 | env->active_tc.gpr[4], | |
2229 | env->active_tc.gpr[5], | |
2230 | env->active_tc.gpr[6], | |
2231 | env->active_tc.gpr[7], | |
2232 | arg5, arg6, arg7, arg8); | |
2233 | } | |
2234 | done_syscall: | |
2235 | # else | |
2236 | ret = do_syscall(env, env->active_tc.gpr[2], | |
2237 | env->active_tc.gpr[4], env->active_tc.gpr[5], | |
2238 | env->active_tc.gpr[6], env->active_tc.gpr[7], | |
2239 | env->active_tc.gpr[8], env->active_tc.gpr[9], | |
2240 | env->active_tc.gpr[10], env->active_tc.gpr[11]); | |
2241 | # endif /* O32 */ | |
2242 | if (ret == -TARGET_QEMU_ESIGRETURN) { | |
2243 | /* Returning from a successful sigreturn syscall. | |
2244 | Avoid clobbering register state. */ | |
2245 | break; | |
2246 | } | |
2247 | if ((abi_ulong)ret >= (abi_ulong)-1133) { | |
2248 | env->active_tc.gpr[7] = 1; /* error flag */ | |
2249 | ret = -ret; | |
2250 | } else { | |
2251 | env->active_tc.gpr[7] = 0; /* error flag */ | |
2252 | } | |
2253 | env->active_tc.gpr[2] = ret; | |
2254 | break; | |
2255 | case EXCP_TLBL: | |
2256 | case EXCP_TLBS: | |
2257 | case EXCP_AdEL: | |
2258 | case EXCP_AdES: | |
2259 | info.si_signo = TARGET_SIGSEGV; | |
2260 | info.si_errno = 0; | |
2261 | /* XXX: check env->error_code */ | |
2262 | info.si_code = TARGET_SEGV_MAPERR; | |
2263 | info._sifields._sigfault._addr = env->CP0_BadVAddr; | |
2264 | queue_signal(env, info.si_signo, &info); | |
2265 | break; | |
2266 | case EXCP_CpU: | |
2267 | case EXCP_RI: | |
2268 | info.si_signo = TARGET_SIGILL; | |
2269 | info.si_errno = 0; | |
2270 | info.si_code = 0; | |
2271 | queue_signal(env, info.si_signo, &info); | |
2272 | break; | |
2273 | case EXCP_INTERRUPT: | |
2274 | /* just indicate that signals should be handled asap */ | |
2275 | break; | |
2276 | case EXCP_DEBUG: | |
2277 | { | |
2278 | int sig; | |
2279 | ||
2280 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
2281 | if (sig) | |
2282 | { | |
2283 | info.si_signo = sig; | |
2284 | info.si_errno = 0; | |
2285 | info.si_code = TARGET_TRAP_BRKPT; | |
2286 | queue_signal(env, info.si_signo, &info); | |
2287 | } | |
2288 | } | |
2289 | break; | |
2290 | case EXCP_SC: | |
2291 | if (do_store_exclusive(env)) { | |
2292 | info.si_signo = TARGET_SIGSEGV; | |
2293 | info.si_errno = 0; | |
2294 | info.si_code = TARGET_SEGV_MAPERR; | |
2295 | info._sifields._sigfault._addr = env->active_tc.PC; | |
2296 | queue_signal(env, info.si_signo, &info); | |
2297 | } | |
2298 | break; | |
2299 | case EXCP_DSPDIS: | |
2300 | info.si_signo = TARGET_SIGILL; | |
2301 | info.si_errno = 0; | |
2302 | info.si_code = TARGET_ILL_ILLOPC; | |
2303 | queue_signal(env, info.si_signo, &info); | |
2304 | break; | |
2305 | /* The code below was inspired by the MIPS Linux kernel trap | |
2306 | * handling code in arch/mips/kernel/traps.c. | |
2307 | */ | |
2308 | case EXCP_BREAK: | |
2309 | { | |
2310 | abi_ulong trap_instr; | |
2311 | unsigned int code; | |
2312 | ||
2313 | if (env->hflags & MIPS_HFLAG_M16) { | |
2314 | if (env->insn_flags & ASE_MICROMIPS) { | |
2315 | /* microMIPS mode */ | |
2316 | abi_ulong instr[2]; | |
2317 | ||
2318 | ret = get_user_u16(instr[0], env->active_tc.PC) || | |
2319 | get_user_u16(instr[1], env->active_tc.PC + 2); | |
2320 | ||
2321 | trap_instr = (instr[0] << 16) | instr[1]; | |
2322 | } else { | |
2323 | /* MIPS16e mode */ | |
2324 | ret = get_user_u16(trap_instr, env->active_tc.PC); | |
2325 | if (ret != 0) { | |
2326 | goto error; | |
2327 | } | |
2328 | code = (trap_instr >> 6) & 0x3f; | |
2329 | if (do_break(env, &info, code) != 0) { | |
2330 | goto error; | |
2331 | } | |
2332 | break; | |
2333 | } | |
2334 | } else { | |
2335 | ret = get_user_ual(trap_instr, env->active_tc.PC); | |
2336 | } | |
2337 | ||
2338 | if (ret != 0) { | |
2339 | goto error; | |
2340 | } | |
2341 | ||
2342 | /* As described in the original Linux kernel code, the | |
2343 | * below checks on 'code' are to work around an old | |
2344 | * assembly bug. | |
2345 | */ | |
2346 | code = ((trap_instr >> 6) & ((1 << 20) - 1)); | |
2347 | if (code >= (1 << 10)) { | |
2348 | code >>= 10; | |
2349 | } | |
2350 | ||
2351 | if (do_break(env, &info, code) != 0) { | |
2352 | goto error; | |
2353 | } | |
2354 | } | |
2355 | break; | |
2356 | case EXCP_TRAP: | |
2357 | { | |
2358 | abi_ulong trap_instr; | |
2359 | unsigned int code = 0; | |
2360 | ||
2361 | if (env->hflags & MIPS_HFLAG_M16) { | |
2362 | /* microMIPS mode */ | |
2363 | abi_ulong instr[2]; | |
2364 | ||
2365 | ret = get_user_u16(instr[0], env->active_tc.PC) || | |
2366 | get_user_u16(instr[1], env->active_tc.PC + 2); | |
2367 | ||
2368 | trap_instr = (instr[0] << 16) | instr[1]; | |
2369 | } else { | |
2370 | ret = get_user_ual(trap_instr, env->active_tc.PC); | |
2371 | } | |
2372 | ||
2373 | if (ret != 0) { | |
2374 | goto error; | |
2375 | } | |
2376 | ||
2377 | /* The immediate versions don't provide a code. */ | |
2378 | if (!(trap_instr & 0xFC000000)) { | |
2379 | if (env->hflags & MIPS_HFLAG_M16) { | |
2380 | /* microMIPS mode */ | |
2381 | code = ((trap_instr >> 12) & ((1 << 4) - 1)); | |
2382 | } else { | |
2383 | code = ((trap_instr >> 6) & ((1 << 10) - 1)); | |
2384 | } | |
2385 | } | |
2386 | ||
2387 | if (do_break(env, &info, code) != 0) { | |
2388 | goto error; | |
2389 | } | |
2390 | } | |
2391 | break; | |
2392 | default: | |
2393 | error: | |
2394 | fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", | |
2395 | trapnr); | |
2396 | cpu_dump_state(cs, stderr, fprintf, 0); | |
2397 | abort(); | |
2398 | } | |
2399 | process_pending_signals(env); | |
2400 | } | |
2401 | } | |
2402 | #endif | |
2403 | ||
2404 | #ifdef TARGET_OPENRISC | |
2405 | ||
2406 | void cpu_loop(CPUOpenRISCState *env) | |
2407 | { | |
2408 | CPUState *cs = CPU(openrisc_env_get_cpu(env)); | |
2409 | int trapnr, gdbsig; | |
2410 | ||
2411 | for (;;) { | |
2412 | trapnr = cpu_exec(env); | |
2413 | gdbsig = 0; | |
2414 | ||
2415 | switch (trapnr) { | |
2416 | case EXCP_RESET: | |
2417 | qemu_log("\nReset request, exit, pc is %#x\n", env->pc); | |
2418 | exit(1); | |
2419 | break; | |
2420 | case EXCP_BUSERR: | |
2421 | qemu_log("\nBus error, exit, pc is %#x\n", env->pc); | |
2422 | gdbsig = SIGBUS; | |
2423 | break; | |
2424 | case EXCP_DPF: | |
2425 | case EXCP_IPF: | |
2426 | cpu_dump_state(cs, stderr, fprintf, 0); | |
2427 | gdbsig = TARGET_SIGSEGV; | |
2428 | break; | |
2429 | case EXCP_TICK: | |
2430 | qemu_log("\nTick time interrupt pc is %#x\n", env->pc); | |
2431 | break; | |
2432 | case EXCP_ALIGN: | |
2433 | qemu_log("\nAlignment pc is %#x\n", env->pc); | |
2434 | gdbsig = SIGBUS; | |
2435 | break; | |
2436 | case EXCP_ILLEGAL: | |
2437 | qemu_log("\nIllegal instructionpc is %#x\n", env->pc); | |
2438 | gdbsig = SIGILL; | |
2439 | break; | |
2440 | case EXCP_INT: | |
2441 | qemu_log("\nExternal interruptpc is %#x\n", env->pc); | |
2442 | break; | |
2443 | case EXCP_DTLBMISS: | |
2444 | case EXCP_ITLBMISS: | |
2445 | qemu_log("\nTLB miss\n"); | |
2446 | break; | |
2447 | case EXCP_RANGE: | |
2448 | qemu_log("\nRange\n"); | |
2449 | gdbsig = SIGSEGV; | |
2450 | break; | |
2451 | case EXCP_SYSCALL: | |
2452 | env->pc += 4; /* 0xc00; */ | |
2453 | env->gpr[11] = do_syscall(env, | |
2454 | env->gpr[11], /* return value */ | |
2455 | env->gpr[3], /* r3 - r7 are params */ | |
2456 | env->gpr[4], | |
2457 | env->gpr[5], | |
2458 | env->gpr[6], | |
2459 | env->gpr[7], | |
2460 | env->gpr[8], 0, 0); | |
2461 | break; | |
2462 | case EXCP_FPE: | |
2463 | qemu_log("\nFloating point error\n"); | |
2464 | break; | |
2465 | case EXCP_TRAP: | |
2466 | qemu_log("\nTrap\n"); | |
2467 | gdbsig = SIGTRAP; | |
2468 | break; | |
2469 | case EXCP_NR: | |
2470 | qemu_log("\nNR\n"); | |
2471 | break; | |
2472 | default: | |
2473 | qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n", | |
2474 | trapnr); | |
2475 | cpu_dump_state(cs, stderr, fprintf, 0); | |
2476 | gdbsig = TARGET_SIGILL; | |
2477 | break; | |
2478 | } | |
2479 | if (gdbsig) { | |
2480 | gdb_handlesig(env, gdbsig); | |
2481 | if (gdbsig != TARGET_SIGTRAP) { | |
2482 | exit(1); | |
2483 | } | |
2484 | } | |
2485 | ||
2486 | process_pending_signals(env); | |
2487 | } | |
2488 | } | |
2489 | ||
2490 | #endif /* TARGET_OPENRISC */ | |
2491 | ||
2492 | #ifdef TARGET_SH4 | |
2493 | void cpu_loop(CPUSH4State *env) | |
2494 | { | |
2495 | CPUState *cs = CPU(sh_env_get_cpu(env)); | |
2496 | int trapnr, ret; | |
2497 | target_siginfo_t info; | |
2498 | ||
2499 | while (1) { | |
2500 | trapnr = cpu_sh4_exec (env); | |
2501 | ||
2502 | switch (trapnr) { | |
2503 | case 0x160: | |
2504 | env->pc += 2; | |
2505 | ret = do_syscall(env, | |
2506 | env->gregs[3], | |
2507 | env->gregs[4], | |
2508 | env->gregs[5], | |
2509 | env->gregs[6], | |
2510 | env->gregs[7], | |
2511 | env->gregs[0], | |
2512 | env->gregs[1], | |
2513 | 0, 0); | |
2514 | env->gregs[0] = ret; | |
2515 | break; | |
2516 | case EXCP_INTERRUPT: | |
2517 | /* just indicate that signals should be handled asap */ | |
2518 | break; | |
2519 | case EXCP_DEBUG: | |
2520 | { | |
2521 | int sig; | |
2522 | ||
2523 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
2524 | if (sig) | |
2525 | { | |
2526 | info.si_signo = sig; | |
2527 | info.si_errno = 0; | |
2528 | info.si_code = TARGET_TRAP_BRKPT; | |
2529 | queue_signal(env, info.si_signo, &info); | |
2530 | } | |
2531 | } | |
2532 | break; | |
2533 | case 0xa0: | |
2534 | case 0xc0: | |
2535 | info.si_signo = SIGSEGV; | |
2536 | info.si_errno = 0; | |
2537 | info.si_code = TARGET_SEGV_MAPERR; | |
2538 | info._sifields._sigfault._addr = env->tea; | |
2539 | queue_signal(env, info.si_signo, &info); | |
2540 | break; | |
2541 | ||
2542 | default: | |
2543 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
2544 | cpu_dump_state(cs, stderr, fprintf, 0); | |
2545 | exit (1); | |
2546 | } | |
2547 | process_pending_signals (env); | |
2548 | } | |
2549 | } | |
2550 | #endif | |
2551 | ||
2552 | #ifdef TARGET_CRIS | |
2553 | void cpu_loop(CPUCRISState *env) | |
2554 | { | |
2555 | CPUState *cs = CPU(cris_env_get_cpu(env)); | |
2556 | int trapnr, ret; | |
2557 | target_siginfo_t info; | |
2558 | ||
2559 | while (1) { | |
2560 | trapnr = cpu_cris_exec (env); | |
2561 | switch (trapnr) { | |
2562 | case 0xaa: | |
2563 | { | |
2564 | info.si_signo = SIGSEGV; | |
2565 | info.si_errno = 0; | |
2566 | /* XXX: check env->error_code */ | |
2567 | info.si_code = TARGET_SEGV_MAPERR; | |
2568 | info._sifields._sigfault._addr = env->pregs[PR_EDA]; | |
2569 | queue_signal(env, info.si_signo, &info); | |
2570 | } | |
2571 | break; | |
2572 | case EXCP_INTERRUPT: | |
2573 | /* just indicate that signals should be handled asap */ | |
2574 | break; | |
2575 | case EXCP_BREAK: | |
2576 | ret = do_syscall(env, | |
2577 | env->regs[9], | |
2578 | env->regs[10], | |
2579 | env->regs[11], | |
2580 | env->regs[12], | |
2581 | env->regs[13], | |
2582 | env->pregs[7], | |
2583 | env->pregs[11], | |
2584 | 0, 0); | |
2585 | env->regs[10] = ret; | |
2586 | break; | |
2587 | case EXCP_DEBUG: | |
2588 | { | |
2589 | int sig; | |
2590 | ||
2591 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
2592 | if (sig) | |
2593 | { | |
2594 | info.si_signo = sig; | |
2595 | info.si_errno = 0; | |
2596 | info.si_code = TARGET_TRAP_BRKPT; | |
2597 | queue_signal(env, info.si_signo, &info); | |
2598 | } | |
2599 | } | |
2600 | break; | |
2601 | default: | |
2602 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
2603 | cpu_dump_state(cs, stderr, fprintf, 0); | |
2604 | exit (1); | |
2605 | } | |
2606 | process_pending_signals (env); | |
2607 | } | |
2608 | } | |
2609 | #endif | |
2610 | ||
2611 | #ifdef TARGET_MICROBLAZE | |
2612 | void cpu_loop(CPUMBState *env) | |
2613 | { | |
2614 | CPUState *cs = CPU(mb_env_get_cpu(env)); | |
2615 | int trapnr, ret; | |
2616 | target_siginfo_t info; | |
2617 | ||
2618 | while (1) { | |
2619 | trapnr = cpu_mb_exec (env); | |
2620 | switch (trapnr) { | |
2621 | case 0xaa: | |
2622 | { | |
2623 | info.si_signo = SIGSEGV; | |
2624 | info.si_errno = 0; | |
2625 | /* XXX: check env->error_code */ | |
2626 | info.si_code = TARGET_SEGV_MAPERR; | |
2627 | info._sifields._sigfault._addr = 0; | |
2628 | queue_signal(env, info.si_signo, &info); | |
2629 | } | |
2630 | break; | |
2631 | case EXCP_INTERRUPT: | |
2632 | /* just indicate that signals should be handled asap */ | |
2633 | break; | |
2634 | case EXCP_BREAK: | |
2635 | /* Return address is 4 bytes after the call. */ | |
2636 | env->regs[14] += 4; | |
2637 | env->sregs[SR_PC] = env->regs[14]; | |
2638 | ret = do_syscall(env, | |
2639 | env->regs[12], | |
2640 | env->regs[5], | |
2641 | env->regs[6], | |
2642 | env->regs[7], | |
2643 | env->regs[8], | |
2644 | env->regs[9], | |
2645 | env->regs[10], | |
2646 | 0, 0); | |
2647 | env->regs[3] = ret; | |
2648 | break; | |
2649 | case EXCP_HW_EXCP: | |
2650 | env->regs[17] = env->sregs[SR_PC] + 4; | |
2651 | if (env->iflags & D_FLAG) { | |
2652 | env->sregs[SR_ESR] |= 1 << 12; | |
2653 | env->sregs[SR_PC] -= 4; | |
2654 | /* FIXME: if branch was immed, replay the imm as well. */ | |
2655 | } | |
2656 | ||
2657 | env->iflags &= ~(IMM_FLAG | D_FLAG); | |
2658 | ||
2659 | switch (env->sregs[SR_ESR] & 31) { | |
2660 | case ESR_EC_DIVZERO: | |
2661 | info.si_signo = SIGFPE; | |
2662 | info.si_errno = 0; | |
2663 | info.si_code = TARGET_FPE_FLTDIV; | |
2664 | info._sifields._sigfault._addr = 0; | |
2665 | queue_signal(env, info.si_signo, &info); | |
2666 | break; | |
2667 | case ESR_EC_FPU: | |
2668 | info.si_signo = SIGFPE; | |
2669 | info.si_errno = 0; | |
2670 | if (env->sregs[SR_FSR] & FSR_IO) { | |
2671 | info.si_code = TARGET_FPE_FLTINV; | |
2672 | } | |
2673 | if (env->sregs[SR_FSR] & FSR_DZ) { | |
2674 | info.si_code = TARGET_FPE_FLTDIV; | |
2675 | } | |
2676 | info._sifields._sigfault._addr = 0; | |
2677 | queue_signal(env, info.si_signo, &info); | |
2678 | break; | |
2679 | default: | |
2680 | printf ("Unhandled hw-exception: 0x%x\n", | |
2681 | env->sregs[SR_ESR] & ESR_EC_MASK); | |
2682 | cpu_dump_state(cs, stderr, fprintf, 0); | |
2683 | exit (1); | |
2684 | break; | |
2685 | } | |
2686 | break; | |
2687 | case EXCP_DEBUG: | |
2688 | { | |
2689 | int sig; | |
2690 | ||
2691 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
2692 | if (sig) | |
2693 | { | |
2694 | info.si_signo = sig; | |
2695 | info.si_errno = 0; | |
2696 | info.si_code = TARGET_TRAP_BRKPT; | |
2697 | queue_signal(env, info.si_signo, &info); | |
2698 | } | |
2699 | } | |
2700 | break; | |
2701 | default: | |
2702 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
2703 | cpu_dump_state(cs, stderr, fprintf, 0); | |
2704 | exit (1); | |
2705 | } | |
2706 | process_pending_signals (env); | |
2707 | } | |
2708 | } | |
2709 | #endif | |
2710 | ||
2711 | #ifdef TARGET_M68K | |
2712 | ||
2713 | void cpu_loop(CPUM68KState *env) | |
2714 | { | |
2715 | CPUState *cs = CPU(m68k_env_get_cpu(env)); | |
2716 | int trapnr; | |
2717 | unsigned int n; | |
2718 | target_siginfo_t info; | |
2719 | TaskState *ts = env->opaque; | |
2720 | ||
2721 | for(;;) { | |
2722 | trapnr = cpu_m68k_exec(env); | |
2723 | switch(trapnr) { | |
2724 | case EXCP_ILLEGAL: | |
2725 | { | |
2726 | if (ts->sim_syscalls) { | |
2727 | uint16_t nr; | |
2728 | nr = lduw(env->pc + 2); | |
2729 | env->pc += 4; | |
2730 | do_m68k_simcall(env, nr); | |
2731 | } else { | |
2732 | goto do_sigill; | |
2733 | } | |
2734 | } | |
2735 | break; | |
2736 | case EXCP_HALT_INSN: | |
2737 | /* Semihosing syscall. */ | |
2738 | env->pc += 4; | |
2739 | do_m68k_semihosting(env, env->dregs[0]); | |
2740 | break; | |
2741 | case EXCP_LINEA: | |
2742 | case EXCP_LINEF: | |
2743 | case EXCP_UNSUPPORTED: | |
2744 | do_sigill: | |
2745 | info.si_signo = SIGILL; | |
2746 | info.si_errno = 0; | |
2747 | info.si_code = TARGET_ILL_ILLOPN; | |
2748 | info._sifields._sigfault._addr = env->pc; | |
2749 | queue_signal(env, info.si_signo, &info); | |
2750 | break; | |
2751 | case EXCP_TRAP0: | |
2752 | { | |
2753 | ts->sim_syscalls = 0; | |
2754 | n = env->dregs[0]; | |
2755 | env->pc += 2; | |
2756 | env->dregs[0] = do_syscall(env, | |
2757 | n, | |
2758 | env->dregs[1], | |
2759 | env->dregs[2], | |
2760 | env->dregs[3], | |
2761 | env->dregs[4], | |
2762 | env->dregs[5], | |
2763 | env->aregs[0], | |
2764 | 0, 0); | |
2765 | } | |
2766 | break; | |
2767 | case EXCP_INTERRUPT: | |
2768 | /* just indicate that signals should be handled asap */ | |
2769 | break; | |
2770 | case EXCP_ACCESS: | |
2771 | { | |
2772 | info.si_signo = SIGSEGV; | |
2773 | info.si_errno = 0; | |
2774 | /* XXX: check env->error_code */ | |
2775 | info.si_code = TARGET_SEGV_MAPERR; | |
2776 | info._sifields._sigfault._addr = env->mmu.ar; | |
2777 | queue_signal(env, info.si_signo, &info); | |
2778 | } | |
2779 | break; | |
2780 | case EXCP_DEBUG: | |
2781 | { | |
2782 | int sig; | |
2783 | ||
2784 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
2785 | if (sig) | |
2786 | { | |
2787 | info.si_signo = sig; | |
2788 | info.si_errno = 0; | |
2789 | info.si_code = TARGET_TRAP_BRKPT; | |
2790 | queue_signal(env, info.si_signo, &info); | |
2791 | } | |
2792 | } | |
2793 | break; | |
2794 | default: | |
2795 | fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", | |
2796 | trapnr); | |
2797 | cpu_dump_state(cs, stderr, fprintf, 0); | |
2798 | abort(); | |
2799 | } | |
2800 | process_pending_signals(env); | |
2801 | } | |
2802 | } | |
2803 | #endif /* TARGET_M68K */ | |
2804 | ||
2805 | #ifdef TARGET_ALPHA | |
2806 | static void do_store_exclusive(CPUAlphaState *env, int reg, int quad) | |
2807 | { | |
2808 | target_ulong addr, val, tmp; | |
2809 | target_siginfo_t info; | |
2810 | int ret = 0; | |
2811 | ||
2812 | addr = env->lock_addr; | |
2813 | tmp = env->lock_st_addr; | |
2814 | env->lock_addr = -1; | |
2815 | env->lock_st_addr = 0; | |
2816 | ||
2817 | start_exclusive(); | |
2818 | mmap_lock(); | |
2819 | ||
2820 | if (addr == tmp) { | |
2821 | if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { | |
2822 | goto do_sigsegv; | |
2823 | } | |
2824 | ||
2825 | if (val == env->lock_value) { | |
2826 | tmp = env->ir[reg]; | |
2827 | if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) { | |
2828 | goto do_sigsegv; | |
2829 | } | |
2830 | ret = 1; | |
2831 | } | |
2832 | } | |
2833 | env->ir[reg] = ret; | |
2834 | env->pc += 4; | |
2835 | ||
2836 | mmap_unlock(); | |
2837 | end_exclusive(); | |
2838 | return; | |
2839 | ||
2840 | do_sigsegv: | |
2841 | mmap_unlock(); | |
2842 | end_exclusive(); | |
2843 | ||
2844 | info.si_signo = TARGET_SIGSEGV; | |
2845 | info.si_errno = 0; | |
2846 | info.si_code = TARGET_SEGV_MAPERR; | |
2847 | info._sifields._sigfault._addr = addr; | |
2848 | queue_signal(env, TARGET_SIGSEGV, &info); | |
2849 | } | |
2850 | ||
2851 | void cpu_loop(CPUAlphaState *env) | |
2852 | { | |
2853 | CPUState *cs = CPU(alpha_env_get_cpu(env)); | |
2854 | int trapnr; | |
2855 | target_siginfo_t info; | |
2856 | abi_long sysret; | |
2857 | ||
2858 | while (1) { | |
2859 | trapnr = cpu_alpha_exec (env); | |
2860 | ||
2861 | /* All of the traps imply a transition through PALcode, which | |
2862 | implies an REI instruction has been executed. Which means | |
2863 | that the intr_flag should be cleared. */ | |
2864 | env->intr_flag = 0; | |
2865 | ||
2866 | switch (trapnr) { | |
2867 | case EXCP_RESET: | |
2868 | fprintf(stderr, "Reset requested. Exit\n"); | |
2869 | exit(1); | |
2870 | break; | |
2871 | case EXCP_MCHK: | |
2872 | fprintf(stderr, "Machine check exception. Exit\n"); | |
2873 | exit(1); | |
2874 | break; | |
2875 | case EXCP_SMP_INTERRUPT: | |
2876 | case EXCP_CLK_INTERRUPT: | |
2877 | case EXCP_DEV_INTERRUPT: | |
2878 | fprintf(stderr, "External interrupt. Exit\n"); | |
2879 | exit(1); | |
2880 | break; | |
2881 | case EXCP_MMFAULT: | |
2882 | env->lock_addr = -1; | |
2883 | info.si_signo = TARGET_SIGSEGV; | |
2884 | info.si_errno = 0; | |
2885 | info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID | |
2886 | ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); | |
2887 | info._sifields._sigfault._addr = env->trap_arg0; | |
2888 | queue_signal(env, info.si_signo, &info); | |
2889 | break; | |
2890 | case EXCP_UNALIGN: | |
2891 | env->lock_addr = -1; | |
2892 | info.si_signo = TARGET_SIGBUS; | |
2893 | info.si_errno = 0; | |
2894 | info.si_code = TARGET_BUS_ADRALN; | |
2895 | info._sifields._sigfault._addr = env->trap_arg0; | |
2896 | queue_signal(env, info.si_signo, &info); | |
2897 | break; | |
2898 | case EXCP_OPCDEC: | |
2899 | do_sigill: | |
2900 | env->lock_addr = -1; | |
2901 | info.si_signo = TARGET_SIGILL; | |
2902 | info.si_errno = 0; | |
2903 | info.si_code = TARGET_ILL_ILLOPC; | |
2904 | info._sifields._sigfault._addr = env->pc; | |
2905 | queue_signal(env, info.si_signo, &info); | |
2906 | break; | |
2907 | case EXCP_ARITH: | |
2908 | env->lock_addr = -1; | |
2909 | info.si_signo = TARGET_SIGFPE; | |
2910 | info.si_errno = 0; | |
2911 | info.si_code = TARGET_FPE_FLTINV; | |
2912 | info._sifields._sigfault._addr = env->pc; | |
2913 | queue_signal(env, info.si_signo, &info); | |
2914 | break; | |
2915 | case EXCP_FEN: | |
2916 | /* No-op. Linux simply re-enables the FPU. */ | |
2917 | break; | |
2918 | case EXCP_CALL_PAL: | |
2919 | env->lock_addr = -1; | |
2920 | switch (env->error_code) { | |
2921 | case 0x80: | |
2922 | /* BPT */ | |
2923 | info.si_signo = TARGET_SIGTRAP; | |
2924 | info.si_errno = 0; | |
2925 | info.si_code = TARGET_TRAP_BRKPT; | |
2926 | info._sifields._sigfault._addr = env->pc; | |
2927 | queue_signal(env, info.si_signo, &info); | |
2928 | break; | |
2929 | case 0x81: | |
2930 | /* BUGCHK */ | |
2931 | info.si_signo = TARGET_SIGTRAP; | |
2932 | info.si_errno = 0; | |
2933 | info.si_code = 0; | |
2934 | info._sifields._sigfault._addr = env->pc; | |
2935 | queue_signal(env, info.si_signo, &info); | |
2936 | break; | |
2937 | case 0x83: | |
2938 | /* CALLSYS */ | |
2939 | trapnr = env->ir[IR_V0]; | |
2940 | sysret = do_syscall(env, trapnr, | |
2941 | env->ir[IR_A0], env->ir[IR_A1], | |
2942 | env->ir[IR_A2], env->ir[IR_A3], | |
2943 | env->ir[IR_A4], env->ir[IR_A5], | |
2944 | 0, 0); | |
2945 | if (trapnr == TARGET_NR_sigreturn | |
2946 | || trapnr == TARGET_NR_rt_sigreturn) { | |
2947 | break; | |
2948 | } | |
2949 | /* Syscall writes 0 to V0 to bypass error check, similar | |
2950 | to how this is handled internal to Linux kernel. | |
2951 | (Ab)use trapnr temporarily as boolean indicating error. */ | |
2952 | trapnr = (env->ir[IR_V0] != 0 && sysret < 0); | |
2953 | env->ir[IR_V0] = (trapnr ? -sysret : sysret); | |
2954 | env->ir[IR_A3] = trapnr; | |
2955 | break; | |
2956 | case 0x86: | |
2957 | /* IMB */ | |
2958 | /* ??? We can probably elide the code using page_unprotect | |
2959 | that is checking for self-modifying code. Instead we | |
2960 | could simply call tb_flush here. Until we work out the | |
2961 | changes required to turn off the extra write protection, | |
2962 | this can be a no-op. */ | |
2963 | break; | |
2964 | case 0x9E: | |
2965 | /* RDUNIQUE */ | |
2966 | /* Handled in the translator for usermode. */ | |
2967 | abort(); | |
2968 | case 0x9F: | |
2969 | /* WRUNIQUE */ | |
2970 | /* Handled in the translator for usermode. */ | |
2971 | abort(); | |
2972 | case 0xAA: | |
2973 | /* GENTRAP */ | |
2974 | info.si_signo = TARGET_SIGFPE; | |
2975 | switch (env->ir[IR_A0]) { | |
2976 | case TARGET_GEN_INTOVF: | |
2977 | info.si_code = TARGET_FPE_INTOVF; | |
2978 | break; | |
2979 | case TARGET_GEN_INTDIV: | |
2980 | info.si_code = TARGET_FPE_INTDIV; | |
2981 | break; | |
2982 | case TARGET_GEN_FLTOVF: | |
2983 | info.si_code = TARGET_FPE_FLTOVF; | |
2984 | break; | |
2985 | case TARGET_GEN_FLTUND: | |
2986 | info.si_code = TARGET_FPE_FLTUND; | |
2987 | break; | |
2988 | case TARGET_GEN_FLTINV: | |
2989 | info.si_code = TARGET_FPE_FLTINV; | |
2990 | break; | |
2991 | case TARGET_GEN_FLTINE: | |
2992 | info.si_code = TARGET_FPE_FLTRES; | |
2993 | break; | |
2994 | case TARGET_GEN_ROPRAND: | |
2995 | info.si_code = 0; | |
2996 | break; | |
2997 | default: | |
2998 | info.si_signo = TARGET_SIGTRAP; | |
2999 | info.si_code = 0; | |
3000 | break; | |
3001 | } | |
3002 | info.si_errno = 0; | |
3003 | info._sifields._sigfault._addr = env->pc; | |
3004 | queue_signal(env, info.si_signo, &info); | |
3005 | break; | |
3006 | default: | |
3007 | goto do_sigill; | |
3008 | } | |
3009 | break; | |
3010 | case EXCP_DEBUG: | |
3011 | info.si_signo = gdb_handlesig (env, TARGET_SIGTRAP); | |
3012 | if (info.si_signo) { | |
3013 | env->lock_addr = -1; | |
3014 | info.si_errno = 0; | |
3015 | info.si_code = TARGET_TRAP_BRKPT; | |
3016 | queue_signal(env, info.si_signo, &info); | |
3017 | } | |
3018 | break; | |
3019 | case EXCP_STL_C: | |
3020 | case EXCP_STQ_C: | |
3021 | do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C); | |
3022 | break; | |
3023 | case EXCP_INTERRUPT: | |
3024 | /* Just indicate that signals should be handled asap. */ | |
3025 | break; | |
3026 | default: | |
3027 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
3028 | cpu_dump_state(cs, stderr, fprintf, 0); | |
3029 | exit (1); | |
3030 | } | |
3031 | process_pending_signals (env); | |
3032 | } | |
3033 | } | |
3034 | #endif /* TARGET_ALPHA */ | |
3035 | ||
3036 | #ifdef TARGET_S390X | |
3037 | void cpu_loop(CPUS390XState *env) | |
3038 | { | |
3039 | CPUState *cs = CPU(s390_env_get_cpu(env)); | |
3040 | int trapnr, n, sig; | |
3041 | target_siginfo_t info; | |
3042 | target_ulong addr; | |
3043 | ||
3044 | while (1) { | |
3045 | trapnr = cpu_s390x_exec(env); | |
3046 | switch (trapnr) { | |
3047 | case EXCP_INTERRUPT: | |
3048 | /* Just indicate that signals should be handled asap. */ | |
3049 | break; | |
3050 | ||
3051 | case EXCP_SVC: | |
3052 | n = env->int_svc_code; | |
3053 | if (!n) { | |
3054 | /* syscalls > 255 */ | |
3055 | n = env->regs[1]; | |
3056 | } | |
3057 | env->psw.addr += env->int_svc_ilen; | |
3058 | env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3], | |
3059 | env->regs[4], env->regs[5], | |
3060 | env->regs[6], env->regs[7], 0, 0); | |
3061 | break; | |
3062 | ||
3063 | case EXCP_DEBUG: | |
3064 | sig = gdb_handlesig(env, TARGET_SIGTRAP); | |
3065 | if (sig) { | |
3066 | n = TARGET_TRAP_BRKPT; | |
3067 | goto do_signal_pc; | |
3068 | } | |
3069 | break; | |
3070 | case EXCP_PGM: | |
3071 | n = env->int_pgm_code; | |
3072 | switch (n) { | |
3073 | case PGM_OPERATION: | |
3074 | case PGM_PRIVILEGED: | |
3075 | sig = SIGILL; | |
3076 | n = TARGET_ILL_ILLOPC; | |
3077 | goto do_signal_pc; | |
3078 | case PGM_PROTECTION: | |
3079 | case PGM_ADDRESSING: | |
3080 | sig = SIGSEGV; | |
3081 | /* XXX: check env->error_code */ | |
3082 | n = TARGET_SEGV_MAPERR; | |
3083 | addr = env->__excp_addr; | |
3084 | goto do_signal; | |
3085 | case PGM_EXECUTE: | |
3086 | case PGM_SPECIFICATION: | |
3087 | case PGM_SPECIAL_OP: | |
3088 | case PGM_OPERAND: | |
3089 | do_sigill_opn: | |
3090 | sig = SIGILL; | |
3091 | n = TARGET_ILL_ILLOPN; | |
3092 | goto do_signal_pc; | |
3093 | ||
3094 | case PGM_FIXPT_OVERFLOW: | |
3095 | sig = SIGFPE; | |
3096 | n = TARGET_FPE_INTOVF; | |
3097 | goto do_signal_pc; | |
3098 | case PGM_FIXPT_DIVIDE: | |
3099 | sig = SIGFPE; | |
3100 | n = TARGET_FPE_INTDIV; | |
3101 | goto do_signal_pc; | |
3102 | ||
3103 | case PGM_DATA: | |
3104 | n = (env->fpc >> 8) & 0xff; | |
3105 | if (n == 0xff) { | |
3106 | /* compare-and-trap */ | |
3107 | goto do_sigill_opn; | |
3108 | } else { | |
3109 | /* An IEEE exception, simulated or otherwise. */ | |
3110 | if (n & 0x80) { | |
3111 | n = TARGET_FPE_FLTINV; | |
3112 | } else if (n & 0x40) { | |
3113 | n = TARGET_FPE_FLTDIV; | |
3114 | } else if (n & 0x20) { | |
3115 | n = TARGET_FPE_FLTOVF; | |
3116 | } else if (n & 0x10) { | |
3117 | n = TARGET_FPE_FLTUND; | |
3118 | } else if (n & 0x08) { | |
3119 | n = TARGET_FPE_FLTRES; | |
3120 | } else { | |
3121 | /* ??? Quantum exception; BFP, DFP error. */ | |
3122 | goto do_sigill_opn; | |
3123 | } | |
3124 | sig = SIGFPE; | |
3125 | goto do_signal_pc; | |
3126 | } | |
3127 | ||
3128 | default: | |
3129 | fprintf(stderr, "Unhandled program exception: %#x\n", n); | |
3130 | cpu_dump_state(cs, stderr, fprintf, 0); | |
3131 | exit(1); | |
3132 | } | |
3133 | break; | |
3134 | ||
3135 | do_signal_pc: | |
3136 | addr = env->psw.addr; | |
3137 | do_signal: | |
3138 | info.si_signo = sig; | |
3139 | info.si_errno = 0; | |
3140 | info.si_code = n; | |
3141 | info._sifields._sigfault._addr = addr; | |
3142 | queue_signal(env, info.si_signo, &info); | |
3143 | break; | |
3144 | ||
3145 | default: | |
3146 | fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr); | |
3147 | cpu_dump_state(cs, stderr, fprintf, 0); | |
3148 | exit(1); | |
3149 | } | |
3150 | process_pending_signals (env); | |
3151 | } | |
3152 | } | |
3153 | ||
3154 | #endif /* TARGET_S390X */ | |
3155 | ||
3156 | THREAD CPUState *thread_cpu; | |
3157 | ||
3158 | void task_settid(TaskState *ts) | |
3159 | { | |
3160 | if (ts->ts_tid == 0) { | |
3161 | ts->ts_tid = (pid_t)syscall(SYS_gettid); | |
3162 | } | |
3163 | } | |
3164 | ||
3165 | void stop_all_tasks(void) | |
3166 | { | |
3167 | /* | |
3168 | * We trust that when using NPTL, start_exclusive() | |
3169 | * handles thread stopping correctly. | |
3170 | */ | |
3171 | start_exclusive(); | |
3172 | } | |
3173 | ||
3174 | /* Assumes contents are already zeroed. */ | |
3175 | void init_task_state(TaskState *ts) | |
3176 | { | |
3177 | int i; | |
3178 | ||
3179 | ts->used = 1; | |
3180 | ts->first_free = ts->sigqueue_table; | |
3181 | for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) { | |
3182 | ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1]; | |
3183 | } | |
3184 | ts->sigqueue_table[i].next = NULL; | |
3185 | } | |
3186 | ||
3187 | static void handle_arg_help(const char *arg) | |
3188 | { | |
3189 | usage(); | |
3190 | } | |
3191 | ||
3192 | static void handle_arg_log(const char *arg) | |
3193 | { | |
3194 | int mask; | |
3195 | ||
3196 | mask = qemu_str_to_log_mask(arg); | |
3197 | if (!mask) { | |
3198 | qemu_print_log_usage(stdout); | |
3199 | exit(1); | |
3200 | } | |
3201 | qemu_set_log(mask); | |
3202 | } | |
3203 | ||
3204 | static void handle_arg_log_filename(const char *arg) | |
3205 | { | |
3206 | qemu_set_log_filename(arg); | |
3207 | } | |
3208 | ||
3209 | static void handle_arg_set_env(const char *arg) | |
3210 | { | |
3211 | char *r, *p, *token; | |
3212 | r = p = strdup(arg); | |
3213 | while ((token = strsep(&p, ",")) != NULL) { | |
3214 | if (envlist_setenv(envlist, token) != 0) { | |
3215 | usage(); | |
3216 | } | |
3217 | } | |
3218 | free(r); | |
3219 | } | |
3220 | ||
3221 | static void handle_arg_unset_env(const char *arg) | |
3222 | { | |
3223 | char *r, *p, *token; | |
3224 | r = p = strdup(arg); | |
3225 | while ((token = strsep(&p, ",")) != NULL) { | |
3226 | if (envlist_unsetenv(envlist, token) != 0) { | |
3227 | usage(); | |
3228 | } | |
3229 | } | |
3230 | free(r); | |
3231 | } | |
3232 | ||
3233 | static void handle_arg_argv0(const char *arg) | |
3234 | { | |
3235 | argv0 = strdup(arg); | |
3236 | } | |
3237 | ||
3238 | static void handle_arg_stack_size(const char *arg) | |
3239 | { | |
3240 | char *p; | |
3241 | guest_stack_size = strtoul(arg, &p, 0); | |
3242 | if (guest_stack_size == 0) { | |
3243 | usage(); | |
3244 | } | |
3245 | ||
3246 | if (*p == 'M') { | |
3247 | guest_stack_size *= 1024 * 1024; | |
3248 | } else if (*p == 'k' || *p == 'K') { | |
3249 | guest_stack_size *= 1024; | |
3250 | } | |
3251 | } | |
3252 | ||
3253 | static void handle_arg_ld_prefix(const char *arg) | |
3254 | { | |
3255 | interp_prefix = strdup(arg); | |
3256 | } | |
3257 | ||
3258 | static void handle_arg_pagesize(const char *arg) | |
3259 | { | |
3260 | qemu_host_page_size = atoi(arg); | |
3261 | if (qemu_host_page_size == 0 || | |
3262 | (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) { | |
3263 | fprintf(stderr, "page size must be a power of two\n"); | |
3264 | exit(1); | |
3265 | } | |
3266 | } | |
3267 | ||
3268 | static void handle_arg_gdb(const char *arg) | |
3269 | { | |
3270 | gdbstub_port = atoi(arg); | |
3271 | } | |
3272 | ||
3273 | static void handle_arg_uname(const char *arg) | |
3274 | { | |
3275 | qemu_uname_release = strdup(arg); | |
3276 | } | |
3277 | ||
3278 | static void handle_arg_cpu(const char *arg) | |
3279 | { | |
3280 | cpu_model = strdup(arg); | |
3281 | if (cpu_model == NULL || is_help_option(cpu_model)) { | |
3282 | /* XXX: implement xxx_cpu_list for targets that still miss it */ | |
3283 | #if defined(cpu_list) | |
3284 | cpu_list(stdout, &fprintf); | |
3285 | #endif | |
3286 | exit(1); | |
3287 | } | |
3288 | } | |
3289 | ||
3290 | #if defined(CONFIG_USE_GUEST_BASE) | |
3291 | static void handle_arg_guest_base(const char *arg) | |
3292 | { | |
3293 | guest_base = strtol(arg, NULL, 0); | |
3294 | have_guest_base = 1; | |
3295 | } | |
3296 | ||
3297 | static void handle_arg_reserved_va(const char *arg) | |
3298 | { | |
3299 | char *p; | |
3300 | int shift = 0; | |
3301 | reserved_va = strtoul(arg, &p, 0); | |
3302 | switch (*p) { | |
3303 | case 'k': | |
3304 | case 'K': | |
3305 | shift = 10; | |
3306 | break; | |
3307 | case 'M': | |
3308 | shift = 20; | |
3309 | break; | |
3310 | case 'G': | |
3311 | shift = 30; | |
3312 | break; | |
3313 | } | |
3314 | if (shift) { | |
3315 | unsigned long unshifted = reserved_va; | |
3316 | p++; | |
3317 | reserved_va <<= shift; | |
3318 | if (((reserved_va >> shift) != unshifted) | |
3319 | #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS | |
3320 | || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) | |
3321 | #endif | |
3322 | ) { | |
3323 | fprintf(stderr, "Reserved virtual address too big\n"); | |
3324 | exit(1); | |
3325 | } | |
3326 | } | |
3327 | if (*p) { | |
3328 | fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p); | |
3329 | exit(1); | |
3330 | } | |
3331 | } | |
3332 | #endif | |
3333 | ||
3334 | static void handle_arg_singlestep(const char *arg) | |
3335 | { | |
3336 | singlestep = 1; | |
3337 | } | |
3338 | ||
3339 | static void handle_arg_strace(const char *arg) | |
3340 | { | |
3341 | do_strace = 1; | |
3342 | } | |
3343 | ||
3344 | static void handle_arg_version(const char *arg) | |
3345 | { | |
3346 | printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION | |
3347 | ", Copyright (c) 2003-2008 Fabrice Bellard\n"); | |
3348 | exit(0); | |
3349 | } | |
3350 | ||
3351 | struct qemu_argument { | |
3352 | const char *argv; | |
3353 | const char *env; | |
3354 | bool has_arg; | |
3355 | void (*handle_opt)(const char *arg); | |
3356 | const char *example; | |
3357 | const char *help; | |
3358 | }; | |
3359 | ||
3360 | static const struct qemu_argument arg_table[] = { | |
3361 | {"h", "", false, handle_arg_help, | |
3362 | "", "print this help"}, | |
3363 | {"g", "QEMU_GDB", true, handle_arg_gdb, | |
3364 | "port", "wait gdb connection to 'port'"}, | |
3365 | {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix, | |
3366 | "path", "set the elf interpreter prefix to 'path'"}, | |
3367 | {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size, | |
3368 | "size", "set the stack size to 'size' bytes"}, | |
3369 | {"cpu", "QEMU_CPU", true, handle_arg_cpu, | |
3370 | "model", "select CPU (-cpu help for list)"}, | |
3371 | {"E", "QEMU_SET_ENV", true, handle_arg_set_env, | |
3372 | "var=value", "sets targets environment variable (see below)"}, | |
3373 | {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env, | |
3374 | "var", "unsets targets environment variable (see below)"}, | |
3375 | {"0", "QEMU_ARGV0", true, handle_arg_argv0, | |
3376 | "argv0", "forces target process argv[0] to be 'argv0'"}, | |
3377 | {"r", "QEMU_UNAME", true, handle_arg_uname, | |
3378 | "uname", "set qemu uname release string to 'uname'"}, | |
3379 | #if defined(CONFIG_USE_GUEST_BASE) | |
3380 | {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base, | |
3381 | "address", "set guest_base address to 'address'"}, | |
3382 | {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va, | |
3383 | "size", "reserve 'size' bytes for guest virtual address space"}, | |
3384 | #endif | |
3385 | {"d", "QEMU_LOG", true, handle_arg_log, | |
3386 | "item[,...]", "enable logging of specified items " | |
3387 | "(use '-d help' for a list of items)"}, | |
3388 | {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename, | |
3389 | "logfile", "write logs to 'logfile' (default stderr)"}, | |
3390 | {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize, | |
3391 | "pagesize", "set the host page size to 'pagesize'"}, | |
3392 | {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep, | |
3393 | "", "run in singlestep mode"}, | |
3394 | {"strace", "QEMU_STRACE", false, handle_arg_strace, | |
3395 | "", "log system calls"}, | |
3396 | {"version", "QEMU_VERSION", false, handle_arg_version, | |
3397 | "", "display version information and exit"}, | |
3398 | {NULL, NULL, false, NULL, NULL, NULL} | |
3399 | }; | |
3400 | ||
3401 | static void usage(void) | |
3402 | { | |
3403 | const struct qemu_argument *arginfo; | |
3404 | int maxarglen; | |
3405 | int maxenvlen; | |
3406 | ||
3407 | printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n" | |
3408 | "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n" | |
3409 | "\n" | |
3410 | "Options and associated environment variables:\n" | |
3411 | "\n"); | |
3412 | ||
3413 | /* Calculate column widths. We must always have at least enough space | |
3414 | * for the column header. | |
3415 | */ | |
3416 | maxarglen = strlen("Argument"); | |
3417 | maxenvlen = strlen("Env-variable"); | |
3418 | ||
3419 | for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { | |
3420 | int arglen = strlen(arginfo->argv); | |
3421 | if (arginfo->has_arg) { | |
3422 | arglen += strlen(arginfo->example) + 1; | |
3423 | } | |
3424 | if (strlen(arginfo->env) > maxenvlen) { | |
3425 | maxenvlen = strlen(arginfo->env); | |
3426 | } | |
3427 | if (arglen > maxarglen) { | |
3428 | maxarglen = arglen; | |
3429 | } | |
3430 | } | |
3431 | ||
3432 | printf("%-*s %-*s Description\n", maxarglen+1, "Argument", | |
3433 | maxenvlen, "Env-variable"); | |
3434 | ||
3435 | for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { | |
3436 | if (arginfo->has_arg) { | |
3437 | printf("-%s %-*s %-*s %s\n", arginfo->argv, | |
3438 | (int)(maxarglen - strlen(arginfo->argv) - 1), | |
3439 | arginfo->example, maxenvlen, arginfo->env, arginfo->help); | |
3440 | } else { | |
3441 | printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv, | |
3442 | maxenvlen, arginfo->env, | |
3443 | arginfo->help); | |
3444 | } | |
3445 | } | |
3446 | ||
3447 | printf("\n" | |
3448 | "Defaults:\n" | |
3449 | "QEMU_LD_PREFIX = %s\n" | |
3450 | "QEMU_STACK_SIZE = %ld byte\n", | |
3451 | interp_prefix, | |
3452 | guest_stack_size); | |
3453 | ||
3454 | printf("\n" | |
3455 | "You can use -E and -U options or the QEMU_SET_ENV and\n" | |
3456 | "QEMU_UNSET_ENV environment variables to set and unset\n" | |
3457 | "environment variables for the target process.\n" | |
3458 | "It is possible to provide several variables by separating them\n" | |
3459 | "by commas in getsubopt(3) style. Additionally it is possible to\n" | |
3460 | "provide the -E and -U options multiple times.\n" | |
3461 | "The following lines are equivalent:\n" | |
3462 | " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n" | |
3463 | " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n" | |
3464 | " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n" | |
3465 | "Note that if you provide several changes to a single variable\n" | |
3466 | "the last change will stay in effect.\n"); | |
3467 | ||
3468 | exit(1); | |
3469 | } | |
3470 | ||
3471 | static int parse_args(int argc, char **argv) | |
3472 | { | |
3473 | const char *r; | |
3474 | int optind; | |
3475 | const struct qemu_argument *arginfo; | |
3476 | ||
3477 | for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { | |
3478 | if (arginfo->env == NULL) { | |
3479 | continue; | |
3480 | } | |
3481 | ||
3482 | r = getenv(arginfo->env); | |
3483 | if (r != NULL) { | |
3484 | arginfo->handle_opt(r); | |
3485 | } | |
3486 | } | |
3487 | ||
3488 | optind = 1; | |
3489 | for (;;) { | |
3490 | if (optind >= argc) { | |
3491 | break; | |
3492 | } | |
3493 | r = argv[optind]; | |
3494 | if (r[0] != '-') { | |
3495 | break; | |
3496 | } | |
3497 | optind++; | |
3498 | r++; | |
3499 | if (!strcmp(r, "-")) { | |
3500 | break; | |
3501 | } | |
3502 | ||
3503 | for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { | |
3504 | if (!strcmp(r, arginfo->argv)) { | |
3505 | if (arginfo->has_arg) { | |
3506 | if (optind >= argc) { | |
3507 | usage(); | |
3508 | } | |
3509 | arginfo->handle_opt(argv[optind]); | |
3510 | optind++; | |
3511 | } else { | |
3512 | arginfo->handle_opt(NULL); | |
3513 | } | |
3514 | break; | |
3515 | } | |
3516 | } | |
3517 | ||
3518 | /* no option matched the current argv */ | |
3519 | if (arginfo->handle_opt == NULL) { | |
3520 | usage(); | |
3521 | } | |
3522 | } | |
3523 | ||
3524 | if (optind >= argc) { | |
3525 | usage(); | |
3526 | } | |
3527 | ||
3528 | filename = argv[optind]; | |
3529 | exec_path = argv[optind]; | |
3530 | ||
3531 | return optind; | |
3532 | } | |
3533 | ||
3534 | int main(int argc, char **argv, char **envp) | |
3535 | { | |
3536 | struct target_pt_regs regs1, *regs = ®s1; | |
3537 | struct image_info info1, *info = &info1; | |
3538 | struct linux_binprm bprm; | |
3539 | TaskState *ts; | |
3540 | CPUArchState *env; | |
3541 | int optind; | |
3542 | char **target_environ, **wrk; | |
3543 | char **target_argv; | |
3544 | int target_argc; | |
3545 | int i; | |
3546 | int ret; | |
3547 | ||
3548 | module_call_init(MODULE_INIT_QOM); | |
3549 | ||
3550 | qemu_cache_utils_init(envp); | |
3551 | ||
3552 | if ((envlist = envlist_create()) == NULL) { | |
3553 | (void) fprintf(stderr, "Unable to allocate envlist\n"); | |
3554 | exit(1); | |
3555 | } | |
3556 | ||
3557 | /* add current environment into the list */ | |
3558 | for (wrk = environ; *wrk != NULL; wrk++) { | |
3559 | (void) envlist_setenv(envlist, *wrk); | |
3560 | } | |
3561 | ||
3562 | /* Read the stack limit from the kernel. If it's "unlimited", | |
3563 | then we can do little else besides use the default. */ | |
3564 | { | |
3565 | struct rlimit lim; | |
3566 | if (getrlimit(RLIMIT_STACK, &lim) == 0 | |
3567 | && lim.rlim_cur != RLIM_INFINITY | |
3568 | && lim.rlim_cur == (target_long)lim.rlim_cur) { | |
3569 | guest_stack_size = lim.rlim_cur; | |
3570 | } | |
3571 | } | |
3572 | ||
3573 | cpu_model = NULL; | |
3574 | #if defined(cpudef_setup) | |
3575 | cpudef_setup(); /* parse cpu definitions in target config file (TBD) */ | |
3576 | #endif | |
3577 | ||
3578 | optind = parse_args(argc, argv); | |
3579 | ||
3580 | /* Zero out regs */ | |
3581 | memset(regs, 0, sizeof(struct target_pt_regs)); | |
3582 | ||
3583 | /* Zero out image_info */ | |
3584 | memset(info, 0, sizeof(struct image_info)); | |
3585 | ||
3586 | memset(&bprm, 0, sizeof (bprm)); | |
3587 | ||
3588 | /* Scan interp_prefix dir for replacement files. */ | |
3589 | init_paths(interp_prefix); | |
3590 | ||
3591 | if (cpu_model == NULL) { | |
3592 | #if defined(TARGET_I386) | |
3593 | #ifdef TARGET_X86_64 | |
3594 | cpu_model = "qemu64"; | |
3595 | #else | |
3596 | cpu_model = "qemu32"; | |
3597 | #endif | |
3598 | #elif defined(TARGET_ARM) | |
3599 | cpu_model = "any"; | |
3600 | #elif defined(TARGET_UNICORE32) | |
3601 | cpu_model = "any"; | |
3602 | #elif defined(TARGET_M68K) | |
3603 | cpu_model = "any"; | |
3604 | #elif defined(TARGET_SPARC) | |
3605 | #ifdef TARGET_SPARC64 | |
3606 | cpu_model = "TI UltraSparc II"; | |
3607 | #else | |
3608 | cpu_model = "Fujitsu MB86904"; | |
3609 | #endif | |
3610 | #elif defined(TARGET_MIPS) | |
3611 | #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) | |
3612 | cpu_model = "20Kc"; | |
3613 | #else | |
3614 | cpu_model = "24Kf"; | |
3615 | #endif | |
3616 | #elif defined TARGET_OPENRISC | |
3617 | cpu_model = "or1200"; | |
3618 | #elif defined(TARGET_PPC) | |
3619 | #ifdef TARGET_PPC64 | |
3620 | cpu_model = "970fx"; | |
3621 | #else | |
3622 | cpu_model = "750"; | |
3623 | #endif | |
3624 | #else | |
3625 | cpu_model = "any"; | |
3626 | #endif | |
3627 | } | |
3628 | tcg_exec_init(0); | |
3629 | cpu_exec_init_all(); | |
3630 | /* NOTE: we need to init the CPU at this stage to get | |
3631 | qemu_host_page_size */ | |
3632 | env = cpu_init(cpu_model); | |
3633 | if (!env) { | |
3634 | fprintf(stderr, "Unable to find CPU definition\n"); | |
3635 | exit(1); | |
3636 | } | |
3637 | cpu_reset(ENV_GET_CPU(env)); | |
3638 | ||
3639 | thread_cpu = ENV_GET_CPU(env); | |
3640 | ||
3641 | if (getenv("QEMU_STRACE")) { | |
3642 | do_strace = 1; | |
3643 | } | |
3644 | ||
3645 | target_environ = envlist_to_environ(envlist, NULL); | |
3646 | envlist_free(envlist); | |
3647 | ||
3648 | #if defined(CONFIG_USE_GUEST_BASE) | |
3649 | /* | |
3650 | * Now that page sizes are configured in cpu_init() we can do | |
3651 | * proper page alignment for guest_base. | |
3652 | */ | |
3653 | guest_base = HOST_PAGE_ALIGN(guest_base); | |
3654 | ||
3655 | if (reserved_va || have_guest_base) { | |
3656 | guest_base = init_guest_space(guest_base, reserved_va, 0, | |
3657 | have_guest_base); | |
3658 | if (guest_base == (unsigned long)-1) { | |
3659 | fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address " | |
3660 | "space for use as guest address space (check your virtual " | |
3661 | "memory ulimit setting or reserve less using -R option)\n", | |
3662 | reserved_va); | |
3663 | exit(1); | |
3664 | } | |
3665 | ||
3666 | if (reserved_va) { | |
3667 | mmap_next_start = reserved_va; | |
3668 | } | |
3669 | } | |
3670 | #endif /* CONFIG_USE_GUEST_BASE */ | |
3671 | ||
3672 | /* | |
3673 | * Read in mmap_min_addr kernel parameter. This value is used | |
3674 | * When loading the ELF image to determine whether guest_base | |
3675 | * is needed. It is also used in mmap_find_vma. | |
3676 | */ | |
3677 | { | |
3678 | FILE *fp; | |
3679 | ||
3680 | if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) { | |
3681 | unsigned long tmp; | |
3682 | if (fscanf(fp, "%lu", &tmp) == 1) { | |
3683 | mmap_min_addr = tmp; | |
3684 | qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr); | |
3685 | } | |
3686 | fclose(fp); | |
3687 | } | |
3688 | } | |
3689 | ||
3690 | /* | |
3691 | * Prepare copy of argv vector for target. | |
3692 | */ | |
3693 | target_argc = argc - optind; | |
3694 | target_argv = calloc(target_argc + 1, sizeof (char *)); | |
3695 | if (target_argv == NULL) { | |
3696 | (void) fprintf(stderr, "Unable to allocate memory for target_argv\n"); | |
3697 | exit(1); | |
3698 | } | |
3699 | ||
3700 | /* | |
3701 | * If argv0 is specified (using '-0' switch) we replace | |
3702 | * argv[0] pointer with the given one. | |
3703 | */ | |
3704 | i = 0; | |
3705 | if (argv0 != NULL) { | |
3706 | target_argv[i++] = strdup(argv0); | |
3707 | } | |
3708 | for (; i < target_argc; i++) { | |
3709 | target_argv[i] = strdup(argv[optind + i]); | |
3710 | } | |
3711 | target_argv[target_argc] = NULL; | |
3712 | ||
3713 | ts = g_malloc0 (sizeof(TaskState)); | |
3714 | init_task_state(ts); | |
3715 | /* build Task State */ | |
3716 | ts->info = info; | |
3717 | ts->bprm = &bprm; | |
3718 | env->opaque = ts; | |
3719 | task_settid(ts); | |
3720 | ||
3721 | ret = loader_exec(filename, target_argv, target_environ, regs, | |
3722 | info, &bprm); | |
3723 | if (ret != 0) { | |
3724 | printf("Error while loading %s: %s\n", filename, strerror(-ret)); | |
3725 | _exit(1); | |
3726 | } | |
3727 | ||
3728 | for (wrk = target_environ; *wrk; wrk++) { | |
3729 | free(*wrk); | |
3730 | } | |
3731 | ||
3732 | free(target_environ); | |
3733 | ||
3734 | if (qemu_log_enabled()) { | |
3735 | #if defined(CONFIG_USE_GUEST_BASE) | |
3736 | qemu_log("guest_base 0x%lx\n", guest_base); | |
3737 | #endif | |
3738 | log_page_dump(); | |
3739 | ||
3740 | qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); | |
3741 | qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code); | |
3742 | qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", | |
3743 | info->start_code); | |
3744 | qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", | |
3745 | info->start_data); | |
3746 | qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data); | |
3747 | qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", | |
3748 | info->start_stack); | |
3749 | qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk); | |
3750 | qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry); | |
3751 | } | |
3752 | ||
3753 | target_set_brk(info->brk); | |
3754 | syscall_init(); | |
3755 | signal_init(); | |
3756 | ||
3757 | #if defined(CONFIG_USE_GUEST_BASE) | |
3758 | /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay | |
3759 | generating the prologue until now so that the prologue can take | |
3760 | the real value of GUEST_BASE into account. */ | |
3761 | tcg_prologue_init(&tcg_ctx); | |
3762 | #endif | |
3763 | ||
3764 | #if defined(TARGET_I386) | |
3765 | cpu_x86_set_cpl(env, 3); | |
3766 | ||
3767 | env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; | |
3768 | env->hflags |= HF_PE_MASK; | |
3769 | if (env->features[FEAT_1_EDX] & CPUID_SSE) { | |
3770 | env->cr[4] |= CR4_OSFXSR_MASK; | |
3771 | env->hflags |= HF_OSFXSR_MASK; | |
3772 | } | |
3773 | #ifndef TARGET_ABI32 | |
3774 | /* enable 64 bit mode if possible */ | |
3775 | if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) { | |
3776 | fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n"); | |
3777 | exit(1); | |
3778 | } | |
3779 | env->cr[4] |= CR4_PAE_MASK; | |
3780 | env->efer |= MSR_EFER_LMA | MSR_EFER_LME; | |
3781 | env->hflags |= HF_LMA_MASK; | |
3782 | #endif | |
3783 | ||
3784 | /* flags setup : we activate the IRQs by default as in user mode */ | |
3785 | env->eflags |= IF_MASK; | |
3786 | ||
3787 | /* linux register setup */ | |
3788 | #ifndef TARGET_ABI32 | |
3789 | env->regs[R_EAX] = regs->rax; | |
3790 | env->regs[R_EBX] = regs->rbx; | |
3791 | env->regs[R_ECX] = regs->rcx; | |
3792 | env->regs[R_EDX] = regs->rdx; | |
3793 | env->regs[R_ESI] = regs->rsi; | |
3794 | env->regs[R_EDI] = regs->rdi; | |
3795 | env->regs[R_EBP] = regs->rbp; | |
3796 | env->regs[R_ESP] = regs->rsp; | |
3797 | env->eip = regs->rip; | |
3798 | #else | |
3799 | env->regs[R_EAX] = regs->eax; | |
3800 | env->regs[R_EBX] = regs->ebx; | |
3801 | env->regs[R_ECX] = regs->ecx; | |
3802 | env->regs[R_EDX] = regs->edx; | |
3803 | env->regs[R_ESI] = regs->esi; | |
3804 | env->regs[R_EDI] = regs->edi; | |
3805 | env->regs[R_EBP] = regs->ebp; | |
3806 | env->regs[R_ESP] = regs->esp; | |
3807 | env->eip = regs->eip; | |
3808 | #endif | |
3809 | ||
3810 | /* linux interrupt setup */ | |
3811 | #ifndef TARGET_ABI32 | |
3812 | env->idt.limit = 511; | |
3813 | #else | |
3814 | env->idt.limit = 255; | |
3815 | #endif | |
3816 | env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), | |
3817 | PROT_READ|PROT_WRITE, | |
3818 | MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); | |
3819 | idt_table = g2h(env->idt.base); | |
3820 | set_idt(0, 0); | |
3821 | set_idt(1, 0); | |
3822 | set_idt(2, 0); | |
3823 | set_idt(3, 3); | |
3824 | set_idt(4, 3); | |
3825 | set_idt(5, 0); | |
3826 | set_idt(6, 0); | |
3827 | set_idt(7, 0); | |
3828 | set_idt(8, 0); | |
3829 | set_idt(9, 0); | |
3830 | set_idt(10, 0); | |
3831 | set_idt(11, 0); | |
3832 | set_idt(12, 0); | |
3833 | set_idt(13, 0); | |
3834 | set_idt(14, 0); | |
3835 | set_idt(15, 0); | |
3836 | set_idt(16, 0); | |
3837 | set_idt(17, 0); | |
3838 | set_idt(18, 0); | |
3839 | set_idt(19, 0); | |
3840 | set_idt(0x80, 3); | |
3841 | ||
3842 | /* linux segment setup */ | |
3843 | { | |
3844 | uint64_t *gdt_table; | |
3845 | env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, | |
3846 | PROT_READ|PROT_WRITE, | |
3847 | MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); | |
3848 | env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; | |
3849 | gdt_table = g2h(env->gdt.base); | |
3850 | #ifdef TARGET_ABI32 | |
3851 | write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, | |
3852 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | | |
3853 | (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); | |
3854 | #else | |
3855 | /* 64 bit code segment */ | |
3856 | write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, | |
3857 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | | |
3858 | DESC_L_MASK | | |
3859 | (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); | |
3860 | #endif | |
3861 | write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, | |
3862 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | | |
3863 | (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); | |
3864 | } | |
3865 | cpu_x86_load_seg(env, R_CS, __USER_CS); | |
3866 | cpu_x86_load_seg(env, R_SS, __USER_DS); | |
3867 | #ifdef TARGET_ABI32 | |
3868 | cpu_x86_load_seg(env, R_DS, __USER_DS); | |
3869 | cpu_x86_load_seg(env, R_ES, __USER_DS); | |
3870 | cpu_x86_load_seg(env, R_FS, __USER_DS); | |
3871 | cpu_x86_load_seg(env, R_GS, __USER_DS); | |
3872 | /* This hack makes Wine work... */ | |
3873 | env->segs[R_FS].selector = 0; | |
3874 | #else | |
3875 | cpu_x86_load_seg(env, R_DS, 0); | |
3876 | cpu_x86_load_seg(env, R_ES, 0); | |
3877 | cpu_x86_load_seg(env, R_FS, 0); | |
3878 | cpu_x86_load_seg(env, R_GS, 0); | |
3879 | #endif | |
3880 | #elif defined(TARGET_ARM) | |
3881 | { | |
3882 | int i; | |
3883 | cpsr_write(env, regs->uregs[16], 0xffffffff); | |
3884 | for(i = 0; i < 16; i++) { | |
3885 | env->regs[i] = regs->uregs[i]; | |
3886 | } | |
3887 | /* Enable BE8. */ | |
3888 | if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4 | |
3889 | && (info->elf_flags & EF_ARM_BE8)) { | |
3890 | env->bswap_code = 1; | |
3891 | } | |
3892 | } | |
3893 | #elif defined(TARGET_UNICORE32) | |
3894 | { | |
3895 | int i; | |
3896 | cpu_asr_write(env, regs->uregs[32], 0xffffffff); | |
3897 | for (i = 0; i < 32; i++) { | |
3898 | env->regs[i] = regs->uregs[i]; | |
3899 | } | |
3900 | } | |
3901 | #elif defined(TARGET_SPARC) | |
3902 | { | |
3903 | int i; | |
3904 | env->pc = regs->pc; | |
3905 | env->npc = regs->npc; | |
3906 | env->y = regs->y; | |
3907 | for(i = 0; i < 8; i++) | |
3908 | env->gregs[i] = regs->u_regs[i]; | |
3909 | for(i = 0; i < 8; i++) | |
3910 | env->regwptr[i] = regs->u_regs[i + 8]; | |
3911 | } | |
3912 | #elif defined(TARGET_PPC) | |
3913 | { | |
3914 | int i; | |
3915 | ||
3916 | #if defined(TARGET_PPC64) | |
3917 | #if defined(TARGET_ABI32) | |
3918 | env->msr &= ~((target_ulong)1 << MSR_SF); | |
3919 | #else | |
3920 | env->msr |= (target_ulong)1 << MSR_SF; | |
3921 | #endif | |
3922 | #endif | |
3923 | env->nip = regs->nip; | |
3924 | for(i = 0; i < 32; i++) { | |
3925 | env->gpr[i] = regs->gpr[i]; | |
3926 | } | |
3927 | } | |
3928 | #elif defined(TARGET_M68K) | |
3929 | { | |
3930 | env->pc = regs->pc; | |
3931 | env->dregs[0] = regs->d0; | |
3932 | env->dregs[1] = regs->d1; | |
3933 | env->dregs[2] = regs->d2; | |
3934 | env->dregs[3] = regs->d3; | |
3935 | env->dregs[4] = regs->d4; | |
3936 | env->dregs[5] = regs->d5; | |
3937 | env->dregs[6] = regs->d6; | |
3938 | env->dregs[7] = regs->d7; | |
3939 | env->aregs[0] = regs->a0; | |
3940 | env->aregs[1] = regs->a1; | |
3941 | env->aregs[2] = regs->a2; | |
3942 | env->aregs[3] = regs->a3; | |
3943 | env->aregs[4] = regs->a4; | |
3944 | env->aregs[5] = regs->a5; | |
3945 | env->aregs[6] = regs->a6; | |
3946 | env->aregs[7] = regs->usp; | |
3947 | env->sr = regs->sr; | |
3948 | ts->sim_syscalls = 1; | |
3949 | } | |
3950 | #elif defined(TARGET_MICROBLAZE) | |
3951 | { | |
3952 | env->regs[0] = regs->r0; | |
3953 | env->regs[1] = regs->r1; | |
3954 | env->regs[2] = regs->r2; | |
3955 | env->regs[3] = regs->r3; | |
3956 | env->regs[4] = regs->r4; | |
3957 | env->regs[5] = regs->r5; | |
3958 | env->regs[6] = regs->r6; | |
3959 | env->regs[7] = regs->r7; | |
3960 | env->regs[8] = regs->r8; | |
3961 | env->regs[9] = regs->r9; | |
3962 | env->regs[10] = regs->r10; | |
3963 | env->regs[11] = regs->r11; | |
3964 | env->regs[12] = regs->r12; | |
3965 | env->regs[13] = regs->r13; | |
3966 | env->regs[14] = regs->r14; | |
3967 | env->regs[15] = regs->r15; | |
3968 | env->regs[16] = regs->r16; | |
3969 | env->regs[17] = regs->r17; | |
3970 | env->regs[18] = regs->r18; | |
3971 | env->regs[19] = regs->r19; | |
3972 | env->regs[20] = regs->r20; | |
3973 | env->regs[21] = regs->r21; | |
3974 | env->regs[22] = regs->r22; | |
3975 | env->regs[23] = regs->r23; | |
3976 | env->regs[24] = regs->r24; | |
3977 | env->regs[25] = regs->r25; | |
3978 | env->regs[26] = regs->r26; | |
3979 | env->regs[27] = regs->r27; | |
3980 | env->regs[28] = regs->r28; | |
3981 | env->regs[29] = regs->r29; | |
3982 | env->regs[30] = regs->r30; | |
3983 | env->regs[31] = regs->r31; | |
3984 | env->sregs[SR_PC] = regs->pc; | |
3985 | } | |
3986 | #elif defined(TARGET_MIPS) | |
3987 | { | |
3988 | int i; | |
3989 | ||
3990 | for(i = 0; i < 32; i++) { | |
3991 | env->active_tc.gpr[i] = regs->regs[i]; | |
3992 | } | |
3993 | env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1; | |
3994 | if (regs->cp0_epc & 1) { | |
3995 | env->hflags |= MIPS_HFLAG_M16; | |
3996 | } | |
3997 | } | |
3998 | #elif defined(TARGET_OPENRISC) | |
3999 | { | |
4000 | int i; | |
4001 | ||
4002 | for (i = 0; i < 32; i++) { | |
4003 | env->gpr[i] = regs->gpr[i]; | |
4004 | } | |
4005 | ||
4006 | env->sr = regs->sr; | |
4007 | env->pc = regs->pc; | |
4008 | } | |
4009 | #elif defined(TARGET_SH4) | |
4010 | { | |
4011 | int i; | |
4012 | ||
4013 | for(i = 0; i < 16; i++) { | |
4014 | env->gregs[i] = regs->regs[i]; | |
4015 | } | |
4016 | env->pc = regs->pc; | |
4017 | } | |
4018 | #elif defined(TARGET_ALPHA) | |
4019 | { | |
4020 | int i; | |
4021 | ||
4022 | for(i = 0; i < 28; i++) { | |
4023 | env->ir[i] = ((abi_ulong *)regs)[i]; | |
4024 | } | |
4025 | env->ir[IR_SP] = regs->usp; | |
4026 | env->pc = regs->pc; | |
4027 | } | |
4028 | #elif defined(TARGET_CRIS) | |
4029 | { | |
4030 | env->regs[0] = regs->r0; | |
4031 | env->regs[1] = regs->r1; | |
4032 | env->regs[2] = regs->r2; | |
4033 | env->regs[3] = regs->r3; | |
4034 | env->regs[4] = regs->r4; | |
4035 | env->regs[5] = regs->r5; | |
4036 | env->regs[6] = regs->r6; | |
4037 | env->regs[7] = regs->r7; | |
4038 | env->regs[8] = regs->r8; | |
4039 | env->regs[9] = regs->r9; | |
4040 | env->regs[10] = regs->r10; | |
4041 | env->regs[11] = regs->r11; | |
4042 | env->regs[12] = regs->r12; | |
4043 | env->regs[13] = regs->r13; | |
4044 | env->regs[14] = info->start_stack; | |
4045 | env->regs[15] = regs->acr; | |
4046 | env->pc = regs->erp; | |
4047 | } | |
4048 | #elif defined(TARGET_S390X) | |
4049 | { | |
4050 | int i; | |
4051 | for (i = 0; i < 16; i++) { | |
4052 | env->regs[i] = regs->gprs[i]; | |
4053 | } | |
4054 | env->psw.mask = regs->psw.mask; | |
4055 | env->psw.addr = regs->psw.addr; | |
4056 | } | |
4057 | #else | |
4058 | #error unsupported target CPU | |
4059 | #endif | |
4060 | ||
4061 | #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32) | |
4062 | ts->stack_base = info->start_stack; | |
4063 | ts->heap_base = info->brk; | |
4064 | /* This will be filled in on the first SYS_HEAPINFO call. */ | |
4065 | ts->heap_limit = 0; | |
4066 | #endif | |
4067 | ||
4068 | if (gdbstub_port) { | |
4069 | if (gdbserver_start(gdbstub_port) < 0) { | |
4070 | fprintf(stderr, "qemu: could not open gdbserver on port %d\n", | |
4071 | gdbstub_port); | |
4072 | exit(1); | |
4073 | } | |
4074 | gdb_handlesig(env, 0); | |
4075 | } | |
4076 | cpu_loop(env); | |
4077 | /* never exits */ | |
4078 | return 0; | |
4079 | } |