[qemu.git] / softmmu_template.h

/*
 *  Software MMU support
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include "qemu-timer.h"

#define DATA_SIZE (1 << SHIFT)

#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#else
#error unsupported data size
#endif

#ifdef SOFTMMU_CODE_ACCESS
#define READ_ACCESS_TYPE 2
#define ADDR_READ addr_code
#else
#define READ_ACCESS_TYPE 0
#define ADDR_READ addr_read
#endif

static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                        int mmu_idx,
                                                        void *retaddr);
static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
                                              target_ulong addr,
                                              void *retaddr)
{
    DATA_TYPE res;
    int index;
    index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
    env->mem_io_pc = (unsigned long)retaddr;
    if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
            && !can_do_io(env)) {
        cpu_io_recompile(env, retaddr);
    }

    env->mem_io_vaddr = addr;
#if SHIFT <= 2
    res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
    res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
#else
    res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
    res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
#endif
#endif /* SHIFT > 2 */
    return res;
}

/* handle all cases except unaligned access which span two pages */
DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                      int mmu_idx)
{
    DATA_TYPE res;
    int index;
    target_ulong tlb_addr;
    target_phys_addr_t ioaddr;
    unsigned long addend;
    void *retaddr;

    /* test if there is match for unaligned or IO access */
    /* XXX: could done more in memory macro in a non portable way */
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            retaddr = GETPC();
            ioaddr = env->iotlb[mmu_idx][index];
            res = glue(io_read, SUFFIX)(ioaddr, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
            /* slow unaligned access (it spans two pages or IO) */
        do_unaligned_access:
            retaddr = GETPC();
#ifdef ALIGNED_ONLY
            do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
            res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
                                                         mmu_idx, retaddr);
        } else {
            /* unaligned/aligned access in the same page */
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                retaddr = GETPC();
                do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
            }
#endif
            addend = env->tlb_table[mmu_idx][index].addend;
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
        tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        goto redo;
    }
    return res;
}

/* handle all unaligned cases */
static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                        int mmu_idx,
                                                        void *retaddr)
{
    DATA_TYPE res, res1, res2;
    int index, shift;
    target_phys_addr_t ioaddr;
    unsigned long addend;
    target_ulong tlb_addr, addr1, addr2;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            ioaddr = env->iotlb[mmu_idx][index];
            res = glue(io_read, SUFFIX)(ioaddr, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* slow unaligned access (it spans two pages) */
            addr1 = addr & ~(DATA_SIZE - 1);
            addr2 = addr1 + DATA_SIZE;
            res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
                                                          mmu_idx, retaddr);
            res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
                                                          mmu_idx, retaddr);
            shift = (addr & (DATA_SIZE - 1)) * 8;
#ifdef TARGET_WORDS_BIGENDIAN
            res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
#else
            res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
#endif
            res = (DATA_TYPE)res;
        } else {
            /* unaligned/aligned access in the same page */
            addend = env->tlb_table[mmu_idx][index].addend;
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        goto redo;
    }
    return res;
}

#ifndef SOFTMMU_CODE_ACCESS

static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                   DATA_TYPE val,
                                                   int mmu_idx,
                                                   void *retaddr);

static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
                                          DATA_TYPE val,
                                          target_ulong addr,
                                          void *retaddr)
{
    int index;
    index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
    if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
            && !can_do_io(env)) {
        cpu_io_recompile(env, retaddr);
    }

    env->mem_io_vaddr = addr;
    env->mem_io_pc = (unsigned long)retaddr;
#if SHIFT <= 2
    io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
#else
    io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
#endif
#endif /* SHIFT > 2 */
}

void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                 DATA_TYPE val,
                                                 int mmu_idx)
{
    target_phys_addr_t ioaddr;
    unsigned long addend;
    target_ulong tlb_addr;
    void *retaddr;
    int index;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            retaddr = GETPC();
            ioaddr = env->iotlb[mmu_idx][index];
            glue(io_write, SUFFIX)(ioaddr, val, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            retaddr = GETPC();
#ifdef ALIGNED_ONLY
            do_unaligned_access(addr, 1, mmu_idx, retaddr);
#endif
            glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
                                                   mmu_idx, retaddr);
        } else {
            /* aligned/unaligned access in the same page */
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                retaddr = GETPC();
                do_unaligned_access(addr, 1, mmu_idx, retaddr);
            }
#endif
            addend = env->tlb_table[mmu_idx][index].addend;
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(addr, 1, mmu_idx, retaddr);
#endif
        tlb_fill(addr, 1, mmu_idx, retaddr);
        goto redo;
    }
}

/* handles all unaligned cases */
static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                   DATA_TYPE val,
                                                   int mmu_idx,
                                                   void *retaddr)
{
    target_phys_addr_t ioaddr;
    unsigned long addend;
    target_ulong tlb_addr;
    int index, i;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            ioaddr = env->iotlb[mmu_idx][index];
            glue(io_write, SUFFIX)(ioaddr, val, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* XXX: not efficient, but simple */
            /* Note: relies on the fact that tlb_fill() does not remove the
             * previous page from the TLB cache.  */
            for(i = DATA_SIZE - 1; i >= 0; i--) {
#ifdef TARGET_WORDS_BIGENDIAN
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
                                          mmu_idx, retaddr);
#else
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
                                          mmu_idx, retaddr);
#endif
            }
        } else {
            /* aligned/unaligned access in the same page */
            addend = env->tlb_table[mmu_idx][index].addend;
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(addr, 1, mmu_idx, retaddr);
        goto redo;
    }
}

#endif /* !defined(SOFTMMU_CODE_ACCESS) */

#undef READ_ACCESS_TYPE
#undef SHIFT
#undef DATA_TYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
#undef ADDR_READ
Commit	Line	Data
	1	/*
	2	* Software MMU support
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#include "qemu-timer.h"
	20
	21	#define DATA_SIZE (1 << SHIFT)
	22
	23	#if DATA_SIZE == 8
	24	#define SUFFIX q
	25	#define USUFFIX q
	26	#define DATA_TYPE uint64_t
	27	#elif DATA_SIZE == 4
	28	#define SUFFIX l
	29	#define USUFFIX l
	30	#define DATA_TYPE uint32_t
	31	#elif DATA_SIZE == 2
	32	#define SUFFIX w
	33	#define USUFFIX uw
	34	#define DATA_TYPE uint16_t
	35	#elif DATA_SIZE == 1
	36	#define SUFFIX b
	37	#define USUFFIX ub
	38	#define DATA_TYPE uint8_t
	39	#else
	40	#error unsupported data size
	41	#endif
	42
	43	#ifdef SOFTMMU_CODE_ACCESS
	44	#define READ_ACCESS_TYPE 2
	45	#define ADDR_READ addr_code
	46	#else
	47	#define READ_ACCESS_TYPE 0
	48	#define ADDR_READ addr_read
	49	#endif
	50
	51	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
	52	int mmu_idx,
	53	void *retaddr);
	54	static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
	55	target_ulong addr,
	56	void *retaddr)
	57	{
	58	DATA_TYPE res;
	59	int index;
	60	index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
	61	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
	62	env->mem_io_pc = (unsigned long)retaddr;
	63	if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
	64	&& !can_do_io(env)) {
	65	cpu_io_recompile(env, retaddr);
	66	}
	67
	68	env->mem_io_vaddr = addr;
	69	#if SHIFT <= 2
	70	res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
	71	#else
	72	#ifdef TARGET_WORDS_BIGENDIAN
	73	res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
	74	res \|= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
	75	#else
	76	res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
	77	res \|= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
	78	#endif
	79	#endif /* SHIFT > 2 */
	80	return res;
	81	}
	82
	83	/* handle all cases except unaligned access which span two pages */
	84	DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
	85	int mmu_idx)
	86	{
	87	DATA_TYPE res;
	88	int index;
	89	target_ulong tlb_addr;
	90	target_phys_addr_t ioaddr;
	91	unsigned long addend;
	92	void *retaddr;
	93
	94	/* test if there is match for unaligned or IO access */
	95	/* XXX: could done more in memory macro in a non portable way */
	96	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	97	redo:
	98	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
	99	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
	100	if (tlb_addr & ~TARGET_PAGE_MASK) {
	101	/* IO access */
	102	if ((addr & (DATA_SIZE - 1)) != 0)
	103	goto do_unaligned_access;
	104	retaddr = GETPC();
	105	ioaddr = env->iotlb[mmu_idx][index];
	106	res = glue(io_read, SUFFIX)(ioaddr, addr, retaddr);
	107	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
	108	/* slow unaligned access (it spans two pages or IO) */
	109	do_unaligned_access:
	110	retaddr = GETPC();
	111	#ifdef ALIGNED_ONLY
	112	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
	113	#endif
	114	res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
	115	mmu_idx, retaddr);
	116	} else {
	117	/* unaligned/aligned access in the same page */
	118	#ifdef ALIGNED_ONLY
	119	if ((addr & (DATA_SIZE - 1)) != 0) {
	120	retaddr = GETPC();
	121	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
	122	}
	123	#endif
	124	addend = env->tlb_table[mmu_idx][index].addend;
	125	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
	126	}
	127	} else {
	128	/* the page is not in the TLB : fill it */
	129	retaddr = GETPC();
	130	#ifdef ALIGNED_ONLY
	131	if ((addr & (DATA_SIZE - 1)) != 0)
	132	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
	133	#endif
	134	tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
	135	goto redo;
	136	}
	137	return res;
	138	}
	139
	140	/* handle all unaligned cases */
	141	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
	142	int mmu_idx,
	143	void *retaddr)
	144	{
	145	DATA_TYPE res, res1, res2;
	146	int index, shift;
	147	target_phys_addr_t ioaddr;
	148	unsigned long addend;
	149	target_ulong tlb_addr, addr1, addr2;
	150
	151	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	152	redo:
	153	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
	154	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
	155	if (tlb_addr & ~TARGET_PAGE_MASK) {
	156	/* IO access */
	157	if ((addr & (DATA_SIZE - 1)) != 0)
	158	goto do_unaligned_access;
	159	ioaddr = env->iotlb[mmu_idx][index];
	160	res = glue(io_read, SUFFIX)(ioaddr, addr, retaddr);
	161	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
	162	do_unaligned_access:
	163	/* slow unaligned access (it spans two pages) */
	164	addr1 = addr & ~(DATA_SIZE - 1);
	165	addr2 = addr1 + DATA_SIZE;
	166	res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
	167	mmu_idx, retaddr);
	168	res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
	169	mmu_idx, retaddr);
	170	shift = (addr & (DATA_SIZE - 1)) * 8;
	171	#ifdef TARGET_WORDS_BIGENDIAN
	172	res = (res1 << shift) \| (res2 >> ((DATA_SIZE * 8) - shift));
	173	#else
	174	res = (res1 >> shift) \| (res2 << ((DATA_SIZE * 8) - shift));
	175	#endif
	176	res = (DATA_TYPE)res;
	177	} else {
	178	/* unaligned/aligned access in the same page */
	179	addend = env->tlb_table[mmu_idx][index].addend;
	180	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
	181	}
	182	} else {
	183	/* the page is not in the TLB : fill it */
	184	tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
	185	goto redo;
	186	}
	187	return res;
	188	}
	189
	190	#ifndef SOFTMMU_CODE_ACCESS
	191
	192	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
	193	DATA_TYPE val,
	194	int mmu_idx,
	195	void *retaddr);
	196
	197	static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
	198	DATA_TYPE val,
	199	target_ulong addr,
	200	void *retaddr)
	201	{
	202	int index;
	203	index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
	204	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
	205	if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
	206	&& !can_do_io(env)) {
	207	cpu_io_recompile(env, retaddr);
	208	}
	209
	210	env->mem_io_vaddr = addr;
	211	env->mem_io_pc = (unsigned long)retaddr;
	212	#if SHIFT <= 2
	213	io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
	214	#else
	215	#ifdef TARGET_WORDS_BIGENDIAN
	216	io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
	217	io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
	218	#else
	219	io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
	220	io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
	221	#endif
	222	#endif /* SHIFT > 2 */
	223	}
	224
	225	void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
	226	DATA_TYPE val,
	227	int mmu_idx)
	228	{
	229	target_phys_addr_t ioaddr;
	230	unsigned long addend;
	231	target_ulong tlb_addr;
	232	void *retaddr;
	233	int index;
	234
	235	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	236	redo:
	237	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
	238	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
	239	if (tlb_addr & ~TARGET_PAGE_MASK) {
	240	/* IO access */
	241	if ((addr & (DATA_SIZE - 1)) != 0)
	242	goto do_unaligned_access;
	243	retaddr = GETPC();
	244	ioaddr = env->iotlb[mmu_idx][index];
	245	glue(io_write, SUFFIX)(ioaddr, val, addr, retaddr);
	246	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
	247	do_unaligned_access:
	248	retaddr = GETPC();
	249	#ifdef ALIGNED_ONLY
	250	do_unaligned_access(addr, 1, mmu_idx, retaddr);
	251	#endif
	252	glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
	253	mmu_idx, retaddr);
	254	} else {
	255	/* aligned/unaligned access in the same page */
	256	#ifdef ALIGNED_ONLY
	257	if ((addr & (DATA_SIZE - 1)) != 0) {
	258	retaddr = GETPC();
	259	do_unaligned_access(addr, 1, mmu_idx, retaddr);
	260	}
	261	#endif
	262	addend = env->tlb_table[mmu_idx][index].addend;
	263	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
	264	}
	265	} else {
	266	/* the page is not in the TLB : fill it */
	267	retaddr = GETPC();
	268	#ifdef ALIGNED_ONLY
	269	if ((addr & (DATA_SIZE - 1)) != 0)
	270	do_unaligned_access(addr, 1, mmu_idx, retaddr);
	271	#endif
	272	tlb_fill(addr, 1, mmu_idx, retaddr);
	273	goto redo;
	274	}
	275	}
	276
	277	/* handles all unaligned cases */
	278	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
	279	DATA_TYPE val,
	280	int mmu_idx,
	281	void *retaddr)
	282	{
	283	target_phys_addr_t ioaddr;
	284	unsigned long addend;
	285	target_ulong tlb_addr;
	286	int index, i;
	287
	288	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	289	redo:
	290	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
	291	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
	292	if (tlb_addr & ~TARGET_PAGE_MASK) {
	293	/* IO access */
	294	if ((addr & (DATA_SIZE - 1)) != 0)
	295	goto do_unaligned_access;
	296	ioaddr = env->iotlb[mmu_idx][index];
	297	glue(io_write, SUFFIX)(ioaddr, val, addr, retaddr);
	298	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
	299	do_unaligned_access:
	300	/* XXX: not efficient, but simple */
	301	/* Note: relies on the fact that tlb_fill() does not remove the
	302	* previous page from the TLB cache. */
	303	for(i = DATA_SIZE - 1; i >= 0; i--) {
	304	#ifdef TARGET_WORDS_BIGENDIAN
	305	glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
	306	mmu_idx, retaddr);
	307	#else
	308	glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
	309	mmu_idx, retaddr);
	310	#endif
	311	}
	312	} else {
	313	/* aligned/unaligned access in the same page */
	314	addend = env->tlb_table[mmu_idx][index].addend;
	315	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
	316	}
	317	} else {
	318	/* the page is not in the TLB : fill it */
	319	tlb_fill(addr, 1, mmu_idx, retaddr);
	320	goto redo;
	321	}
	322	}
	323
	324	#endif /* !defined(SOFTMMU_CODE_ACCESS) */
	325
	326	#undef READ_ACCESS_TYPE
	327	#undef SHIFT
	328	#undef DATA_TYPE
	329	#undef SUFFIX
	330	#undef USUFFIX
	331	#undef DATA_SIZE
	332	#undef ADDR_READ