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1 | /* | |
2 | * CRIS helper routines. | |
3 | * | |
4 | * Copyright (c) 2007 AXIS Communications AB | |
5 | * Written by Edgar E. Iglesias. | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | ||
25 | #include "config.h" | |
26 | #include "cpu.h" | |
27 | #include "mmu.h" | |
28 | #include "exec-all.h" | |
29 | ||
30 | #if defined(CONFIG_USER_ONLY) | |
31 | ||
32 | void do_interrupt (CPUState *env) | |
33 | { | |
34 | env->exception_index = -1; | |
35 | } | |
36 | ||
37 | int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw, | |
38 | int is_user, int is_softmmu) | |
39 | { | |
40 | env->exception_index = 0xaa; | |
41 | env->debug1 = address; | |
42 | cpu_dump_state(env, stderr, fprintf, 0); | |
43 | printf("%s addr=%x env->pc=%x\n", __func__, address, env->pc); | |
44 | return 1; | |
45 | } | |
46 | ||
47 | target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) | |
48 | { | |
49 | return addr; | |
50 | } | |
51 | ||
52 | #else /* !CONFIG_USER_ONLY */ | |
53 | ||
54 | int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw, | |
55 | int is_user, int is_softmmu) | |
56 | { | |
57 | struct cris_mmu_result_t res; | |
58 | int prot, miss; | |
59 | target_ulong phy; | |
60 | ||
61 | address &= TARGET_PAGE_MASK; | |
62 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
63 | // printf ("%s pc=%x %x w=%d smmu=%d\n", __func__, env->pc, address, rw, is_softmmu); | |
64 | miss = cris_mmu_translate(&res, env, address, rw, is_user); | |
65 | if (miss) | |
66 | { | |
67 | /* handle the miss. */ | |
68 | phy = 0; | |
69 | env->exception_index = EXCP_MMU_MISS; | |
70 | } | |
71 | else | |
72 | { | |
73 | phy = res.phy; | |
74 | } | |
75 | // printf ("a=%x phy=%x\n", address, phy); | |
76 | return tlb_set_page(env, address, phy, prot, is_user, is_softmmu); | |
77 | } | |
78 | ||
79 | ||
80 | static void cris_shift_ccs(CPUState *env) | |
81 | { | |
82 | uint32_t ccs; | |
83 | /* Apply the ccs shift. */ | |
84 | ccs = env->pregs[SR_CCS]; | |
85 | ccs = (ccs & 0xc0000000) | ((ccs << 12) >> 2); | |
86 | // printf ("ccs=%x %x\n", env->pregs[SR_CCS], ccs); | |
87 | env->pregs[SR_CCS] = ccs; | |
88 | } | |
89 | ||
90 | void do_interrupt(CPUState *env) | |
91 | { | |
92 | uint32_t ebp, isr; | |
93 | int irqnum; | |
94 | ||
95 | fflush(NULL); | |
96 | ||
97 | #if 0 | |
98 | printf ("exception index=%d interrupt_req=%d\n", | |
99 | env->exception_index, | |
100 | env->interrupt_request); | |
101 | #endif | |
102 | ||
103 | switch (env->exception_index) | |
104 | { | |
105 | case EXCP_BREAK: | |
106 | // printf ("BREAK! %d\n", env->trapnr); | |
107 | irqnum = env->trapnr; | |
108 | ebp = env->pregs[SR_EBP]; | |
109 | isr = ldl_code(ebp + irqnum * 4); | |
110 | env->pregs[SR_ERP] = env->pc + 2; | |
111 | env->pc = isr; | |
112 | ||
113 | cris_shift_ccs(env); | |
114 | ||
115 | break; | |
116 | case EXCP_MMU_MISS: | |
117 | // printf ("MMU miss\n"); | |
118 | irqnum = 4; | |
119 | ebp = env->pregs[SR_EBP]; | |
120 | isr = ldl_code(ebp + irqnum * 4); | |
121 | env->pregs[SR_ERP] = env->pc; | |
122 | env->pc = isr; | |
123 | cris_shift_ccs(env); | |
124 | break; | |
125 | ||
126 | default: | |
127 | { | |
128 | /* Maybe the irq was acked by sw before we got a | |
129 | change to take it. */ | |
130 | if (env->interrupt_request & CPU_INTERRUPT_HARD) { | |
131 | if (!env->pending_interrupts) | |
132 | return; | |
133 | if (!(env->pregs[SR_CCS] & I_FLAG)) { | |
134 | return; | |
135 | } | |
136 | ||
137 | irqnum = 31 - | |
138 | __builtin_clz(env->pending_interrupts); | |
139 | irqnum += 0x30; | |
140 | ebp = env->pregs[SR_EBP]; | |
141 | isr = ldl_code(ebp + irqnum * 4); | |
142 | env->pregs[SR_ERP] = env->pc; | |
143 | env->pc = isr; | |
144 | ||
145 | cris_shift_ccs(env); | |
146 | #if 0 | |
147 | printf ("%s ebp=%x %x isr=%x %d" | |
148 | " ir=%x pending=%x\n", | |
149 | __func__, | |
150 | ebp, ebp + irqnum * 4, | |
151 | isr, env->exception_index, | |
152 | env->interrupt_request, | |
153 | env->pending_interrupts); | |
154 | #endif | |
155 | } | |
156 | ||
157 | } | |
158 | break; | |
159 | } | |
160 | } | |
161 | ||
162 | target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) | |
163 | { | |
164 | // printf ("%s\n", __func__); | |
165 | uint32_t phy = addr; | |
166 | struct cris_mmu_result_t res; | |
167 | int miss; | |
168 | miss = cris_mmu_translate(&res, env, addr, 0, 0); | |
169 | if (!miss) | |
170 | phy = res.phy; | |
171 | return phy; | |
172 | } | |
173 | #endif |