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1 | /* | |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <sys/types.h> | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
18 | #include <sys/utsname.h> | |
19 | ||
20 | #include <linux/kvm.h> | |
21 | #include <linux/kvm_para.h> | |
22 | ||
23 | #include "qemu-common.h" | |
24 | #include "sysemu.h" | |
25 | #include "kvm.h" | |
26 | #include "cpu.h" | |
27 | #include "gdbstub.h" | |
28 | #include "host-utils.h" | |
29 | #include "hw/pc.h" | |
30 | #include "hw/apic.h" | |
31 | #include "ioport.h" | |
32 | ||
33 | //#define DEBUG_KVM | |
34 | ||
35 | #ifdef DEBUG_KVM | |
36 | #define DPRINTF(fmt, ...) \ | |
37 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) | |
38 | #else | |
39 | #define DPRINTF(fmt, ...) \ | |
40 | do { } while (0) | |
41 | #endif | |
42 | ||
43 | #define MSR_KVM_WALL_CLOCK 0x11 | |
44 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
45 | ||
46 | #ifndef BUS_MCEERR_AR | |
47 | #define BUS_MCEERR_AR 4 | |
48 | #endif | |
49 | #ifndef BUS_MCEERR_AO | |
50 | #define BUS_MCEERR_AO 5 | |
51 | #endif | |
52 | ||
53 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { | |
54 | KVM_CAP_INFO(SET_TSS_ADDR), | |
55 | KVM_CAP_INFO(EXT_CPUID), | |
56 | KVM_CAP_INFO(MP_STATE), | |
57 | KVM_CAP_LAST_INFO | |
58 | }; | |
59 | ||
60 | static bool has_msr_star; | |
61 | static bool has_msr_hsave_pa; | |
62 | static bool has_msr_async_pf_en; | |
63 | static int lm_capable_kernel; | |
64 | ||
65 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) | |
66 | { | |
67 | struct kvm_cpuid2 *cpuid; | |
68 | int r, size; | |
69 | ||
70 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
71 | cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size); | |
72 | cpuid->nent = max; | |
73 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
74 | if (r == 0 && cpuid->nent >= max) { | |
75 | r = -E2BIG; | |
76 | } | |
77 | if (r < 0) { | |
78 | if (r == -E2BIG) { | |
79 | qemu_free(cpuid); | |
80 | return NULL; | |
81 | } else { | |
82 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
83 | strerror(-r)); | |
84 | exit(1); | |
85 | } | |
86 | } | |
87 | return cpuid; | |
88 | } | |
89 | ||
90 | struct kvm_para_features { | |
91 | int cap; | |
92 | int feature; | |
93 | } para_features[] = { | |
94 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, | |
95 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, | |
96 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, | |
97 | { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF }, | |
98 | { -1, -1 } | |
99 | }; | |
100 | ||
101 | static int get_para_features(KVMState *s) | |
102 | { | |
103 | int i, features = 0; | |
104 | ||
105 | for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) { | |
106 | if (kvm_check_extension(s, para_features[i].cap)) { | |
107 | features |= (1 << para_features[i].feature); | |
108 | } | |
109 | } | |
110 | ||
111 | return features; | |
112 | } | |
113 | ||
114 | ||
115 | uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, | |
116 | uint32_t index, int reg) | |
117 | { | |
118 | struct kvm_cpuid2 *cpuid; | |
119 | int i, max; | |
120 | uint32_t ret = 0; | |
121 | uint32_t cpuid_1_edx; | |
122 | int has_kvm_features = 0; | |
123 | ||
124 | max = 1; | |
125 | while ((cpuid = try_get_cpuid(s, max)) == NULL) { | |
126 | max *= 2; | |
127 | } | |
128 | ||
129 | for (i = 0; i < cpuid->nent; ++i) { | |
130 | if (cpuid->entries[i].function == function && | |
131 | cpuid->entries[i].index == index) { | |
132 | if (cpuid->entries[i].function == KVM_CPUID_FEATURES) { | |
133 | has_kvm_features = 1; | |
134 | } | |
135 | switch (reg) { | |
136 | case R_EAX: | |
137 | ret = cpuid->entries[i].eax; | |
138 | break; | |
139 | case R_EBX: | |
140 | ret = cpuid->entries[i].ebx; | |
141 | break; | |
142 | case R_ECX: | |
143 | ret = cpuid->entries[i].ecx; | |
144 | break; | |
145 | case R_EDX: | |
146 | ret = cpuid->entries[i].edx; | |
147 | switch (function) { | |
148 | case 1: | |
149 | /* KVM before 2.6.30 misreports the following features */ | |
150 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
151 | break; | |
152 | case 0x80000001: | |
153 | /* On Intel, kvm returns cpuid according to the Intel spec, | |
154 | * so add missing bits according to the AMD spec: | |
155 | */ | |
156 | cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); | |
157 | ret |= cpuid_1_edx & 0x183f7ff; | |
158 | break; | |
159 | } | |
160 | break; | |
161 | } | |
162 | } | |
163 | } | |
164 | ||
165 | qemu_free(cpuid); | |
166 | ||
167 | /* fallback for older kernels */ | |
168 | if (!has_kvm_features && (function == KVM_CPUID_FEATURES)) { | |
169 | ret = get_para_features(s); | |
170 | } | |
171 | ||
172 | return ret; | |
173 | } | |
174 | ||
175 | typedef struct HWPoisonPage { | |
176 | ram_addr_t ram_addr; | |
177 | QLIST_ENTRY(HWPoisonPage) list; | |
178 | } HWPoisonPage; | |
179 | ||
180 | static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list = | |
181 | QLIST_HEAD_INITIALIZER(hwpoison_page_list); | |
182 | ||
183 | static void kvm_unpoison_all(void *param) | |
184 | { | |
185 | HWPoisonPage *page, *next_page; | |
186 | ||
187 | QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) { | |
188 | QLIST_REMOVE(page, list); | |
189 | qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE); | |
190 | qemu_free(page); | |
191 | } | |
192 | } | |
193 | ||
194 | static void kvm_hwpoison_page_add(ram_addr_t ram_addr) | |
195 | { | |
196 | HWPoisonPage *page; | |
197 | ||
198 | QLIST_FOREACH(page, &hwpoison_page_list, list) { | |
199 | if (page->ram_addr == ram_addr) { | |
200 | return; | |
201 | } | |
202 | } | |
203 | page = qemu_malloc(sizeof(HWPoisonPage)); | |
204 | page->ram_addr = ram_addr; | |
205 | QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); | |
206 | } | |
207 | ||
208 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, | |
209 | int *max_banks) | |
210 | { | |
211 | int r; | |
212 | ||
213 | r = kvm_check_extension(s, KVM_CAP_MCE); | |
214 | if (r > 0) { | |
215 | *max_banks = r; | |
216 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
217 | } | |
218 | return -ENOSYS; | |
219 | } | |
220 | ||
221 | static void kvm_mce_inject(CPUState *env, target_phys_addr_t paddr, int code) | |
222 | { | |
223 | uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | | |
224 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; | |
225 | uint64_t mcg_status = MCG_STATUS_MCIP; | |
226 | ||
227 | if (code == BUS_MCEERR_AR) { | |
228 | status |= MCI_STATUS_AR | 0x134; | |
229 | mcg_status |= MCG_STATUS_EIPV; | |
230 | } else { | |
231 | status |= 0xc0; | |
232 | mcg_status |= MCG_STATUS_RIPV; | |
233 | } | |
234 | cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr, | |
235 | (MCM_ADDR_PHYS << 6) | 0xc, | |
236 | cpu_x86_support_mca_broadcast(env) ? | |
237 | MCE_INJECT_BROADCAST : 0); | |
238 | } | |
239 | ||
240 | static void hardware_memory_error(void) | |
241 | { | |
242 | fprintf(stderr, "Hardware memory error!\n"); | |
243 | exit(1); | |
244 | } | |
245 | ||
246 | int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr) | |
247 | { | |
248 | ram_addr_t ram_addr; | |
249 | target_phys_addr_t paddr; | |
250 | ||
251 | if ((env->mcg_cap & MCG_SER_P) && addr | |
252 | && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) { | |
253 | if (qemu_ram_addr_from_host(addr, &ram_addr) || | |
254 | !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, | |
255 | &paddr)) { | |
256 | fprintf(stderr, "Hardware memory error for memory used by " | |
257 | "QEMU itself instead of guest system!\n"); | |
258 | /* Hope we are lucky for AO MCE */ | |
259 | if (code == BUS_MCEERR_AO) { | |
260 | return 0; | |
261 | } else { | |
262 | hardware_memory_error(); | |
263 | } | |
264 | } | |
265 | kvm_hwpoison_page_add(ram_addr); | |
266 | kvm_mce_inject(env, paddr, code); | |
267 | } else { | |
268 | if (code == BUS_MCEERR_AO) { | |
269 | return 0; | |
270 | } else if (code == BUS_MCEERR_AR) { | |
271 | hardware_memory_error(); | |
272 | } else { | |
273 | return 1; | |
274 | } | |
275 | } | |
276 | return 0; | |
277 | } | |
278 | ||
279 | int kvm_arch_on_sigbus(int code, void *addr) | |
280 | { | |
281 | if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) { | |
282 | ram_addr_t ram_addr; | |
283 | target_phys_addr_t paddr; | |
284 | ||
285 | /* Hope we are lucky for AO MCE */ | |
286 | if (qemu_ram_addr_from_host(addr, &ram_addr) || | |
287 | !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, | |
288 | &paddr)) { | |
289 | fprintf(stderr, "Hardware memory error for memory used by " | |
290 | "QEMU itself instead of guest system!: %p\n", addr); | |
291 | return 0; | |
292 | } | |
293 | kvm_hwpoison_page_add(ram_addr); | |
294 | kvm_mce_inject(first_cpu, paddr, code); | |
295 | } else { | |
296 | if (code == BUS_MCEERR_AO) { | |
297 | return 0; | |
298 | } else if (code == BUS_MCEERR_AR) { | |
299 | hardware_memory_error(); | |
300 | } else { | |
301 | return 1; | |
302 | } | |
303 | } | |
304 | return 0; | |
305 | } | |
306 | ||
307 | static int kvm_inject_mce_oldstyle(CPUState *env) | |
308 | { | |
309 | if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) { | |
310 | unsigned int bank, bank_num = env->mcg_cap & 0xff; | |
311 | struct kvm_x86_mce mce; | |
312 | ||
313 | env->exception_injected = -1; | |
314 | ||
315 | /* | |
316 | * There must be at least one bank in use if an MCE is pending. | |
317 | * Find it and use its values for the event injection. | |
318 | */ | |
319 | for (bank = 0; bank < bank_num; bank++) { | |
320 | if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) { | |
321 | break; | |
322 | } | |
323 | } | |
324 | assert(bank < bank_num); | |
325 | ||
326 | mce.bank = bank; | |
327 | mce.status = env->mce_banks[bank * 4 + 1]; | |
328 | mce.mcg_status = env->mcg_status; | |
329 | mce.addr = env->mce_banks[bank * 4 + 2]; | |
330 | mce.misc = env->mce_banks[bank * 4 + 3]; | |
331 | ||
332 | return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce); | |
333 | } | |
334 | return 0; | |
335 | } | |
336 | ||
337 | static void cpu_update_state(void *opaque, int running, int reason) | |
338 | { | |
339 | CPUState *env = opaque; | |
340 | ||
341 | if (running) { | |
342 | env->tsc_valid = false; | |
343 | } | |
344 | } | |
345 | ||
346 | int kvm_arch_init_vcpu(CPUState *env) | |
347 | { | |
348 | struct { | |
349 | struct kvm_cpuid2 cpuid; | |
350 | struct kvm_cpuid_entry2 entries[100]; | |
351 | } __attribute__((packed)) cpuid_data; | |
352 | KVMState *s = env->kvm_state; | |
353 | uint32_t limit, i, j, cpuid_i; | |
354 | uint32_t unused; | |
355 | struct kvm_cpuid_entry2 *c; | |
356 | uint32_t signature[3]; | |
357 | ||
358 | env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); | |
359 | ||
360 | i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR; | |
361 | env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX); | |
362 | env->cpuid_ext_features |= i; | |
363 | ||
364 | env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001, | |
365 | 0, R_EDX); | |
366 | env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001, | |
367 | 0, R_ECX); | |
368 | env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(s, 0x8000000A, | |
369 | 0, R_EDX); | |
370 | ||
371 | cpuid_i = 0; | |
372 | ||
373 | /* Paravirtualization CPUIDs */ | |
374 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
375 | c = &cpuid_data.entries[cpuid_i++]; | |
376 | memset(c, 0, sizeof(*c)); | |
377 | c->function = KVM_CPUID_SIGNATURE; | |
378 | c->eax = 0; | |
379 | c->ebx = signature[0]; | |
380 | c->ecx = signature[1]; | |
381 | c->edx = signature[2]; | |
382 | ||
383 | c = &cpuid_data.entries[cpuid_i++]; | |
384 | memset(c, 0, sizeof(*c)); | |
385 | c->function = KVM_CPUID_FEATURES; | |
386 | c->eax = env->cpuid_kvm_features & | |
387 | kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX); | |
388 | ||
389 | has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF); | |
390 | ||
391 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); | |
392 | ||
393 | for (i = 0; i <= limit; i++) { | |
394 | c = &cpuid_data.entries[cpuid_i++]; | |
395 | ||
396 | switch (i) { | |
397 | case 2: { | |
398 | /* Keep reading function 2 till all the input is received */ | |
399 | int times; | |
400 | ||
401 | c->function = i; | |
402 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | | |
403 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
404 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
405 | times = c->eax & 0xff; | |
406 | ||
407 | for (j = 1; j < times; ++j) { | |
408 | c = &cpuid_data.entries[cpuid_i++]; | |
409 | c->function = i; | |
410 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; | |
411 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
412 | } | |
413 | break; | |
414 | } | |
415 | case 4: | |
416 | case 0xb: | |
417 | case 0xd: | |
418 | for (j = 0; ; j++) { | |
419 | if (i == 0xd && j == 64) { | |
420 | break; | |
421 | } | |
422 | c->function = i; | |
423 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
424 | c->index = j; | |
425 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
426 | ||
427 | if (i == 4 && c->eax == 0) { | |
428 | break; | |
429 | } | |
430 | if (i == 0xb && !(c->ecx & 0xff00)) { | |
431 | break; | |
432 | } | |
433 | if (i == 0xd && c->eax == 0) { | |
434 | continue; | |
435 | } | |
436 | c = &cpuid_data.entries[cpuid_i++]; | |
437 | } | |
438 | break; | |
439 | default: | |
440 | c->function = i; | |
441 | c->flags = 0; | |
442 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
443 | break; | |
444 | } | |
445 | } | |
446 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); | |
447 | ||
448 | for (i = 0x80000000; i <= limit; i++) { | |
449 | c = &cpuid_data.entries[cpuid_i++]; | |
450 | ||
451 | c->function = i; | |
452 | c->flags = 0; | |
453 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
454 | } | |
455 | ||
456 | /* Call Centaur's CPUID instructions they are supported. */ | |
457 | if (env->cpuid_xlevel2 > 0) { | |
458 | env->cpuid_ext4_features &= | |
459 | kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX); | |
460 | cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused); | |
461 | ||
462 | for (i = 0xC0000000; i <= limit; i++) { | |
463 | c = &cpuid_data.entries[cpuid_i++]; | |
464 | ||
465 | c->function = i; | |
466 | c->flags = 0; | |
467 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
468 | } | |
469 | } | |
470 | ||
471 | cpuid_data.cpuid.nent = cpuid_i; | |
472 | ||
473 | if (((env->cpuid_version >> 8)&0xF) >= 6 | |
474 | && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA) | |
475 | && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) { | |
476 | uint64_t mcg_cap; | |
477 | int banks; | |
478 | int ret; | |
479 | ||
480 | ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks); | |
481 | if (ret < 0) { | |
482 | fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret)); | |
483 | return ret; | |
484 | } | |
485 | ||
486 | if (banks > MCE_BANKS_DEF) { | |
487 | banks = MCE_BANKS_DEF; | |
488 | } | |
489 | mcg_cap &= MCE_CAP_DEF; | |
490 | mcg_cap |= banks; | |
491 | ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap); | |
492 | if (ret < 0) { | |
493 | fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret)); | |
494 | return ret; | |
495 | } | |
496 | ||
497 | env->mcg_cap = mcg_cap; | |
498 | } | |
499 | ||
500 | qemu_add_vm_change_state_handler(cpu_update_state, env); | |
501 | ||
502 | return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data); | |
503 | } | |
504 | ||
505 | void kvm_arch_reset_vcpu(CPUState *env) | |
506 | { | |
507 | env->exception_injected = -1; | |
508 | env->interrupt_injected = -1; | |
509 | env->xcr0 = 1; | |
510 | if (kvm_irqchip_in_kernel()) { | |
511 | env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE : | |
512 | KVM_MP_STATE_UNINITIALIZED; | |
513 | } else { | |
514 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
515 | } | |
516 | } | |
517 | ||
518 | static int kvm_get_supported_msrs(KVMState *s) | |
519 | { | |
520 | static int kvm_supported_msrs; | |
521 | int ret = 0; | |
522 | ||
523 | /* first time */ | |
524 | if (kvm_supported_msrs == 0) { | |
525 | struct kvm_msr_list msr_list, *kvm_msr_list; | |
526 | ||
527 | kvm_supported_msrs = -1; | |
528 | ||
529 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
530 | * save/restore */ | |
531 | msr_list.nmsrs = 0; | |
532 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); | |
533 | if (ret < 0 && ret != -E2BIG) { | |
534 | return ret; | |
535 | } | |
536 | /* Old kernel modules had a bug and could write beyond the provided | |
537 | memory. Allocate at least a safe amount of 1K. */ | |
538 | kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) + | |
539 | msr_list.nmsrs * | |
540 | sizeof(msr_list.indices[0]))); | |
541 | ||
542 | kvm_msr_list->nmsrs = msr_list.nmsrs; | |
543 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); | |
544 | if (ret >= 0) { | |
545 | int i; | |
546 | ||
547 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
548 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
549 | has_msr_star = true; | |
550 | continue; | |
551 | } | |
552 | if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) { | |
553 | has_msr_hsave_pa = true; | |
554 | continue; | |
555 | } | |
556 | } | |
557 | } | |
558 | ||
559 | qemu_free(kvm_msr_list); | |
560 | } | |
561 | ||
562 | return ret; | |
563 | } | |
564 | ||
565 | int kvm_arch_init(KVMState *s) | |
566 | { | |
567 | uint64_t identity_base = 0xfffbc000; | |
568 | int ret; | |
569 | struct utsname utsname; | |
570 | ||
571 | ret = kvm_get_supported_msrs(s); | |
572 | if (ret < 0) { | |
573 | return ret; | |
574 | } | |
575 | ||
576 | uname(&utsname); | |
577 | lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; | |
578 | ||
579 | /* | |
580 | * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. | |
581 | * In order to use vm86 mode, an EPT identity map and a TSS are needed. | |
582 | * Since these must be part of guest physical memory, we need to allocate | |
583 | * them, both by setting their start addresses in the kernel and by | |
584 | * creating a corresponding e820 entry. We need 4 pages before the BIOS. | |
585 | * | |
586 | * Older KVM versions may not support setting the identity map base. In | |
587 | * that case we need to stick with the default, i.e. a 256K maximum BIOS | |
588 | * size. | |
589 | */ | |
590 | if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { | |
591 | /* Allows up to 16M BIOSes. */ | |
592 | identity_base = 0xfeffc000; | |
593 | ||
594 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); | |
595 | if (ret < 0) { | |
596 | return ret; | |
597 | } | |
598 | } | |
599 | ||
600 | /* Set TSS base one page after EPT identity map. */ | |
601 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); | |
602 | if (ret < 0) { | |
603 | return ret; | |
604 | } | |
605 | ||
606 | /* Tell fw_cfg to notify the BIOS to reserve the range. */ | |
607 | ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); | |
608 | if (ret < 0) { | |
609 | fprintf(stderr, "e820_add_entry() table is full\n"); | |
610 | return ret; | |
611 | } | |
612 | qemu_register_reset(kvm_unpoison_all, NULL); | |
613 | ||
614 | return 0; | |
615 | } | |
616 | ||
617 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
618 | { | |
619 | lhs->selector = rhs->selector; | |
620 | lhs->base = rhs->base; | |
621 | lhs->limit = rhs->limit; | |
622 | lhs->type = 3; | |
623 | lhs->present = 1; | |
624 | lhs->dpl = 3; | |
625 | lhs->db = 0; | |
626 | lhs->s = 1; | |
627 | lhs->l = 0; | |
628 | lhs->g = 0; | |
629 | lhs->avl = 0; | |
630 | lhs->unusable = 0; | |
631 | } | |
632 | ||
633 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
634 | { | |
635 | unsigned flags = rhs->flags; | |
636 | lhs->selector = rhs->selector; | |
637 | lhs->base = rhs->base; | |
638 | lhs->limit = rhs->limit; | |
639 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
640 | lhs->present = (flags & DESC_P_MASK) != 0; | |
641 | lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; | |
642 | lhs->db = (flags >> DESC_B_SHIFT) & 1; | |
643 | lhs->s = (flags & DESC_S_MASK) != 0; | |
644 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
645 | lhs->g = (flags & DESC_G_MASK) != 0; | |
646 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
647 | lhs->unusable = 0; | |
648 | } | |
649 | ||
650 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
651 | { | |
652 | lhs->selector = rhs->selector; | |
653 | lhs->base = rhs->base; | |
654 | lhs->limit = rhs->limit; | |
655 | lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | | |
656 | (rhs->present * DESC_P_MASK) | | |
657 | (rhs->dpl << DESC_DPL_SHIFT) | | |
658 | (rhs->db << DESC_B_SHIFT) | | |
659 | (rhs->s * DESC_S_MASK) | | |
660 | (rhs->l << DESC_L_SHIFT) | | |
661 | (rhs->g * DESC_G_MASK) | | |
662 | (rhs->avl * DESC_AVL_MASK); | |
663 | } | |
664 | ||
665 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
666 | { | |
667 | if (set) { | |
668 | *kvm_reg = *qemu_reg; | |
669 | } else { | |
670 | *qemu_reg = *kvm_reg; | |
671 | } | |
672 | } | |
673 | ||
674 | static int kvm_getput_regs(CPUState *env, int set) | |
675 | { | |
676 | struct kvm_regs regs; | |
677 | int ret = 0; | |
678 | ||
679 | if (!set) { | |
680 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
681 | if (ret < 0) { | |
682 | return ret; | |
683 | } | |
684 | } | |
685 | ||
686 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
687 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
688 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
689 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
690 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
691 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
692 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
693 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
694 | #ifdef TARGET_X86_64 | |
695 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
696 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
697 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
698 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
699 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
700 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
701 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
702 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
703 | #endif | |
704 | ||
705 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
706 | kvm_getput_reg(®s.rip, &env->eip, set); | |
707 | ||
708 | if (set) { | |
709 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); | |
710 | } | |
711 | ||
712 | return ret; | |
713 | } | |
714 | ||
715 | static int kvm_put_fpu(CPUState *env) | |
716 | { | |
717 | struct kvm_fpu fpu; | |
718 | int i; | |
719 | ||
720 | memset(&fpu, 0, sizeof fpu); | |
721 | fpu.fsw = env->fpus & ~(7 << 11); | |
722 | fpu.fsw |= (env->fpstt & 7) << 11; | |
723 | fpu.fcw = env->fpuc; | |
724 | fpu.last_opcode = env->fpop; | |
725 | fpu.last_ip = env->fpip; | |
726 | fpu.last_dp = env->fpdp; | |
727 | for (i = 0; i < 8; ++i) { | |
728 | fpu.ftwx |= (!env->fptags[i]) << i; | |
729 | } | |
730 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); | |
731 | memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs); | |
732 | fpu.mxcsr = env->mxcsr; | |
733 | ||
734 | return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu); | |
735 | } | |
736 | ||
737 | #define XSAVE_CWD_RIP 2 | |
738 | #define XSAVE_CWD_RDP 4 | |
739 | #define XSAVE_MXCSR 6 | |
740 | #define XSAVE_ST_SPACE 8 | |
741 | #define XSAVE_XMM_SPACE 40 | |
742 | #define XSAVE_XSTATE_BV 128 | |
743 | #define XSAVE_YMMH_SPACE 144 | |
744 | ||
745 | static int kvm_put_xsave(CPUState *env) | |
746 | { | |
747 | int i, r; | |
748 | struct kvm_xsave* xsave; | |
749 | uint16_t cwd, swd, twd; | |
750 | ||
751 | if (!kvm_has_xsave()) { | |
752 | return kvm_put_fpu(env); | |
753 | } | |
754 | ||
755 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
756 | memset(xsave, 0, sizeof(struct kvm_xsave)); | |
757 | cwd = swd = twd = 0; | |
758 | swd = env->fpus & ~(7 << 11); | |
759 | swd |= (env->fpstt & 7) << 11; | |
760 | cwd = env->fpuc; | |
761 | for (i = 0; i < 8; ++i) { | |
762 | twd |= (!env->fptags[i]) << i; | |
763 | } | |
764 | xsave->region[0] = (uint32_t)(swd << 16) + cwd; | |
765 | xsave->region[1] = (uint32_t)(env->fpop << 16) + twd; | |
766 | memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip)); | |
767 | memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp)); | |
768 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, | |
769 | sizeof env->fpregs); | |
770 | memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, | |
771 | sizeof env->xmm_regs); | |
772 | xsave->region[XSAVE_MXCSR] = env->mxcsr; | |
773 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
774 | memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, | |
775 | sizeof env->ymmh_regs); | |
776 | r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave); | |
777 | qemu_free(xsave); | |
778 | return r; | |
779 | } | |
780 | ||
781 | static int kvm_put_xcrs(CPUState *env) | |
782 | { | |
783 | struct kvm_xcrs xcrs; | |
784 | ||
785 | if (!kvm_has_xcrs()) { | |
786 | return 0; | |
787 | } | |
788 | ||
789 | xcrs.nr_xcrs = 1; | |
790 | xcrs.flags = 0; | |
791 | xcrs.xcrs[0].xcr = 0; | |
792 | xcrs.xcrs[0].value = env->xcr0; | |
793 | return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs); | |
794 | } | |
795 | ||
796 | static int kvm_put_sregs(CPUState *env) | |
797 | { | |
798 | struct kvm_sregs sregs; | |
799 | ||
800 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); | |
801 | if (env->interrupt_injected >= 0) { | |
802 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
803 | (uint64_t)1 << (env->interrupt_injected % 64); | |
804 | } | |
805 | ||
806 | if ((env->eflags & VM_MASK)) { | |
807 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); | |
808 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
809 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
810 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
811 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
812 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
813 | } else { | |
814 | set_seg(&sregs.cs, &env->segs[R_CS]); | |
815 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
816 | set_seg(&sregs.es, &env->segs[R_ES]); | |
817 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
818 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
819 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
820 | } | |
821 | ||
822 | set_seg(&sregs.tr, &env->tr); | |
823 | set_seg(&sregs.ldt, &env->ldt); | |
824 | ||
825 | sregs.idt.limit = env->idt.limit; | |
826 | sregs.idt.base = env->idt.base; | |
827 | sregs.gdt.limit = env->gdt.limit; | |
828 | sregs.gdt.base = env->gdt.base; | |
829 | ||
830 | sregs.cr0 = env->cr[0]; | |
831 | sregs.cr2 = env->cr[2]; | |
832 | sregs.cr3 = env->cr[3]; | |
833 | sregs.cr4 = env->cr[4]; | |
834 | ||
835 | sregs.cr8 = cpu_get_apic_tpr(env->apic_state); | |
836 | sregs.apic_base = cpu_get_apic_base(env->apic_state); | |
837 | ||
838 | sregs.efer = env->efer; | |
839 | ||
840 | return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs); | |
841 | } | |
842 | ||
843 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
844 | uint32_t index, uint64_t value) | |
845 | { | |
846 | entry->index = index; | |
847 | entry->data = value; | |
848 | } | |
849 | ||
850 | static int kvm_put_msrs(CPUState *env, int level) | |
851 | { | |
852 | struct { | |
853 | struct kvm_msrs info; | |
854 | struct kvm_msr_entry entries[100]; | |
855 | } msr_data; | |
856 | struct kvm_msr_entry *msrs = msr_data.entries; | |
857 | int n = 0; | |
858 | ||
859 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
860 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
861 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
862 | kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat); | |
863 | if (has_msr_star) { | |
864 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); | |
865 | } | |
866 | if (has_msr_hsave_pa) { | |
867 | kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); | |
868 | } | |
869 | #ifdef TARGET_X86_64 | |
870 | if (lm_capable_kernel) { | |
871 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
872 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
873 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
874 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
875 | } | |
876 | #endif | |
877 | if (level == KVM_PUT_FULL_STATE) { | |
878 | /* | |
879 | * KVM is yet unable to synchronize TSC values of multiple VCPUs on | |
880 | * writeback. Until this is fixed, we only write the offset to SMP | |
881 | * guests after migration, desynchronizing the VCPUs, but avoiding | |
882 | * huge jump-backs that would occur without any writeback at all. | |
883 | */ | |
884 | if (smp_cpus == 1 || env->tsc != 0) { | |
885 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); | |
886 | } | |
887 | } | |
888 | /* | |
889 | * The following paravirtual MSRs have side effects on the guest or are | |
890 | * too heavy for normal writeback. Limit them to reset or full state | |
891 | * updates. | |
892 | */ | |
893 | if (level >= KVM_PUT_RESET_STATE) { | |
894 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, | |
895 | env->system_time_msr); | |
896 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
897 | if (has_msr_async_pf_en) { | |
898 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, | |
899 | env->async_pf_en_msr); | |
900 | } | |
901 | } | |
902 | if (env->mcg_cap) { | |
903 | int i; | |
904 | ||
905 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); | |
906 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); | |
907 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { | |
908 | kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); | |
909 | } | |
910 | } | |
911 | ||
912 | msr_data.info.nmsrs = n; | |
913 | ||
914 | return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data); | |
915 | ||
916 | } | |
917 | ||
918 | ||
919 | static int kvm_get_fpu(CPUState *env) | |
920 | { | |
921 | struct kvm_fpu fpu; | |
922 | int i, ret; | |
923 | ||
924 | ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu); | |
925 | if (ret < 0) { | |
926 | return ret; | |
927 | } | |
928 | ||
929 | env->fpstt = (fpu.fsw >> 11) & 7; | |
930 | env->fpus = fpu.fsw; | |
931 | env->fpuc = fpu.fcw; | |
932 | env->fpop = fpu.last_opcode; | |
933 | env->fpip = fpu.last_ip; | |
934 | env->fpdp = fpu.last_dp; | |
935 | for (i = 0; i < 8; ++i) { | |
936 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
937 | } | |
938 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); | |
939 | memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs); | |
940 | env->mxcsr = fpu.mxcsr; | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
945 | static int kvm_get_xsave(CPUState *env) | |
946 | { | |
947 | struct kvm_xsave* xsave; | |
948 | int ret, i; | |
949 | uint16_t cwd, swd, twd; | |
950 | ||
951 | if (!kvm_has_xsave()) { | |
952 | return kvm_get_fpu(env); | |
953 | } | |
954 | ||
955 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
956 | ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave); | |
957 | if (ret < 0) { | |
958 | qemu_free(xsave); | |
959 | return ret; | |
960 | } | |
961 | ||
962 | cwd = (uint16_t)xsave->region[0]; | |
963 | swd = (uint16_t)(xsave->region[0] >> 16); | |
964 | twd = (uint16_t)xsave->region[1]; | |
965 | env->fpop = (uint16_t)(xsave->region[1] >> 16); | |
966 | env->fpstt = (swd >> 11) & 7; | |
967 | env->fpus = swd; | |
968 | env->fpuc = cwd; | |
969 | for (i = 0; i < 8; ++i) { | |
970 | env->fptags[i] = !((twd >> i) & 1); | |
971 | } | |
972 | memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip)); | |
973 | memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp)); | |
974 | env->mxcsr = xsave->region[XSAVE_MXCSR]; | |
975 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
976 | sizeof env->fpregs); | |
977 | memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], | |
978 | sizeof env->xmm_regs); | |
979 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; | |
980 | memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], | |
981 | sizeof env->ymmh_regs); | |
982 | qemu_free(xsave); | |
983 | return 0; | |
984 | } | |
985 | ||
986 | static int kvm_get_xcrs(CPUState *env) | |
987 | { | |
988 | int i, ret; | |
989 | struct kvm_xcrs xcrs; | |
990 | ||
991 | if (!kvm_has_xcrs()) { | |
992 | return 0; | |
993 | } | |
994 | ||
995 | ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs); | |
996 | if (ret < 0) { | |
997 | return ret; | |
998 | } | |
999 | ||
1000 | for (i = 0; i < xcrs.nr_xcrs; i++) { | |
1001 | /* Only support xcr0 now */ | |
1002 | if (xcrs.xcrs[0].xcr == 0) { | |
1003 | env->xcr0 = xcrs.xcrs[0].value; | |
1004 | break; | |
1005 | } | |
1006 | } | |
1007 | return 0; | |
1008 | } | |
1009 | ||
1010 | static int kvm_get_sregs(CPUState *env) | |
1011 | { | |
1012 | struct kvm_sregs sregs; | |
1013 | uint32_t hflags; | |
1014 | int bit, i, ret; | |
1015 | ||
1016 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); | |
1017 | if (ret < 0) { | |
1018 | return ret; | |
1019 | } | |
1020 | ||
1021 | /* There can only be one pending IRQ set in the bitmap at a time, so try | |
1022 | to find it and save its number instead (-1 for none). */ | |
1023 | env->interrupt_injected = -1; | |
1024 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
1025 | if (sregs.interrupt_bitmap[i]) { | |
1026 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
1027 | env->interrupt_injected = i * 64 + bit; | |
1028 | break; | |
1029 | } | |
1030 | } | |
1031 | ||
1032 | get_seg(&env->segs[R_CS], &sregs.cs); | |
1033 | get_seg(&env->segs[R_DS], &sregs.ds); | |
1034 | get_seg(&env->segs[R_ES], &sregs.es); | |
1035 | get_seg(&env->segs[R_FS], &sregs.fs); | |
1036 | get_seg(&env->segs[R_GS], &sregs.gs); | |
1037 | get_seg(&env->segs[R_SS], &sregs.ss); | |
1038 | ||
1039 | get_seg(&env->tr, &sregs.tr); | |
1040 | get_seg(&env->ldt, &sregs.ldt); | |
1041 | ||
1042 | env->idt.limit = sregs.idt.limit; | |
1043 | env->idt.base = sregs.idt.base; | |
1044 | env->gdt.limit = sregs.gdt.limit; | |
1045 | env->gdt.base = sregs.gdt.base; | |
1046 | ||
1047 | env->cr[0] = sregs.cr0; | |
1048 | env->cr[2] = sregs.cr2; | |
1049 | env->cr[3] = sregs.cr3; | |
1050 | env->cr[4] = sregs.cr4; | |
1051 | ||
1052 | cpu_set_apic_base(env->apic_state, sregs.apic_base); | |
1053 | ||
1054 | env->efer = sregs.efer; | |
1055 | //cpu_set_apic_tpr(env->apic_state, sregs.cr8); | |
1056 | ||
1057 | #define HFLAG_COPY_MASK \ | |
1058 | ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
1059 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
1060 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
1061 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
1062 | ||
1063 | hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; | |
1064 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); | |
1065 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
1066 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); | |
1067 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); | |
1068 | hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << | |
1069 | (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); | |
1070 | ||
1071 | if (env->efer & MSR_EFER_LMA) { | |
1072 | hflags |= HF_LMA_MASK; | |
1073 | } | |
1074 | ||
1075 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
1076 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1077 | } else { | |
1078 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
1079 | (DESC_B_SHIFT - HF_CS32_SHIFT); | |
1080 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> | |
1081 | (DESC_B_SHIFT - HF_SS32_SHIFT); | |
1082 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || | |
1083 | !(hflags & HF_CS32_MASK)) { | |
1084 | hflags |= HF_ADDSEG_MASK; | |
1085 | } else { | |
1086 | hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | | |
1087 | env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; | |
1088 | } | |
1089 | } | |
1090 | env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; | |
1091 | ||
1092 | return 0; | |
1093 | } | |
1094 | ||
1095 | static int kvm_get_msrs(CPUState *env) | |
1096 | { | |
1097 | struct { | |
1098 | struct kvm_msrs info; | |
1099 | struct kvm_msr_entry entries[100]; | |
1100 | } msr_data; | |
1101 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1102 | int ret, i, n; | |
1103 | ||
1104 | n = 0; | |
1105 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
1106 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
1107 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
1108 | msrs[n++].index = MSR_PAT; | |
1109 | if (has_msr_star) { | |
1110 | msrs[n++].index = MSR_STAR; | |
1111 | } | |
1112 | if (has_msr_hsave_pa) { | |
1113 | msrs[n++].index = MSR_VM_HSAVE_PA; | |
1114 | } | |
1115 | ||
1116 | if (!env->tsc_valid) { | |
1117 | msrs[n++].index = MSR_IA32_TSC; | |
1118 | env->tsc_valid = !vm_running; | |
1119 | } | |
1120 | ||
1121 | #ifdef TARGET_X86_64 | |
1122 | if (lm_capable_kernel) { | |
1123 | msrs[n++].index = MSR_CSTAR; | |
1124 | msrs[n++].index = MSR_KERNELGSBASE; | |
1125 | msrs[n++].index = MSR_FMASK; | |
1126 | msrs[n++].index = MSR_LSTAR; | |
1127 | } | |
1128 | #endif | |
1129 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; | |
1130 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
1131 | if (has_msr_async_pf_en) { | |
1132 | msrs[n++].index = MSR_KVM_ASYNC_PF_EN; | |
1133 | } | |
1134 | ||
1135 | if (env->mcg_cap) { | |
1136 | msrs[n++].index = MSR_MCG_STATUS; | |
1137 | msrs[n++].index = MSR_MCG_CTL; | |
1138 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { | |
1139 | msrs[n++].index = MSR_MC0_CTL + i; | |
1140 | } | |
1141 | } | |
1142 | ||
1143 | msr_data.info.nmsrs = n; | |
1144 | ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data); | |
1145 | if (ret < 0) { | |
1146 | return ret; | |
1147 | } | |
1148 | ||
1149 | for (i = 0; i < ret; i++) { | |
1150 | switch (msrs[i].index) { | |
1151 | case MSR_IA32_SYSENTER_CS: | |
1152 | env->sysenter_cs = msrs[i].data; | |
1153 | break; | |
1154 | case MSR_IA32_SYSENTER_ESP: | |
1155 | env->sysenter_esp = msrs[i].data; | |
1156 | break; | |
1157 | case MSR_IA32_SYSENTER_EIP: | |
1158 | env->sysenter_eip = msrs[i].data; | |
1159 | break; | |
1160 | case MSR_PAT: | |
1161 | env->pat = msrs[i].data; | |
1162 | break; | |
1163 | case MSR_STAR: | |
1164 | env->star = msrs[i].data; | |
1165 | break; | |
1166 | #ifdef TARGET_X86_64 | |
1167 | case MSR_CSTAR: | |
1168 | env->cstar = msrs[i].data; | |
1169 | break; | |
1170 | case MSR_KERNELGSBASE: | |
1171 | env->kernelgsbase = msrs[i].data; | |
1172 | break; | |
1173 | case MSR_FMASK: | |
1174 | env->fmask = msrs[i].data; | |
1175 | break; | |
1176 | case MSR_LSTAR: | |
1177 | env->lstar = msrs[i].data; | |
1178 | break; | |
1179 | #endif | |
1180 | case MSR_IA32_TSC: | |
1181 | env->tsc = msrs[i].data; | |
1182 | break; | |
1183 | case MSR_VM_HSAVE_PA: | |
1184 | env->vm_hsave = msrs[i].data; | |
1185 | break; | |
1186 | case MSR_KVM_SYSTEM_TIME: | |
1187 | env->system_time_msr = msrs[i].data; | |
1188 | break; | |
1189 | case MSR_KVM_WALL_CLOCK: | |
1190 | env->wall_clock_msr = msrs[i].data; | |
1191 | break; | |
1192 | case MSR_MCG_STATUS: | |
1193 | env->mcg_status = msrs[i].data; | |
1194 | break; | |
1195 | case MSR_MCG_CTL: | |
1196 | env->mcg_ctl = msrs[i].data; | |
1197 | break; | |
1198 | default: | |
1199 | if (msrs[i].index >= MSR_MC0_CTL && | |
1200 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
1201 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
1202 | } | |
1203 | break; | |
1204 | case MSR_KVM_ASYNC_PF_EN: | |
1205 | env->async_pf_en_msr = msrs[i].data; | |
1206 | break; | |
1207 | } | |
1208 | } | |
1209 | ||
1210 | return 0; | |
1211 | } | |
1212 | ||
1213 | static int kvm_put_mp_state(CPUState *env) | |
1214 | { | |
1215 | struct kvm_mp_state mp_state = { .mp_state = env->mp_state }; | |
1216 | ||
1217 | return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state); | |
1218 | } | |
1219 | ||
1220 | static int kvm_get_mp_state(CPUState *env) | |
1221 | { | |
1222 | struct kvm_mp_state mp_state; | |
1223 | int ret; | |
1224 | ||
1225 | ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state); | |
1226 | if (ret < 0) { | |
1227 | return ret; | |
1228 | } | |
1229 | env->mp_state = mp_state.mp_state; | |
1230 | if (kvm_irqchip_in_kernel()) { | |
1231 | env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); | |
1232 | } | |
1233 | return 0; | |
1234 | } | |
1235 | ||
1236 | static int kvm_put_vcpu_events(CPUState *env, int level) | |
1237 | { | |
1238 | struct kvm_vcpu_events events; | |
1239 | ||
1240 | if (!kvm_has_vcpu_events()) { | |
1241 | return 0; | |
1242 | } | |
1243 | ||
1244 | events.exception.injected = (env->exception_injected >= 0); | |
1245 | events.exception.nr = env->exception_injected; | |
1246 | events.exception.has_error_code = env->has_error_code; | |
1247 | events.exception.error_code = env->error_code; | |
1248 | ||
1249 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
1250 | events.interrupt.nr = env->interrupt_injected; | |
1251 | events.interrupt.soft = env->soft_interrupt; | |
1252 | ||
1253 | events.nmi.injected = env->nmi_injected; | |
1254 | events.nmi.pending = env->nmi_pending; | |
1255 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
1256 | ||
1257 | events.sipi_vector = env->sipi_vector; | |
1258 | ||
1259 | events.flags = 0; | |
1260 | if (level >= KVM_PUT_RESET_STATE) { | |
1261 | events.flags |= | |
1262 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
1263 | } | |
1264 | ||
1265 | return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events); | |
1266 | } | |
1267 | ||
1268 | static int kvm_get_vcpu_events(CPUState *env) | |
1269 | { | |
1270 | struct kvm_vcpu_events events; | |
1271 | int ret; | |
1272 | ||
1273 | if (!kvm_has_vcpu_events()) { | |
1274 | return 0; | |
1275 | } | |
1276 | ||
1277 | ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events); | |
1278 | if (ret < 0) { | |
1279 | return ret; | |
1280 | } | |
1281 | env->exception_injected = | |
1282 | events.exception.injected ? events.exception.nr : -1; | |
1283 | env->has_error_code = events.exception.has_error_code; | |
1284 | env->error_code = events.exception.error_code; | |
1285 | ||
1286 | env->interrupt_injected = | |
1287 | events.interrupt.injected ? events.interrupt.nr : -1; | |
1288 | env->soft_interrupt = events.interrupt.soft; | |
1289 | ||
1290 | env->nmi_injected = events.nmi.injected; | |
1291 | env->nmi_pending = events.nmi.pending; | |
1292 | if (events.nmi.masked) { | |
1293 | env->hflags2 |= HF2_NMI_MASK; | |
1294 | } else { | |
1295 | env->hflags2 &= ~HF2_NMI_MASK; | |
1296 | } | |
1297 | ||
1298 | env->sipi_vector = events.sipi_vector; | |
1299 | ||
1300 | return 0; | |
1301 | } | |
1302 | ||
1303 | static int kvm_guest_debug_workarounds(CPUState *env) | |
1304 | { | |
1305 | int ret = 0; | |
1306 | unsigned long reinject_trap = 0; | |
1307 | ||
1308 | if (!kvm_has_vcpu_events()) { | |
1309 | if (env->exception_injected == 1) { | |
1310 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
1311 | } else if (env->exception_injected == 3) { | |
1312 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
1313 | } | |
1314 | env->exception_injected = -1; | |
1315 | } | |
1316 | ||
1317 | /* | |
1318 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
1319 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
1320 | * by updating the debug state once again if single-stepping is on. | |
1321 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
1322 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
1323 | * reinject them via SET_GUEST_DEBUG. | |
1324 | */ | |
1325 | if (reinject_trap || | |
1326 | (!kvm_has_robust_singlestep() && env->singlestep_enabled)) { | |
1327 | ret = kvm_update_guest_debug(env, reinject_trap); | |
1328 | } | |
1329 | return ret; | |
1330 | } | |
1331 | ||
1332 | static int kvm_put_debugregs(CPUState *env) | |
1333 | { | |
1334 | struct kvm_debugregs dbgregs; | |
1335 | int i; | |
1336 | ||
1337 | if (!kvm_has_debugregs()) { | |
1338 | return 0; | |
1339 | } | |
1340 | ||
1341 | for (i = 0; i < 4; i++) { | |
1342 | dbgregs.db[i] = env->dr[i]; | |
1343 | } | |
1344 | dbgregs.dr6 = env->dr[6]; | |
1345 | dbgregs.dr7 = env->dr[7]; | |
1346 | dbgregs.flags = 0; | |
1347 | ||
1348 | return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs); | |
1349 | } | |
1350 | ||
1351 | static int kvm_get_debugregs(CPUState *env) | |
1352 | { | |
1353 | struct kvm_debugregs dbgregs; | |
1354 | int i, ret; | |
1355 | ||
1356 | if (!kvm_has_debugregs()) { | |
1357 | return 0; | |
1358 | } | |
1359 | ||
1360 | ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs); | |
1361 | if (ret < 0) { | |
1362 | return ret; | |
1363 | } | |
1364 | for (i = 0; i < 4; i++) { | |
1365 | env->dr[i] = dbgregs.db[i]; | |
1366 | } | |
1367 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
1368 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
1369 | ||
1370 | return 0; | |
1371 | } | |
1372 | ||
1373 | int kvm_arch_put_registers(CPUState *env, int level) | |
1374 | { | |
1375 | int ret; | |
1376 | ||
1377 | assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); | |
1378 | ||
1379 | ret = kvm_getput_regs(env, 1); | |
1380 | if (ret < 0) { | |
1381 | return ret; | |
1382 | } | |
1383 | ret = kvm_put_xsave(env); | |
1384 | if (ret < 0) { | |
1385 | return ret; | |
1386 | } | |
1387 | ret = kvm_put_xcrs(env); | |
1388 | if (ret < 0) { | |
1389 | return ret; | |
1390 | } | |
1391 | ret = kvm_put_sregs(env); | |
1392 | if (ret < 0) { | |
1393 | return ret; | |
1394 | } | |
1395 | /* must be before kvm_put_msrs */ | |
1396 | ret = kvm_inject_mce_oldstyle(env); | |
1397 | if (ret < 0) { | |
1398 | return ret; | |
1399 | } | |
1400 | ret = kvm_put_msrs(env, level); | |
1401 | if (ret < 0) { | |
1402 | return ret; | |
1403 | } | |
1404 | if (level >= KVM_PUT_RESET_STATE) { | |
1405 | ret = kvm_put_mp_state(env); | |
1406 | if (ret < 0) { | |
1407 | return ret; | |
1408 | } | |
1409 | } | |
1410 | ret = kvm_put_vcpu_events(env, level); | |
1411 | if (ret < 0) { | |
1412 | return ret; | |
1413 | } | |
1414 | ret = kvm_put_debugregs(env); | |
1415 | if (ret < 0) { | |
1416 | return ret; | |
1417 | } | |
1418 | /* must be last */ | |
1419 | ret = kvm_guest_debug_workarounds(env); | |
1420 | if (ret < 0) { | |
1421 | return ret; | |
1422 | } | |
1423 | return 0; | |
1424 | } | |
1425 | ||
1426 | int kvm_arch_get_registers(CPUState *env) | |
1427 | { | |
1428 | int ret; | |
1429 | ||
1430 | assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); | |
1431 | ||
1432 | ret = kvm_getput_regs(env, 0); | |
1433 | if (ret < 0) { | |
1434 | return ret; | |
1435 | } | |
1436 | ret = kvm_get_xsave(env); | |
1437 | if (ret < 0) { | |
1438 | return ret; | |
1439 | } | |
1440 | ret = kvm_get_xcrs(env); | |
1441 | if (ret < 0) { | |
1442 | return ret; | |
1443 | } | |
1444 | ret = kvm_get_sregs(env); | |
1445 | if (ret < 0) { | |
1446 | return ret; | |
1447 | } | |
1448 | ret = kvm_get_msrs(env); | |
1449 | if (ret < 0) { | |
1450 | return ret; | |
1451 | } | |
1452 | ret = kvm_get_mp_state(env); | |
1453 | if (ret < 0) { | |
1454 | return ret; | |
1455 | } | |
1456 | ret = kvm_get_vcpu_events(env); | |
1457 | if (ret < 0) { | |
1458 | return ret; | |
1459 | } | |
1460 | ret = kvm_get_debugregs(env); | |
1461 | if (ret < 0) { | |
1462 | return ret; | |
1463 | } | |
1464 | return 0; | |
1465 | } | |
1466 | ||
1467 | void kvm_arch_pre_run(CPUState *env, struct kvm_run *run) | |
1468 | { | |
1469 | int ret; | |
1470 | ||
1471 | /* Inject NMI */ | |
1472 | if (env->interrupt_request & CPU_INTERRUPT_NMI) { | |
1473 | env->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
1474 | DPRINTF("injected NMI\n"); | |
1475 | ret = kvm_vcpu_ioctl(env, KVM_NMI); | |
1476 | if (ret < 0) { | |
1477 | fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", | |
1478 | strerror(-ret)); | |
1479 | } | |
1480 | } | |
1481 | ||
1482 | if (!kvm_irqchip_in_kernel()) { | |
1483 | /* Force the VCPU out of its inner loop to process the INIT request */ | |
1484 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { | |
1485 | env->exit_request = 1; | |
1486 | } | |
1487 | ||
1488 | /* Try to inject an interrupt if the guest can accept it */ | |
1489 | if (run->ready_for_interrupt_injection && | |
1490 | (env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1491 | (env->eflags & IF_MASK)) { | |
1492 | int irq; | |
1493 | ||
1494 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
1495 | irq = cpu_get_pic_interrupt(env); | |
1496 | if (irq >= 0) { | |
1497 | struct kvm_interrupt intr; | |
1498 | ||
1499 | intr.irq = irq; | |
1500 | DPRINTF("injected interrupt %d\n", irq); | |
1501 | ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr); | |
1502 | if (ret < 0) { | |
1503 | fprintf(stderr, | |
1504 | "KVM: injection failed, interrupt lost (%s)\n", | |
1505 | strerror(-ret)); | |
1506 | } | |
1507 | } | |
1508 | } | |
1509 | ||
1510 | /* If we have an interrupt but the guest is not ready to receive an | |
1511 | * interrupt, request an interrupt window exit. This will | |
1512 | * cause a return to userspace as soon as the guest is ready to | |
1513 | * receive interrupts. */ | |
1514 | if ((env->interrupt_request & CPU_INTERRUPT_HARD)) { | |
1515 | run->request_interrupt_window = 1; | |
1516 | } else { | |
1517 | run->request_interrupt_window = 0; | |
1518 | } | |
1519 | ||
1520 | DPRINTF("setting tpr\n"); | |
1521 | run->cr8 = cpu_get_apic_tpr(env->apic_state); | |
1522 | } | |
1523 | } | |
1524 | ||
1525 | void kvm_arch_post_run(CPUState *env, struct kvm_run *run) | |
1526 | { | |
1527 | if (run->if_flag) { | |
1528 | env->eflags |= IF_MASK; | |
1529 | } else { | |
1530 | env->eflags &= ~IF_MASK; | |
1531 | } | |
1532 | cpu_set_apic_tpr(env->apic_state, run->cr8); | |
1533 | cpu_set_apic_base(env->apic_state, run->apic_base); | |
1534 | } | |
1535 | ||
1536 | int kvm_arch_process_async_events(CPUState *env) | |
1537 | { | |
1538 | if (env->interrupt_request & CPU_INTERRUPT_MCE) { | |
1539 | /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ | |
1540 | assert(env->mcg_cap); | |
1541 | ||
1542 | env->interrupt_request &= ~CPU_INTERRUPT_MCE; | |
1543 | ||
1544 | kvm_cpu_synchronize_state(env); | |
1545 | ||
1546 | if (env->exception_injected == EXCP08_DBLE) { | |
1547 | /* this means triple fault */ | |
1548 | qemu_system_reset_request(); | |
1549 | env->exit_request = 1; | |
1550 | return 0; | |
1551 | } | |
1552 | env->exception_injected = EXCP12_MCHK; | |
1553 | env->has_error_code = 0; | |
1554 | ||
1555 | env->halted = 0; | |
1556 | if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) { | |
1557 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
1558 | } | |
1559 | } | |
1560 | ||
1561 | if (kvm_irqchip_in_kernel()) { | |
1562 | return 0; | |
1563 | } | |
1564 | ||
1565 | if (((env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1566 | (env->eflags & IF_MASK)) || | |
1567 | (env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
1568 | env->halted = 0; | |
1569 | } | |
1570 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { | |
1571 | kvm_cpu_synchronize_state(env); | |
1572 | do_cpu_init(env); | |
1573 | } | |
1574 | if (env->interrupt_request & CPU_INTERRUPT_SIPI) { | |
1575 | kvm_cpu_synchronize_state(env); | |
1576 | do_cpu_sipi(env); | |
1577 | } | |
1578 | ||
1579 | return env->halted; | |
1580 | } | |
1581 | ||
1582 | static int kvm_handle_halt(CPUState *env) | |
1583 | { | |
1584 | if (!((env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1585 | (env->eflags & IF_MASK)) && | |
1586 | !(env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
1587 | env->halted = 1; | |
1588 | return EXCP_HLT; | |
1589 | } | |
1590 | ||
1591 | return 0; | |
1592 | } | |
1593 | ||
1594 | int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) | |
1595 | { | |
1596 | static const uint8_t int3 = 0xcc; | |
1597 | ||
1598 | if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || | |
1599 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) { | |
1600 | return -EINVAL; | |
1601 | } | |
1602 | return 0; | |
1603 | } | |
1604 | ||
1605 | int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) | |
1606 | { | |
1607 | uint8_t int3; | |
1608 | ||
1609 | if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc || | |
1610 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { | |
1611 | return -EINVAL; | |
1612 | } | |
1613 | return 0; | |
1614 | } | |
1615 | ||
1616 | static struct { | |
1617 | target_ulong addr; | |
1618 | int len; | |
1619 | int type; | |
1620 | } hw_breakpoint[4]; | |
1621 | ||
1622 | static int nb_hw_breakpoint; | |
1623 | ||
1624 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
1625 | { | |
1626 | int n; | |
1627 | ||
1628 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
1629 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && | |
1630 | (hw_breakpoint[n].len == len || len == -1)) { | |
1631 | return n; | |
1632 | } | |
1633 | } | |
1634 | return -1; | |
1635 | } | |
1636 | ||
1637 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
1638 | target_ulong len, int type) | |
1639 | { | |
1640 | switch (type) { | |
1641 | case GDB_BREAKPOINT_HW: | |
1642 | len = 1; | |
1643 | break; | |
1644 | case GDB_WATCHPOINT_WRITE: | |
1645 | case GDB_WATCHPOINT_ACCESS: | |
1646 | switch (len) { | |
1647 | case 1: | |
1648 | break; | |
1649 | case 2: | |
1650 | case 4: | |
1651 | case 8: | |
1652 | if (addr & (len - 1)) { | |
1653 | return -EINVAL; | |
1654 | } | |
1655 | break; | |
1656 | default: | |
1657 | return -EINVAL; | |
1658 | } | |
1659 | break; | |
1660 | default: | |
1661 | return -ENOSYS; | |
1662 | } | |
1663 | ||
1664 | if (nb_hw_breakpoint == 4) { | |
1665 | return -ENOBUFS; | |
1666 | } | |
1667 | if (find_hw_breakpoint(addr, len, type) >= 0) { | |
1668 | return -EEXIST; | |
1669 | } | |
1670 | hw_breakpoint[nb_hw_breakpoint].addr = addr; | |
1671 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
1672 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
1673 | nb_hw_breakpoint++; | |
1674 | ||
1675 | return 0; | |
1676 | } | |
1677 | ||
1678 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
1679 | target_ulong len, int type) | |
1680 | { | |
1681 | int n; | |
1682 | ||
1683 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
1684 | if (n < 0) { | |
1685 | return -ENOENT; | |
1686 | } | |
1687 | nb_hw_breakpoint--; | |
1688 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
1689 | ||
1690 | return 0; | |
1691 | } | |
1692 | ||
1693 | void kvm_arch_remove_all_hw_breakpoints(void) | |
1694 | { | |
1695 | nb_hw_breakpoint = 0; | |
1696 | } | |
1697 | ||
1698 | static CPUWatchpoint hw_watchpoint; | |
1699 | ||
1700 | static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info) | |
1701 | { | |
1702 | int ret = 0; | |
1703 | int n; | |
1704 | ||
1705 | if (arch_info->exception == 1) { | |
1706 | if (arch_info->dr6 & (1 << 14)) { | |
1707 | if (cpu_single_env->singlestep_enabled) { | |
1708 | ret = EXCP_DEBUG; | |
1709 | } | |
1710 | } else { | |
1711 | for (n = 0; n < 4; n++) { | |
1712 | if (arch_info->dr6 & (1 << n)) { | |
1713 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { | |
1714 | case 0x0: | |
1715 | ret = EXCP_DEBUG; | |
1716 | break; | |
1717 | case 0x1: | |
1718 | ret = EXCP_DEBUG; | |
1719 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1720 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1721 | hw_watchpoint.flags = BP_MEM_WRITE; | |
1722 | break; | |
1723 | case 0x3: | |
1724 | ret = EXCP_DEBUG; | |
1725 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1726 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1727 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
1728 | break; | |
1729 | } | |
1730 | } | |
1731 | } | |
1732 | } | |
1733 | } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) { | |
1734 | ret = EXCP_DEBUG; | |
1735 | } | |
1736 | if (ret == 0) { | |
1737 | cpu_synchronize_state(cpu_single_env); | |
1738 | assert(cpu_single_env->exception_injected == -1); | |
1739 | ||
1740 | /* pass to guest */ | |
1741 | cpu_single_env->exception_injected = arch_info->exception; | |
1742 | cpu_single_env->has_error_code = 0; | |
1743 | } | |
1744 | ||
1745 | return ret; | |
1746 | } | |
1747 | ||
1748 | void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg) | |
1749 | { | |
1750 | const uint8_t type_code[] = { | |
1751 | [GDB_BREAKPOINT_HW] = 0x0, | |
1752 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
1753 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
1754 | }; | |
1755 | const uint8_t len_code[] = { | |
1756 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
1757 | }; | |
1758 | int n; | |
1759 | ||
1760 | if (kvm_sw_breakpoints_active(env)) { | |
1761 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; | |
1762 | } | |
1763 | if (nb_hw_breakpoint > 0) { | |
1764 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
1765 | dbg->arch.debugreg[7] = 0x0600; | |
1766 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
1767 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
1768 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
1769 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
1770 | ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); | |
1771 | } | |
1772 | } | |
1773 | } | |
1774 | ||
1775 | static bool host_supports_vmx(void) | |
1776 | { | |
1777 | uint32_t ecx, unused; | |
1778 | ||
1779 | host_cpuid(1, 0, &unused, &unused, &ecx, &unused); | |
1780 | return ecx & CPUID_EXT_VMX; | |
1781 | } | |
1782 | ||
1783 | #define VMX_INVALID_GUEST_STATE 0x80000021 | |
1784 | ||
1785 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) | |
1786 | { | |
1787 | uint64_t code; | |
1788 | int ret; | |
1789 | ||
1790 | switch (run->exit_reason) { | |
1791 | case KVM_EXIT_HLT: | |
1792 | DPRINTF("handle_hlt\n"); | |
1793 | ret = kvm_handle_halt(env); | |
1794 | break; | |
1795 | case KVM_EXIT_SET_TPR: | |
1796 | ret = 0; | |
1797 | break; | |
1798 | case KVM_EXIT_FAIL_ENTRY: | |
1799 | code = run->fail_entry.hardware_entry_failure_reason; | |
1800 | fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", | |
1801 | code); | |
1802 | if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { | |
1803 | fprintf(stderr, | |
1804 | "\nIf you're runnning a guest on an Intel machine without " | |
1805 | "unrestricted mode\n" | |
1806 | "support, the failure can be most likely due to the guest " | |
1807 | "entering an invalid\n" | |
1808 | "state for Intel VT. For example, the guest maybe running " | |
1809 | "in big real mode\n" | |
1810 | "which is not supported on less recent Intel processors." | |
1811 | "\n\n"); | |
1812 | } | |
1813 | ret = -1; | |
1814 | break; | |
1815 | case KVM_EXIT_EXCEPTION: | |
1816 | fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", | |
1817 | run->ex.exception, run->ex.error_code); | |
1818 | ret = -1; | |
1819 | break; | |
1820 | case KVM_EXIT_DEBUG: | |
1821 | DPRINTF("kvm_exit_debug\n"); | |
1822 | ret = kvm_handle_debug(&run->debug.arch); | |
1823 | break; | |
1824 | default: | |
1825 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
1826 | ret = -1; | |
1827 | break; | |
1828 | } | |
1829 | ||
1830 | return ret; | |
1831 | } | |
1832 | ||
1833 | bool kvm_arch_stop_on_emulation_error(CPUState *env) | |
1834 | { | |
1835 | return !(env->cr[0] & CR0_PE_MASK) || | |
1836 | ((env->segs[R_CS].selector & 3) != 3); | |
1837 | } |