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1 | /* | |
2 | * QEMU OpenRISC CPU | |
3 | * | |
4 | * Copyright (c) 2012 Jia Liu <proljc@gmail.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "cpu.h" | |
21 | #include "qemu-common.h" | |
22 | ||
23 | static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) | |
24 | { | |
25 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); | |
26 | ||
27 | cpu->env.pc = value; | |
28 | } | |
29 | ||
30 | /* CPUClass::reset() */ | |
31 | static void openrisc_cpu_reset(CPUState *s) | |
32 | { | |
33 | OpenRISCCPU *cpu = OPENRISC_CPU(s); | |
34 | OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); | |
35 | ||
36 | occ->parent_reset(s); | |
37 | ||
38 | memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints)); | |
39 | ||
40 | tlb_flush(&cpu->env, 1); | |
41 | /*tb_flush(&cpu->env); FIXME: Do we need it? */ | |
42 | ||
43 | cpu->env.pc = 0x100; | |
44 | cpu->env.sr = SR_FO | SR_SM; | |
45 | cpu->env.exception_index = -1; | |
46 | ||
47 | cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; | |
48 | cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S; | |
49 | cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2)); | |
50 | cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2)); | |
51 | ||
52 | #ifndef CONFIG_USER_ONLY | |
53 | cpu->env.picmr = 0x00000000; | |
54 | cpu->env.picsr = 0x00000000; | |
55 | ||
56 | cpu->env.ttmr = 0x00000000; | |
57 | cpu->env.ttcr = 0x00000000; | |
58 | #endif | |
59 | } | |
60 | ||
61 | static inline void set_feature(OpenRISCCPU *cpu, int feature) | |
62 | { | |
63 | cpu->feature |= feature; | |
64 | cpu->env.cpucfgr = cpu->feature; | |
65 | } | |
66 | ||
67 | static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) | |
68 | { | |
69 | OpenRISCCPU *cpu = OPENRISC_CPU(dev); | |
70 | OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); | |
71 | ||
72 | cpu_reset(CPU(cpu)); | |
73 | ||
74 | occ->parent_realize(dev, errp); | |
75 | } | |
76 | ||
77 | static void openrisc_cpu_initfn(Object *obj) | |
78 | { | |
79 | CPUState *cs = CPU(obj); | |
80 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
81 | static int inited; | |
82 | ||
83 | cs->env_ptr = &cpu->env; | |
84 | cpu_exec_init(&cpu->env); | |
85 | ||
86 | #ifndef CONFIG_USER_ONLY | |
87 | cpu_openrisc_mmu_init(cpu); | |
88 | #endif | |
89 | ||
90 | if (tcg_enabled() && !inited) { | |
91 | inited = 1; | |
92 | openrisc_translate_init(); | |
93 | } | |
94 | } | |
95 | ||
96 | /* CPU models */ | |
97 | ||
98 | static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) | |
99 | { | |
100 | ObjectClass *oc; | |
101 | char *typename; | |
102 | ||
103 | if (cpu_model == NULL) { | |
104 | return NULL; | |
105 | } | |
106 | ||
107 | typename = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, cpu_model); | |
108 | oc = object_class_by_name(typename); | |
109 | g_free(typename); | |
110 | if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) || | |
111 | object_class_is_abstract(oc))) { | |
112 | return NULL; | |
113 | } | |
114 | return oc; | |
115 | } | |
116 | ||
117 | static void or1200_initfn(Object *obj) | |
118 | { | |
119 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
120 | ||
121 | set_feature(cpu, OPENRISC_FEATURE_OB32S); | |
122 | set_feature(cpu, OPENRISC_FEATURE_OF32S); | |
123 | } | |
124 | ||
125 | static void openrisc_any_initfn(Object *obj) | |
126 | { | |
127 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
128 | ||
129 | set_feature(cpu, OPENRISC_FEATURE_OB32S); | |
130 | } | |
131 | ||
132 | typedef struct OpenRISCCPUInfo { | |
133 | const char *name; | |
134 | void (*initfn)(Object *obj); | |
135 | } OpenRISCCPUInfo; | |
136 | ||
137 | static const OpenRISCCPUInfo openrisc_cpus[] = { | |
138 | { .name = "or1200", .initfn = or1200_initfn }, | |
139 | { .name = "any", .initfn = openrisc_any_initfn }, | |
140 | }; | |
141 | ||
142 | static void openrisc_cpu_class_init(ObjectClass *oc, void *data) | |
143 | { | |
144 | OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); | |
145 | CPUClass *cc = CPU_CLASS(occ); | |
146 | DeviceClass *dc = DEVICE_CLASS(oc); | |
147 | ||
148 | occ->parent_realize = dc->realize; | |
149 | dc->realize = openrisc_cpu_realizefn; | |
150 | ||
151 | occ->parent_reset = cc->reset; | |
152 | cc->reset = openrisc_cpu_reset; | |
153 | ||
154 | cc->class_by_name = openrisc_cpu_class_by_name; | |
155 | cc->do_interrupt = openrisc_cpu_do_interrupt; | |
156 | cc->dump_state = openrisc_cpu_dump_state; | |
157 | cc->set_pc = openrisc_cpu_set_pc; | |
158 | #ifndef CONFIG_USER_ONLY | |
159 | cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; | |
160 | dc->vmsd = &vmstate_openrisc_cpu; | |
161 | #endif | |
162 | cc->gdb_num_core_regs = 32 + 3; | |
163 | } | |
164 | ||
165 | static void cpu_register(const OpenRISCCPUInfo *info) | |
166 | { | |
167 | TypeInfo type_info = { | |
168 | .parent = TYPE_OPENRISC_CPU, | |
169 | .instance_size = sizeof(OpenRISCCPU), | |
170 | .instance_init = info->initfn, | |
171 | .class_size = sizeof(OpenRISCCPUClass), | |
172 | }; | |
173 | ||
174 | type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name); | |
175 | type_register(&type_info); | |
176 | g_free((void *)type_info.name); | |
177 | } | |
178 | ||
179 | static const TypeInfo openrisc_cpu_type_info = { | |
180 | .name = TYPE_OPENRISC_CPU, | |
181 | .parent = TYPE_CPU, | |
182 | .instance_size = sizeof(OpenRISCCPU), | |
183 | .instance_init = openrisc_cpu_initfn, | |
184 | .abstract = true, | |
185 | .class_size = sizeof(OpenRISCCPUClass), | |
186 | .class_init = openrisc_cpu_class_init, | |
187 | }; | |
188 | ||
189 | static void openrisc_cpu_register_types(void) | |
190 | { | |
191 | int i; | |
192 | ||
193 | type_register_static(&openrisc_cpu_type_info); | |
194 | for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) { | |
195 | cpu_register(&openrisc_cpus[i]); | |
196 | } | |
197 | } | |
198 | ||
199 | OpenRISCCPU *cpu_openrisc_init(const char *cpu_model) | |
200 | { | |
201 | OpenRISCCPU *cpu; | |
202 | ObjectClass *oc; | |
203 | ||
204 | oc = openrisc_cpu_class_by_name(cpu_model); | |
205 | if (oc == NULL) { | |
206 | return NULL; | |
207 | } | |
208 | cpu = OPENRISC_CPU(object_new(object_class_get_name(oc))); | |
209 | cpu->env.cpu_model_str = cpu_model; | |
210 | ||
211 | object_property_set_bool(OBJECT(cpu), true, "realized", NULL); | |
212 | ||
213 | return cpu; | |
214 | } | |
215 | ||
216 | /* Sort alphabetically by type name, except for "any". */ | |
217 | static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b) | |
218 | { | |
219 | ObjectClass *class_a = (ObjectClass *)a; | |
220 | ObjectClass *class_b = (ObjectClass *)b; | |
221 | const char *name_a, *name_b; | |
222 | ||
223 | name_a = object_class_get_name(class_a); | |
224 | name_b = object_class_get_name(class_b); | |
225 | if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) { | |
226 | return 1; | |
227 | } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) { | |
228 | return -1; | |
229 | } else { | |
230 | return strcmp(name_a, name_b); | |
231 | } | |
232 | } | |
233 | ||
234 | static void openrisc_cpu_list_entry(gpointer data, gpointer user_data) | |
235 | { | |
236 | ObjectClass *oc = data; | |
237 | CPUListState *s = user_data; | |
238 | const char *typename; | |
239 | char *name; | |
240 | ||
241 | typename = object_class_get_name(oc); | |
242 | name = g_strndup(typename, | |
243 | strlen(typename) - strlen("-" TYPE_OPENRISC_CPU)); | |
244 | (*s->cpu_fprintf)(s->file, " %s\n", | |
245 | name); | |
246 | g_free(name); | |
247 | } | |
248 | ||
249 | void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf) | |
250 | { | |
251 | CPUListState s = { | |
252 | .file = f, | |
253 | .cpu_fprintf = cpu_fprintf, | |
254 | }; | |
255 | GSList *list; | |
256 | ||
257 | list = object_class_get_list(TYPE_OPENRISC_CPU, false); | |
258 | list = g_slist_sort(list, openrisc_cpu_list_compare); | |
259 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
260 | g_slist_foreach(list, openrisc_cpu_list_entry, &s); | |
261 | g_slist_free(list); | |
262 | } | |
263 | ||
264 | type_init(openrisc_cpu_register_types) |