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1/*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
26#include "cpu.h"
27#include "disas.h"
28#include "tcg-op.h"
29#include "qemu-common.h"
30#include "host-utils.h"
31
32#include "helper.h"
33#define GEN_HELPER 1
34#include "helper.h"
35
36#define CPU_SINGLE_STEP 0x1
37#define CPU_BRANCH_STEP 0x2
38#define GDBSTUB_SINGLE_STEP 0x4
39
40/* Include definitions for instructions classes and implementations flags */
41//#define PPC_DEBUG_DISAS
42//#define DO_PPC_STATISTICS
43
44#ifdef PPC_DEBUG_DISAS
45# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46#else
47# define LOG_DISAS(...) do { } while (0)
48#endif
49/*****************************************************************************/
50/* Code translation helpers */
51
52/* global register indexes */
53static TCGv_ptr cpu_env;
54static char cpu_reg_names[10*3 + 22*4 /* GPR */
55#if !defined(TARGET_PPC64)
56 + 10*4 + 22*5 /* SPE GPRh */
57#endif
58 + 10*4 + 22*5 /* FPR */
59 + 2*(10*6 + 22*7) /* AVRh, AVRl */
60 + 8*5 /* CRF */];
61static TCGv cpu_gpr[32];
62#if !defined(TARGET_PPC64)
63static TCGv cpu_gprh[32];
64#endif
65static TCGv_i64 cpu_fpr[32];
66static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
67static TCGv_i32 cpu_crf[8];
68static TCGv cpu_nip;
69static TCGv cpu_msr;
70static TCGv cpu_ctr;
71static TCGv cpu_lr;
72#if defined(TARGET_PPC64)
73static TCGv cpu_cfar;
74#endif
75static TCGv cpu_xer;
76static TCGv cpu_reserve;
77static TCGv_i32 cpu_fpscr;
78static TCGv_i32 cpu_access_type;
79
80#include "gen-icount.h"
81
82void ppc_translate_init(void)
83{
84 int i;
85 char* p;
86 size_t cpu_reg_names_size;
87 static int done_init = 0;
88
89 if (done_init)
90 return;
91
92 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
93
94 p = cpu_reg_names;
95 cpu_reg_names_size = sizeof(cpu_reg_names);
96
97 for (i = 0; i < 8; i++) {
98 snprintf(p, cpu_reg_names_size, "crf%d", i);
99 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
100 offsetof(CPUState, crf[i]), p);
101 p += 5;
102 cpu_reg_names_size -= 5;
103 }
104
105 for (i = 0; i < 32; i++) {
106 snprintf(p, cpu_reg_names_size, "r%d", i);
107 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
108 offsetof(CPUState, gpr[i]), p);
109 p += (i < 10) ? 3 : 4;
110 cpu_reg_names_size -= (i < 10) ? 3 : 4;
111#if !defined(TARGET_PPC64)
112 snprintf(p, cpu_reg_names_size, "r%dH", i);
113 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
114 offsetof(CPUState, gprh[i]), p);
115 p += (i < 10) ? 4 : 5;
116 cpu_reg_names_size -= (i < 10) ? 4 : 5;
117#endif
118
119 snprintf(p, cpu_reg_names_size, "fp%d", i);
120 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
121 offsetof(CPUState, fpr[i]), p);
122 p += (i < 10) ? 4 : 5;
123 cpu_reg_names_size -= (i < 10) ? 4 : 5;
124
125 snprintf(p, cpu_reg_names_size, "avr%dH", i);
126#ifdef HOST_WORDS_BIGENDIAN
127 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
128 offsetof(CPUState, avr[i].u64[0]), p);
129#else
130 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
131 offsetof(CPUState, avr[i].u64[1]), p);
132#endif
133 p += (i < 10) ? 6 : 7;
134 cpu_reg_names_size -= (i < 10) ? 6 : 7;
135
136 snprintf(p, cpu_reg_names_size, "avr%dL", i);
137#ifdef HOST_WORDS_BIGENDIAN
138 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
139 offsetof(CPUState, avr[i].u64[1]), p);
140#else
141 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
142 offsetof(CPUState, avr[i].u64[0]), p);
143#endif
144 p += (i < 10) ? 6 : 7;
145 cpu_reg_names_size -= (i < 10) ? 6 : 7;
146 }
147
148 cpu_nip = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUState, nip), "nip");
150
151 cpu_msr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUState, msr), "msr");
153
154 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
155 offsetof(CPUState, ctr), "ctr");
156
157 cpu_lr = tcg_global_mem_new(TCG_AREG0,
158 offsetof(CPUState, lr), "lr");
159
160#if defined(TARGET_PPC64)
161 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUState, cfar), "cfar");
163#endif
164
165 cpu_xer = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUState, xer), "xer");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
173 offsetof(CPUState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUState, access_type), "access_type");
177
178 /* register helpers */
179#define GEN_HELPER 2
180#include "helper.h"
181
182 done_init = 1;
183}
184
185/* internal defines */
186typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196#if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199#endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205} DisasContext;
206
207struct opc_handler_t {
208 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
209 uint32_t inval1;
210 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
211 uint32_t inval2;
212 /* instruction type */
213 uint64_t type;
214 /* extended instruction type */
215 uint64_t type2;
216 /* handler */
217 void (*handler)(DisasContext *ctx);
218#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
219 const char *oname;
220#endif
221#if defined(DO_PPC_STATISTICS)
222 uint64_t count;
223#endif
224};
225
226static inline void gen_reset_fpstatus(void)
227{
228 gen_helper_reset_fpstatus();
229}
230
231static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
232{
233 TCGv_i32 t0 = tcg_temp_new_i32();
234
235 if (set_fprf != 0) {
236 /* This case might be optimized later */
237 tcg_gen_movi_i32(t0, 1);
238 gen_helper_compute_fprf(t0, arg, t0);
239 if (unlikely(set_rc)) {
240 tcg_gen_mov_i32(cpu_crf[1], t0);
241 }
242 gen_helper_float_check_status();
243 } else if (unlikely(set_rc)) {
244 /* We always need to compute fpcc */
245 tcg_gen_movi_i32(t0, 0);
246 gen_helper_compute_fprf(t0, arg, t0);
247 tcg_gen_mov_i32(cpu_crf[1], t0);
248 }
249
250 tcg_temp_free_i32(t0);
251}
252
253static inline void gen_set_access_type(DisasContext *ctx, int access_type)
254{
255 if (ctx->access_type != access_type) {
256 tcg_gen_movi_i32(cpu_access_type, access_type);
257 ctx->access_type = access_type;
258 }
259}
260
261static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
262{
263#if defined(TARGET_PPC64)
264 if (ctx->sf_mode)
265 tcg_gen_movi_tl(cpu_nip, nip);
266 else
267#endif
268 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
269}
270
271static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
272{
273 TCGv_i32 t0, t1;
274 if (ctx->exception == POWERPC_EXCP_NONE) {
275 gen_update_nip(ctx, ctx->nip);
276 }
277 t0 = tcg_const_i32(excp);
278 t1 = tcg_const_i32(error);
279 gen_helper_raise_exception_err(t0, t1);
280 tcg_temp_free_i32(t0);
281 tcg_temp_free_i32(t1);
282 ctx->exception = (excp);
283}
284
285static inline void gen_exception(DisasContext *ctx, uint32_t excp)
286{
287 TCGv_i32 t0;
288 if (ctx->exception == POWERPC_EXCP_NONE) {
289 gen_update_nip(ctx, ctx->nip);
290 }
291 t0 = tcg_const_i32(excp);
292 gen_helper_raise_exception(t0);
293 tcg_temp_free_i32(t0);
294 ctx->exception = (excp);
295}
296
297static inline void gen_debug_exception(DisasContext *ctx)
298{
299 TCGv_i32 t0;
300
301 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
302 (ctx->exception != POWERPC_EXCP_SYNC)) {
303 gen_update_nip(ctx, ctx->nip);
304 }
305 t0 = tcg_const_i32(EXCP_DEBUG);
306 gen_helper_raise_exception(t0);
307 tcg_temp_free_i32(t0);
308}
309
310static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
311{
312 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
313}
314
315/* Stop translation */
316static inline void gen_stop_exception(DisasContext *ctx)
317{
318 gen_update_nip(ctx, ctx->nip);
319 ctx->exception = POWERPC_EXCP_STOP;
320}
321
322/* No need to update nip here, as execution flow will change */
323static inline void gen_sync_exception(DisasContext *ctx)
324{
325 ctx->exception = POWERPC_EXCP_SYNC;
326}
327
328#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
329GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
330
331#define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
332GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
333
334#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
335GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
336
337#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
338GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
339
340typedef struct opcode_t {
341 unsigned char opc1, opc2, opc3;
342#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
343 unsigned char pad[5];
344#else
345 unsigned char pad[1];
346#endif
347 opc_handler_t handler;
348 const char *oname;
349} opcode_t;
350
351/*****************************************************************************/
352/*** Instruction decoding ***/
353#define EXTRACT_HELPER(name, shift, nb) \
354static inline uint32_t name(uint32_t opcode) \
355{ \
356 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
357}
358
359#define EXTRACT_SHELPER(name, shift, nb) \
360static inline int32_t name(uint32_t opcode) \
361{ \
362 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
363}
364
365/* Opcode part 1 */
366EXTRACT_HELPER(opc1, 26, 6);
367/* Opcode part 2 */
368EXTRACT_HELPER(opc2, 1, 5);
369/* Opcode part 3 */
370EXTRACT_HELPER(opc3, 6, 5);
371/* Update Cr0 flags */
372EXTRACT_HELPER(Rc, 0, 1);
373/* Destination */
374EXTRACT_HELPER(rD, 21, 5);
375/* Source */
376EXTRACT_HELPER(rS, 21, 5);
377/* First operand */
378EXTRACT_HELPER(rA, 16, 5);
379/* Second operand */
380EXTRACT_HELPER(rB, 11, 5);
381/* Third operand */
382EXTRACT_HELPER(rC, 6, 5);
383/*** Get CRn ***/
384EXTRACT_HELPER(crfD, 23, 3);
385EXTRACT_HELPER(crfS, 18, 3);
386EXTRACT_HELPER(crbD, 21, 5);
387EXTRACT_HELPER(crbA, 16, 5);
388EXTRACT_HELPER(crbB, 11, 5);
389/* SPR / TBL */
390EXTRACT_HELPER(_SPR, 11, 10);
391static inline uint32_t SPR(uint32_t opcode)
392{
393 uint32_t sprn = _SPR(opcode);
394
395 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
396}
397/*** Get constants ***/
398EXTRACT_HELPER(IMM, 12, 8);
399/* 16 bits signed immediate value */
400EXTRACT_SHELPER(SIMM, 0, 16);
401/* 16 bits unsigned immediate value */
402EXTRACT_HELPER(UIMM, 0, 16);
403/* 5 bits signed immediate value */
404EXTRACT_HELPER(SIMM5, 16, 5);
405/* 5 bits signed immediate value */
406EXTRACT_HELPER(UIMM5, 16, 5);
407/* Bit count */
408EXTRACT_HELPER(NB, 11, 5);
409/* Shift count */
410EXTRACT_HELPER(SH, 11, 5);
411/* Vector shift count */
412EXTRACT_HELPER(VSH, 6, 4);
413/* Mask start */
414EXTRACT_HELPER(MB, 6, 5);
415/* Mask end */
416EXTRACT_HELPER(ME, 1, 5);
417/* Trap operand */
418EXTRACT_HELPER(TO, 21, 5);
419
420EXTRACT_HELPER(CRM, 12, 8);
421EXTRACT_HELPER(FM, 17, 8);
422EXTRACT_HELPER(SR, 16, 4);
423EXTRACT_HELPER(FPIMM, 12, 4);
424
425/*** Jump target decoding ***/
426/* Displacement */
427EXTRACT_SHELPER(d, 0, 16);
428/* Immediate address */
429static inline target_ulong LI(uint32_t opcode)
430{
431 return (opcode >> 0) & 0x03FFFFFC;
432}
433
434static inline uint32_t BD(uint32_t opcode)
435{
436 return (opcode >> 0) & 0xFFFC;
437}
438
439EXTRACT_HELPER(BO, 21, 5);
440EXTRACT_HELPER(BI, 16, 5);
441/* Absolute/relative address */
442EXTRACT_HELPER(AA, 1, 1);
443/* Link */
444EXTRACT_HELPER(LK, 0, 1);
445
446/* Create a mask between <start> and <end> bits */
447static inline target_ulong MASK(uint32_t start, uint32_t end)
448{
449 target_ulong ret;
450
451#if defined(TARGET_PPC64)
452 if (likely(start == 0)) {
453 ret = UINT64_MAX << (63 - end);
454 } else if (likely(end == 63)) {
455 ret = UINT64_MAX >> start;
456 }
457#else
458 if (likely(start == 0)) {
459 ret = UINT32_MAX << (31 - end);
460 } else if (likely(end == 31)) {
461 ret = UINT32_MAX >> start;
462 }
463#endif
464 else {
465 ret = (((target_ulong)(-1ULL)) >> (start)) ^
466 (((target_ulong)(-1ULL) >> (end)) >> 1);
467 if (unlikely(start > end))
468 return ~ret;
469 }
470
471 return ret;
472}
473
474/*****************************************************************************/
475/* PowerPC instructions table */
476
477#if defined(DO_PPC_STATISTICS)
478#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
479{ \
480 .opc1 = op1, \
481 .opc2 = op2, \
482 .opc3 = op3, \
483 .pad = { 0, }, \
484 .handler = { \
485 .inval1 = invl, \
486 .type = _typ, \
487 .type2 = _typ2, \
488 .handler = &gen_##name, \
489 .oname = stringify(name), \
490 }, \
491 .oname = stringify(name), \
492}
493#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
494{ \
495 .opc1 = op1, \
496 .opc2 = op2, \
497 .opc3 = op3, \
498 .pad = { 0, }, \
499 .handler = { \
500 .inval1 = invl1, \
501 .inval2 = invl2, \
502 .type = _typ, \
503 .type2 = _typ2, \
504 .handler = &gen_##name, \
505 .oname = stringify(name), \
506 }, \
507 .oname = stringify(name), \
508}
509#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
510{ \
511 .opc1 = op1, \
512 .opc2 = op2, \
513 .opc3 = op3, \
514 .pad = { 0, }, \
515 .handler = { \
516 .inval1 = invl, \
517 .type = _typ, \
518 .type2 = _typ2, \
519 .handler = &gen_##name, \
520 .oname = onam, \
521 }, \
522 .oname = onam, \
523}
524#else
525#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
526{ \
527 .opc1 = op1, \
528 .opc2 = op2, \
529 .opc3 = op3, \
530 .pad = { 0, }, \
531 .handler = { \
532 .inval1 = invl, \
533 .type = _typ, \
534 .type2 = _typ2, \
535 .handler = &gen_##name, \
536 }, \
537 .oname = stringify(name), \
538}
539#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
540{ \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl1, \
547 .inval2 = invl2, \
548 .type = _typ, \
549 .type2 = _typ2, \
550 .handler = &gen_##name, \
551 }, \
552 .oname = stringify(name), \
553}
554#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
555{ \
556 .opc1 = op1, \
557 .opc2 = op2, \
558 .opc3 = op3, \
559 .pad = { 0, }, \
560 .handler = { \
561 .inval1 = invl, \
562 .type = _typ, \
563 .type2 = _typ2, \
564 .handler = &gen_##name, \
565 }, \
566 .oname = onam, \
567}
568#endif
569
570/* SPR load/store helpers */
571static inline void gen_load_spr(TCGv t, int reg)
572{
573 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
574}
575
576static inline void gen_store_spr(int reg, TCGv t)
577{
578 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
579}
580
581/* Invalid instruction */
582static void gen_invalid(DisasContext *ctx)
583{
584 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
585}
586
587static opc_handler_t invalid_handler = {
588 .inval1 = 0xFFFFFFFF,
589 .inval2 = 0xFFFFFFFF,
590 .type = PPC_NONE,
591 .type2 = PPC_NONE,
592 .handler = gen_invalid,
593};
594
595/*** Integer comparison ***/
596
597static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
598{
599 int l1, l2, l3;
600
601 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
602 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
603 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
604
605 l1 = gen_new_label();
606 l2 = gen_new_label();
607 l3 = gen_new_label();
608 if (s) {
609 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
610 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
611 } else {
612 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
613 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
614 }
615 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
616 tcg_gen_br(l3);
617 gen_set_label(l1);
618 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
619 tcg_gen_br(l3);
620 gen_set_label(l2);
621 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
622 gen_set_label(l3);
623}
624
625static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
626{
627 TCGv t0 = tcg_const_local_tl(arg1);
628 gen_op_cmp(arg0, t0, s, crf);
629 tcg_temp_free(t0);
630}
631
632#if defined(TARGET_PPC64)
633static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
634{
635 TCGv t0, t1;
636 t0 = tcg_temp_local_new();
637 t1 = tcg_temp_local_new();
638 if (s) {
639 tcg_gen_ext32s_tl(t0, arg0);
640 tcg_gen_ext32s_tl(t1, arg1);
641 } else {
642 tcg_gen_ext32u_tl(t0, arg0);
643 tcg_gen_ext32u_tl(t1, arg1);
644 }
645 gen_op_cmp(t0, t1, s, crf);
646 tcg_temp_free(t1);
647 tcg_temp_free(t0);
648}
649
650static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
651{
652 TCGv t0 = tcg_const_local_tl(arg1);
653 gen_op_cmp32(arg0, t0, s, crf);
654 tcg_temp_free(t0);
655}
656#endif
657
658static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
659{
660#if defined(TARGET_PPC64)
661 if (!(ctx->sf_mode))
662 gen_op_cmpi32(reg, 0, 1, 0);
663 else
664#endif
665 gen_op_cmpi(reg, 0, 1, 0);
666}
667
668/* cmp */
669static void gen_cmp(DisasContext *ctx)
670{
671#if defined(TARGET_PPC64)
672 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
673 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
674 1, crfD(ctx->opcode));
675 else
676#endif
677 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
678 1, crfD(ctx->opcode));
679}
680
681/* cmpi */
682static void gen_cmpi(DisasContext *ctx)
683{
684#if defined(TARGET_PPC64)
685 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
686 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
687 1, crfD(ctx->opcode));
688 else
689#endif
690 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
691 1, crfD(ctx->opcode));
692}
693
694/* cmpl */
695static void gen_cmpl(DisasContext *ctx)
696{
697#if defined(TARGET_PPC64)
698 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
699 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
700 0, crfD(ctx->opcode));
701 else
702#endif
703 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
704 0, crfD(ctx->opcode));
705}
706
707/* cmpli */
708static void gen_cmpli(DisasContext *ctx)
709{
710#if defined(TARGET_PPC64)
711 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
712 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
713 0, crfD(ctx->opcode));
714 else
715#endif
716 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
717 0, crfD(ctx->opcode));
718}
719
720/* isel (PowerPC 2.03 specification) */
721static void gen_isel(DisasContext *ctx)
722{
723 int l1, l2;
724 uint32_t bi = rC(ctx->opcode);
725 uint32_t mask;
726 TCGv_i32 t0;
727
728 l1 = gen_new_label();
729 l2 = gen_new_label();
730
731 mask = 1 << (3 - (bi & 0x03));
732 t0 = tcg_temp_new_i32();
733 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
734 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
735 if (rA(ctx->opcode) == 0)
736 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
737 else
738 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
739 tcg_gen_br(l2);
740 gen_set_label(l1);
741 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
742 gen_set_label(l2);
743 tcg_temp_free_i32(t0);
744}
745
746/*** Integer arithmetic ***/
747
748static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
749 TCGv arg1, TCGv arg2, int sub)
750{
751 int l1;
752 TCGv t0;
753
754 l1 = gen_new_label();
755 /* Start with XER OV disabled, the most likely case */
756 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
757 t0 = tcg_temp_local_new();
758 tcg_gen_xor_tl(t0, arg0, arg1);
759#if defined(TARGET_PPC64)
760 if (!ctx->sf_mode)
761 tcg_gen_ext32s_tl(t0, t0);
762#endif
763 if (sub)
764 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
765 else
766 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
767 tcg_gen_xor_tl(t0, arg1, arg2);
768#if defined(TARGET_PPC64)
769 if (!ctx->sf_mode)
770 tcg_gen_ext32s_tl(t0, t0);
771#endif
772 if (sub)
773 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
774 else
775 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
776 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
777 gen_set_label(l1);
778 tcg_temp_free(t0);
779}
780
781static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
782 TCGv arg2, int sub)
783{
784 int l1 = gen_new_label();
785
786#if defined(TARGET_PPC64)
787 if (!(ctx->sf_mode)) {
788 TCGv t0, t1;
789 t0 = tcg_temp_new();
790 t1 = tcg_temp_new();
791
792 tcg_gen_ext32u_tl(t0, arg1);
793 tcg_gen_ext32u_tl(t1, arg2);
794 if (sub) {
795 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
796 } else {
797 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
798 }
799 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
800 gen_set_label(l1);
801 tcg_temp_free(t0);
802 tcg_temp_free(t1);
803 } else
804#endif
805 {
806 if (sub) {
807 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
808 } else {
809 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
810 }
811 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
812 gen_set_label(l1);
813 }
814}
815
816/* Common add function */
817static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
818 TCGv arg2, int add_ca, int compute_ca,
819 int compute_ov)
820{
821 TCGv t0, t1;
822
823 if ((!compute_ca && !compute_ov) ||
824 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
825 t0 = ret;
826 } else {
827 t0 = tcg_temp_local_new();
828 }
829
830 if (add_ca) {
831 t1 = tcg_temp_local_new();
832 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
833 tcg_gen_shri_tl(t1, t1, XER_CA);
834 } else {
835 TCGV_UNUSED(t1);
836 }
837
838 if (compute_ca && compute_ov) {
839 /* Start with XER CA and OV disabled, the most likely case */
840 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
841 } else if (compute_ca) {
842 /* Start with XER CA disabled, the most likely case */
843 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
844 } else if (compute_ov) {
845 /* Start with XER OV disabled, the most likely case */
846 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
847 }
848
849 tcg_gen_add_tl(t0, arg1, arg2);
850
851 if (compute_ca) {
852 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
853 }
854 if (add_ca) {
855 tcg_gen_add_tl(t0, t0, t1);
856 gen_op_arith_compute_ca(ctx, t0, t1, 0);
857 tcg_temp_free(t1);
858 }
859 if (compute_ov) {
860 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
861 }
862
863 if (unlikely(Rc(ctx->opcode) != 0))
864 gen_set_Rc0(ctx, t0);
865
866 if (!TCGV_EQUAL(t0, ret)) {
867 tcg_gen_mov_tl(ret, t0);
868 tcg_temp_free(t0);
869 }
870}
871/* Add functions with two operands */
872#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
873static void glue(gen_, name)(DisasContext *ctx) \
874{ \
875 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
876 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
877 add_ca, compute_ca, compute_ov); \
878}
879/* Add functions with one operand and one immediate */
880#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
881 add_ca, compute_ca, compute_ov) \
882static void glue(gen_, name)(DisasContext *ctx) \
883{ \
884 TCGv t0 = tcg_const_local_tl(const_val); \
885 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
886 cpu_gpr[rA(ctx->opcode)], t0, \
887 add_ca, compute_ca, compute_ov); \
888 tcg_temp_free(t0); \
889}
890
891/* add add. addo addo. */
892GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
893GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
894/* addc addc. addco addco. */
895GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
896GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
897/* adde adde. addeo addeo. */
898GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
899GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
900/* addme addme. addmeo addmeo. */
901GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
902GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
903/* addze addze. addzeo addzeo.*/
904GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
905GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
906/* addi */
907static void gen_addi(DisasContext *ctx)
908{
909 target_long simm = SIMM(ctx->opcode);
910
911 if (rA(ctx->opcode) == 0) {
912 /* li case */
913 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
914 } else {
915 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
916 }
917}
918/* addic addic.*/
919static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1,
920 int compute_Rc0)
921{
922 target_long simm = SIMM(ctx->opcode);
923
924 /* Start with XER CA and OV disabled, the most likely case */
925 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
926
927 if (likely(simm != 0)) {
928 TCGv t0 = tcg_temp_local_new();
929 tcg_gen_addi_tl(t0, arg1, simm);
930 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
931 tcg_gen_mov_tl(ret, t0);
932 tcg_temp_free(t0);
933 } else {
934 tcg_gen_mov_tl(ret, arg1);
935 }
936 if (compute_Rc0) {
937 gen_set_Rc0(ctx, ret);
938 }
939}
940
941static void gen_addic(DisasContext *ctx)
942{
943 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
944}
945
946static void gen_addic_(DisasContext *ctx)
947{
948 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
949}
950
951/* addis */
952static void gen_addis(DisasContext *ctx)
953{
954 target_long simm = SIMM(ctx->opcode);
955
956 if (rA(ctx->opcode) == 0) {
957 /* lis case */
958 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
959 } else {
960 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
961 }
962}
963
964static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
965 TCGv arg2, int sign, int compute_ov)
966{
967 int l1 = gen_new_label();
968 int l2 = gen_new_label();
969 TCGv_i32 t0 = tcg_temp_local_new_i32();
970 TCGv_i32 t1 = tcg_temp_local_new_i32();
971
972 tcg_gen_trunc_tl_i32(t0, arg1);
973 tcg_gen_trunc_tl_i32(t1, arg2);
974 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
975 if (sign) {
976 int l3 = gen_new_label();
977 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
978 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
979 gen_set_label(l3);
980 tcg_gen_div_i32(t0, t0, t1);
981 } else {
982 tcg_gen_divu_i32(t0, t0, t1);
983 }
984 if (compute_ov) {
985 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
986 }
987 tcg_gen_br(l2);
988 gen_set_label(l1);
989 if (sign) {
990 tcg_gen_sari_i32(t0, t0, 31);
991 } else {
992 tcg_gen_movi_i32(t0, 0);
993 }
994 if (compute_ov) {
995 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
996 }
997 gen_set_label(l2);
998 tcg_gen_extu_i32_tl(ret, t0);
999 tcg_temp_free_i32(t0);
1000 tcg_temp_free_i32(t1);
1001 if (unlikely(Rc(ctx->opcode) != 0))
1002 gen_set_Rc0(ctx, ret);
1003}
1004/* Div functions */
1005#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1006static void glue(gen_, name)(DisasContext *ctx) \
1007{ \
1008 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1009 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1010 sign, compute_ov); \
1011}
1012/* divwu divwu. divwuo divwuo. */
1013GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1014GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1015/* divw divw. divwo divwo. */
1016GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1017GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1018#if defined(TARGET_PPC64)
1019static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1020 TCGv arg2, int sign, int compute_ov)
1021{
1022 int l1 = gen_new_label();
1023 int l2 = gen_new_label();
1024
1025 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1026 if (sign) {
1027 int l3 = gen_new_label();
1028 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1029 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1030 gen_set_label(l3);
1031 tcg_gen_div_i64(ret, arg1, arg2);
1032 } else {
1033 tcg_gen_divu_i64(ret, arg1, arg2);
1034 }
1035 if (compute_ov) {
1036 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1037 }
1038 tcg_gen_br(l2);
1039 gen_set_label(l1);
1040 if (sign) {
1041 tcg_gen_sari_i64(ret, arg1, 63);
1042 } else {
1043 tcg_gen_movi_i64(ret, 0);
1044 }
1045 if (compute_ov) {
1046 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1047 }
1048 gen_set_label(l2);
1049 if (unlikely(Rc(ctx->opcode) != 0))
1050 gen_set_Rc0(ctx, ret);
1051}
1052#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1053static void glue(gen_, name)(DisasContext *ctx) \
1054{ \
1055 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1056 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1057 sign, compute_ov); \
1058}
1059/* divwu divwu. divwuo divwuo. */
1060GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1061GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1062/* divw divw. divwo divwo. */
1063GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1064GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1065#endif
1066
1067/* mulhw mulhw. */
1068static void gen_mulhw(DisasContext *ctx)
1069{
1070 TCGv_i64 t0, t1;
1071
1072 t0 = tcg_temp_new_i64();
1073 t1 = tcg_temp_new_i64();
1074#if defined(TARGET_PPC64)
1075 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1076 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1077 tcg_gen_mul_i64(t0, t0, t1);
1078 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1079#else
1080 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1081 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1082 tcg_gen_mul_i64(t0, t0, t1);
1083 tcg_gen_shri_i64(t0, t0, 32);
1084 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1085#endif
1086 tcg_temp_free_i64(t0);
1087 tcg_temp_free_i64(t1);
1088 if (unlikely(Rc(ctx->opcode) != 0))
1089 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1090}
1091
1092/* mulhwu mulhwu. */
1093static void gen_mulhwu(DisasContext *ctx)
1094{
1095 TCGv_i64 t0, t1;
1096
1097 t0 = tcg_temp_new_i64();
1098 t1 = tcg_temp_new_i64();
1099#if defined(TARGET_PPC64)
1100 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1101 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1102 tcg_gen_mul_i64(t0, t0, t1);
1103 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1104#else
1105 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1106 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1107 tcg_gen_mul_i64(t0, t0, t1);
1108 tcg_gen_shri_i64(t0, t0, 32);
1109 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1110#endif
1111 tcg_temp_free_i64(t0);
1112 tcg_temp_free_i64(t1);
1113 if (unlikely(Rc(ctx->opcode) != 0))
1114 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1115}
1116
1117/* mullw mullw. */
1118static void gen_mullw(DisasContext *ctx)
1119{
1120 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1121 cpu_gpr[rB(ctx->opcode)]);
1122 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1123 if (unlikely(Rc(ctx->opcode) != 0))
1124 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1125}
1126
1127/* mullwo mullwo. */
1128static void gen_mullwo(DisasContext *ctx)
1129{
1130 int l1;
1131 TCGv_i64 t0, t1;
1132
1133 t0 = tcg_temp_new_i64();
1134 t1 = tcg_temp_new_i64();
1135 l1 = gen_new_label();
1136 /* Start with XER OV disabled, the most likely case */
1137 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1138#if defined(TARGET_PPC64)
1139 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1140 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1141#else
1142 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1143 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1144#endif
1145 tcg_gen_mul_i64(t0, t0, t1);
1146#if defined(TARGET_PPC64)
1147 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1148 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1149#else
1150 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1151 tcg_gen_ext32s_i64(t1, t0);
1152 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1153#endif
1154 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1155 gen_set_label(l1);
1156 tcg_temp_free_i64(t0);
1157 tcg_temp_free_i64(t1);
1158 if (unlikely(Rc(ctx->opcode) != 0))
1159 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1160}
1161
1162/* mulli */
1163static void gen_mulli(DisasContext *ctx)
1164{
1165 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1166 SIMM(ctx->opcode));
1167}
1168#if defined(TARGET_PPC64)
1169#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1170static void glue(gen_, name)(DisasContext *ctx) \
1171{ \
1172 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1173 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1174 if (unlikely(Rc(ctx->opcode) != 0)) \
1175 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1176}
1177/* mulhd mulhd. */
1178GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1179/* mulhdu mulhdu. */
1180GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1181
1182/* mulld mulld. */
1183static void gen_mulld(DisasContext *ctx)
1184{
1185 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1186 cpu_gpr[rB(ctx->opcode)]);
1187 if (unlikely(Rc(ctx->opcode) != 0))
1188 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1189}
1190/* mulldo mulldo. */
1191GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1192#endif
1193
1194/* neg neg. nego nego. */
1195static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1,
1196 int ov_check)
1197{
1198 int l1 = gen_new_label();
1199 int l2 = gen_new_label();
1200 TCGv t0 = tcg_temp_local_new();
1201#if defined(TARGET_PPC64)
1202 if (ctx->sf_mode) {
1203 tcg_gen_mov_tl(t0, arg1);
1204 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1205 } else
1206#endif
1207 {
1208 tcg_gen_ext32s_tl(t0, arg1);
1209 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1210 }
1211 tcg_gen_neg_tl(ret, arg1);
1212 if (ov_check) {
1213 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1214 }
1215 tcg_gen_br(l2);
1216 gen_set_label(l1);
1217 tcg_gen_mov_tl(ret, t0);
1218 if (ov_check) {
1219 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1220 }
1221 gen_set_label(l2);
1222 tcg_temp_free(t0);
1223 if (unlikely(Rc(ctx->opcode) != 0))
1224 gen_set_Rc0(ctx, ret);
1225}
1226
1227static void gen_neg(DisasContext *ctx)
1228{
1229 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1230}
1231
1232static void gen_nego(DisasContext *ctx)
1233{
1234 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1235}
1236
1237/* Common subf function */
1238static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1239 TCGv arg2, int add_ca, int compute_ca,
1240 int compute_ov)
1241{
1242 TCGv t0, t1;
1243
1244 if ((!compute_ca && !compute_ov) ||
1245 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1246 t0 = ret;
1247 } else {
1248 t0 = tcg_temp_local_new();
1249 }
1250
1251 if (add_ca) {
1252 t1 = tcg_temp_local_new();
1253 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1254 tcg_gen_shri_tl(t1, t1, XER_CA);
1255 } else {
1256 TCGV_UNUSED(t1);
1257 }
1258
1259 if (compute_ca && compute_ov) {
1260 /* Start with XER CA and OV disabled, the most likely case */
1261 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1262 } else if (compute_ca) {
1263 /* Start with XER CA disabled, the most likely case */
1264 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1265 } else if (compute_ov) {
1266 /* Start with XER OV disabled, the most likely case */
1267 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1268 }
1269
1270 if (add_ca) {
1271 tcg_gen_not_tl(t0, arg1);
1272 tcg_gen_add_tl(t0, t0, arg2);
1273 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1274 tcg_gen_add_tl(t0, t0, t1);
1275 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1276 tcg_temp_free(t1);
1277 } else {
1278 tcg_gen_sub_tl(t0, arg2, arg1);
1279 if (compute_ca) {
1280 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1281 }
1282 }
1283 if (compute_ov) {
1284 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1285 }
1286
1287 if (unlikely(Rc(ctx->opcode) != 0))
1288 gen_set_Rc0(ctx, t0);
1289
1290 if (!TCGV_EQUAL(t0, ret)) {
1291 tcg_gen_mov_tl(ret, t0);
1292 tcg_temp_free(t0);
1293 }
1294}
1295/* Sub functions with Two operands functions */
1296#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1297static void glue(gen_, name)(DisasContext *ctx) \
1298{ \
1299 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1300 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1301 add_ca, compute_ca, compute_ov); \
1302}
1303/* Sub functions with one operand and one immediate */
1304#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1305 add_ca, compute_ca, compute_ov) \
1306static void glue(gen_, name)(DisasContext *ctx) \
1307{ \
1308 TCGv t0 = tcg_const_local_tl(const_val); \
1309 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1310 cpu_gpr[rA(ctx->opcode)], t0, \
1311 add_ca, compute_ca, compute_ov); \
1312 tcg_temp_free(t0); \
1313}
1314/* subf subf. subfo subfo. */
1315GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1316GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1317/* subfc subfc. subfco subfco. */
1318GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1319GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1320/* subfe subfe. subfeo subfo. */
1321GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1322GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1323/* subfme subfme. subfmeo subfmeo. */
1324GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1325GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1326/* subfze subfze. subfzeo subfzeo.*/
1327GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1328GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1329
1330/* subfic */
1331static void gen_subfic(DisasContext *ctx)
1332{
1333 /* Start with XER CA and OV disabled, the most likely case */
1334 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1335 TCGv t0 = tcg_temp_local_new();
1336 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1337 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1338 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1339 tcg_temp_free(t1);
1340 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1341 tcg_temp_free(t0);
1342}
1343
1344/*** Integer logical ***/
1345#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1346static void glue(gen_, name)(DisasContext *ctx) \
1347{ \
1348 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1349 cpu_gpr[rB(ctx->opcode)]); \
1350 if (unlikely(Rc(ctx->opcode) != 0)) \
1351 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1352}
1353
1354#define GEN_LOGICAL1(name, tcg_op, opc, type) \
1355static void glue(gen_, name)(DisasContext *ctx) \
1356{ \
1357 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1358 if (unlikely(Rc(ctx->opcode) != 0)) \
1359 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1360}
1361
1362/* and & and. */
1363GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1364/* andc & andc. */
1365GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1366
1367/* andi. */
1368static void gen_andi_(DisasContext *ctx)
1369{
1370 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1371 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1372}
1373
1374/* andis. */
1375static void gen_andis_(DisasContext *ctx)
1376{
1377 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1378 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1379}
1380
1381/* cntlzw */
1382static void gen_cntlzw(DisasContext *ctx)
1383{
1384 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1385 if (unlikely(Rc(ctx->opcode) != 0))
1386 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1387}
1388/* eqv & eqv. */
1389GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1390/* extsb & extsb. */
1391GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1392/* extsh & extsh. */
1393GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1394/* nand & nand. */
1395GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1396/* nor & nor. */
1397GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1398
1399/* or & or. */
1400static void gen_or(DisasContext *ctx)
1401{
1402 int rs, ra, rb;
1403
1404 rs = rS(ctx->opcode);
1405 ra = rA(ctx->opcode);
1406 rb = rB(ctx->opcode);
1407 /* Optimisation for mr. ri case */
1408 if (rs != ra || rs != rb) {
1409 if (rs != rb)
1410 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1411 else
1412 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1413 if (unlikely(Rc(ctx->opcode) != 0))
1414 gen_set_Rc0(ctx, cpu_gpr[ra]);
1415 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1416 gen_set_Rc0(ctx, cpu_gpr[rs]);
1417#if defined(TARGET_PPC64)
1418 } else {
1419 int prio = 0;
1420
1421 switch (rs) {
1422 case 1:
1423 /* Set process priority to low */
1424 prio = 2;
1425 break;
1426 case 6:
1427 /* Set process priority to medium-low */
1428 prio = 3;
1429 break;
1430 case 2:
1431 /* Set process priority to normal */
1432 prio = 4;
1433 break;
1434#if !defined(CONFIG_USER_ONLY)
1435 case 31:
1436 if (ctx->mem_idx > 0) {
1437 /* Set process priority to very low */
1438 prio = 1;
1439 }
1440 break;
1441 case 5:
1442 if (ctx->mem_idx > 0) {
1443 /* Set process priority to medium-hight */
1444 prio = 5;
1445 }
1446 break;
1447 case 3:
1448 if (ctx->mem_idx > 0) {
1449 /* Set process priority to high */
1450 prio = 6;
1451 }
1452 break;
1453 case 7:
1454 if (ctx->mem_idx > 1) {
1455 /* Set process priority to very high */
1456 prio = 7;
1457 }
1458 break;
1459#endif
1460 default:
1461 /* nop */
1462 break;
1463 }
1464 if (prio) {
1465 TCGv t0 = tcg_temp_new();
1466 gen_load_spr(t0, SPR_PPR);
1467 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1468 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1469 gen_store_spr(SPR_PPR, t0);
1470 tcg_temp_free(t0);
1471 }
1472#endif
1473 }
1474}
1475/* orc & orc. */
1476GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1477
1478/* xor & xor. */
1479static void gen_xor(DisasContext *ctx)
1480{
1481 /* Optimisation for "set to zero" case */
1482 if (rS(ctx->opcode) != rB(ctx->opcode))
1483 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1484 else
1485 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1486 if (unlikely(Rc(ctx->opcode) != 0))
1487 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1488}
1489
1490/* ori */
1491static void gen_ori(DisasContext *ctx)
1492{
1493 target_ulong uimm = UIMM(ctx->opcode);
1494
1495 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1496 /* NOP */
1497 /* XXX: should handle special NOPs for POWER series */
1498 return;
1499 }
1500 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1501}
1502
1503/* oris */
1504static void gen_oris(DisasContext *ctx)
1505{
1506 target_ulong uimm = UIMM(ctx->opcode);
1507
1508 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1509 /* NOP */
1510 return;
1511 }
1512 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1513}
1514
1515/* xori */
1516static void gen_xori(DisasContext *ctx)
1517{
1518 target_ulong uimm = UIMM(ctx->opcode);
1519
1520 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1521 /* NOP */
1522 return;
1523 }
1524 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1525}
1526
1527/* xoris */
1528static void gen_xoris(DisasContext *ctx)
1529{
1530 target_ulong uimm = UIMM(ctx->opcode);
1531
1532 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1533 /* NOP */
1534 return;
1535 }
1536 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1537}
1538
1539/* popcntb : PowerPC 2.03 specification */
1540static void gen_popcntb(DisasContext *ctx)
1541{
1542 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1543}
1544
1545static void gen_popcntw(DisasContext *ctx)
1546{
1547 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1548}
1549
1550#if defined(TARGET_PPC64)
1551/* popcntd: PowerPC 2.06 specification */
1552static void gen_popcntd(DisasContext *ctx)
1553{
1554 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1555}
1556#endif
1557
1558#if defined(TARGET_PPC64)
1559/* extsw & extsw. */
1560GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1561
1562/* cntlzd */
1563static void gen_cntlzd(DisasContext *ctx)
1564{
1565 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1566 if (unlikely(Rc(ctx->opcode) != 0))
1567 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1568}
1569#endif
1570
1571/*** Integer rotate ***/
1572
1573/* rlwimi & rlwimi. */
1574static void gen_rlwimi(DisasContext *ctx)
1575{
1576 uint32_t mb, me, sh;
1577
1578 mb = MB(ctx->opcode);
1579 me = ME(ctx->opcode);
1580 sh = SH(ctx->opcode);
1581 if (likely(sh == 0 && mb == 0 && me == 31)) {
1582 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1583 } else {
1584 target_ulong mask;
1585 TCGv t1;
1586 TCGv t0 = tcg_temp_new();
1587#if defined(TARGET_PPC64)
1588 TCGv_i32 t2 = tcg_temp_new_i32();
1589 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1590 tcg_gen_rotli_i32(t2, t2, sh);
1591 tcg_gen_extu_i32_i64(t0, t2);
1592 tcg_temp_free_i32(t2);
1593#else
1594 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1595#endif
1596#if defined(TARGET_PPC64)
1597 mb += 32;
1598 me += 32;
1599#endif
1600 mask = MASK(mb, me);
1601 t1 = tcg_temp_new();
1602 tcg_gen_andi_tl(t0, t0, mask);
1603 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1604 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1605 tcg_temp_free(t0);
1606 tcg_temp_free(t1);
1607 }
1608 if (unlikely(Rc(ctx->opcode) != 0))
1609 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1610}
1611
1612/* rlwinm & rlwinm. */
1613static void gen_rlwinm(DisasContext *ctx)
1614{
1615 uint32_t mb, me, sh;
1616
1617 sh = SH(ctx->opcode);
1618 mb = MB(ctx->opcode);
1619 me = ME(ctx->opcode);
1620
1621 if (likely(mb == 0 && me == (31 - sh))) {
1622 if (likely(sh == 0)) {
1623 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1624 } else {
1625 TCGv t0 = tcg_temp_new();
1626 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1627 tcg_gen_shli_tl(t0, t0, sh);
1628 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1629 tcg_temp_free(t0);
1630 }
1631 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1632 TCGv t0 = tcg_temp_new();
1633 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1634 tcg_gen_shri_tl(t0, t0, mb);
1635 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1636 tcg_temp_free(t0);
1637 } else {
1638 TCGv t0 = tcg_temp_new();
1639#if defined(TARGET_PPC64)
1640 TCGv_i32 t1 = tcg_temp_new_i32();
1641 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1642 tcg_gen_rotli_i32(t1, t1, sh);
1643 tcg_gen_extu_i32_i64(t0, t1);
1644 tcg_temp_free_i32(t1);
1645#else
1646 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1647#endif
1648#if defined(TARGET_PPC64)
1649 mb += 32;
1650 me += 32;
1651#endif
1652 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1653 tcg_temp_free(t0);
1654 }
1655 if (unlikely(Rc(ctx->opcode) != 0))
1656 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1657}
1658
1659/* rlwnm & rlwnm. */
1660static void gen_rlwnm(DisasContext *ctx)
1661{
1662 uint32_t mb, me;
1663 TCGv t0;
1664#if defined(TARGET_PPC64)
1665 TCGv_i32 t1, t2;
1666#endif
1667
1668 mb = MB(ctx->opcode);
1669 me = ME(ctx->opcode);
1670 t0 = tcg_temp_new();
1671 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1672#if defined(TARGET_PPC64)
1673 t1 = tcg_temp_new_i32();
1674 t2 = tcg_temp_new_i32();
1675 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1676 tcg_gen_trunc_i64_i32(t2, t0);
1677 tcg_gen_rotl_i32(t1, t1, t2);
1678 tcg_gen_extu_i32_i64(t0, t1);
1679 tcg_temp_free_i32(t1);
1680 tcg_temp_free_i32(t2);
1681#else
1682 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1683#endif
1684 if (unlikely(mb != 0 || me != 31)) {
1685#if defined(TARGET_PPC64)
1686 mb += 32;
1687 me += 32;
1688#endif
1689 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1690 } else {
1691 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1692 }
1693 tcg_temp_free(t0);
1694 if (unlikely(Rc(ctx->opcode) != 0))
1695 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1696}
1697
1698#if defined(TARGET_PPC64)
1699#define GEN_PPC64_R2(name, opc1, opc2) \
1700static void glue(gen_, name##0)(DisasContext *ctx) \
1701{ \
1702 gen_##name(ctx, 0); \
1703} \
1704 \
1705static void glue(gen_, name##1)(DisasContext *ctx) \
1706{ \
1707 gen_##name(ctx, 1); \
1708}
1709#define GEN_PPC64_R4(name, opc1, opc2) \
1710static void glue(gen_, name##0)(DisasContext *ctx) \
1711{ \
1712 gen_##name(ctx, 0, 0); \
1713} \
1714 \
1715static void glue(gen_, name##1)(DisasContext *ctx) \
1716{ \
1717 gen_##name(ctx, 0, 1); \
1718} \
1719 \
1720static void glue(gen_, name##2)(DisasContext *ctx) \
1721{ \
1722 gen_##name(ctx, 1, 0); \
1723} \
1724 \
1725static void glue(gen_, name##3)(DisasContext *ctx) \
1726{ \
1727 gen_##name(ctx, 1, 1); \
1728}
1729
1730static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1731 uint32_t sh)
1732{
1733 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1734 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1735 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1736 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1737 } else {
1738 TCGv t0 = tcg_temp_new();
1739 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1740 if (likely(mb == 0 && me == 63)) {
1741 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1742 } else {
1743 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1744 }
1745 tcg_temp_free(t0);
1746 }
1747 if (unlikely(Rc(ctx->opcode) != 0))
1748 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1749}
1750/* rldicl - rldicl. */
1751static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1752{
1753 uint32_t sh, mb;
1754
1755 sh = SH(ctx->opcode) | (shn << 5);
1756 mb = MB(ctx->opcode) | (mbn << 5);
1757 gen_rldinm(ctx, mb, 63, sh);
1758}
1759GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1760/* rldicr - rldicr. */
1761static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1762{
1763 uint32_t sh, me;
1764
1765 sh = SH(ctx->opcode) | (shn << 5);
1766 me = MB(ctx->opcode) | (men << 5);
1767 gen_rldinm(ctx, 0, me, sh);
1768}
1769GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1770/* rldic - rldic. */
1771static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1772{
1773 uint32_t sh, mb;
1774
1775 sh = SH(ctx->opcode) | (shn << 5);
1776 mb = MB(ctx->opcode) | (mbn << 5);
1777 gen_rldinm(ctx, mb, 63 - sh, sh);
1778}
1779GEN_PPC64_R4(rldic, 0x1E, 0x04);
1780
1781static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1782{
1783 TCGv t0;
1784
1785 mb = MB(ctx->opcode);
1786 me = ME(ctx->opcode);
1787 t0 = tcg_temp_new();
1788 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1789 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1790 if (unlikely(mb != 0 || me != 63)) {
1791 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1792 } else {
1793 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1794 }
1795 tcg_temp_free(t0);
1796 if (unlikely(Rc(ctx->opcode) != 0))
1797 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1798}
1799
1800/* rldcl - rldcl. */
1801static inline void gen_rldcl(DisasContext *ctx, int mbn)
1802{
1803 uint32_t mb;
1804
1805 mb = MB(ctx->opcode) | (mbn << 5);
1806 gen_rldnm(ctx, mb, 63);
1807}
1808GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1809/* rldcr - rldcr. */
1810static inline void gen_rldcr(DisasContext *ctx, int men)
1811{
1812 uint32_t me;
1813
1814 me = MB(ctx->opcode) | (men << 5);
1815 gen_rldnm(ctx, 0, me);
1816}
1817GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1818/* rldimi - rldimi. */
1819static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1820{
1821 uint32_t sh, mb, me;
1822
1823 sh = SH(ctx->opcode) | (shn << 5);
1824 mb = MB(ctx->opcode) | (mbn << 5);
1825 me = 63 - sh;
1826 if (unlikely(sh == 0 && mb == 0)) {
1827 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1828 } else {
1829 TCGv t0, t1;
1830 target_ulong mask;
1831
1832 t0 = tcg_temp_new();
1833 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1834 t1 = tcg_temp_new();
1835 mask = MASK(mb, me);
1836 tcg_gen_andi_tl(t0, t0, mask);
1837 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1838 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1839 tcg_temp_free(t0);
1840 tcg_temp_free(t1);
1841 }
1842 if (unlikely(Rc(ctx->opcode) != 0))
1843 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1844}
1845GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1846#endif
1847
1848/*** Integer shift ***/
1849
1850/* slw & slw. */
1851static void gen_slw(DisasContext *ctx)
1852{
1853 TCGv t0, t1;
1854
1855 t0 = tcg_temp_new();
1856 /* AND rS with a mask that is 0 when rB >= 0x20 */
1857#if defined(TARGET_PPC64)
1858 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1859 tcg_gen_sari_tl(t0, t0, 0x3f);
1860#else
1861 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1862 tcg_gen_sari_tl(t0, t0, 0x1f);
1863#endif
1864 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1865 t1 = tcg_temp_new();
1866 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1867 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1868 tcg_temp_free(t1);
1869 tcg_temp_free(t0);
1870 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1871 if (unlikely(Rc(ctx->opcode) != 0))
1872 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1873}
1874
1875/* sraw & sraw. */
1876static void gen_sraw(DisasContext *ctx)
1877{
1878 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1879 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1880 if (unlikely(Rc(ctx->opcode) != 0))
1881 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1882}
1883
1884/* srawi & srawi. */
1885static void gen_srawi(DisasContext *ctx)
1886{
1887 int sh = SH(ctx->opcode);
1888 if (sh != 0) {
1889 int l1, l2;
1890 TCGv t0;
1891 l1 = gen_new_label();
1892 l2 = gen_new_label();
1893 t0 = tcg_temp_local_new();
1894 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1895 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1896 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1897 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1898 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1899 tcg_gen_br(l2);
1900 gen_set_label(l1);
1901 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1902 gen_set_label(l2);
1903 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1904 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1905 tcg_temp_free(t0);
1906 } else {
1907 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1908 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1909 }
1910 if (unlikely(Rc(ctx->opcode) != 0))
1911 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1912}
1913
1914/* srw & srw. */
1915static void gen_srw(DisasContext *ctx)
1916{
1917 TCGv t0, t1;
1918
1919 t0 = tcg_temp_new();
1920 /* AND rS with a mask that is 0 when rB >= 0x20 */
1921#if defined(TARGET_PPC64)
1922 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1923 tcg_gen_sari_tl(t0, t0, 0x3f);
1924#else
1925 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1926 tcg_gen_sari_tl(t0, t0, 0x1f);
1927#endif
1928 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1929 tcg_gen_ext32u_tl(t0, t0);
1930 t1 = tcg_temp_new();
1931 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1932 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1933 tcg_temp_free(t1);
1934 tcg_temp_free(t0);
1935 if (unlikely(Rc(ctx->opcode) != 0))
1936 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1937}
1938
1939#if defined(TARGET_PPC64)
1940/* sld & sld. */
1941static void gen_sld(DisasContext *ctx)
1942{
1943 TCGv t0, t1;
1944
1945 t0 = tcg_temp_new();
1946 /* AND rS with a mask that is 0 when rB >= 0x40 */
1947 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1948 tcg_gen_sari_tl(t0, t0, 0x3f);
1949 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1950 t1 = tcg_temp_new();
1951 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1952 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1953 tcg_temp_free(t1);
1954 tcg_temp_free(t0);
1955 if (unlikely(Rc(ctx->opcode) != 0))
1956 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1957}
1958
1959/* srad & srad. */
1960static void gen_srad(DisasContext *ctx)
1961{
1962 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
1963 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1964 if (unlikely(Rc(ctx->opcode) != 0))
1965 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1966}
1967/* sradi & sradi. */
1968static inline void gen_sradi(DisasContext *ctx, int n)
1969{
1970 int sh = SH(ctx->opcode) + (n << 5);
1971 if (sh != 0) {
1972 int l1, l2;
1973 TCGv t0;
1974 l1 = gen_new_label();
1975 l2 = gen_new_label();
1976 t0 = tcg_temp_local_new();
1977 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1978 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1979 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1980 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1981 tcg_gen_br(l2);
1982 gen_set_label(l1);
1983 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1984 gen_set_label(l2);
1985 tcg_temp_free(t0);
1986 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1987 } else {
1988 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1989 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1990 }
1991 if (unlikely(Rc(ctx->opcode) != 0))
1992 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1993}
1994
1995static void gen_sradi0(DisasContext *ctx)
1996{
1997 gen_sradi(ctx, 0);
1998}
1999
2000static void gen_sradi1(DisasContext *ctx)
2001{
2002 gen_sradi(ctx, 1);
2003}
2004
2005/* srd & srd. */
2006static void gen_srd(DisasContext *ctx)
2007{
2008 TCGv t0, t1;
2009
2010 t0 = tcg_temp_new();
2011 /* AND rS with a mask that is 0 when rB >= 0x40 */
2012 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2013 tcg_gen_sari_tl(t0, t0, 0x3f);
2014 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2015 t1 = tcg_temp_new();
2016 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2017 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2018 tcg_temp_free(t1);
2019 tcg_temp_free(t0);
2020 if (unlikely(Rc(ctx->opcode) != 0))
2021 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2022}
2023#endif
2024
2025/*** Floating-Point arithmetic ***/
2026#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2027static void gen_f##name(DisasContext *ctx) \
2028{ \
2029 if (unlikely(!ctx->fpu_enabled)) { \
2030 gen_exception(ctx, POWERPC_EXCP_FPU); \
2031 return; \
2032 } \
2033 /* NIP cannot be restored if the memory exception comes from an helper */ \
2034 gen_update_nip(ctx, ctx->nip - 4); \
2035 gen_reset_fpstatus(); \
2036 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2037 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2038 if (isfloat) { \
2039 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2040 } \
2041 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2042 Rc(ctx->opcode) != 0); \
2043}
2044
2045#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2046_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2047_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2048
2049#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2050static void gen_f##name(DisasContext *ctx) \
2051{ \
2052 if (unlikely(!ctx->fpu_enabled)) { \
2053 gen_exception(ctx, POWERPC_EXCP_FPU); \
2054 return; \
2055 } \
2056 /* NIP cannot be restored if the memory exception comes from an helper */ \
2057 gen_update_nip(ctx, ctx->nip - 4); \
2058 gen_reset_fpstatus(); \
2059 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2060 cpu_fpr[rB(ctx->opcode)]); \
2061 if (isfloat) { \
2062 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2063 } \
2064 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2065 set_fprf, Rc(ctx->opcode) != 0); \
2066}
2067#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2068_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2069_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2070
2071#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2072static void gen_f##name(DisasContext *ctx) \
2073{ \
2074 if (unlikely(!ctx->fpu_enabled)) { \
2075 gen_exception(ctx, POWERPC_EXCP_FPU); \
2076 return; \
2077 } \
2078 /* NIP cannot be restored if the memory exception comes from an helper */ \
2079 gen_update_nip(ctx, ctx->nip - 4); \
2080 gen_reset_fpstatus(); \
2081 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2082 cpu_fpr[rC(ctx->opcode)]); \
2083 if (isfloat) { \
2084 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2085 } \
2086 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2087 set_fprf, Rc(ctx->opcode) != 0); \
2088}
2089#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2090_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2091_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2092
2093#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2094static void gen_f##name(DisasContext *ctx) \
2095{ \
2096 if (unlikely(!ctx->fpu_enabled)) { \
2097 gen_exception(ctx, POWERPC_EXCP_FPU); \
2098 return; \
2099 } \
2100 /* NIP cannot be restored if the memory exception comes from an helper */ \
2101 gen_update_nip(ctx, ctx->nip - 4); \
2102 gen_reset_fpstatus(); \
2103 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2104 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2105 set_fprf, Rc(ctx->opcode) != 0); \
2106}
2107
2108#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2109static void gen_f##name(DisasContext *ctx) \
2110{ \
2111 if (unlikely(!ctx->fpu_enabled)) { \
2112 gen_exception(ctx, POWERPC_EXCP_FPU); \
2113 return; \
2114 } \
2115 /* NIP cannot be restored if the memory exception comes from an helper */ \
2116 gen_update_nip(ctx, ctx->nip - 4); \
2117 gen_reset_fpstatus(); \
2118 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2119 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2120 set_fprf, Rc(ctx->opcode) != 0); \
2121}
2122
2123/* fadd - fadds */
2124GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2125/* fdiv - fdivs */
2126GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2127/* fmul - fmuls */
2128GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2129
2130/* fre */
2131GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2132
2133/* fres */
2134GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2135
2136/* frsqrte */
2137GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2138
2139/* frsqrtes */
2140static void gen_frsqrtes(DisasContext *ctx)
2141{
2142 if (unlikely(!ctx->fpu_enabled)) {
2143 gen_exception(ctx, POWERPC_EXCP_FPU);
2144 return;
2145 }
2146 /* NIP cannot be restored if the memory exception comes from an helper */
2147 gen_update_nip(ctx, ctx->nip - 4);
2148 gen_reset_fpstatus();
2149 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2150 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2151 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2152}
2153
2154/* fsel */
2155_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2156/* fsub - fsubs */
2157GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2158/* Optional: */
2159
2160/* fsqrt */
2161static void gen_fsqrt(DisasContext *ctx)
2162{
2163 if (unlikely(!ctx->fpu_enabled)) {
2164 gen_exception(ctx, POWERPC_EXCP_FPU);
2165 return;
2166 }
2167 /* NIP cannot be restored if the memory exception comes from an helper */
2168 gen_update_nip(ctx, ctx->nip - 4);
2169 gen_reset_fpstatus();
2170 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2171 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2172}
2173
2174static void gen_fsqrts(DisasContext *ctx)
2175{
2176 if (unlikely(!ctx->fpu_enabled)) {
2177 gen_exception(ctx, POWERPC_EXCP_FPU);
2178 return;
2179 }
2180 /* NIP cannot be restored if the memory exception comes from an helper */
2181 gen_update_nip(ctx, ctx->nip - 4);
2182 gen_reset_fpstatus();
2183 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2184 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2185 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2186}
2187
2188/*** Floating-Point multiply-and-add ***/
2189/* fmadd - fmadds */
2190GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2191/* fmsub - fmsubs */
2192GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2193/* fnmadd - fnmadds */
2194GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2195/* fnmsub - fnmsubs */
2196GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2197
2198/*** Floating-Point round & convert ***/
2199/* fctiw */
2200GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2201/* fctiwz */
2202GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2203/* frsp */
2204GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2205#if defined(TARGET_PPC64)
2206/* fcfid */
2207GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2208/* fctid */
2209GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2210/* fctidz */
2211GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2212#endif
2213
2214/* frin */
2215GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2216/* friz */
2217GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2218/* frip */
2219GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2220/* frim */
2221GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2222
2223/*** Floating-Point compare ***/
2224
2225/* fcmpo */
2226static void gen_fcmpo(DisasContext *ctx)
2227{
2228 TCGv_i32 crf;
2229 if (unlikely(!ctx->fpu_enabled)) {
2230 gen_exception(ctx, POWERPC_EXCP_FPU);
2231 return;
2232 }
2233 /* NIP cannot be restored if the memory exception comes from an helper */
2234 gen_update_nip(ctx, ctx->nip - 4);
2235 gen_reset_fpstatus();
2236 crf = tcg_const_i32(crfD(ctx->opcode));
2237 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2238 tcg_temp_free_i32(crf);
2239 gen_helper_float_check_status();
2240}
2241
2242/* fcmpu */
2243static void gen_fcmpu(DisasContext *ctx)
2244{
2245 TCGv_i32 crf;
2246 if (unlikely(!ctx->fpu_enabled)) {
2247 gen_exception(ctx, POWERPC_EXCP_FPU);
2248 return;
2249 }
2250 /* NIP cannot be restored if the memory exception comes from an helper */
2251 gen_update_nip(ctx, ctx->nip - 4);
2252 gen_reset_fpstatus();
2253 crf = tcg_const_i32(crfD(ctx->opcode));
2254 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2255 tcg_temp_free_i32(crf);
2256 gen_helper_float_check_status();
2257}
2258
2259/*** Floating-point move ***/
2260/* fabs */
2261/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2262GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2263
2264/* fmr - fmr. */
2265/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2266static void gen_fmr(DisasContext *ctx)
2267{
2268 if (unlikely(!ctx->fpu_enabled)) {
2269 gen_exception(ctx, POWERPC_EXCP_FPU);
2270 return;
2271 }
2272 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2273 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2274}
2275
2276/* fnabs */
2277/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2278GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2279/* fneg */
2280/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2281GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2282
2283/*** Floating-Point status & ctrl register ***/
2284
2285/* mcrfs */
2286static void gen_mcrfs(DisasContext *ctx)
2287{
2288 int bfa;
2289
2290 if (unlikely(!ctx->fpu_enabled)) {
2291 gen_exception(ctx, POWERPC_EXCP_FPU);
2292 return;
2293 }
2294 bfa = 4 * (7 - crfS(ctx->opcode));
2295 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2296 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2297 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2298}
2299
2300/* mffs */
2301static void gen_mffs(DisasContext *ctx)
2302{
2303 if (unlikely(!ctx->fpu_enabled)) {
2304 gen_exception(ctx, POWERPC_EXCP_FPU);
2305 return;
2306 }
2307 gen_reset_fpstatus();
2308 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2309 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2310}
2311
2312/* mtfsb0 */
2313static void gen_mtfsb0(DisasContext *ctx)
2314{
2315 uint8_t crb;
2316
2317 if (unlikely(!ctx->fpu_enabled)) {
2318 gen_exception(ctx, POWERPC_EXCP_FPU);
2319 return;
2320 }
2321 crb = 31 - crbD(ctx->opcode);
2322 gen_reset_fpstatus();
2323 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2324 TCGv_i32 t0;
2325 /* NIP cannot be restored if the memory exception comes from an helper */
2326 gen_update_nip(ctx, ctx->nip - 4);
2327 t0 = tcg_const_i32(crb);
2328 gen_helper_fpscr_clrbit(t0);
2329 tcg_temp_free_i32(t0);
2330 }
2331 if (unlikely(Rc(ctx->opcode) != 0)) {
2332 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2333 }
2334}
2335
2336/* mtfsb1 */
2337static void gen_mtfsb1(DisasContext *ctx)
2338{
2339 uint8_t crb;
2340
2341 if (unlikely(!ctx->fpu_enabled)) {
2342 gen_exception(ctx, POWERPC_EXCP_FPU);
2343 return;
2344 }
2345 crb = 31 - crbD(ctx->opcode);
2346 gen_reset_fpstatus();
2347 /* XXX: we pretend we can only do IEEE floating-point computations */
2348 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2349 TCGv_i32 t0;
2350 /* NIP cannot be restored if the memory exception comes from an helper */
2351 gen_update_nip(ctx, ctx->nip - 4);
2352 t0 = tcg_const_i32(crb);
2353 gen_helper_fpscr_setbit(t0);
2354 tcg_temp_free_i32(t0);
2355 }
2356 if (unlikely(Rc(ctx->opcode) != 0)) {
2357 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2358 }
2359 /* We can raise a differed exception */
2360 gen_helper_float_check_status();
2361}
2362
2363/* mtfsf */
2364static void gen_mtfsf(DisasContext *ctx)
2365{
2366 TCGv_i32 t0;
2367 int L = ctx->opcode & 0x02000000;
2368
2369 if (unlikely(!ctx->fpu_enabled)) {
2370 gen_exception(ctx, POWERPC_EXCP_FPU);
2371 return;
2372 }
2373 /* NIP cannot be restored if the memory exception comes from an helper */
2374 gen_update_nip(ctx, ctx->nip - 4);
2375 gen_reset_fpstatus();
2376 if (L)
2377 t0 = tcg_const_i32(0xff);
2378 else
2379 t0 = tcg_const_i32(FM(ctx->opcode));
2380 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2381 tcg_temp_free_i32(t0);
2382 if (unlikely(Rc(ctx->opcode) != 0)) {
2383 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2384 }
2385 /* We can raise a differed exception */
2386 gen_helper_float_check_status();
2387}
2388
2389/* mtfsfi */
2390static void gen_mtfsfi(DisasContext *ctx)
2391{
2392 int bf, sh;
2393 TCGv_i64 t0;
2394 TCGv_i32 t1;
2395
2396 if (unlikely(!ctx->fpu_enabled)) {
2397 gen_exception(ctx, POWERPC_EXCP_FPU);
2398 return;
2399 }
2400 bf = crbD(ctx->opcode) >> 2;
2401 sh = 7 - bf;
2402 /* NIP cannot be restored if the memory exception comes from an helper */
2403 gen_update_nip(ctx, ctx->nip - 4);
2404 gen_reset_fpstatus();
2405 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2406 t1 = tcg_const_i32(1 << sh);
2407 gen_helper_store_fpscr(t0, t1);
2408 tcg_temp_free_i64(t0);
2409 tcg_temp_free_i32(t1);
2410 if (unlikely(Rc(ctx->opcode) != 0)) {
2411 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2412 }
2413 /* We can raise a differed exception */
2414 gen_helper_float_check_status();
2415}
2416
2417/*** Addressing modes ***/
2418/* Register indirect with immediate index : EA = (rA|0) + SIMM */
2419static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2420 target_long maskl)
2421{
2422 target_long simm = SIMM(ctx->opcode);
2423
2424 simm &= ~maskl;
2425 if (rA(ctx->opcode) == 0) {
2426#if defined(TARGET_PPC64)
2427 if (!ctx->sf_mode) {
2428 tcg_gen_movi_tl(EA, (uint32_t)simm);
2429 } else
2430#endif
2431 tcg_gen_movi_tl(EA, simm);
2432 } else if (likely(simm != 0)) {
2433 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2434#if defined(TARGET_PPC64)
2435 if (!ctx->sf_mode) {
2436 tcg_gen_ext32u_tl(EA, EA);
2437 }
2438#endif
2439 } else {
2440#if defined(TARGET_PPC64)
2441 if (!ctx->sf_mode) {
2442 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2443 } else
2444#endif
2445 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2446 }
2447}
2448
2449static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2450{
2451 if (rA(ctx->opcode) == 0) {
2452#if defined(TARGET_PPC64)
2453 if (!ctx->sf_mode) {
2454 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2455 } else
2456#endif
2457 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2458 } else {
2459 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2460#if defined(TARGET_PPC64)
2461 if (!ctx->sf_mode) {
2462 tcg_gen_ext32u_tl(EA, EA);
2463 }
2464#endif
2465 }
2466}
2467
2468static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2469{
2470 if (rA(ctx->opcode) == 0) {
2471 tcg_gen_movi_tl(EA, 0);
2472 } else {
2473#if defined(TARGET_PPC64)
2474 if (!ctx->sf_mode) {
2475 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2476 } else
2477#endif
2478 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2479 }
2480}
2481
2482static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2483 target_long val)
2484{
2485 tcg_gen_addi_tl(ret, arg1, val);
2486#if defined(TARGET_PPC64)
2487 if (!ctx->sf_mode) {
2488 tcg_gen_ext32u_tl(ret, ret);
2489 }
2490#endif
2491}
2492
2493static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2494{
2495 int l1 = gen_new_label();
2496 TCGv t0 = tcg_temp_new();
2497 TCGv_i32 t1, t2;
2498 /* NIP cannot be restored if the memory exception comes from an helper */
2499 gen_update_nip(ctx, ctx->nip - 4);
2500 tcg_gen_andi_tl(t0, EA, mask);
2501 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2502 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2503 t2 = tcg_const_i32(0);
2504 gen_helper_raise_exception_err(t1, t2);
2505 tcg_temp_free_i32(t1);
2506 tcg_temp_free_i32(t2);
2507 gen_set_label(l1);
2508 tcg_temp_free(t0);
2509}
2510
2511/*** Integer load ***/
2512static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2513{
2514 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2515}
2516
2517static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2518{
2519 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2520}
2521
2522static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2523{
2524 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2525 if (unlikely(ctx->le_mode)) {
2526 tcg_gen_bswap16_tl(arg1, arg1);
2527 }
2528}
2529
2530static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2531{
2532 if (unlikely(ctx->le_mode)) {
2533 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2534 tcg_gen_bswap16_tl(arg1, arg1);
2535 tcg_gen_ext16s_tl(arg1, arg1);
2536 } else {
2537 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2538 }
2539}
2540
2541static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2542{
2543 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2544 if (unlikely(ctx->le_mode)) {
2545 tcg_gen_bswap32_tl(arg1, arg1);
2546 }
2547}
2548
2549#if defined(TARGET_PPC64)
2550static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2551{
2552 if (unlikely(ctx->le_mode)) {
2553 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2554 tcg_gen_bswap32_tl(arg1, arg1);
2555 tcg_gen_ext32s_tl(arg1, arg1);
2556 } else
2557 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2558}
2559#endif
2560
2561static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2562{
2563 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2564 if (unlikely(ctx->le_mode)) {
2565 tcg_gen_bswap64_i64(arg1, arg1);
2566 }
2567}
2568
2569static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2570{
2571 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2572}
2573
2574static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2575{
2576 if (unlikely(ctx->le_mode)) {
2577 TCGv t0 = tcg_temp_new();
2578 tcg_gen_ext16u_tl(t0, arg1);
2579 tcg_gen_bswap16_tl(t0, t0);
2580 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2581 tcg_temp_free(t0);
2582 } else {
2583 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2584 }
2585}
2586
2587static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2588{
2589 if (unlikely(ctx->le_mode)) {
2590 TCGv t0 = tcg_temp_new();
2591 tcg_gen_ext32u_tl(t0, arg1);
2592 tcg_gen_bswap32_tl(t0, t0);
2593 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2594 tcg_temp_free(t0);
2595 } else {
2596 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2597 }
2598}
2599
2600static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2601{
2602 if (unlikely(ctx->le_mode)) {
2603 TCGv_i64 t0 = tcg_temp_new_i64();
2604 tcg_gen_bswap64_i64(t0, arg1);
2605 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2606 tcg_temp_free_i64(t0);
2607 } else
2608 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2609}
2610
2611#define GEN_LD(name, ldop, opc, type) \
2612static void glue(gen_, name)(DisasContext *ctx) \
2613{ \
2614 TCGv EA; \
2615 gen_set_access_type(ctx, ACCESS_INT); \
2616 EA = tcg_temp_new(); \
2617 gen_addr_imm_index(ctx, EA, 0); \
2618 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2619 tcg_temp_free(EA); \
2620}
2621
2622#define GEN_LDU(name, ldop, opc, type) \
2623static void glue(gen_, name##u)(DisasContext *ctx) \
2624{ \
2625 TCGv EA; \
2626 if (unlikely(rA(ctx->opcode) == 0 || \
2627 rA(ctx->opcode) == rD(ctx->opcode))) { \
2628 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2629 return; \
2630 } \
2631 gen_set_access_type(ctx, ACCESS_INT); \
2632 EA = tcg_temp_new(); \
2633 if (type == PPC_64B) \
2634 gen_addr_imm_index(ctx, EA, 0x03); \
2635 else \
2636 gen_addr_imm_index(ctx, EA, 0); \
2637 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2638 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2639 tcg_temp_free(EA); \
2640}
2641
2642#define GEN_LDUX(name, ldop, opc2, opc3, type) \
2643static void glue(gen_, name##ux)(DisasContext *ctx) \
2644{ \
2645 TCGv EA; \
2646 if (unlikely(rA(ctx->opcode) == 0 || \
2647 rA(ctx->opcode) == rD(ctx->opcode))) { \
2648 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2649 return; \
2650 } \
2651 gen_set_access_type(ctx, ACCESS_INT); \
2652 EA = tcg_temp_new(); \
2653 gen_addr_reg_index(ctx, EA); \
2654 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2655 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2656 tcg_temp_free(EA); \
2657}
2658
2659#define GEN_LDX(name, ldop, opc2, opc3, type) \
2660static void glue(gen_, name##x)(DisasContext *ctx) \
2661{ \
2662 TCGv EA; \
2663 gen_set_access_type(ctx, ACCESS_INT); \
2664 EA = tcg_temp_new(); \
2665 gen_addr_reg_index(ctx, EA); \
2666 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2667 tcg_temp_free(EA); \
2668}
2669
2670#define GEN_LDS(name, ldop, op, type) \
2671GEN_LD(name, ldop, op | 0x20, type); \
2672GEN_LDU(name, ldop, op | 0x21, type); \
2673GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2674GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2675
2676/* lbz lbzu lbzux lbzx */
2677GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2678/* lha lhau lhaux lhax */
2679GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2680/* lhz lhzu lhzux lhzx */
2681GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2682/* lwz lwzu lwzux lwzx */
2683GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2684#if defined(TARGET_PPC64)
2685/* lwaux */
2686GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2687/* lwax */
2688GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2689/* ldux */
2690GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2691/* ldx */
2692GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2693
2694static void gen_ld(DisasContext *ctx)
2695{
2696 TCGv EA;
2697 if (Rc(ctx->opcode)) {
2698 if (unlikely(rA(ctx->opcode) == 0 ||
2699 rA(ctx->opcode) == rD(ctx->opcode))) {
2700 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2701 return;
2702 }
2703 }
2704 gen_set_access_type(ctx, ACCESS_INT);
2705 EA = tcg_temp_new();
2706 gen_addr_imm_index(ctx, EA, 0x03);
2707 if (ctx->opcode & 0x02) {
2708 /* lwa (lwau is undefined) */
2709 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2710 } else {
2711 /* ld - ldu */
2712 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2713 }
2714 if (Rc(ctx->opcode))
2715 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2716 tcg_temp_free(EA);
2717}
2718
2719/* lq */
2720static void gen_lq(DisasContext *ctx)
2721{
2722#if defined(CONFIG_USER_ONLY)
2723 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2724#else
2725 int ra, rd;
2726 TCGv EA;
2727
2728 /* Restore CPU state */
2729 if (unlikely(ctx->mem_idx == 0)) {
2730 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2731 return;
2732 }
2733 ra = rA(ctx->opcode);
2734 rd = rD(ctx->opcode);
2735 if (unlikely((rd & 1) || rd == ra)) {
2736 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2737 return;
2738 }
2739 if (unlikely(ctx->le_mode)) {
2740 /* Little-endian mode is not handled */
2741 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2742 return;
2743 }
2744 gen_set_access_type(ctx, ACCESS_INT);
2745 EA = tcg_temp_new();
2746 gen_addr_imm_index(ctx, EA, 0x0F);
2747 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2748 gen_addr_add(ctx, EA, EA, 8);
2749 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2750 tcg_temp_free(EA);
2751#endif
2752}
2753#endif
2754
2755/*** Integer store ***/
2756#define GEN_ST(name, stop, opc, type) \
2757static void glue(gen_, name)(DisasContext *ctx) \
2758{ \
2759 TCGv EA; \
2760 gen_set_access_type(ctx, ACCESS_INT); \
2761 EA = tcg_temp_new(); \
2762 gen_addr_imm_index(ctx, EA, 0); \
2763 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2764 tcg_temp_free(EA); \
2765}
2766
2767#define GEN_STU(name, stop, opc, type) \
2768static void glue(gen_, stop##u)(DisasContext *ctx) \
2769{ \
2770 TCGv EA; \
2771 if (unlikely(rA(ctx->opcode) == 0)) { \
2772 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2773 return; \
2774 } \
2775 gen_set_access_type(ctx, ACCESS_INT); \
2776 EA = tcg_temp_new(); \
2777 if (type == PPC_64B) \
2778 gen_addr_imm_index(ctx, EA, 0x03); \
2779 else \
2780 gen_addr_imm_index(ctx, EA, 0); \
2781 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2782 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2783 tcg_temp_free(EA); \
2784}
2785
2786#define GEN_STUX(name, stop, opc2, opc3, type) \
2787static void glue(gen_, name##ux)(DisasContext *ctx) \
2788{ \
2789 TCGv EA; \
2790 if (unlikely(rA(ctx->opcode) == 0)) { \
2791 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2792 return; \
2793 } \
2794 gen_set_access_type(ctx, ACCESS_INT); \
2795 EA = tcg_temp_new(); \
2796 gen_addr_reg_index(ctx, EA); \
2797 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2798 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2799 tcg_temp_free(EA); \
2800}
2801
2802#define GEN_STX(name, stop, opc2, opc3, type) \
2803static void glue(gen_, name##x)(DisasContext *ctx) \
2804{ \
2805 TCGv EA; \
2806 gen_set_access_type(ctx, ACCESS_INT); \
2807 EA = tcg_temp_new(); \
2808 gen_addr_reg_index(ctx, EA); \
2809 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2810 tcg_temp_free(EA); \
2811}
2812
2813#define GEN_STS(name, stop, op, type) \
2814GEN_ST(name, stop, op | 0x20, type); \
2815GEN_STU(name, stop, op | 0x21, type); \
2816GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2817GEN_STX(name, stop, 0x17, op | 0x00, type)
2818
2819/* stb stbu stbux stbx */
2820GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2821/* sth sthu sthux sthx */
2822GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2823/* stw stwu stwux stwx */
2824GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2825#if defined(TARGET_PPC64)
2826GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2827GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2828
2829static void gen_std(DisasContext *ctx)
2830{
2831 int rs;
2832 TCGv EA;
2833
2834 rs = rS(ctx->opcode);
2835 if ((ctx->opcode & 0x3) == 0x2) {
2836#if defined(CONFIG_USER_ONLY)
2837 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2838#else
2839 /* stq */
2840 if (unlikely(ctx->mem_idx == 0)) {
2841 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2842 return;
2843 }
2844 if (unlikely(rs & 1)) {
2845 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2846 return;
2847 }
2848 if (unlikely(ctx->le_mode)) {
2849 /* Little-endian mode is not handled */
2850 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2851 return;
2852 }
2853 gen_set_access_type(ctx, ACCESS_INT);
2854 EA = tcg_temp_new();
2855 gen_addr_imm_index(ctx, EA, 0x03);
2856 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2857 gen_addr_add(ctx, EA, EA, 8);
2858 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2859 tcg_temp_free(EA);
2860#endif
2861 } else {
2862 /* std / stdu */
2863 if (Rc(ctx->opcode)) {
2864 if (unlikely(rA(ctx->opcode) == 0)) {
2865 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2866 return;
2867 }
2868 }
2869 gen_set_access_type(ctx, ACCESS_INT);
2870 EA = tcg_temp_new();
2871 gen_addr_imm_index(ctx, EA, 0x03);
2872 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2873 if (Rc(ctx->opcode))
2874 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2875 tcg_temp_free(EA);
2876 }
2877}
2878#endif
2879/*** Integer load and store with byte reverse ***/
2880/* lhbrx */
2881static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2882{
2883 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2884 if (likely(!ctx->le_mode)) {
2885 tcg_gen_bswap16_tl(arg1, arg1);
2886 }
2887}
2888GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2889
2890/* lwbrx */
2891static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2892{
2893 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2894 if (likely(!ctx->le_mode)) {
2895 tcg_gen_bswap32_tl(arg1, arg1);
2896 }
2897}
2898GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2899
2900/* sthbrx */
2901static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2902{
2903 if (likely(!ctx->le_mode)) {
2904 TCGv t0 = tcg_temp_new();
2905 tcg_gen_ext16u_tl(t0, arg1);
2906 tcg_gen_bswap16_tl(t0, t0);
2907 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2908 tcg_temp_free(t0);
2909 } else {
2910 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2911 }
2912}
2913GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2914
2915/* stwbrx */
2916static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2917{
2918 if (likely(!ctx->le_mode)) {
2919 TCGv t0 = tcg_temp_new();
2920 tcg_gen_ext32u_tl(t0, arg1);
2921 tcg_gen_bswap32_tl(t0, t0);
2922 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2923 tcg_temp_free(t0);
2924 } else {
2925 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2926 }
2927}
2928GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2929
2930/*** Integer load and store multiple ***/
2931
2932/* lmw */
2933static void gen_lmw(DisasContext *ctx)
2934{
2935 TCGv t0;
2936 TCGv_i32 t1;
2937 gen_set_access_type(ctx, ACCESS_INT);
2938 /* NIP cannot be restored if the memory exception comes from an helper */
2939 gen_update_nip(ctx, ctx->nip - 4);
2940 t0 = tcg_temp_new();
2941 t1 = tcg_const_i32(rD(ctx->opcode));
2942 gen_addr_imm_index(ctx, t0, 0);
2943 gen_helper_lmw(t0, t1);
2944 tcg_temp_free(t0);
2945 tcg_temp_free_i32(t1);
2946}
2947
2948/* stmw */
2949static void gen_stmw(DisasContext *ctx)
2950{
2951 TCGv t0;
2952 TCGv_i32 t1;
2953 gen_set_access_type(ctx, ACCESS_INT);
2954 /* NIP cannot be restored if the memory exception comes from an helper */
2955 gen_update_nip(ctx, ctx->nip - 4);
2956 t0 = tcg_temp_new();
2957 t1 = tcg_const_i32(rS(ctx->opcode));
2958 gen_addr_imm_index(ctx, t0, 0);
2959 gen_helper_stmw(t0, t1);
2960 tcg_temp_free(t0);
2961 tcg_temp_free_i32(t1);
2962}
2963
2964/*** Integer load and store strings ***/
2965
2966/* lswi */
2967/* PowerPC32 specification says we must generate an exception if
2968 * rA is in the range of registers to be loaded.
2969 * In an other hand, IBM says this is valid, but rA won't be loaded.
2970 * For now, I'll follow the spec...
2971 */
2972static void gen_lswi(DisasContext *ctx)
2973{
2974 TCGv t0;
2975 TCGv_i32 t1, t2;
2976 int nb = NB(ctx->opcode);
2977 int start = rD(ctx->opcode);
2978 int ra = rA(ctx->opcode);
2979 int nr;
2980
2981 if (nb == 0)
2982 nb = 32;
2983 nr = nb / 4;
2984 if (unlikely(((start + nr) > 32 &&
2985 start <= ra && (start + nr - 32) > ra) ||
2986 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2987 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2988 return;
2989 }
2990 gen_set_access_type(ctx, ACCESS_INT);
2991 /* NIP cannot be restored if the memory exception comes from an helper */
2992 gen_update_nip(ctx, ctx->nip - 4);
2993 t0 = tcg_temp_new();
2994 gen_addr_register(ctx, t0);
2995 t1 = tcg_const_i32(nb);
2996 t2 = tcg_const_i32(start);
2997 gen_helper_lsw(t0, t1, t2);
2998 tcg_temp_free(t0);
2999 tcg_temp_free_i32(t1);
3000 tcg_temp_free_i32(t2);
3001}
3002
3003/* lswx */
3004static void gen_lswx(DisasContext *ctx)
3005{
3006 TCGv t0;
3007 TCGv_i32 t1, t2, t3;
3008 gen_set_access_type(ctx, ACCESS_INT);
3009 /* NIP cannot be restored if the memory exception comes from an helper */
3010 gen_update_nip(ctx, ctx->nip - 4);
3011 t0 = tcg_temp_new();
3012 gen_addr_reg_index(ctx, t0);
3013 t1 = tcg_const_i32(rD(ctx->opcode));
3014 t2 = tcg_const_i32(rA(ctx->opcode));
3015 t3 = tcg_const_i32(rB(ctx->opcode));
3016 gen_helper_lswx(t0, t1, t2, t3);
3017 tcg_temp_free(t0);
3018 tcg_temp_free_i32(t1);
3019 tcg_temp_free_i32(t2);
3020 tcg_temp_free_i32(t3);
3021}
3022
3023/* stswi */
3024static void gen_stswi(DisasContext *ctx)
3025{
3026 TCGv t0;
3027 TCGv_i32 t1, t2;
3028 int nb = NB(ctx->opcode);
3029 gen_set_access_type(ctx, ACCESS_INT);
3030 /* NIP cannot be restored if the memory exception comes from an helper */
3031 gen_update_nip(ctx, ctx->nip - 4);
3032 t0 = tcg_temp_new();
3033 gen_addr_register(ctx, t0);
3034 if (nb == 0)
3035 nb = 32;
3036 t1 = tcg_const_i32(nb);
3037 t2 = tcg_const_i32(rS(ctx->opcode));
3038 gen_helper_stsw(t0, t1, t2);
3039 tcg_temp_free(t0);
3040 tcg_temp_free_i32(t1);
3041 tcg_temp_free_i32(t2);
3042}
3043
3044/* stswx */
3045static void gen_stswx(DisasContext *ctx)
3046{
3047 TCGv t0;
3048 TCGv_i32 t1, t2;
3049 gen_set_access_type(ctx, ACCESS_INT);
3050 /* NIP cannot be restored if the memory exception comes from an helper */
3051 gen_update_nip(ctx, ctx->nip - 4);
3052 t0 = tcg_temp_new();
3053 gen_addr_reg_index(ctx, t0);
3054 t1 = tcg_temp_new_i32();
3055 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3056 tcg_gen_andi_i32(t1, t1, 0x7F);
3057 t2 = tcg_const_i32(rS(ctx->opcode));
3058 gen_helper_stsw(t0, t1, t2);
3059 tcg_temp_free(t0);
3060 tcg_temp_free_i32(t1);
3061 tcg_temp_free_i32(t2);
3062}
3063
3064/*** Memory synchronisation ***/
3065/* eieio */
3066static void gen_eieio(DisasContext *ctx)
3067{
3068}
3069
3070/* isync */
3071static void gen_isync(DisasContext *ctx)
3072{
3073 gen_stop_exception(ctx);
3074}
3075
3076/* lwarx */
3077static void gen_lwarx(DisasContext *ctx)
3078{
3079 TCGv t0;
3080 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3081 gen_set_access_type(ctx, ACCESS_RES);
3082 t0 = tcg_temp_local_new();
3083 gen_addr_reg_index(ctx, t0);
3084 gen_check_align(ctx, t0, 0x03);
3085 gen_qemu_ld32u(ctx, gpr, t0);
3086 tcg_gen_mov_tl(cpu_reserve, t0);
3087 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
3088 tcg_temp_free(t0);
3089}
3090
3091#if defined(CONFIG_USER_ONLY)
3092static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3093 int reg, int size)
3094{
3095 TCGv t0 = tcg_temp_new();
3096 uint32_t save_exception = ctx->exception;
3097
3098 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUState, reserve_ea));
3099 tcg_gen_movi_tl(t0, (size << 5) | reg);
3100 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, reserve_info));
3101 tcg_temp_free(t0);
3102 gen_update_nip(ctx, ctx->nip-4);
3103 ctx->exception = POWERPC_EXCP_BRANCH;
3104 gen_exception(ctx, POWERPC_EXCP_STCX);
3105 ctx->exception = save_exception;
3106}
3107#endif
3108
3109/* stwcx. */
3110static void gen_stwcx_(DisasContext *ctx)
3111{
3112 TCGv t0;
3113 gen_set_access_type(ctx, ACCESS_RES);
3114 t0 = tcg_temp_local_new();
3115 gen_addr_reg_index(ctx, t0);
3116 gen_check_align(ctx, t0, 0x03);
3117#if defined(CONFIG_USER_ONLY)
3118 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3119#else
3120 {
3121 int l1;
3122
3123 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3124 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3125 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3126 l1 = gen_new_label();
3127 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3128 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3129 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3130 gen_set_label(l1);
3131 tcg_gen_movi_tl(cpu_reserve, -1);
3132 }
3133#endif
3134 tcg_temp_free(t0);
3135}
3136
3137#if defined(TARGET_PPC64)
3138/* ldarx */
3139static void gen_ldarx(DisasContext *ctx)
3140{
3141 TCGv t0;
3142 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3143 gen_set_access_type(ctx, ACCESS_RES);
3144 t0 = tcg_temp_local_new();
3145 gen_addr_reg_index(ctx, t0);
3146 gen_check_align(ctx, t0, 0x07);
3147 gen_qemu_ld64(ctx, gpr, t0);
3148 tcg_gen_mov_tl(cpu_reserve, t0);
3149 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
3150 tcg_temp_free(t0);
3151}
3152
3153/* stdcx. */
3154static void gen_stdcx_(DisasContext *ctx)
3155{
3156 TCGv t0;
3157 gen_set_access_type(ctx, ACCESS_RES);
3158 t0 = tcg_temp_local_new();
3159 gen_addr_reg_index(ctx, t0);
3160 gen_check_align(ctx, t0, 0x07);
3161#if defined(CONFIG_USER_ONLY)
3162 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3163#else
3164 {
3165 int l1;
3166 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3167 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3168 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3169 l1 = gen_new_label();
3170 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3171 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3172 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3173 gen_set_label(l1);
3174 tcg_gen_movi_tl(cpu_reserve, -1);
3175 }
3176#endif
3177 tcg_temp_free(t0);
3178}
3179#endif /* defined(TARGET_PPC64) */
3180
3181/* sync */
3182static void gen_sync(DisasContext *ctx)
3183{
3184}
3185
3186/* wait */
3187static void gen_wait(DisasContext *ctx)
3188{
3189 TCGv_i32 t0 = tcg_temp_new_i32();
3190 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3191 tcg_temp_free_i32(t0);
3192 /* Stop translation, as the CPU is supposed to sleep from now */
3193 gen_exception_err(ctx, EXCP_HLT, 1);
3194}
3195
3196/*** Floating-point load ***/
3197#define GEN_LDF(name, ldop, opc, type) \
3198static void glue(gen_, name)(DisasContext *ctx) \
3199{ \
3200 TCGv EA; \
3201 if (unlikely(!ctx->fpu_enabled)) { \
3202 gen_exception(ctx, POWERPC_EXCP_FPU); \
3203 return; \
3204 } \
3205 gen_set_access_type(ctx, ACCESS_FLOAT); \
3206 EA = tcg_temp_new(); \
3207 gen_addr_imm_index(ctx, EA, 0); \
3208 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3209 tcg_temp_free(EA); \
3210}
3211
3212#define GEN_LDUF(name, ldop, opc, type) \
3213static void glue(gen_, name##u)(DisasContext *ctx) \
3214{ \
3215 TCGv EA; \
3216 if (unlikely(!ctx->fpu_enabled)) { \
3217 gen_exception(ctx, POWERPC_EXCP_FPU); \
3218 return; \
3219 } \
3220 if (unlikely(rA(ctx->opcode) == 0)) { \
3221 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3222 return; \
3223 } \
3224 gen_set_access_type(ctx, ACCESS_FLOAT); \
3225 EA = tcg_temp_new(); \
3226 gen_addr_imm_index(ctx, EA, 0); \
3227 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3228 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3229 tcg_temp_free(EA); \
3230}
3231
3232#define GEN_LDUXF(name, ldop, opc, type) \
3233static void glue(gen_, name##ux)(DisasContext *ctx) \
3234{ \
3235 TCGv EA; \
3236 if (unlikely(!ctx->fpu_enabled)) { \
3237 gen_exception(ctx, POWERPC_EXCP_FPU); \
3238 return; \
3239 } \
3240 if (unlikely(rA(ctx->opcode) == 0)) { \
3241 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3242 return; \
3243 } \
3244 gen_set_access_type(ctx, ACCESS_FLOAT); \
3245 EA = tcg_temp_new(); \
3246 gen_addr_reg_index(ctx, EA); \
3247 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3248 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3249 tcg_temp_free(EA); \
3250}
3251
3252#define GEN_LDXF(name, ldop, opc2, opc3, type) \
3253static void glue(gen_, name##x)(DisasContext *ctx) \
3254{ \
3255 TCGv EA; \
3256 if (unlikely(!ctx->fpu_enabled)) { \
3257 gen_exception(ctx, POWERPC_EXCP_FPU); \
3258 return; \
3259 } \
3260 gen_set_access_type(ctx, ACCESS_FLOAT); \
3261 EA = tcg_temp_new(); \
3262 gen_addr_reg_index(ctx, EA); \
3263 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3264 tcg_temp_free(EA); \
3265}
3266
3267#define GEN_LDFS(name, ldop, op, type) \
3268GEN_LDF(name, ldop, op | 0x20, type); \
3269GEN_LDUF(name, ldop, op | 0x21, type); \
3270GEN_LDUXF(name, ldop, op | 0x01, type); \
3271GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3272
3273static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3274{
3275 TCGv t0 = tcg_temp_new();
3276 TCGv_i32 t1 = tcg_temp_new_i32();
3277 gen_qemu_ld32u(ctx, t0, arg2);
3278 tcg_gen_trunc_tl_i32(t1, t0);
3279 tcg_temp_free(t0);
3280 gen_helper_float32_to_float64(arg1, t1);
3281 tcg_temp_free_i32(t1);
3282}
3283
3284 /* lfd lfdu lfdux lfdx */
3285GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3286 /* lfs lfsu lfsux lfsx */
3287GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3288
3289/*** Floating-point store ***/
3290#define GEN_STF(name, stop, opc, type) \
3291static void glue(gen_, name)(DisasContext *ctx) \
3292{ \
3293 TCGv EA; \
3294 if (unlikely(!ctx->fpu_enabled)) { \
3295 gen_exception(ctx, POWERPC_EXCP_FPU); \
3296 return; \
3297 } \
3298 gen_set_access_type(ctx, ACCESS_FLOAT); \
3299 EA = tcg_temp_new(); \
3300 gen_addr_imm_index(ctx, EA, 0); \
3301 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3302 tcg_temp_free(EA); \
3303}
3304
3305#define GEN_STUF(name, stop, opc, type) \
3306static void glue(gen_, name##u)(DisasContext *ctx) \
3307{ \
3308 TCGv EA; \
3309 if (unlikely(!ctx->fpu_enabled)) { \
3310 gen_exception(ctx, POWERPC_EXCP_FPU); \
3311 return; \
3312 } \
3313 if (unlikely(rA(ctx->opcode) == 0)) { \
3314 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3315 return; \
3316 } \
3317 gen_set_access_type(ctx, ACCESS_FLOAT); \
3318 EA = tcg_temp_new(); \
3319 gen_addr_imm_index(ctx, EA, 0); \
3320 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3321 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3322 tcg_temp_free(EA); \
3323}
3324
3325#define GEN_STUXF(name, stop, opc, type) \
3326static void glue(gen_, name##ux)(DisasContext *ctx) \
3327{ \
3328 TCGv EA; \
3329 if (unlikely(!ctx->fpu_enabled)) { \
3330 gen_exception(ctx, POWERPC_EXCP_FPU); \
3331 return; \
3332 } \
3333 if (unlikely(rA(ctx->opcode) == 0)) { \
3334 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3335 return; \
3336 } \
3337 gen_set_access_type(ctx, ACCESS_FLOAT); \
3338 EA = tcg_temp_new(); \
3339 gen_addr_reg_index(ctx, EA); \
3340 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3341 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3342 tcg_temp_free(EA); \
3343}
3344
3345#define GEN_STXF(name, stop, opc2, opc3, type) \
3346static void glue(gen_, name##x)(DisasContext *ctx) \
3347{ \
3348 TCGv EA; \
3349 if (unlikely(!ctx->fpu_enabled)) { \
3350 gen_exception(ctx, POWERPC_EXCP_FPU); \
3351 return; \
3352 } \
3353 gen_set_access_type(ctx, ACCESS_FLOAT); \
3354 EA = tcg_temp_new(); \
3355 gen_addr_reg_index(ctx, EA); \
3356 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3357 tcg_temp_free(EA); \
3358}
3359
3360#define GEN_STFS(name, stop, op, type) \
3361GEN_STF(name, stop, op | 0x20, type); \
3362GEN_STUF(name, stop, op | 0x21, type); \
3363GEN_STUXF(name, stop, op | 0x01, type); \
3364GEN_STXF(name, stop, 0x17, op | 0x00, type)
3365
3366static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3367{
3368 TCGv_i32 t0 = tcg_temp_new_i32();
3369 TCGv t1 = tcg_temp_new();
3370 gen_helper_float64_to_float32(t0, arg1);
3371 tcg_gen_extu_i32_tl(t1, t0);
3372 tcg_temp_free_i32(t0);
3373 gen_qemu_st32(ctx, t1, arg2);
3374 tcg_temp_free(t1);
3375}
3376
3377/* stfd stfdu stfdux stfdx */
3378GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3379/* stfs stfsu stfsux stfsx */
3380GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3381
3382/* Optional: */
3383static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3384{
3385 TCGv t0 = tcg_temp_new();
3386 tcg_gen_trunc_i64_tl(t0, arg1),
3387 gen_qemu_st32(ctx, t0, arg2);
3388 tcg_temp_free(t0);
3389}
3390/* stfiwx */
3391GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3392
3393static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3394{
3395#if defined(TARGET_PPC64)
3396 if (ctx->has_cfar)
3397 tcg_gen_movi_tl(cpu_cfar, nip);
3398#endif
3399}
3400
3401/*** Branch ***/
3402static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3403{
3404 TranslationBlock *tb;
3405 tb = ctx->tb;
3406#if defined(TARGET_PPC64)
3407 if (!ctx->sf_mode)
3408 dest = (uint32_t) dest;
3409#endif
3410 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3411 likely(!ctx->singlestep_enabled)) {
3412 tcg_gen_goto_tb(n);
3413 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3414 tcg_gen_exit_tb((tcg_target_long)tb + n);
3415 } else {
3416 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3417 if (unlikely(ctx->singlestep_enabled)) {
3418 if ((ctx->singlestep_enabled &
3419 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3420 ctx->exception == POWERPC_EXCP_BRANCH) {
3421 target_ulong tmp = ctx->nip;
3422 ctx->nip = dest;
3423 gen_exception(ctx, POWERPC_EXCP_TRACE);
3424 ctx->nip = tmp;
3425 }
3426 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3427 gen_debug_exception(ctx);
3428 }
3429 }
3430 tcg_gen_exit_tb(0);
3431 }
3432}
3433
3434static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3435{
3436#if defined(TARGET_PPC64)
3437 if (ctx->sf_mode == 0)
3438 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3439 else
3440#endif
3441 tcg_gen_movi_tl(cpu_lr, nip);
3442}
3443
3444/* b ba bl bla */
3445static void gen_b(DisasContext *ctx)
3446{
3447 target_ulong li, target;
3448
3449 ctx->exception = POWERPC_EXCP_BRANCH;
3450 /* sign extend LI */
3451#if defined(TARGET_PPC64)
3452 if (ctx->sf_mode)
3453 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3454 else
3455#endif
3456 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3457 if (likely(AA(ctx->opcode) == 0))
3458 target = ctx->nip + li - 4;
3459 else
3460 target = li;
3461 if (LK(ctx->opcode))
3462 gen_setlr(ctx, ctx->nip);
3463 gen_update_cfar(ctx, ctx->nip);
3464 gen_goto_tb(ctx, 0, target);
3465}
3466
3467#define BCOND_IM 0
3468#define BCOND_LR 1
3469#define BCOND_CTR 2
3470
3471static inline void gen_bcond(DisasContext *ctx, int type)
3472{
3473 uint32_t bo = BO(ctx->opcode);
3474 int l1;
3475 TCGv target;
3476
3477 ctx->exception = POWERPC_EXCP_BRANCH;
3478 if (type == BCOND_LR || type == BCOND_CTR) {
3479 target = tcg_temp_local_new();
3480 if (type == BCOND_CTR)
3481 tcg_gen_mov_tl(target, cpu_ctr);
3482 else
3483 tcg_gen_mov_tl(target, cpu_lr);
3484 } else {
3485 TCGV_UNUSED(target);
3486 }
3487 if (LK(ctx->opcode))
3488 gen_setlr(ctx, ctx->nip);
3489 l1 = gen_new_label();
3490 if ((bo & 0x4) == 0) {
3491 /* Decrement and test CTR */
3492 TCGv temp = tcg_temp_new();
3493 if (unlikely(type == BCOND_CTR)) {
3494 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3495 return;
3496 }
3497 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3498#if defined(TARGET_PPC64)
3499 if (!ctx->sf_mode)
3500 tcg_gen_ext32u_tl(temp, cpu_ctr);
3501 else
3502#endif
3503 tcg_gen_mov_tl(temp, cpu_ctr);
3504 if (bo & 0x2) {
3505 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3506 } else {
3507 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3508 }
3509 tcg_temp_free(temp);
3510 }
3511 if ((bo & 0x10) == 0) {
3512 /* Test CR */
3513 uint32_t bi = BI(ctx->opcode);
3514 uint32_t mask = 1 << (3 - (bi & 0x03));
3515 TCGv_i32 temp = tcg_temp_new_i32();
3516
3517 if (bo & 0x8) {
3518 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3519 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3520 } else {
3521 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3522 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3523 }
3524 tcg_temp_free_i32(temp);
3525 }
3526 gen_update_cfar(ctx, ctx->nip);
3527 if (type == BCOND_IM) {
3528 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3529 if (likely(AA(ctx->opcode) == 0)) {
3530 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3531 } else {
3532 gen_goto_tb(ctx, 0, li);
3533 }
3534 gen_set_label(l1);
3535 gen_goto_tb(ctx, 1, ctx->nip);
3536 } else {
3537#if defined(TARGET_PPC64)
3538 if (!(ctx->sf_mode))
3539 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3540 else
3541#endif
3542 tcg_gen_andi_tl(cpu_nip, target, ~3);
3543 tcg_gen_exit_tb(0);
3544 gen_set_label(l1);
3545#if defined(TARGET_PPC64)
3546 if (!(ctx->sf_mode))
3547 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3548 else
3549#endif
3550 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3551 tcg_gen_exit_tb(0);
3552 }
3553}
3554
3555static void gen_bc(DisasContext *ctx)
3556{
3557 gen_bcond(ctx, BCOND_IM);
3558}
3559
3560static void gen_bcctr(DisasContext *ctx)
3561{
3562 gen_bcond(ctx, BCOND_CTR);
3563}
3564
3565static void gen_bclr(DisasContext *ctx)
3566{
3567 gen_bcond(ctx, BCOND_LR);
3568}
3569
3570/*** Condition register logical ***/
3571#define GEN_CRLOGIC(name, tcg_op, opc) \
3572static void glue(gen_, name)(DisasContext *ctx) \
3573{ \
3574 uint8_t bitmask; \
3575 int sh; \
3576 TCGv_i32 t0, t1; \
3577 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3578 t0 = tcg_temp_new_i32(); \
3579 if (sh > 0) \
3580 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3581 else if (sh < 0) \
3582 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3583 else \
3584 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3585 t1 = tcg_temp_new_i32(); \
3586 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3587 if (sh > 0) \
3588 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3589 else if (sh < 0) \
3590 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3591 else \
3592 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3593 tcg_op(t0, t0, t1); \
3594 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3595 tcg_gen_andi_i32(t0, t0, bitmask); \
3596 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3597 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3598 tcg_temp_free_i32(t0); \
3599 tcg_temp_free_i32(t1); \
3600}
3601
3602/* crand */
3603GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3604/* crandc */
3605GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3606/* creqv */
3607GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3608/* crnand */
3609GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3610/* crnor */
3611GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3612/* cror */
3613GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3614/* crorc */
3615GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3616/* crxor */
3617GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3618
3619/* mcrf */
3620static void gen_mcrf(DisasContext *ctx)
3621{
3622 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3623}
3624
3625/*** System linkage ***/
3626
3627/* rfi (mem_idx only) */
3628static void gen_rfi(DisasContext *ctx)
3629{
3630#if defined(CONFIG_USER_ONLY)
3631 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3632#else
3633 /* Restore CPU state */
3634 if (unlikely(!ctx->mem_idx)) {
3635 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3636 return;
3637 }
3638 gen_update_cfar(ctx, ctx->nip);
3639 gen_helper_rfi();
3640 gen_sync_exception(ctx);
3641#endif
3642}
3643
3644#if defined(TARGET_PPC64)
3645static void gen_rfid(DisasContext *ctx)
3646{
3647#if defined(CONFIG_USER_ONLY)
3648 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3649#else
3650 /* Restore CPU state */
3651 if (unlikely(!ctx->mem_idx)) {
3652 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3653 return;
3654 }
3655 gen_update_cfar(ctx, ctx->nip);
3656 gen_helper_rfid();
3657 gen_sync_exception(ctx);
3658#endif
3659}
3660
3661static void gen_hrfid(DisasContext *ctx)
3662{
3663#if defined(CONFIG_USER_ONLY)
3664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3665#else
3666 /* Restore CPU state */
3667 if (unlikely(ctx->mem_idx <= 1)) {
3668 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3669 return;
3670 }
3671 gen_helper_hrfid();
3672 gen_sync_exception(ctx);
3673#endif
3674}
3675#endif
3676
3677/* sc */
3678#if defined(CONFIG_USER_ONLY)
3679#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3680#else
3681#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3682#endif
3683static void gen_sc(DisasContext *ctx)
3684{
3685 uint32_t lev;
3686
3687 lev = (ctx->opcode >> 5) & 0x7F;
3688 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3689}
3690
3691/*** Trap ***/
3692
3693/* tw */
3694static void gen_tw(DisasContext *ctx)
3695{
3696 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3697 /* Update the nip since this might generate a trap exception */
3698 gen_update_nip(ctx, ctx->nip);
3699 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3700 tcg_temp_free_i32(t0);
3701}
3702
3703/* twi */
3704static void gen_twi(DisasContext *ctx)
3705{
3706 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3707 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3708 /* Update the nip since this might generate a trap exception */
3709 gen_update_nip(ctx, ctx->nip);
3710 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3711 tcg_temp_free(t0);
3712 tcg_temp_free_i32(t1);
3713}
3714
3715#if defined(TARGET_PPC64)
3716/* td */
3717static void gen_td(DisasContext *ctx)
3718{
3719 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3720 /* Update the nip since this might generate a trap exception */
3721 gen_update_nip(ctx, ctx->nip);
3722 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3723 tcg_temp_free_i32(t0);
3724}
3725
3726/* tdi */
3727static void gen_tdi(DisasContext *ctx)
3728{
3729 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3730 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3731 /* Update the nip since this might generate a trap exception */
3732 gen_update_nip(ctx, ctx->nip);
3733 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3734 tcg_temp_free(t0);
3735 tcg_temp_free_i32(t1);
3736}
3737#endif
3738
3739/*** Processor control ***/
3740
3741/* mcrxr */
3742static void gen_mcrxr(DisasContext *ctx)
3743{
3744 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3745 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3746 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3747}
3748
3749/* mfcr mfocrf */
3750static void gen_mfcr(DisasContext *ctx)
3751{
3752 uint32_t crm, crn;
3753
3754 if (likely(ctx->opcode & 0x00100000)) {
3755 crm = CRM(ctx->opcode);
3756 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3757 crn = ctz32 (crm);
3758 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3759 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3760 cpu_gpr[rD(ctx->opcode)], crn * 4);
3761 }
3762 } else {
3763 TCGv_i32 t0 = tcg_temp_new_i32();
3764 tcg_gen_mov_i32(t0, cpu_crf[0]);
3765 tcg_gen_shli_i32(t0, t0, 4);
3766 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3767 tcg_gen_shli_i32(t0, t0, 4);
3768 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3769 tcg_gen_shli_i32(t0, t0, 4);
3770 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3771 tcg_gen_shli_i32(t0, t0, 4);
3772 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3773 tcg_gen_shli_i32(t0, t0, 4);
3774 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3775 tcg_gen_shli_i32(t0, t0, 4);
3776 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3777 tcg_gen_shli_i32(t0, t0, 4);
3778 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3779 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3780 tcg_temp_free_i32(t0);
3781 }
3782}
3783
3784/* mfmsr */
3785static void gen_mfmsr(DisasContext *ctx)
3786{
3787#if defined(CONFIG_USER_ONLY)
3788 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3789#else
3790 if (unlikely(!ctx->mem_idx)) {
3791 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3792 return;
3793 }
3794 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3795#endif
3796}
3797
3798static void spr_noaccess(void *opaque, int gprn, int sprn)
3799{
3800#if 0
3801 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3802 printf("ERROR: try to access SPR %d !\n", sprn);
3803#endif
3804}
3805#define SPR_NOACCESS (&spr_noaccess)
3806
3807/* mfspr */
3808static inline void gen_op_mfspr(DisasContext *ctx)
3809{
3810 void (*read_cb)(void *opaque, int gprn, int sprn);
3811 uint32_t sprn = SPR(ctx->opcode);
3812
3813#if !defined(CONFIG_USER_ONLY)
3814 if (ctx->mem_idx == 2)
3815 read_cb = ctx->spr_cb[sprn].hea_read;
3816 else if (ctx->mem_idx)
3817 read_cb = ctx->spr_cb[sprn].oea_read;
3818 else
3819#endif
3820 read_cb = ctx->spr_cb[sprn].uea_read;
3821 if (likely(read_cb != NULL)) {
3822 if (likely(read_cb != SPR_NOACCESS)) {
3823 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3824 } else {
3825 /* Privilege exception */
3826 /* This is a hack to avoid warnings when running Linux:
3827 * this OS breaks the PowerPC virtualisation model,
3828 * allowing userland application to read the PVR
3829 */
3830 if (sprn != SPR_PVR) {
3831 qemu_log("Trying to read privileged spr %d %03x at "
3832 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3833 printf("Trying to read privileged spr %d %03x at "
3834 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3835 }
3836 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3837 }
3838 } else {
3839 /* Not defined */
3840 qemu_log("Trying to read invalid spr %d %03x at "
3841 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3842 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3843 sprn, sprn, ctx->nip);
3844 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3845 }
3846}
3847
3848static void gen_mfspr(DisasContext *ctx)
3849{
3850 gen_op_mfspr(ctx);
3851}
3852
3853/* mftb */
3854static void gen_mftb(DisasContext *ctx)
3855{
3856 gen_op_mfspr(ctx);
3857}
3858
3859/* mtcrf mtocrf*/
3860static void gen_mtcrf(DisasContext *ctx)
3861{
3862 uint32_t crm, crn;
3863
3864 crm = CRM(ctx->opcode);
3865 if (likely((ctx->opcode & 0x00100000))) {
3866 if (crm && ((crm & (crm - 1)) == 0)) {
3867 TCGv_i32 temp = tcg_temp_new_i32();
3868 crn = ctz32 (crm);
3869 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3870 tcg_gen_shri_i32(temp, temp, crn * 4);
3871 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3872 tcg_temp_free_i32(temp);
3873 }
3874 } else {
3875 TCGv_i32 temp = tcg_temp_new_i32();
3876 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3877 for (crn = 0 ; crn < 8 ; crn++) {
3878 if (crm & (1 << crn)) {
3879 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3880 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3881 }
3882 }
3883 tcg_temp_free_i32(temp);
3884 }
3885}
3886
3887/* mtmsr */
3888#if defined(TARGET_PPC64)
3889static void gen_mtmsrd(DisasContext *ctx)
3890{
3891#if defined(CONFIG_USER_ONLY)
3892 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3893#else
3894 if (unlikely(!ctx->mem_idx)) {
3895 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3896 return;
3897 }
3898 if (ctx->opcode & 0x00010000) {
3899 /* Special form that does not need any synchronisation */
3900 TCGv t0 = tcg_temp_new();
3901 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3902 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3903 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3904 tcg_temp_free(t0);
3905 } else {
3906 /* XXX: we need to update nip before the store
3907 * if we enter power saving mode, we will exit the loop
3908 * directly from ppc_store_msr
3909 */
3910 gen_update_nip(ctx, ctx->nip);
3911 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3912 /* Must stop the translation as machine state (may have) changed */
3913 /* Note that mtmsr is not always defined as context-synchronizing */
3914 gen_stop_exception(ctx);
3915 }
3916#endif
3917}
3918#endif
3919
3920static void gen_mtmsr(DisasContext *ctx)
3921{
3922#if defined(CONFIG_USER_ONLY)
3923 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3924#else
3925 if (unlikely(!ctx->mem_idx)) {
3926 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3927 return;
3928 }
3929 if (ctx->opcode & 0x00010000) {
3930 /* Special form that does not need any synchronisation */
3931 TCGv t0 = tcg_temp_new();
3932 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3933 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3934 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3935 tcg_temp_free(t0);
3936 } else {
3937 TCGv msr = tcg_temp_new();
3938
3939 /* XXX: we need to update nip before the store
3940 * if we enter power saving mode, we will exit the loop
3941 * directly from ppc_store_msr
3942 */
3943 gen_update_nip(ctx, ctx->nip);
3944#if defined(TARGET_PPC64)
3945 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3946#else
3947 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3948#endif
3949 gen_helper_store_msr(msr);
3950 /* Must stop the translation as machine state (may have) changed */
3951 /* Note that mtmsr is not always defined as context-synchronizing */
3952 gen_stop_exception(ctx);
3953 }
3954#endif
3955}
3956
3957/* mtspr */
3958static void gen_mtspr(DisasContext *ctx)
3959{
3960 void (*write_cb)(void *opaque, int sprn, int gprn);
3961 uint32_t sprn = SPR(ctx->opcode);
3962
3963#if !defined(CONFIG_USER_ONLY)
3964 if (ctx->mem_idx == 2)
3965 write_cb = ctx->spr_cb[sprn].hea_write;
3966 else if (ctx->mem_idx)
3967 write_cb = ctx->spr_cb[sprn].oea_write;
3968 else
3969#endif
3970 write_cb = ctx->spr_cb[sprn].uea_write;
3971 if (likely(write_cb != NULL)) {
3972 if (likely(write_cb != SPR_NOACCESS)) {
3973 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3974 } else {
3975 /* Privilege exception */
3976 qemu_log("Trying to write privileged spr %d %03x at "
3977 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3978 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3979 "\n", sprn, sprn, ctx->nip);
3980 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3981 }
3982 } else {
3983 /* Not defined */
3984 qemu_log("Trying to write invalid spr %d %03x at "
3985 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3986 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
3987 sprn, sprn, ctx->nip);
3988 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3989 }
3990}
3991
3992/*** Cache management ***/
3993
3994/* dcbf */
3995static void gen_dcbf(DisasContext *ctx)
3996{
3997 /* XXX: specification says this is treated as a load by the MMU */
3998 TCGv t0;
3999 gen_set_access_type(ctx, ACCESS_CACHE);
4000 t0 = tcg_temp_new();
4001 gen_addr_reg_index(ctx, t0);
4002 gen_qemu_ld8u(ctx, t0, t0);
4003 tcg_temp_free(t0);
4004}
4005
4006/* dcbi (Supervisor only) */
4007static void gen_dcbi(DisasContext *ctx)
4008{
4009#if defined(CONFIG_USER_ONLY)
4010 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4011#else
4012 TCGv EA, val;
4013 if (unlikely(!ctx->mem_idx)) {
4014 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4015 return;
4016 }
4017 EA = tcg_temp_new();
4018 gen_set_access_type(ctx, ACCESS_CACHE);
4019 gen_addr_reg_index(ctx, EA);
4020 val = tcg_temp_new();
4021 /* XXX: specification says this should be treated as a store by the MMU */
4022 gen_qemu_ld8u(ctx, val, EA);
4023 gen_qemu_st8(ctx, val, EA);
4024 tcg_temp_free(val);
4025 tcg_temp_free(EA);
4026#endif
4027}
4028
4029/* dcdst */
4030static void gen_dcbst(DisasContext *ctx)
4031{
4032 /* XXX: specification say this is treated as a load by the MMU */
4033 TCGv t0;
4034 gen_set_access_type(ctx, ACCESS_CACHE);
4035 t0 = tcg_temp_new();
4036 gen_addr_reg_index(ctx, t0);
4037 gen_qemu_ld8u(ctx, t0, t0);
4038 tcg_temp_free(t0);
4039}
4040
4041/* dcbt */
4042static void gen_dcbt(DisasContext *ctx)
4043{
4044 /* interpreted as no-op */
4045 /* XXX: specification say this is treated as a load by the MMU
4046 * but does not generate any exception
4047 */
4048}
4049
4050/* dcbtst */
4051static void gen_dcbtst(DisasContext *ctx)
4052{
4053 /* interpreted as no-op */
4054 /* XXX: specification say this is treated as a load by the MMU
4055 * but does not generate any exception
4056 */
4057}
4058
4059/* dcbz */
4060static void gen_dcbz(DisasContext *ctx)
4061{
4062 TCGv t0;
4063 gen_set_access_type(ctx, ACCESS_CACHE);
4064 /* NIP cannot be restored if the memory exception comes from an helper */
4065 gen_update_nip(ctx, ctx->nip - 4);
4066 t0 = tcg_temp_new();
4067 gen_addr_reg_index(ctx, t0);
4068 gen_helper_dcbz(t0);
4069 tcg_temp_free(t0);
4070}
4071
4072static void gen_dcbz_970(DisasContext *ctx)
4073{
4074 TCGv t0;
4075 gen_set_access_type(ctx, ACCESS_CACHE);
4076 /* NIP cannot be restored if the memory exception comes from an helper */
4077 gen_update_nip(ctx, ctx->nip - 4);
4078 t0 = tcg_temp_new();
4079 gen_addr_reg_index(ctx, t0);
4080 if (ctx->opcode & 0x00200000)
4081 gen_helper_dcbz(t0);
4082 else
4083 gen_helper_dcbz_970(t0);
4084 tcg_temp_free(t0);
4085}
4086
4087/* dst / dstt */
4088static void gen_dst(DisasContext *ctx)
4089{
4090 if (rA(ctx->opcode) == 0) {
4091 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4092 } else {
4093 /* interpreted as no-op */
4094 }
4095}
4096
4097/* dstst /dststt */
4098static void gen_dstst(DisasContext *ctx)
4099{
4100 if (rA(ctx->opcode) == 0) {
4101 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4102 } else {
4103 /* interpreted as no-op */
4104 }
4105
4106}
4107
4108/* dss / dssall */
4109static void gen_dss(DisasContext *ctx)
4110{
4111 /* interpreted as no-op */
4112}
4113
4114/* icbi */
4115static void gen_icbi(DisasContext *ctx)
4116{
4117 TCGv t0;
4118 gen_set_access_type(ctx, ACCESS_CACHE);
4119 /* NIP cannot be restored if the memory exception comes from an helper */
4120 gen_update_nip(ctx, ctx->nip - 4);
4121 t0 = tcg_temp_new();
4122 gen_addr_reg_index(ctx, t0);
4123 gen_helper_icbi(t0);
4124 tcg_temp_free(t0);
4125}
4126
4127/* Optional: */
4128/* dcba */
4129static void gen_dcba(DisasContext *ctx)
4130{
4131 /* interpreted as no-op */
4132 /* XXX: specification say this is treated as a store by the MMU
4133 * but does not generate any exception
4134 */
4135}
4136
4137/*** Segment register manipulation ***/
4138/* Supervisor only: */
4139
4140/* mfsr */
4141static void gen_mfsr(DisasContext *ctx)
4142{
4143#if defined(CONFIG_USER_ONLY)
4144 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4145#else
4146 TCGv t0;
4147 if (unlikely(!ctx->mem_idx)) {
4148 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4149 return;
4150 }
4151 t0 = tcg_const_tl(SR(ctx->opcode));
4152 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4153 tcg_temp_free(t0);
4154#endif
4155}
4156
4157/* mfsrin */
4158static void gen_mfsrin(DisasContext *ctx)
4159{
4160#if defined(CONFIG_USER_ONLY)
4161 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4162#else
4163 TCGv t0;
4164 if (unlikely(!ctx->mem_idx)) {
4165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4166 return;
4167 }
4168 t0 = tcg_temp_new();
4169 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4170 tcg_gen_andi_tl(t0, t0, 0xF);
4171 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4172 tcg_temp_free(t0);
4173#endif
4174}
4175
4176/* mtsr */
4177static void gen_mtsr(DisasContext *ctx)
4178{
4179#if defined(CONFIG_USER_ONLY)
4180 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4181#else
4182 TCGv t0;
4183 if (unlikely(!ctx->mem_idx)) {
4184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4185 return;
4186 }
4187 t0 = tcg_const_tl(SR(ctx->opcode));
4188 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4189 tcg_temp_free(t0);
4190#endif
4191}
4192
4193/* mtsrin */
4194static void gen_mtsrin(DisasContext *ctx)
4195{
4196#if defined(CONFIG_USER_ONLY)
4197 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4198#else
4199 TCGv t0;
4200 if (unlikely(!ctx->mem_idx)) {
4201 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4202 return;
4203 }
4204 t0 = tcg_temp_new();
4205 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4206 tcg_gen_andi_tl(t0, t0, 0xF);
4207 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4208 tcg_temp_free(t0);
4209#endif
4210}
4211
4212#if defined(TARGET_PPC64)
4213/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4214
4215/* mfsr */
4216static void gen_mfsr_64b(DisasContext *ctx)
4217{
4218#if defined(CONFIG_USER_ONLY)
4219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4220#else
4221 TCGv t0;
4222 if (unlikely(!ctx->mem_idx)) {
4223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4224 return;
4225 }
4226 t0 = tcg_const_tl(SR(ctx->opcode));
4227 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4228 tcg_temp_free(t0);
4229#endif
4230}
4231
4232/* mfsrin */
4233static void gen_mfsrin_64b(DisasContext *ctx)
4234{
4235#if defined(CONFIG_USER_ONLY)
4236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4237#else
4238 TCGv t0;
4239 if (unlikely(!ctx->mem_idx)) {
4240 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4241 return;
4242 }
4243 t0 = tcg_temp_new();
4244 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4245 tcg_gen_andi_tl(t0, t0, 0xF);
4246 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4247 tcg_temp_free(t0);
4248#endif
4249}
4250
4251/* mtsr */
4252static void gen_mtsr_64b(DisasContext *ctx)
4253{
4254#if defined(CONFIG_USER_ONLY)
4255 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4256#else
4257 TCGv t0;
4258 if (unlikely(!ctx->mem_idx)) {
4259 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4260 return;
4261 }
4262 t0 = tcg_const_tl(SR(ctx->opcode));
4263 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4264 tcg_temp_free(t0);
4265#endif
4266}
4267
4268/* mtsrin */
4269static void gen_mtsrin_64b(DisasContext *ctx)
4270{
4271#if defined(CONFIG_USER_ONLY)
4272 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4273#else
4274 TCGv t0;
4275 if (unlikely(!ctx->mem_idx)) {
4276 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4277 return;
4278 }
4279 t0 = tcg_temp_new();
4280 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4281 tcg_gen_andi_tl(t0, t0, 0xF);
4282 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4283 tcg_temp_free(t0);
4284#endif
4285}
4286
4287/* slbmte */
4288static void gen_slbmte(DisasContext *ctx)
4289{
4290#if defined(CONFIG_USER_ONLY)
4291 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4292#else
4293 if (unlikely(!ctx->mem_idx)) {
4294 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4295 return;
4296 }
4297 gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
4298#endif
4299}
4300
4301static void gen_slbmfee(DisasContext *ctx)
4302{
4303#if defined(CONFIG_USER_ONLY)
4304 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4305#else
4306 if (unlikely(!ctx->mem_idx)) {
4307 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4308 return;
4309 }
4310 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)],
4311 cpu_gpr[rB(ctx->opcode)]);
4312#endif
4313}
4314
4315static void gen_slbmfev(DisasContext *ctx)
4316{
4317#if defined(CONFIG_USER_ONLY)
4318 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4319#else
4320 if (unlikely(!ctx->mem_idx)) {
4321 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4322 return;
4323 }
4324 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)],
4325 cpu_gpr[rB(ctx->opcode)]);
4326#endif
4327}
4328#endif /* defined(TARGET_PPC64) */
4329
4330/*** Lookaside buffer management ***/
4331/* Optional & mem_idx only: */
4332
4333/* tlbia */
4334static void gen_tlbia(DisasContext *ctx)
4335{
4336#if defined(CONFIG_USER_ONLY)
4337 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4338#else
4339 if (unlikely(!ctx->mem_idx)) {
4340 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4341 return;
4342 }
4343 gen_helper_tlbia();
4344#endif
4345}
4346
4347/* tlbiel */
4348static void gen_tlbiel(DisasContext *ctx)
4349{
4350#if defined(CONFIG_USER_ONLY)
4351 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4352#else
4353 if (unlikely(!ctx->mem_idx)) {
4354 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4355 return;
4356 }
4357 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4358#endif
4359}
4360
4361/* tlbie */
4362static void gen_tlbie(DisasContext *ctx)
4363{
4364#if defined(CONFIG_USER_ONLY)
4365 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4366#else
4367 if (unlikely(!ctx->mem_idx)) {
4368 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4369 return;
4370 }
4371#if defined(TARGET_PPC64)
4372 if (!ctx->sf_mode) {
4373 TCGv t0 = tcg_temp_new();
4374 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4375 gen_helper_tlbie(t0);
4376 tcg_temp_free(t0);
4377 } else
4378#endif
4379 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4380#endif
4381}
4382
4383/* tlbsync */
4384static void gen_tlbsync(DisasContext *ctx)
4385{
4386#if defined(CONFIG_USER_ONLY)
4387 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4388#else
4389 if (unlikely(!ctx->mem_idx)) {
4390 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4391 return;
4392 }
4393 /* This has no effect: it should ensure that all previous
4394 * tlbie have completed
4395 */
4396 gen_stop_exception(ctx);
4397#endif
4398}
4399
4400#if defined(TARGET_PPC64)
4401/* slbia */
4402static void gen_slbia(DisasContext *ctx)
4403{
4404#if defined(CONFIG_USER_ONLY)
4405 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4406#else
4407 if (unlikely(!ctx->mem_idx)) {
4408 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4409 return;
4410 }
4411 gen_helper_slbia();
4412#endif
4413}
4414
4415/* slbie */
4416static void gen_slbie(DisasContext *ctx)
4417{
4418#if defined(CONFIG_USER_ONLY)
4419 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4420#else
4421 if (unlikely(!ctx->mem_idx)) {
4422 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4423 return;
4424 }
4425 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4426#endif
4427}
4428#endif
4429
4430/*** External control ***/
4431/* Optional: */
4432
4433/* eciwx */
4434static void gen_eciwx(DisasContext *ctx)
4435{
4436 TCGv t0;
4437 /* Should check EAR[E] ! */
4438 gen_set_access_type(ctx, ACCESS_EXT);
4439 t0 = tcg_temp_new();
4440 gen_addr_reg_index(ctx, t0);
4441 gen_check_align(ctx, t0, 0x03);
4442 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4443 tcg_temp_free(t0);
4444}
4445
4446/* ecowx */
4447static void gen_ecowx(DisasContext *ctx)
4448{
4449 TCGv t0;
4450 /* Should check EAR[E] ! */
4451 gen_set_access_type(ctx, ACCESS_EXT);
4452 t0 = tcg_temp_new();
4453 gen_addr_reg_index(ctx, t0);
4454 gen_check_align(ctx, t0, 0x03);
4455 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4456 tcg_temp_free(t0);
4457}
4458
4459/* PowerPC 601 specific instructions */
4460
4461/* abs - abs. */
4462static void gen_abs(DisasContext *ctx)
4463{
4464 int l1 = gen_new_label();
4465 int l2 = gen_new_label();
4466 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4467 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4468 tcg_gen_br(l2);
4469 gen_set_label(l1);
4470 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4471 gen_set_label(l2);
4472 if (unlikely(Rc(ctx->opcode) != 0))
4473 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4474}
4475
4476/* abso - abso. */
4477static void gen_abso(DisasContext *ctx)
4478{
4479 int l1 = gen_new_label();
4480 int l2 = gen_new_label();
4481 int l3 = gen_new_label();
4482 /* Start with XER OV disabled, the most likely case */
4483 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4484 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4485 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4486 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4487 tcg_gen_br(l2);
4488 gen_set_label(l1);
4489 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4490 tcg_gen_br(l3);
4491 gen_set_label(l2);
4492 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4493 gen_set_label(l3);
4494 if (unlikely(Rc(ctx->opcode) != 0))
4495 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4496}
4497
4498/* clcs */
4499static void gen_clcs(DisasContext *ctx)
4500{
4501 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4502 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4503 tcg_temp_free_i32(t0);
4504 /* Rc=1 sets CR0 to an undefined state */
4505}
4506
4507/* div - div. */
4508static void gen_div(DisasContext *ctx)
4509{
4510 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4511 if (unlikely(Rc(ctx->opcode) != 0))
4512 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4513}
4514
4515/* divo - divo. */
4516static void gen_divo(DisasContext *ctx)
4517{
4518 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4519 if (unlikely(Rc(ctx->opcode) != 0))
4520 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4521}
4522
4523/* divs - divs. */
4524static void gen_divs(DisasContext *ctx)
4525{
4526 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4527 if (unlikely(Rc(ctx->opcode) != 0))
4528 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4529}
4530
4531/* divso - divso. */
4532static void gen_divso(DisasContext *ctx)
4533{
4534 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4535 if (unlikely(Rc(ctx->opcode) != 0))
4536 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4537}
4538
4539/* doz - doz. */
4540static void gen_doz(DisasContext *ctx)
4541{
4542 int l1 = gen_new_label();
4543 int l2 = gen_new_label();
4544 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4545 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4546 tcg_gen_br(l2);
4547 gen_set_label(l1);
4548 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4549 gen_set_label(l2);
4550 if (unlikely(Rc(ctx->opcode) != 0))
4551 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4552}
4553
4554/* dozo - dozo. */
4555static void gen_dozo(DisasContext *ctx)
4556{
4557 int l1 = gen_new_label();
4558 int l2 = gen_new_label();
4559 TCGv t0 = tcg_temp_new();
4560 TCGv t1 = tcg_temp_new();
4561 TCGv t2 = tcg_temp_new();
4562 /* Start with XER OV disabled, the most likely case */
4563 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4564 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4565 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4566 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4567 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4568 tcg_gen_andc_tl(t1, t1, t2);
4569 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4570 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4571 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4572 tcg_gen_br(l2);
4573 gen_set_label(l1);
4574 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4575 gen_set_label(l2);
4576 tcg_temp_free(t0);
4577 tcg_temp_free(t1);
4578 tcg_temp_free(t2);
4579 if (unlikely(Rc(ctx->opcode) != 0))
4580 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4581}
4582
4583/* dozi */
4584static void gen_dozi(DisasContext *ctx)
4585{
4586 target_long simm = SIMM(ctx->opcode);
4587 int l1 = gen_new_label();
4588 int l2 = gen_new_label();
4589 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4590 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4591 tcg_gen_br(l2);
4592 gen_set_label(l1);
4593 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4594 gen_set_label(l2);
4595 if (unlikely(Rc(ctx->opcode) != 0))
4596 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4597}
4598
4599/* lscbx - lscbx. */
4600static void gen_lscbx(DisasContext *ctx)
4601{
4602 TCGv t0 = tcg_temp_new();
4603 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4604 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4605 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4606
4607 gen_addr_reg_index(ctx, t0);
4608 /* NIP cannot be restored if the memory exception comes from an helper */
4609 gen_update_nip(ctx, ctx->nip - 4);
4610 gen_helper_lscbx(t0, t0, t1, t2, t3);
4611 tcg_temp_free_i32(t1);
4612 tcg_temp_free_i32(t2);
4613 tcg_temp_free_i32(t3);
4614 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4615 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4616 if (unlikely(Rc(ctx->opcode) != 0))
4617 gen_set_Rc0(ctx, t0);
4618 tcg_temp_free(t0);
4619}
4620
4621/* maskg - maskg. */
4622static void gen_maskg(DisasContext *ctx)
4623{
4624 int l1 = gen_new_label();
4625 TCGv t0 = tcg_temp_new();
4626 TCGv t1 = tcg_temp_new();
4627 TCGv t2 = tcg_temp_new();
4628 TCGv t3 = tcg_temp_new();
4629 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4630 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4631 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4632 tcg_gen_addi_tl(t2, t0, 1);
4633 tcg_gen_shr_tl(t2, t3, t2);
4634 tcg_gen_shr_tl(t3, t3, t1);
4635 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4636 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4637 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4638 gen_set_label(l1);
4639 tcg_temp_free(t0);
4640 tcg_temp_free(t1);
4641 tcg_temp_free(t2);
4642 tcg_temp_free(t3);
4643 if (unlikely(Rc(ctx->opcode) != 0))
4644 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4645}
4646
4647/* maskir - maskir. */
4648static void gen_maskir(DisasContext *ctx)
4649{
4650 TCGv t0 = tcg_temp_new();
4651 TCGv t1 = tcg_temp_new();
4652 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4653 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4654 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4655 tcg_temp_free(t0);
4656 tcg_temp_free(t1);
4657 if (unlikely(Rc(ctx->opcode) != 0))
4658 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4659}
4660
4661/* mul - mul. */
4662static void gen_mul(DisasContext *ctx)
4663{
4664 TCGv_i64 t0 = tcg_temp_new_i64();
4665 TCGv_i64 t1 = tcg_temp_new_i64();
4666 TCGv t2 = tcg_temp_new();
4667 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4668 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4669 tcg_gen_mul_i64(t0, t0, t1);
4670 tcg_gen_trunc_i64_tl(t2, t0);
4671 gen_store_spr(SPR_MQ, t2);
4672 tcg_gen_shri_i64(t1, t0, 32);
4673 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4674 tcg_temp_free_i64(t0);
4675 tcg_temp_free_i64(t1);
4676 tcg_temp_free(t2);
4677 if (unlikely(Rc(ctx->opcode) != 0))
4678 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4679}
4680
4681/* mulo - mulo. */
4682static void gen_mulo(DisasContext *ctx)
4683{
4684 int l1 = gen_new_label();
4685 TCGv_i64 t0 = tcg_temp_new_i64();
4686 TCGv_i64 t1 = tcg_temp_new_i64();
4687 TCGv t2 = tcg_temp_new();
4688 /* Start with XER OV disabled, the most likely case */
4689 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4690 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4691 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4692 tcg_gen_mul_i64(t0, t0, t1);
4693 tcg_gen_trunc_i64_tl(t2, t0);
4694 gen_store_spr(SPR_MQ, t2);
4695 tcg_gen_shri_i64(t1, t0, 32);
4696 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4697 tcg_gen_ext32s_i64(t1, t0);
4698 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4699 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4700 gen_set_label(l1);
4701 tcg_temp_free_i64(t0);
4702 tcg_temp_free_i64(t1);
4703 tcg_temp_free(t2);
4704 if (unlikely(Rc(ctx->opcode) != 0))
4705 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4706}
4707
4708/* nabs - nabs. */
4709static void gen_nabs(DisasContext *ctx)
4710{
4711 int l1 = gen_new_label();
4712 int l2 = gen_new_label();
4713 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4714 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4715 tcg_gen_br(l2);
4716 gen_set_label(l1);
4717 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4718 gen_set_label(l2);
4719 if (unlikely(Rc(ctx->opcode) != 0))
4720 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4721}
4722
4723/* nabso - nabso. */
4724static void gen_nabso(DisasContext *ctx)
4725{
4726 int l1 = gen_new_label();
4727 int l2 = gen_new_label();
4728 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4729 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4730 tcg_gen_br(l2);
4731 gen_set_label(l1);
4732 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4733 gen_set_label(l2);
4734 /* nabs never overflows */
4735 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4736 if (unlikely(Rc(ctx->opcode) != 0))
4737 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4738}
4739
4740/* rlmi - rlmi. */
4741static void gen_rlmi(DisasContext *ctx)
4742{
4743 uint32_t mb = MB(ctx->opcode);
4744 uint32_t me = ME(ctx->opcode);
4745 TCGv t0 = tcg_temp_new();
4746 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4747 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4748 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4749 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4750 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4751 tcg_temp_free(t0);
4752 if (unlikely(Rc(ctx->opcode) != 0))
4753 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4754}
4755
4756/* rrib - rrib. */
4757static void gen_rrib(DisasContext *ctx)
4758{
4759 TCGv t0 = tcg_temp_new();
4760 TCGv t1 = tcg_temp_new();
4761 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4762 tcg_gen_movi_tl(t1, 0x80000000);
4763 tcg_gen_shr_tl(t1, t1, t0);
4764 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4765 tcg_gen_and_tl(t0, t0, t1);
4766 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4767 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4768 tcg_temp_free(t0);
4769 tcg_temp_free(t1);
4770 if (unlikely(Rc(ctx->opcode) != 0))
4771 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4772}
4773
4774/* sle - sle. */
4775static void gen_sle(DisasContext *ctx)
4776{
4777 TCGv t0 = tcg_temp_new();
4778 TCGv t1 = tcg_temp_new();
4779 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4780 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4781 tcg_gen_subfi_tl(t1, 32, t1);
4782 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4783 tcg_gen_or_tl(t1, t0, t1);
4784 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4785 gen_store_spr(SPR_MQ, t1);
4786 tcg_temp_free(t0);
4787 tcg_temp_free(t1);
4788 if (unlikely(Rc(ctx->opcode) != 0))
4789 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4790}
4791
4792/* sleq - sleq. */
4793static void gen_sleq(DisasContext *ctx)
4794{
4795 TCGv t0 = tcg_temp_new();
4796 TCGv t1 = tcg_temp_new();
4797 TCGv t2 = tcg_temp_new();
4798 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4799 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4800 tcg_gen_shl_tl(t2, t2, t0);
4801 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4802 gen_load_spr(t1, SPR_MQ);
4803 gen_store_spr(SPR_MQ, t0);
4804 tcg_gen_and_tl(t0, t0, t2);
4805 tcg_gen_andc_tl(t1, t1, t2);
4806 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4807 tcg_temp_free(t0);
4808 tcg_temp_free(t1);
4809 tcg_temp_free(t2);
4810 if (unlikely(Rc(ctx->opcode) != 0))
4811 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4812}
4813
4814/* sliq - sliq. */
4815static void gen_sliq(DisasContext *ctx)
4816{
4817 int sh = SH(ctx->opcode);
4818 TCGv t0 = tcg_temp_new();
4819 TCGv t1 = tcg_temp_new();
4820 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4821 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4822 tcg_gen_or_tl(t1, t0, t1);
4823 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4824 gen_store_spr(SPR_MQ, t1);
4825 tcg_temp_free(t0);
4826 tcg_temp_free(t1);
4827 if (unlikely(Rc(ctx->opcode) != 0))
4828 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4829}
4830
4831/* slliq - slliq. */
4832static void gen_slliq(DisasContext *ctx)
4833{
4834 int sh = SH(ctx->opcode);
4835 TCGv t0 = tcg_temp_new();
4836 TCGv t1 = tcg_temp_new();
4837 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4838 gen_load_spr(t1, SPR_MQ);
4839 gen_store_spr(SPR_MQ, t0);
4840 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4841 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4842 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4843 tcg_temp_free(t0);
4844 tcg_temp_free(t1);
4845 if (unlikely(Rc(ctx->opcode) != 0))
4846 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4847}
4848
4849/* sllq - sllq. */
4850static void gen_sllq(DisasContext *ctx)
4851{
4852 int l1 = gen_new_label();
4853 int l2 = gen_new_label();
4854 TCGv t0 = tcg_temp_local_new();
4855 TCGv t1 = tcg_temp_local_new();
4856 TCGv t2 = tcg_temp_local_new();
4857 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4858 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4859 tcg_gen_shl_tl(t1, t1, t2);
4860 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4861 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4862 gen_load_spr(t0, SPR_MQ);
4863 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4864 tcg_gen_br(l2);
4865 gen_set_label(l1);
4866 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4867 gen_load_spr(t2, SPR_MQ);
4868 tcg_gen_andc_tl(t1, t2, t1);
4869 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4870 gen_set_label(l2);
4871 tcg_temp_free(t0);
4872 tcg_temp_free(t1);
4873 tcg_temp_free(t2);
4874 if (unlikely(Rc(ctx->opcode) != 0))
4875 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4876}
4877
4878/* slq - slq. */
4879static void gen_slq(DisasContext *ctx)
4880{
4881 int l1 = gen_new_label();
4882 TCGv t0 = tcg_temp_new();
4883 TCGv t1 = tcg_temp_new();
4884 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4885 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4886 tcg_gen_subfi_tl(t1, 32, t1);
4887 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4888 tcg_gen_or_tl(t1, t0, t1);
4889 gen_store_spr(SPR_MQ, t1);
4890 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4891 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4892 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4893 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4894 gen_set_label(l1);
4895 tcg_temp_free(t0);
4896 tcg_temp_free(t1);
4897 if (unlikely(Rc(ctx->opcode) != 0))
4898 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4899}
4900
4901/* sraiq - sraiq. */
4902static void gen_sraiq(DisasContext *ctx)
4903{
4904 int sh = SH(ctx->opcode);
4905 int l1 = gen_new_label();
4906 TCGv t0 = tcg_temp_new();
4907 TCGv t1 = tcg_temp_new();
4908 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4909 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4910 tcg_gen_or_tl(t0, t0, t1);
4911 gen_store_spr(SPR_MQ, t0);
4912 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4913 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4914 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4915 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4916 gen_set_label(l1);
4917 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4918 tcg_temp_free(t0);
4919 tcg_temp_free(t1);
4920 if (unlikely(Rc(ctx->opcode) != 0))
4921 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4922}
4923
4924/* sraq - sraq. */
4925static void gen_sraq(DisasContext *ctx)
4926{
4927 int l1 = gen_new_label();
4928 int l2 = gen_new_label();
4929 TCGv t0 = tcg_temp_new();
4930 TCGv t1 = tcg_temp_local_new();
4931 TCGv t2 = tcg_temp_local_new();
4932 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4933 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4934 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4935 tcg_gen_subfi_tl(t2, 32, t2);
4936 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4937 tcg_gen_or_tl(t0, t0, t2);
4938 gen_store_spr(SPR_MQ, t0);
4939 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4940 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4941 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4942 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4943 gen_set_label(l1);
4944 tcg_temp_free(t0);
4945 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4946 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4947 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4948 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4949 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4950 gen_set_label(l2);
4951 tcg_temp_free(t1);
4952 tcg_temp_free(t2);
4953 if (unlikely(Rc(ctx->opcode) != 0))
4954 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4955}
4956
4957/* sre - sre. */
4958static void gen_sre(DisasContext *ctx)
4959{
4960 TCGv t0 = tcg_temp_new();
4961 TCGv t1 = tcg_temp_new();
4962 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4963 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4964 tcg_gen_subfi_tl(t1, 32, t1);
4965 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4966 tcg_gen_or_tl(t1, t0, t1);
4967 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4968 gen_store_spr(SPR_MQ, t1);
4969 tcg_temp_free(t0);
4970 tcg_temp_free(t1);
4971 if (unlikely(Rc(ctx->opcode) != 0))
4972 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4973}
4974
4975/* srea - srea. */
4976static void gen_srea(DisasContext *ctx)
4977{
4978 TCGv t0 = tcg_temp_new();
4979 TCGv t1 = tcg_temp_new();
4980 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4981 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4982 gen_store_spr(SPR_MQ, t0);
4983 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4984 tcg_temp_free(t0);
4985 tcg_temp_free(t1);
4986 if (unlikely(Rc(ctx->opcode) != 0))
4987 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4988}
4989
4990/* sreq */
4991static void gen_sreq(DisasContext *ctx)
4992{
4993 TCGv t0 = tcg_temp_new();
4994 TCGv t1 = tcg_temp_new();
4995 TCGv t2 = tcg_temp_new();
4996 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4997 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4998 tcg_gen_shr_tl(t1, t1, t0);
4999 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5000 gen_load_spr(t2, SPR_MQ);
5001 gen_store_spr(SPR_MQ, t0);
5002 tcg_gen_and_tl(t0, t0, t1);
5003 tcg_gen_andc_tl(t2, t2, t1);
5004 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5005 tcg_temp_free(t0);
5006 tcg_temp_free(t1);
5007 tcg_temp_free(t2);
5008 if (unlikely(Rc(ctx->opcode) != 0))
5009 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5010}
5011
5012/* sriq */
5013static void gen_sriq(DisasContext *ctx)
5014{
5015 int sh = SH(ctx->opcode);
5016 TCGv t0 = tcg_temp_new();
5017 TCGv t1 = tcg_temp_new();
5018 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5019 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5020 tcg_gen_or_tl(t1, t0, t1);
5021 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5022 gen_store_spr(SPR_MQ, t1);
5023 tcg_temp_free(t0);
5024 tcg_temp_free(t1);
5025 if (unlikely(Rc(ctx->opcode) != 0))
5026 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5027}
5028
5029/* srliq */
5030static void gen_srliq(DisasContext *ctx)
5031{
5032 int sh = SH(ctx->opcode);
5033 TCGv t0 = tcg_temp_new();
5034 TCGv t1 = tcg_temp_new();
5035 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5036 gen_load_spr(t1, SPR_MQ);
5037 gen_store_spr(SPR_MQ, t0);
5038 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5039 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5040 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5041 tcg_temp_free(t0);
5042 tcg_temp_free(t1);
5043 if (unlikely(Rc(ctx->opcode) != 0))
5044 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5045}
5046
5047/* srlq */
5048static void gen_srlq(DisasContext *ctx)
5049{
5050 int l1 = gen_new_label();
5051 int l2 = gen_new_label();
5052 TCGv t0 = tcg_temp_local_new();
5053 TCGv t1 = tcg_temp_local_new();
5054 TCGv t2 = tcg_temp_local_new();
5055 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5056 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5057 tcg_gen_shr_tl(t2, t1, t2);
5058 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5059 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5060 gen_load_spr(t0, SPR_MQ);
5061 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5062 tcg_gen_br(l2);
5063 gen_set_label(l1);
5064 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5065 tcg_gen_and_tl(t0, t0, t2);
5066 gen_load_spr(t1, SPR_MQ);
5067 tcg_gen_andc_tl(t1, t1, t2);
5068 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5069 gen_set_label(l2);
5070 tcg_temp_free(t0);
5071 tcg_temp_free(t1);
5072 tcg_temp_free(t2);
5073 if (unlikely(Rc(ctx->opcode) != 0))
5074 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5075}
5076
5077/* srq */
5078static void gen_srq(DisasContext *ctx)
5079{
5080 int l1 = gen_new_label();
5081 TCGv t0 = tcg_temp_new();
5082 TCGv t1 = tcg_temp_new();
5083 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5084 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5085 tcg_gen_subfi_tl(t1, 32, t1);
5086 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5087 tcg_gen_or_tl(t1, t0, t1);
5088 gen_store_spr(SPR_MQ, t1);
5089 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5090 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5091 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5092 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5093 gen_set_label(l1);
5094 tcg_temp_free(t0);
5095 tcg_temp_free(t1);
5096 if (unlikely(Rc(ctx->opcode) != 0))
5097 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5098}
5099
5100/* PowerPC 602 specific instructions */
5101
5102/* dsa */
5103static void gen_dsa(DisasContext *ctx)
5104{
5105 /* XXX: TODO */
5106 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5107}
5108
5109/* esa */
5110static void gen_esa(DisasContext *ctx)
5111{
5112 /* XXX: TODO */
5113 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5114}
5115
5116/* mfrom */
5117static void gen_mfrom(DisasContext *ctx)
5118{
5119#if defined(CONFIG_USER_ONLY)
5120 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5121#else
5122 if (unlikely(!ctx->mem_idx)) {
5123 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5124 return;
5125 }
5126 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5127#endif
5128}
5129
5130/* 602 - 603 - G2 TLB management */
5131
5132/* tlbld */
5133static void gen_tlbld_6xx(DisasContext *ctx)
5134{
5135#if defined(CONFIG_USER_ONLY)
5136 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5137#else
5138 if (unlikely(!ctx->mem_idx)) {
5139 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5140 return;
5141 }
5142 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5143#endif
5144}
5145
5146/* tlbli */
5147static void gen_tlbli_6xx(DisasContext *ctx)
5148{
5149#if defined(CONFIG_USER_ONLY)
5150 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5151#else
5152 if (unlikely(!ctx->mem_idx)) {
5153 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5154 return;
5155 }
5156 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5157#endif
5158}
5159
5160/* 74xx TLB management */
5161
5162/* tlbld */
5163static void gen_tlbld_74xx(DisasContext *ctx)
5164{
5165#if defined(CONFIG_USER_ONLY)
5166 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5167#else
5168 if (unlikely(!ctx->mem_idx)) {
5169 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5170 return;
5171 }
5172 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5173#endif
5174}
5175
5176/* tlbli */
5177static void gen_tlbli_74xx(DisasContext *ctx)
5178{
5179#if defined(CONFIG_USER_ONLY)
5180 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5181#else
5182 if (unlikely(!ctx->mem_idx)) {
5183 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5184 return;
5185 }
5186 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5187#endif
5188}
5189
5190/* POWER instructions not in PowerPC 601 */
5191
5192/* clf */
5193static void gen_clf(DisasContext *ctx)
5194{
5195 /* Cache line flush: implemented as no-op */
5196}
5197
5198/* cli */
5199static void gen_cli(DisasContext *ctx)
5200{
5201 /* Cache line invalidate: privileged and treated as no-op */
5202#if defined(CONFIG_USER_ONLY)
5203 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5204#else
5205 if (unlikely(!ctx->mem_idx)) {
5206 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5207 return;
5208 }
5209#endif
5210}
5211
5212/* dclst */
5213static void gen_dclst(DisasContext *ctx)
5214{
5215 /* Data cache line store: treated as no-op */
5216}
5217
5218static void gen_mfsri(DisasContext *ctx)
5219{
5220#if defined(CONFIG_USER_ONLY)
5221 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5222#else
5223 int ra = rA(ctx->opcode);
5224 int rd = rD(ctx->opcode);
5225 TCGv t0;
5226 if (unlikely(!ctx->mem_idx)) {
5227 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5228 return;
5229 }
5230 t0 = tcg_temp_new();
5231 gen_addr_reg_index(ctx, t0);
5232 tcg_gen_shri_tl(t0, t0, 28);
5233 tcg_gen_andi_tl(t0, t0, 0xF);
5234 gen_helper_load_sr(cpu_gpr[rd], t0);
5235 tcg_temp_free(t0);
5236 if (ra != 0 && ra != rd)
5237 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5238#endif
5239}
5240
5241static void gen_rac(DisasContext *ctx)
5242{
5243#if defined(CONFIG_USER_ONLY)
5244 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5245#else
5246 TCGv t0;
5247 if (unlikely(!ctx->mem_idx)) {
5248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5249 return;
5250 }
5251 t0 = tcg_temp_new();
5252 gen_addr_reg_index(ctx, t0);
5253 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5254 tcg_temp_free(t0);
5255#endif
5256}
5257
5258static void gen_rfsvc(DisasContext *ctx)
5259{
5260#if defined(CONFIG_USER_ONLY)
5261 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5262#else
5263 if (unlikely(!ctx->mem_idx)) {
5264 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5265 return;
5266 }
5267 gen_helper_rfsvc();
5268 gen_sync_exception(ctx);
5269#endif
5270}
5271
5272/* svc is not implemented for now */
5273
5274/* POWER2 specific instructions */
5275/* Quad manipulation (load/store two floats at a time) */
5276
5277/* lfq */
5278static void gen_lfq(DisasContext *ctx)
5279{
5280 int rd = rD(ctx->opcode);
5281 TCGv t0;
5282 gen_set_access_type(ctx, ACCESS_FLOAT);
5283 t0 = tcg_temp_new();
5284 gen_addr_imm_index(ctx, t0, 0);
5285 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5286 gen_addr_add(ctx, t0, t0, 8);
5287 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5288 tcg_temp_free(t0);
5289}
5290
5291/* lfqu */
5292static void gen_lfqu(DisasContext *ctx)
5293{
5294 int ra = rA(ctx->opcode);
5295 int rd = rD(ctx->opcode);
5296 TCGv t0, t1;
5297 gen_set_access_type(ctx, ACCESS_FLOAT);
5298 t0 = tcg_temp_new();
5299 t1 = tcg_temp_new();
5300 gen_addr_imm_index(ctx, t0, 0);
5301 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5302 gen_addr_add(ctx, t1, t0, 8);
5303 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5304 if (ra != 0)
5305 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5306 tcg_temp_free(t0);
5307 tcg_temp_free(t1);
5308}
5309
5310/* lfqux */
5311static void gen_lfqux(DisasContext *ctx)
5312{
5313 int ra = rA(ctx->opcode);
5314 int rd = rD(ctx->opcode);
5315 gen_set_access_type(ctx, ACCESS_FLOAT);
5316 TCGv t0, t1;
5317 t0 = tcg_temp_new();
5318 gen_addr_reg_index(ctx, t0);
5319 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5320 t1 = tcg_temp_new();
5321 gen_addr_add(ctx, t1, t0, 8);
5322 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5323 tcg_temp_free(t1);
5324 if (ra != 0)
5325 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5326 tcg_temp_free(t0);
5327}
5328
5329/* lfqx */
5330static void gen_lfqx(DisasContext *ctx)
5331{
5332 int rd = rD(ctx->opcode);
5333 TCGv t0;
5334 gen_set_access_type(ctx, ACCESS_FLOAT);
5335 t0 = tcg_temp_new();
5336 gen_addr_reg_index(ctx, t0);
5337 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5338 gen_addr_add(ctx, t0, t0, 8);
5339 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5340 tcg_temp_free(t0);
5341}
5342
5343/* stfq */
5344static void gen_stfq(DisasContext *ctx)
5345{
5346 int rd = rD(ctx->opcode);
5347 TCGv t0;
5348 gen_set_access_type(ctx, ACCESS_FLOAT);
5349 t0 = tcg_temp_new();
5350 gen_addr_imm_index(ctx, t0, 0);
5351 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5352 gen_addr_add(ctx, t0, t0, 8);
5353 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5354 tcg_temp_free(t0);
5355}
5356
5357/* stfqu */
5358static void gen_stfqu(DisasContext *ctx)
5359{
5360 int ra = rA(ctx->opcode);
5361 int rd = rD(ctx->opcode);
5362 TCGv t0, t1;
5363 gen_set_access_type(ctx, ACCESS_FLOAT);
5364 t0 = tcg_temp_new();
5365 gen_addr_imm_index(ctx, t0, 0);
5366 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5367 t1 = tcg_temp_new();
5368 gen_addr_add(ctx, t1, t0, 8);
5369 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5370 tcg_temp_free(t1);
5371 if (ra != 0)
5372 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5373 tcg_temp_free(t0);
5374}
5375
5376/* stfqux */
5377static void gen_stfqux(DisasContext *ctx)
5378{
5379 int ra = rA(ctx->opcode);
5380 int rd = rD(ctx->opcode);
5381 TCGv t0, t1;
5382 gen_set_access_type(ctx, ACCESS_FLOAT);
5383 t0 = tcg_temp_new();
5384 gen_addr_reg_index(ctx, t0);
5385 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5386 t1 = tcg_temp_new();
5387 gen_addr_add(ctx, t1, t0, 8);
5388 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5389 tcg_temp_free(t1);
5390 if (ra != 0)
5391 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5392 tcg_temp_free(t0);
5393}
5394
5395/* stfqx */
5396static void gen_stfqx(DisasContext *ctx)
5397{
5398 int rd = rD(ctx->opcode);
5399 TCGv t0;
5400 gen_set_access_type(ctx, ACCESS_FLOAT);
5401 t0 = tcg_temp_new();
5402 gen_addr_reg_index(ctx, t0);
5403 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5404 gen_addr_add(ctx, t0, t0, 8);
5405 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5406 tcg_temp_free(t0);
5407}
5408
5409/* BookE specific instructions */
5410
5411/* XXX: not implemented on 440 ? */
5412static void gen_mfapidi(DisasContext *ctx)
5413{
5414 /* XXX: TODO */
5415 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5416}
5417
5418/* XXX: not implemented on 440 ? */
5419static void gen_tlbiva(DisasContext *ctx)
5420{
5421#if defined(CONFIG_USER_ONLY)
5422 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5423#else
5424 TCGv t0;
5425 if (unlikely(!ctx->mem_idx)) {
5426 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5427 return;
5428 }
5429 t0 = tcg_temp_new();
5430 gen_addr_reg_index(ctx, t0);
5431 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5432 tcg_temp_free(t0);
5433#endif
5434}
5435
5436/* All 405 MAC instructions are translated here */
5437static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5438 int ra, int rb, int rt, int Rc)
5439{
5440 TCGv t0, t1;
5441
5442 t0 = tcg_temp_local_new();
5443 t1 = tcg_temp_local_new();
5444
5445 switch (opc3 & 0x0D) {
5446 case 0x05:
5447 /* macchw - macchw. - macchwo - macchwo. */
5448 /* macchws - macchws. - macchwso - macchwso. */
5449 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5450 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5451 /* mulchw - mulchw. */
5452 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5453 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5454 tcg_gen_ext16s_tl(t1, t1);
5455 break;
5456 case 0x04:
5457 /* macchwu - macchwu. - macchwuo - macchwuo. */
5458 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5459 /* mulchwu - mulchwu. */
5460 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5461 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5462 tcg_gen_ext16u_tl(t1, t1);
5463 break;
5464 case 0x01:
5465 /* machhw - machhw. - machhwo - machhwo. */
5466 /* machhws - machhws. - machhwso - machhwso. */
5467 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5468 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5469 /* mulhhw - mulhhw. */
5470 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5471 tcg_gen_ext16s_tl(t0, t0);
5472 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5473 tcg_gen_ext16s_tl(t1, t1);
5474 break;
5475 case 0x00:
5476 /* machhwu - machhwu. - machhwuo - machhwuo. */
5477 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5478 /* mulhhwu - mulhhwu. */
5479 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5480 tcg_gen_ext16u_tl(t0, t0);
5481 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5482 tcg_gen_ext16u_tl(t1, t1);
5483 break;
5484 case 0x0D:
5485 /* maclhw - maclhw. - maclhwo - maclhwo. */
5486 /* maclhws - maclhws. - maclhwso - maclhwso. */
5487 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5488 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5489 /* mullhw - mullhw. */
5490 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5491 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5492 break;
5493 case 0x0C:
5494 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5495 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5496 /* mullhwu - mullhwu. */
5497 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5498 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5499 break;
5500 }
5501 if (opc2 & 0x04) {
5502 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5503 tcg_gen_mul_tl(t1, t0, t1);
5504 if (opc2 & 0x02) {
5505 /* nmultiply-and-accumulate (0x0E) */
5506 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5507 } else {
5508 /* multiply-and-accumulate (0x0C) */
5509 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5510 }
5511
5512 if (opc3 & 0x12) {
5513 /* Check overflow and/or saturate */
5514 int l1 = gen_new_label();
5515
5516 if (opc3 & 0x10) {
5517 /* Start with XER OV disabled, the most likely case */
5518 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5519 }
5520 if (opc3 & 0x01) {
5521 /* Signed */
5522 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5523 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5524 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5525 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5526 if (opc3 & 0x02) {
5527 /* Saturate */
5528 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5529 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5530 }
5531 } else {
5532 /* Unsigned */
5533 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5534 if (opc3 & 0x02) {
5535 /* Saturate */
5536 tcg_gen_movi_tl(t0, UINT32_MAX);
5537 }
5538 }
5539 if (opc3 & 0x10) {
5540 /* Check overflow */
5541 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5542 }
5543 gen_set_label(l1);
5544 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5545 }
5546 } else {
5547 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5548 }
5549 tcg_temp_free(t0);
5550 tcg_temp_free(t1);
5551 if (unlikely(Rc) != 0) {
5552 /* Update Rc0 */
5553 gen_set_Rc0(ctx, cpu_gpr[rt]);
5554 }
5555}
5556
5557#define GEN_MAC_HANDLER(name, opc2, opc3) \
5558static void glue(gen_, name)(DisasContext *ctx) \
5559{ \
5560 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5561 rD(ctx->opcode), Rc(ctx->opcode)); \
5562}
5563
5564/* macchw - macchw. */
5565GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5566/* macchwo - macchwo. */
5567GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5568/* macchws - macchws. */
5569GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5570/* macchwso - macchwso. */
5571GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5572/* macchwsu - macchwsu. */
5573GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5574/* macchwsuo - macchwsuo. */
5575GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5576/* macchwu - macchwu. */
5577GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5578/* macchwuo - macchwuo. */
5579GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5580/* machhw - machhw. */
5581GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5582/* machhwo - machhwo. */
5583GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5584/* machhws - machhws. */
5585GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5586/* machhwso - machhwso. */
5587GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5588/* machhwsu - machhwsu. */
5589GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5590/* machhwsuo - machhwsuo. */
5591GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5592/* machhwu - machhwu. */
5593GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5594/* machhwuo - machhwuo. */
5595GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5596/* maclhw - maclhw. */
5597GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5598/* maclhwo - maclhwo. */
5599GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5600/* maclhws - maclhws. */
5601GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5602/* maclhwso - maclhwso. */
5603GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5604/* maclhwu - maclhwu. */
5605GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5606/* maclhwuo - maclhwuo. */
5607GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5608/* maclhwsu - maclhwsu. */
5609GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5610/* maclhwsuo - maclhwsuo. */
5611GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5612/* nmacchw - nmacchw. */
5613GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5614/* nmacchwo - nmacchwo. */
5615GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5616/* nmacchws - nmacchws. */
5617GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5618/* nmacchwso - nmacchwso. */
5619GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5620/* nmachhw - nmachhw. */
5621GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5622/* nmachhwo - nmachhwo. */
5623GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5624/* nmachhws - nmachhws. */
5625GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5626/* nmachhwso - nmachhwso. */
5627GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5628/* nmaclhw - nmaclhw. */
5629GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5630/* nmaclhwo - nmaclhwo. */
5631GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5632/* nmaclhws - nmaclhws. */
5633GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5634/* nmaclhwso - nmaclhwso. */
5635GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5636
5637/* mulchw - mulchw. */
5638GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5639/* mulchwu - mulchwu. */
5640GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5641/* mulhhw - mulhhw. */
5642GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5643/* mulhhwu - mulhhwu. */
5644GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5645/* mullhw - mullhw. */
5646GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5647/* mullhwu - mullhwu. */
5648GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5649
5650/* mfdcr */
5651static void gen_mfdcr(DisasContext *ctx)
5652{
5653#if defined(CONFIG_USER_ONLY)
5654 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5655#else
5656 TCGv dcrn;
5657 if (unlikely(!ctx->mem_idx)) {
5658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5659 return;
5660 }
5661 /* NIP cannot be restored if the memory exception comes from an helper */
5662 gen_update_nip(ctx, ctx->nip - 4);
5663 dcrn = tcg_const_tl(SPR(ctx->opcode));
5664 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5665 tcg_temp_free(dcrn);
5666#endif
5667}
5668
5669/* mtdcr */
5670static void gen_mtdcr(DisasContext *ctx)
5671{
5672#if defined(CONFIG_USER_ONLY)
5673 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5674#else
5675 TCGv dcrn;
5676 if (unlikely(!ctx->mem_idx)) {
5677 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5678 return;
5679 }
5680 /* NIP cannot be restored if the memory exception comes from an helper */
5681 gen_update_nip(ctx, ctx->nip - 4);
5682 dcrn = tcg_const_tl(SPR(ctx->opcode));
5683 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5684 tcg_temp_free(dcrn);
5685#endif
5686}
5687
5688/* mfdcrx */
5689/* XXX: not implemented on 440 ? */
5690static void gen_mfdcrx(DisasContext *ctx)
5691{
5692#if defined(CONFIG_USER_ONLY)
5693 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5694#else
5695 if (unlikely(!ctx->mem_idx)) {
5696 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5697 return;
5698 }
5699 /* NIP cannot be restored if the memory exception comes from an helper */
5700 gen_update_nip(ctx, ctx->nip - 4);
5701 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5702 /* Note: Rc update flag set leads to undefined state of Rc0 */
5703#endif
5704}
5705
5706/* mtdcrx */
5707/* XXX: not implemented on 440 ? */
5708static void gen_mtdcrx(DisasContext *ctx)
5709{
5710#if defined(CONFIG_USER_ONLY)
5711 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5712#else
5713 if (unlikely(!ctx->mem_idx)) {
5714 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5715 return;
5716 }
5717 /* NIP cannot be restored if the memory exception comes from an helper */
5718 gen_update_nip(ctx, ctx->nip - 4);
5719 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5720 /* Note: Rc update flag set leads to undefined state of Rc0 */
5721#endif
5722}
5723
5724/* mfdcrux (PPC 460) : user-mode access to DCR */
5725static void gen_mfdcrux(DisasContext *ctx)
5726{
5727 /* NIP cannot be restored if the memory exception comes from an helper */
5728 gen_update_nip(ctx, ctx->nip - 4);
5729 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5730 /* Note: Rc update flag set leads to undefined state of Rc0 */
5731}
5732
5733/* mtdcrux (PPC 460) : user-mode access to DCR */
5734static void gen_mtdcrux(DisasContext *ctx)
5735{
5736 /* NIP cannot be restored if the memory exception comes from an helper */
5737 gen_update_nip(ctx, ctx->nip - 4);
5738 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5739 /* Note: Rc update flag set leads to undefined state of Rc0 */
5740}
5741
5742/* dccci */
5743static void gen_dccci(DisasContext *ctx)
5744{
5745#if defined(CONFIG_USER_ONLY)
5746 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5747#else
5748 if (unlikely(!ctx->mem_idx)) {
5749 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5750 return;
5751 }
5752 /* interpreted as no-op */
5753#endif
5754}
5755
5756/* dcread */
5757static void gen_dcread(DisasContext *ctx)
5758{
5759#if defined(CONFIG_USER_ONLY)
5760 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5761#else
5762 TCGv EA, val;
5763 if (unlikely(!ctx->mem_idx)) {
5764 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5765 return;
5766 }
5767 gen_set_access_type(ctx, ACCESS_CACHE);
5768 EA = tcg_temp_new();
5769 gen_addr_reg_index(ctx, EA);
5770 val = tcg_temp_new();
5771 gen_qemu_ld32u(ctx, val, EA);
5772 tcg_temp_free(val);
5773 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5774 tcg_temp_free(EA);
5775#endif
5776}
5777
5778/* icbt */
5779static void gen_icbt_40x(DisasContext *ctx)
5780{
5781 /* interpreted as no-op */
5782 /* XXX: specification say this is treated as a load by the MMU
5783 * but does not generate any exception
5784 */
5785}
5786
5787/* iccci */
5788static void gen_iccci(DisasContext *ctx)
5789{
5790#if defined(CONFIG_USER_ONLY)
5791 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5792#else
5793 if (unlikely(!ctx->mem_idx)) {
5794 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5795 return;
5796 }
5797 /* interpreted as no-op */
5798#endif
5799}
5800
5801/* icread */
5802static void gen_icread(DisasContext *ctx)
5803{
5804#if defined(CONFIG_USER_ONLY)
5805 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5806#else
5807 if (unlikely(!ctx->mem_idx)) {
5808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5809 return;
5810 }
5811 /* interpreted as no-op */
5812#endif
5813}
5814
5815/* rfci (mem_idx only) */
5816static void gen_rfci_40x(DisasContext *ctx)
5817{
5818#if defined(CONFIG_USER_ONLY)
5819 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5820#else
5821 if (unlikely(!ctx->mem_idx)) {
5822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5823 return;
5824 }
5825 /* Restore CPU state */
5826 gen_helper_40x_rfci();
5827 gen_sync_exception(ctx);
5828#endif
5829}
5830
5831static void gen_rfci(DisasContext *ctx)
5832{
5833#if defined(CONFIG_USER_ONLY)
5834 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5835#else
5836 if (unlikely(!ctx->mem_idx)) {
5837 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5838 return;
5839 }
5840 /* Restore CPU state */
5841 gen_helper_rfci();
5842 gen_sync_exception(ctx);
5843#endif
5844}
5845
5846/* BookE specific */
5847
5848/* XXX: not implemented on 440 ? */
5849static void gen_rfdi(DisasContext *ctx)
5850{
5851#if defined(CONFIG_USER_ONLY)
5852 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5853#else
5854 if (unlikely(!ctx->mem_idx)) {
5855 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5856 return;
5857 }
5858 /* Restore CPU state */
5859 gen_helper_rfdi();
5860 gen_sync_exception(ctx);
5861#endif
5862}
5863
5864/* XXX: not implemented on 440 ? */
5865static void gen_rfmci(DisasContext *ctx)
5866{
5867#if defined(CONFIG_USER_ONLY)
5868 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5869#else
5870 if (unlikely(!ctx->mem_idx)) {
5871 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5872 return;
5873 }
5874 /* Restore CPU state */
5875 gen_helper_rfmci();
5876 gen_sync_exception(ctx);
5877#endif
5878}
5879
5880/* TLB management - PowerPC 405 implementation */
5881
5882/* tlbre */
5883static void gen_tlbre_40x(DisasContext *ctx)
5884{
5885#if defined(CONFIG_USER_ONLY)
5886 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5887#else
5888 if (unlikely(!ctx->mem_idx)) {
5889 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5890 return;
5891 }
5892 switch (rB(ctx->opcode)) {
5893 case 0:
5894 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5895 break;
5896 case 1:
5897 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5898 break;
5899 default:
5900 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5901 break;
5902 }
5903#endif
5904}
5905
5906/* tlbsx - tlbsx. */
5907static void gen_tlbsx_40x(DisasContext *ctx)
5908{
5909#if defined(CONFIG_USER_ONLY)
5910 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5911#else
5912 TCGv t0;
5913 if (unlikely(!ctx->mem_idx)) {
5914 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5915 return;
5916 }
5917 t0 = tcg_temp_new();
5918 gen_addr_reg_index(ctx, t0);
5919 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5920 tcg_temp_free(t0);
5921 if (Rc(ctx->opcode)) {
5922 int l1 = gen_new_label();
5923 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5924 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5925 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5926 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5927 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5928 gen_set_label(l1);
5929 }
5930#endif
5931}
5932
5933/* tlbwe */
5934static void gen_tlbwe_40x(DisasContext *ctx)
5935{
5936#if defined(CONFIG_USER_ONLY)
5937 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5938#else
5939 if (unlikely(!ctx->mem_idx)) {
5940 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5941 return;
5942 }
5943 switch (rB(ctx->opcode)) {
5944 case 0:
5945 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5946 break;
5947 case 1:
5948 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5949 break;
5950 default:
5951 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5952 break;
5953 }
5954#endif
5955}
5956
5957/* TLB management - PowerPC 440 implementation */
5958
5959/* tlbre */
5960static void gen_tlbre_440(DisasContext *ctx)
5961{
5962#if defined(CONFIG_USER_ONLY)
5963 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5964#else
5965 if (unlikely(!ctx->mem_idx)) {
5966 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5967 return;
5968 }
5969 switch (rB(ctx->opcode)) {
5970 case 0:
5971 case 1:
5972 case 2:
5973 {
5974 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5975 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], t0, cpu_gpr[rA(ctx->opcode)]);
5976 tcg_temp_free_i32(t0);
5977 }
5978 break;
5979 default:
5980 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5981 break;
5982 }
5983#endif
5984}
5985
5986/* tlbsx - tlbsx. */
5987static void gen_tlbsx_440(DisasContext *ctx)
5988{
5989#if defined(CONFIG_USER_ONLY)
5990 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5991#else
5992 TCGv t0;
5993 if (unlikely(!ctx->mem_idx)) {
5994 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5995 return;
5996 }
5997 t0 = tcg_temp_new();
5998 gen_addr_reg_index(ctx, t0);
5999 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
6000 tcg_temp_free(t0);
6001 if (Rc(ctx->opcode)) {
6002 int l1 = gen_new_label();
6003 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
6004 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
6005 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
6006 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6007 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6008 gen_set_label(l1);
6009 }
6010#endif
6011}
6012
6013/* tlbwe */
6014static void gen_tlbwe_440(DisasContext *ctx)
6015{
6016#if defined(CONFIG_USER_ONLY)
6017 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6018#else
6019 if (unlikely(!ctx->mem_idx)) {
6020 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6021 return;
6022 }
6023 switch (rB(ctx->opcode)) {
6024 case 0:
6025 case 1:
6026 case 2:
6027 {
6028 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6029 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6030 tcg_temp_free_i32(t0);
6031 }
6032 break;
6033 default:
6034 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6035 break;
6036 }
6037#endif
6038}
6039
6040/* TLB management - PowerPC BookE 2.06 implementation */
6041
6042/* tlbre */
6043static void gen_tlbre_booke206(DisasContext *ctx)
6044{
6045#if defined(CONFIG_USER_ONLY)
6046 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6047#else
6048 if (unlikely(!ctx->mem_idx)) {
6049 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6050 return;
6051 }
6052
6053 gen_helper_booke206_tlbre();
6054#endif
6055}
6056
6057/* tlbsx - tlbsx. */
6058static void gen_tlbsx_booke206(DisasContext *ctx)
6059{
6060#if defined(CONFIG_USER_ONLY)
6061 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6062#else
6063 TCGv t0;
6064 if (unlikely(!ctx->mem_idx)) {
6065 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6066 return;
6067 }
6068
6069 if (rA(ctx->opcode)) {
6070 t0 = tcg_temp_new();
6071 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6072 } else {
6073 t0 = tcg_const_tl(0);
6074 }
6075
6076 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6077 gen_helper_booke206_tlbsx(t0);
6078#endif
6079}
6080
6081/* tlbwe */
6082static void gen_tlbwe_booke206(DisasContext *ctx)
6083{
6084#if defined(CONFIG_USER_ONLY)
6085 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6086#else
6087 if (unlikely(!ctx->mem_idx)) {
6088 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6089 return;
6090 }
6091 gen_helper_booke206_tlbwe();
6092#endif
6093}
6094
6095static void gen_tlbivax_booke206(DisasContext *ctx)
6096{
6097#if defined(CONFIG_USER_ONLY)
6098 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6099#else
6100 TCGv t0;
6101 if (unlikely(!ctx->mem_idx)) {
6102 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6103 return;
6104 }
6105
6106 t0 = tcg_temp_new();
6107 gen_addr_reg_index(ctx, t0);
6108
6109 gen_helper_booke206_tlbivax(t0);
6110#endif
6111}
6112
6113static void gen_tlbilx_booke206(DisasContext *ctx)
6114{
6115#if defined(CONFIG_USER_ONLY)
6116 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6117#else
6118 TCGv t0;
6119 if (unlikely(!ctx->mem_idx)) {
6120 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6121 return;
6122 }
6123
6124 t0 = tcg_temp_new();
6125 gen_addr_reg_index(ctx, t0);
6126
6127 switch((ctx->opcode >> 21) & 0x3) {
6128 case 0:
6129 gen_helper_booke206_tlbilx0(t0);
6130 break;
6131 case 1:
6132 gen_helper_booke206_tlbilx1(t0);
6133 break;
6134 case 3:
6135 gen_helper_booke206_tlbilx3(t0);
6136 break;
6137 default:
6138 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6139 break;
6140 }
6141
6142 tcg_temp_free(t0);
6143#endif
6144}
6145
6146
6147/* wrtee */
6148static void gen_wrtee(DisasContext *ctx)
6149{
6150#if defined(CONFIG_USER_ONLY)
6151 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6152#else
6153 TCGv t0;
6154 if (unlikely(!ctx->mem_idx)) {
6155 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6156 return;
6157 }
6158 t0 = tcg_temp_new();
6159 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6160 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6161 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6162 tcg_temp_free(t0);
6163 /* Stop translation to have a chance to raise an exception
6164 * if we just set msr_ee to 1
6165 */
6166 gen_stop_exception(ctx);
6167#endif
6168}
6169
6170/* wrteei */
6171static void gen_wrteei(DisasContext *ctx)
6172{
6173#if defined(CONFIG_USER_ONLY)
6174 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6175#else
6176 if (unlikely(!ctx->mem_idx)) {
6177 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6178 return;
6179 }
6180 if (ctx->opcode & 0x00008000) {
6181 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6182 /* Stop translation to have a chance to raise an exception */
6183 gen_stop_exception(ctx);
6184 } else {
6185 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6186 }
6187#endif
6188}
6189
6190/* PowerPC 440 specific instructions */
6191
6192/* dlmzb */
6193static void gen_dlmzb(DisasContext *ctx)
6194{
6195 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6196 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6197 cpu_gpr[rB(ctx->opcode)], t0);
6198 tcg_temp_free_i32(t0);
6199}
6200
6201/* mbar replaces eieio on 440 */
6202static void gen_mbar(DisasContext *ctx)
6203{
6204 /* interpreted as no-op */
6205}
6206
6207/* msync replaces sync on 440 */
6208static void gen_msync_4xx(DisasContext *ctx)
6209{
6210 /* interpreted as no-op */
6211}
6212
6213/* icbt */
6214static void gen_icbt_440(DisasContext *ctx)
6215{
6216 /* interpreted as no-op */
6217 /* XXX: specification say this is treated as a load by the MMU
6218 * but does not generate any exception
6219 */
6220}
6221
6222/*** Altivec vector extension ***/
6223/* Altivec registers moves */
6224
6225static inline TCGv_ptr gen_avr_ptr(int reg)
6226{
6227 TCGv_ptr r = tcg_temp_new_ptr();
6228 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6229 return r;
6230}
6231
6232#define GEN_VR_LDX(name, opc2, opc3) \
6233static void glue(gen_, name)(DisasContext *ctx) \
6234{ \
6235 TCGv EA; \
6236 if (unlikely(!ctx->altivec_enabled)) { \
6237 gen_exception(ctx, POWERPC_EXCP_VPU); \
6238 return; \
6239 } \
6240 gen_set_access_type(ctx, ACCESS_INT); \
6241 EA = tcg_temp_new(); \
6242 gen_addr_reg_index(ctx, EA); \
6243 tcg_gen_andi_tl(EA, EA, ~0xf); \
6244 if (ctx->le_mode) { \
6245 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6246 tcg_gen_addi_tl(EA, EA, 8); \
6247 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6248 } else { \
6249 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6250 tcg_gen_addi_tl(EA, EA, 8); \
6251 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6252 } \
6253 tcg_temp_free(EA); \
6254}
6255
6256#define GEN_VR_STX(name, opc2, opc3) \
6257static void gen_st##name(DisasContext *ctx) \
6258{ \
6259 TCGv EA; \
6260 if (unlikely(!ctx->altivec_enabled)) { \
6261 gen_exception(ctx, POWERPC_EXCP_VPU); \
6262 return; \
6263 } \
6264 gen_set_access_type(ctx, ACCESS_INT); \
6265 EA = tcg_temp_new(); \
6266 gen_addr_reg_index(ctx, EA); \
6267 tcg_gen_andi_tl(EA, EA, ~0xf); \
6268 if (ctx->le_mode) { \
6269 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6270 tcg_gen_addi_tl(EA, EA, 8); \
6271 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6272 } else { \
6273 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6274 tcg_gen_addi_tl(EA, EA, 8); \
6275 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6276 } \
6277 tcg_temp_free(EA); \
6278}
6279
6280#define GEN_VR_LVE(name, opc2, opc3) \
6281static void gen_lve##name(DisasContext *ctx) \
6282 { \
6283 TCGv EA; \
6284 TCGv_ptr rs; \
6285 if (unlikely(!ctx->altivec_enabled)) { \
6286 gen_exception(ctx, POWERPC_EXCP_VPU); \
6287 return; \
6288 } \
6289 gen_set_access_type(ctx, ACCESS_INT); \
6290 EA = tcg_temp_new(); \
6291 gen_addr_reg_index(ctx, EA); \
6292 rs = gen_avr_ptr(rS(ctx->opcode)); \
6293 gen_helper_lve##name (rs, EA); \
6294 tcg_temp_free(EA); \
6295 tcg_temp_free_ptr(rs); \
6296 }
6297
6298#define GEN_VR_STVE(name, opc2, opc3) \
6299static void gen_stve##name(DisasContext *ctx) \
6300 { \
6301 TCGv EA; \
6302 TCGv_ptr rs; \
6303 if (unlikely(!ctx->altivec_enabled)) { \
6304 gen_exception(ctx, POWERPC_EXCP_VPU); \
6305 return; \
6306 } \
6307 gen_set_access_type(ctx, ACCESS_INT); \
6308 EA = tcg_temp_new(); \
6309 gen_addr_reg_index(ctx, EA); \
6310 rs = gen_avr_ptr(rS(ctx->opcode)); \
6311 gen_helper_stve##name (rs, EA); \
6312 tcg_temp_free(EA); \
6313 tcg_temp_free_ptr(rs); \
6314 }
6315
6316GEN_VR_LDX(lvx, 0x07, 0x03);
6317/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6318GEN_VR_LDX(lvxl, 0x07, 0x0B);
6319
6320GEN_VR_LVE(bx, 0x07, 0x00);
6321GEN_VR_LVE(hx, 0x07, 0x01);
6322GEN_VR_LVE(wx, 0x07, 0x02);
6323
6324GEN_VR_STX(svx, 0x07, 0x07);
6325/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6326GEN_VR_STX(svxl, 0x07, 0x0F);
6327
6328GEN_VR_STVE(bx, 0x07, 0x04);
6329GEN_VR_STVE(hx, 0x07, 0x05);
6330GEN_VR_STVE(wx, 0x07, 0x06);
6331
6332static void gen_lvsl(DisasContext *ctx)
6333{
6334 TCGv_ptr rd;
6335 TCGv EA;
6336 if (unlikely(!ctx->altivec_enabled)) {
6337 gen_exception(ctx, POWERPC_EXCP_VPU);
6338 return;
6339 }
6340 EA = tcg_temp_new();
6341 gen_addr_reg_index(ctx, EA);
6342 rd = gen_avr_ptr(rD(ctx->opcode));
6343 gen_helper_lvsl(rd, EA);
6344 tcg_temp_free(EA);
6345 tcg_temp_free_ptr(rd);
6346}
6347
6348static void gen_lvsr(DisasContext *ctx)
6349{
6350 TCGv_ptr rd;
6351 TCGv EA;
6352 if (unlikely(!ctx->altivec_enabled)) {
6353 gen_exception(ctx, POWERPC_EXCP_VPU);
6354 return;
6355 }
6356 EA = tcg_temp_new();
6357 gen_addr_reg_index(ctx, EA);
6358 rd = gen_avr_ptr(rD(ctx->opcode));
6359 gen_helper_lvsr(rd, EA);
6360 tcg_temp_free(EA);
6361 tcg_temp_free_ptr(rd);
6362}
6363
6364static void gen_mfvscr(DisasContext *ctx)
6365{
6366 TCGv_i32 t;
6367 if (unlikely(!ctx->altivec_enabled)) {
6368 gen_exception(ctx, POWERPC_EXCP_VPU);
6369 return;
6370 }
6371 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6372 t = tcg_temp_new_i32();
6373 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6374 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6375 tcg_temp_free_i32(t);
6376}
6377
6378static void gen_mtvscr(DisasContext *ctx)
6379{
6380 TCGv_ptr p;
6381 if (unlikely(!ctx->altivec_enabled)) {
6382 gen_exception(ctx, POWERPC_EXCP_VPU);
6383 return;
6384 }
6385 p = gen_avr_ptr(rD(ctx->opcode));
6386 gen_helper_mtvscr(p);
6387 tcg_temp_free_ptr(p);
6388}
6389
6390/* Logical operations */
6391#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6392static void glue(gen_, name)(DisasContext *ctx) \
6393{ \
6394 if (unlikely(!ctx->altivec_enabled)) { \
6395 gen_exception(ctx, POWERPC_EXCP_VPU); \
6396 return; \
6397 } \
6398 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6399 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6400}
6401
6402GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6403GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6404GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6405GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6406GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6407
6408#define GEN_VXFORM(name, opc2, opc3) \
6409static void glue(gen_, name)(DisasContext *ctx) \
6410{ \
6411 TCGv_ptr ra, rb, rd; \
6412 if (unlikely(!ctx->altivec_enabled)) { \
6413 gen_exception(ctx, POWERPC_EXCP_VPU); \
6414 return; \
6415 } \
6416 ra = gen_avr_ptr(rA(ctx->opcode)); \
6417 rb = gen_avr_ptr(rB(ctx->opcode)); \
6418 rd = gen_avr_ptr(rD(ctx->opcode)); \
6419 gen_helper_##name (rd, ra, rb); \
6420 tcg_temp_free_ptr(ra); \
6421 tcg_temp_free_ptr(rb); \
6422 tcg_temp_free_ptr(rd); \
6423}
6424
6425GEN_VXFORM(vaddubm, 0, 0);
6426GEN_VXFORM(vadduhm, 0, 1);
6427GEN_VXFORM(vadduwm, 0, 2);
6428GEN_VXFORM(vsububm, 0, 16);
6429GEN_VXFORM(vsubuhm, 0, 17);
6430GEN_VXFORM(vsubuwm, 0, 18);
6431GEN_VXFORM(vmaxub, 1, 0);
6432GEN_VXFORM(vmaxuh, 1, 1);
6433GEN_VXFORM(vmaxuw, 1, 2);
6434GEN_VXFORM(vmaxsb, 1, 4);
6435GEN_VXFORM(vmaxsh, 1, 5);
6436GEN_VXFORM(vmaxsw, 1, 6);
6437GEN_VXFORM(vminub, 1, 8);
6438GEN_VXFORM(vminuh, 1, 9);
6439GEN_VXFORM(vminuw, 1, 10);
6440GEN_VXFORM(vminsb, 1, 12);
6441GEN_VXFORM(vminsh, 1, 13);
6442GEN_VXFORM(vminsw, 1, 14);
6443GEN_VXFORM(vavgub, 1, 16);
6444GEN_VXFORM(vavguh, 1, 17);
6445GEN_VXFORM(vavguw, 1, 18);
6446GEN_VXFORM(vavgsb, 1, 20);
6447GEN_VXFORM(vavgsh, 1, 21);
6448GEN_VXFORM(vavgsw, 1, 22);
6449GEN_VXFORM(vmrghb, 6, 0);
6450GEN_VXFORM(vmrghh, 6, 1);
6451GEN_VXFORM(vmrghw, 6, 2);
6452GEN_VXFORM(vmrglb, 6, 4);
6453GEN_VXFORM(vmrglh, 6, 5);
6454GEN_VXFORM(vmrglw, 6, 6);
6455GEN_VXFORM(vmuloub, 4, 0);
6456GEN_VXFORM(vmulouh, 4, 1);
6457GEN_VXFORM(vmulosb, 4, 4);
6458GEN_VXFORM(vmulosh, 4, 5);
6459GEN_VXFORM(vmuleub, 4, 8);
6460GEN_VXFORM(vmuleuh, 4, 9);
6461GEN_VXFORM(vmulesb, 4, 12);
6462GEN_VXFORM(vmulesh, 4, 13);
6463GEN_VXFORM(vslb, 2, 4);
6464GEN_VXFORM(vslh, 2, 5);
6465GEN_VXFORM(vslw, 2, 6);
6466GEN_VXFORM(vsrb, 2, 8);
6467GEN_VXFORM(vsrh, 2, 9);
6468GEN_VXFORM(vsrw, 2, 10);
6469GEN_VXFORM(vsrab, 2, 12);
6470GEN_VXFORM(vsrah, 2, 13);
6471GEN_VXFORM(vsraw, 2, 14);
6472GEN_VXFORM(vslo, 6, 16);
6473GEN_VXFORM(vsro, 6, 17);
6474GEN_VXFORM(vaddcuw, 0, 6);
6475GEN_VXFORM(vsubcuw, 0, 22);
6476GEN_VXFORM(vaddubs, 0, 8);
6477GEN_VXFORM(vadduhs, 0, 9);
6478GEN_VXFORM(vadduws, 0, 10);
6479GEN_VXFORM(vaddsbs, 0, 12);
6480GEN_VXFORM(vaddshs, 0, 13);
6481GEN_VXFORM(vaddsws, 0, 14);
6482GEN_VXFORM(vsububs, 0, 24);
6483GEN_VXFORM(vsubuhs, 0, 25);
6484GEN_VXFORM(vsubuws, 0, 26);
6485GEN_VXFORM(vsubsbs, 0, 28);
6486GEN_VXFORM(vsubshs, 0, 29);
6487GEN_VXFORM(vsubsws, 0, 30);
6488GEN_VXFORM(vrlb, 2, 0);
6489GEN_VXFORM(vrlh, 2, 1);
6490GEN_VXFORM(vrlw, 2, 2);
6491GEN_VXFORM(vsl, 2, 7);
6492GEN_VXFORM(vsr, 2, 11);
6493GEN_VXFORM(vpkuhum, 7, 0);
6494GEN_VXFORM(vpkuwum, 7, 1);
6495GEN_VXFORM(vpkuhus, 7, 2);
6496GEN_VXFORM(vpkuwus, 7, 3);
6497GEN_VXFORM(vpkshus, 7, 4);
6498GEN_VXFORM(vpkswus, 7, 5);
6499GEN_VXFORM(vpkshss, 7, 6);
6500GEN_VXFORM(vpkswss, 7, 7);
6501GEN_VXFORM(vpkpx, 7, 12);
6502GEN_VXFORM(vsum4ubs, 4, 24);
6503GEN_VXFORM(vsum4sbs, 4, 28);
6504GEN_VXFORM(vsum4shs, 4, 25);
6505GEN_VXFORM(vsum2sws, 4, 26);
6506GEN_VXFORM(vsumsws, 4, 30);
6507GEN_VXFORM(vaddfp, 5, 0);
6508GEN_VXFORM(vsubfp, 5, 1);
6509GEN_VXFORM(vmaxfp, 5, 16);
6510GEN_VXFORM(vminfp, 5, 17);
6511
6512#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6513static void glue(gen_, name)(DisasContext *ctx) \
6514 { \
6515 TCGv_ptr ra, rb, rd; \
6516 if (unlikely(!ctx->altivec_enabled)) { \
6517 gen_exception(ctx, POWERPC_EXCP_VPU); \
6518 return; \
6519 } \
6520 ra = gen_avr_ptr(rA(ctx->opcode)); \
6521 rb = gen_avr_ptr(rB(ctx->opcode)); \
6522 rd = gen_avr_ptr(rD(ctx->opcode)); \
6523 gen_helper_##opname (rd, ra, rb); \
6524 tcg_temp_free_ptr(ra); \
6525 tcg_temp_free_ptr(rb); \
6526 tcg_temp_free_ptr(rd); \
6527 }
6528
6529#define GEN_VXRFORM(name, opc2, opc3) \
6530 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6531 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6532
6533GEN_VXRFORM(vcmpequb, 3, 0)
6534GEN_VXRFORM(vcmpequh, 3, 1)
6535GEN_VXRFORM(vcmpequw, 3, 2)
6536GEN_VXRFORM(vcmpgtsb, 3, 12)
6537GEN_VXRFORM(vcmpgtsh, 3, 13)
6538GEN_VXRFORM(vcmpgtsw, 3, 14)
6539GEN_VXRFORM(vcmpgtub, 3, 8)
6540GEN_VXRFORM(vcmpgtuh, 3, 9)
6541GEN_VXRFORM(vcmpgtuw, 3, 10)
6542GEN_VXRFORM(vcmpeqfp, 3, 3)
6543GEN_VXRFORM(vcmpgefp, 3, 7)
6544GEN_VXRFORM(vcmpgtfp, 3, 11)
6545GEN_VXRFORM(vcmpbfp, 3, 15)
6546
6547#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6548static void glue(gen_, name)(DisasContext *ctx) \
6549 { \
6550 TCGv_ptr rd; \
6551 TCGv_i32 simm; \
6552 if (unlikely(!ctx->altivec_enabled)) { \
6553 gen_exception(ctx, POWERPC_EXCP_VPU); \
6554 return; \
6555 } \
6556 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6557 rd = gen_avr_ptr(rD(ctx->opcode)); \
6558 gen_helper_##name (rd, simm); \
6559 tcg_temp_free_i32(simm); \
6560 tcg_temp_free_ptr(rd); \
6561 }
6562
6563GEN_VXFORM_SIMM(vspltisb, 6, 12);
6564GEN_VXFORM_SIMM(vspltish, 6, 13);
6565GEN_VXFORM_SIMM(vspltisw, 6, 14);
6566
6567#define GEN_VXFORM_NOA(name, opc2, opc3) \
6568static void glue(gen_, name)(DisasContext *ctx) \
6569 { \
6570 TCGv_ptr rb, rd; \
6571 if (unlikely(!ctx->altivec_enabled)) { \
6572 gen_exception(ctx, POWERPC_EXCP_VPU); \
6573 return; \
6574 } \
6575 rb = gen_avr_ptr(rB(ctx->opcode)); \
6576 rd = gen_avr_ptr(rD(ctx->opcode)); \
6577 gen_helper_##name (rd, rb); \
6578 tcg_temp_free_ptr(rb); \
6579 tcg_temp_free_ptr(rd); \
6580 }
6581
6582GEN_VXFORM_NOA(vupkhsb, 7, 8);
6583GEN_VXFORM_NOA(vupkhsh, 7, 9);
6584GEN_VXFORM_NOA(vupklsb, 7, 10);
6585GEN_VXFORM_NOA(vupklsh, 7, 11);
6586GEN_VXFORM_NOA(vupkhpx, 7, 13);
6587GEN_VXFORM_NOA(vupklpx, 7, 15);
6588GEN_VXFORM_NOA(vrefp, 5, 4);
6589GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
6590GEN_VXFORM_NOA(vexptefp, 5, 6);
6591GEN_VXFORM_NOA(vlogefp, 5, 7);
6592GEN_VXFORM_NOA(vrfim, 5, 8);
6593GEN_VXFORM_NOA(vrfin, 5, 9);
6594GEN_VXFORM_NOA(vrfip, 5, 10);
6595GEN_VXFORM_NOA(vrfiz, 5, 11);
6596
6597#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6598static void glue(gen_, name)(DisasContext *ctx) \
6599 { \
6600 TCGv_ptr rd; \
6601 TCGv_i32 simm; \
6602 if (unlikely(!ctx->altivec_enabled)) { \
6603 gen_exception(ctx, POWERPC_EXCP_VPU); \
6604 return; \
6605 } \
6606 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6607 rd = gen_avr_ptr(rD(ctx->opcode)); \
6608 gen_helper_##name (rd, simm); \
6609 tcg_temp_free_i32(simm); \
6610 tcg_temp_free_ptr(rd); \
6611 }
6612
6613#define GEN_VXFORM_UIMM(name, opc2, opc3) \
6614static void glue(gen_, name)(DisasContext *ctx) \
6615 { \
6616 TCGv_ptr rb, rd; \
6617 TCGv_i32 uimm; \
6618 if (unlikely(!ctx->altivec_enabled)) { \
6619 gen_exception(ctx, POWERPC_EXCP_VPU); \
6620 return; \
6621 } \
6622 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6623 rb = gen_avr_ptr(rB(ctx->opcode)); \
6624 rd = gen_avr_ptr(rD(ctx->opcode)); \
6625 gen_helper_##name (rd, rb, uimm); \
6626 tcg_temp_free_i32(uimm); \
6627 tcg_temp_free_ptr(rb); \
6628 tcg_temp_free_ptr(rd); \
6629 }
6630
6631GEN_VXFORM_UIMM(vspltb, 6, 8);
6632GEN_VXFORM_UIMM(vsplth, 6, 9);
6633GEN_VXFORM_UIMM(vspltw, 6, 10);
6634GEN_VXFORM_UIMM(vcfux, 5, 12);
6635GEN_VXFORM_UIMM(vcfsx, 5, 13);
6636GEN_VXFORM_UIMM(vctuxs, 5, 14);
6637GEN_VXFORM_UIMM(vctsxs, 5, 15);
6638
6639static void gen_vsldoi(DisasContext *ctx)
6640{
6641 TCGv_ptr ra, rb, rd;
6642 TCGv_i32 sh;
6643 if (unlikely(!ctx->altivec_enabled)) {
6644 gen_exception(ctx, POWERPC_EXCP_VPU);
6645 return;
6646 }
6647 ra = gen_avr_ptr(rA(ctx->opcode));
6648 rb = gen_avr_ptr(rB(ctx->opcode));
6649 rd = gen_avr_ptr(rD(ctx->opcode));
6650 sh = tcg_const_i32(VSH(ctx->opcode));
6651 gen_helper_vsldoi (rd, ra, rb, sh);
6652 tcg_temp_free_ptr(ra);
6653 tcg_temp_free_ptr(rb);
6654 tcg_temp_free_ptr(rd);
6655 tcg_temp_free_i32(sh);
6656}
6657
6658#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6659static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6660 { \
6661 TCGv_ptr ra, rb, rc, rd; \
6662 if (unlikely(!ctx->altivec_enabled)) { \
6663 gen_exception(ctx, POWERPC_EXCP_VPU); \
6664 return; \
6665 } \
6666 ra = gen_avr_ptr(rA(ctx->opcode)); \
6667 rb = gen_avr_ptr(rB(ctx->opcode)); \
6668 rc = gen_avr_ptr(rC(ctx->opcode)); \
6669 rd = gen_avr_ptr(rD(ctx->opcode)); \
6670 if (Rc(ctx->opcode)) { \
6671 gen_helper_##name1 (rd, ra, rb, rc); \
6672 } else { \
6673 gen_helper_##name0 (rd, ra, rb, rc); \
6674 } \
6675 tcg_temp_free_ptr(ra); \
6676 tcg_temp_free_ptr(rb); \
6677 tcg_temp_free_ptr(rc); \
6678 tcg_temp_free_ptr(rd); \
6679 }
6680
6681GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6682
6683static void gen_vmladduhm(DisasContext *ctx)
6684{
6685 TCGv_ptr ra, rb, rc, rd;
6686 if (unlikely(!ctx->altivec_enabled)) {
6687 gen_exception(ctx, POWERPC_EXCP_VPU);
6688 return;
6689 }
6690 ra = gen_avr_ptr(rA(ctx->opcode));
6691 rb = gen_avr_ptr(rB(ctx->opcode));
6692 rc = gen_avr_ptr(rC(ctx->opcode));
6693 rd = gen_avr_ptr(rD(ctx->opcode));
6694 gen_helper_vmladduhm(rd, ra, rb, rc);
6695 tcg_temp_free_ptr(ra);
6696 tcg_temp_free_ptr(rb);
6697 tcg_temp_free_ptr(rc);
6698 tcg_temp_free_ptr(rd);
6699}
6700
6701GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6702GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6703GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6704GEN_VAFORM_PAIRED(vsel, vperm, 21)
6705GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6706
6707/*** SPE extension ***/
6708/* Register moves */
6709
6710
6711static inline void gen_evmra(DisasContext *ctx)
6712{
6713
6714 if (unlikely(!ctx->spe_enabled)) {
6715 gen_exception(ctx, POWERPC_EXCP_SPEU);
6716 return;
6717 }
6718
6719#if defined(TARGET_PPC64)
6720 /* rD := rA */
6721 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6722
6723 /* spe_acc := rA */
6724 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6725 cpu_env,
6726 offsetof(CPUState, spe_acc));
6727#else
6728 TCGv_i64 tmp = tcg_temp_new_i64();
6729
6730 /* tmp := rA_lo + rA_hi << 32 */
6731 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6732
6733 /* spe_acc := tmp */
6734 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc));
6735 tcg_temp_free_i64(tmp);
6736
6737 /* rD := rA */
6738 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6739 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6740#endif
6741}
6742
6743static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6744{
6745#if defined(TARGET_PPC64)
6746 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6747#else
6748 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6749#endif
6750}
6751
6752static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6753{
6754#if defined(TARGET_PPC64)
6755 tcg_gen_mov_i64(cpu_gpr[reg], t);
6756#else
6757 TCGv_i64 tmp = tcg_temp_new_i64();
6758 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6759 tcg_gen_shri_i64(tmp, t, 32);
6760 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6761 tcg_temp_free_i64(tmp);
6762#endif
6763}
6764
6765#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6766static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6767{ \
6768 if (Rc(ctx->opcode)) \
6769 gen_##name1(ctx); \
6770 else \
6771 gen_##name0(ctx); \
6772}
6773
6774/* Handler for undefined SPE opcodes */
6775static inline void gen_speundef(DisasContext *ctx)
6776{
6777 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6778}
6779
6780/* SPE logic */
6781#if defined(TARGET_PPC64)
6782#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6783static inline void gen_##name(DisasContext *ctx) \
6784{ \
6785 if (unlikely(!ctx->spe_enabled)) { \
6786 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6787 return; \
6788 } \
6789 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6790 cpu_gpr[rB(ctx->opcode)]); \
6791}
6792#else
6793#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6794static inline void gen_##name(DisasContext *ctx) \
6795{ \
6796 if (unlikely(!ctx->spe_enabled)) { \
6797 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6798 return; \
6799 } \
6800 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6801 cpu_gpr[rB(ctx->opcode)]); \
6802 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6803 cpu_gprh[rB(ctx->opcode)]); \
6804}
6805#endif
6806
6807GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6808GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6809GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6810GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6811GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6812GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6813GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6814GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6815
6816/* SPE logic immediate */
6817#if defined(TARGET_PPC64)
6818#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6819static inline void gen_##name(DisasContext *ctx) \
6820{ \
6821 if (unlikely(!ctx->spe_enabled)) { \
6822 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6823 return; \
6824 } \
6825 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6826 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6827 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6828 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6829 tcg_opi(t0, t0, rB(ctx->opcode)); \
6830 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6831 tcg_gen_trunc_i64_i32(t1, t2); \
6832 tcg_temp_free_i64(t2); \
6833 tcg_opi(t1, t1, rB(ctx->opcode)); \
6834 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6835 tcg_temp_free_i32(t0); \
6836 tcg_temp_free_i32(t1); \
6837}
6838#else
6839#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6840static inline void gen_##name(DisasContext *ctx) \
6841{ \
6842 if (unlikely(!ctx->spe_enabled)) { \
6843 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6844 return; \
6845 } \
6846 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6847 rB(ctx->opcode)); \
6848 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6849 rB(ctx->opcode)); \
6850}
6851#endif
6852GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6853GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6854GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6855GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6856
6857/* SPE arithmetic */
6858#if defined(TARGET_PPC64)
6859#define GEN_SPEOP_ARITH1(name, tcg_op) \
6860static inline void gen_##name(DisasContext *ctx) \
6861{ \
6862 if (unlikely(!ctx->spe_enabled)) { \
6863 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6864 return; \
6865 } \
6866 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6867 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6868 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6869 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6870 tcg_op(t0, t0); \
6871 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6872 tcg_gen_trunc_i64_i32(t1, t2); \
6873 tcg_temp_free_i64(t2); \
6874 tcg_op(t1, t1); \
6875 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6876 tcg_temp_free_i32(t0); \
6877 tcg_temp_free_i32(t1); \
6878}
6879#else
6880#define GEN_SPEOP_ARITH1(name, tcg_op) \
6881static inline void gen_##name(DisasContext *ctx) \
6882{ \
6883 if (unlikely(!ctx->spe_enabled)) { \
6884 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6885 return; \
6886 } \
6887 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6888 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6889}
6890#endif
6891
6892static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
6893{
6894 int l1 = gen_new_label();
6895 int l2 = gen_new_label();
6896
6897 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6898 tcg_gen_neg_i32(ret, arg1);
6899 tcg_gen_br(l2);
6900 gen_set_label(l1);
6901 tcg_gen_mov_i32(ret, arg1);
6902 gen_set_label(l2);
6903}
6904GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6905GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6906GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6907GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6908static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
6909{
6910 tcg_gen_addi_i32(ret, arg1, 0x8000);
6911 tcg_gen_ext16u_i32(ret, ret);
6912}
6913GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6914GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6915GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6916
6917#if defined(TARGET_PPC64)
6918#define GEN_SPEOP_ARITH2(name, tcg_op) \
6919static inline void gen_##name(DisasContext *ctx) \
6920{ \
6921 if (unlikely(!ctx->spe_enabled)) { \
6922 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6923 return; \
6924 } \
6925 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6926 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6927 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6928 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6929 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6930 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6931 tcg_op(t0, t0, t2); \
6932 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6933 tcg_gen_trunc_i64_i32(t1, t3); \
6934 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6935 tcg_gen_trunc_i64_i32(t2, t3); \
6936 tcg_temp_free_i64(t3); \
6937 tcg_op(t1, t1, t2); \
6938 tcg_temp_free_i32(t2); \
6939 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6940 tcg_temp_free_i32(t0); \
6941 tcg_temp_free_i32(t1); \
6942}
6943#else
6944#define GEN_SPEOP_ARITH2(name, tcg_op) \
6945static inline void gen_##name(DisasContext *ctx) \
6946{ \
6947 if (unlikely(!ctx->spe_enabled)) { \
6948 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6949 return; \
6950 } \
6951 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6952 cpu_gpr[rB(ctx->opcode)]); \
6953 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6954 cpu_gprh[rB(ctx->opcode)]); \
6955}
6956#endif
6957
6958static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6959{
6960 TCGv_i32 t0;
6961 int l1, l2;
6962
6963 l1 = gen_new_label();
6964 l2 = gen_new_label();
6965 t0 = tcg_temp_local_new_i32();
6966 /* No error here: 6 bits are used */
6967 tcg_gen_andi_i32(t0, arg2, 0x3F);
6968 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6969 tcg_gen_shr_i32(ret, arg1, t0);
6970 tcg_gen_br(l2);
6971 gen_set_label(l1);
6972 tcg_gen_movi_i32(ret, 0);
6973 gen_set_label(l2);
6974 tcg_temp_free_i32(t0);
6975}
6976GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
6977static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6978{
6979 TCGv_i32 t0;
6980 int l1, l2;
6981
6982 l1 = gen_new_label();
6983 l2 = gen_new_label();
6984 t0 = tcg_temp_local_new_i32();
6985 /* No error here: 6 bits are used */
6986 tcg_gen_andi_i32(t0, arg2, 0x3F);
6987 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6988 tcg_gen_sar_i32(ret, arg1, t0);
6989 tcg_gen_br(l2);
6990 gen_set_label(l1);
6991 tcg_gen_movi_i32(ret, 0);
6992 gen_set_label(l2);
6993 tcg_temp_free_i32(t0);
6994}
6995GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
6996static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6997{
6998 TCGv_i32 t0;
6999 int l1, l2;
7000
7001 l1 = gen_new_label();
7002 l2 = gen_new_label();
7003 t0 = tcg_temp_local_new_i32();
7004 /* No error here: 6 bits are used */
7005 tcg_gen_andi_i32(t0, arg2, 0x3F);
7006 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7007 tcg_gen_shl_i32(ret, arg1, t0);
7008 tcg_gen_br(l2);
7009 gen_set_label(l1);
7010 tcg_gen_movi_i32(ret, 0);
7011 gen_set_label(l2);
7012 tcg_temp_free_i32(t0);
7013}
7014GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7015static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7016{
7017 TCGv_i32 t0 = tcg_temp_new_i32();
7018 tcg_gen_andi_i32(t0, arg2, 0x1F);
7019 tcg_gen_rotl_i32(ret, arg1, t0);
7020 tcg_temp_free_i32(t0);
7021}
7022GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7023static inline void gen_evmergehi(DisasContext *ctx)
7024{
7025 if (unlikely(!ctx->spe_enabled)) {
7026 gen_exception(ctx, POWERPC_EXCP_SPEU);
7027 return;
7028 }
7029#if defined(TARGET_PPC64)
7030 TCGv t0 = tcg_temp_new();
7031 TCGv t1 = tcg_temp_new();
7032 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7033 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7034 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7035 tcg_temp_free(t0);
7036 tcg_temp_free(t1);
7037#else
7038 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7039 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7040#endif
7041}
7042GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7043static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7044{
7045 tcg_gen_sub_i32(ret, arg2, arg1);
7046}
7047GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7048
7049/* SPE arithmetic immediate */
7050#if defined(TARGET_PPC64)
7051#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7052static inline void gen_##name(DisasContext *ctx) \
7053{ \
7054 if (unlikely(!ctx->spe_enabled)) { \
7055 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7056 return; \
7057 } \
7058 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7059 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7060 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7061 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7062 tcg_op(t0, t0, rA(ctx->opcode)); \
7063 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7064 tcg_gen_trunc_i64_i32(t1, t2); \
7065 tcg_temp_free_i64(t2); \
7066 tcg_op(t1, t1, rA(ctx->opcode)); \
7067 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7068 tcg_temp_free_i32(t0); \
7069 tcg_temp_free_i32(t1); \
7070}
7071#else
7072#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7073static inline void gen_##name(DisasContext *ctx) \
7074{ \
7075 if (unlikely(!ctx->spe_enabled)) { \
7076 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7077 return; \
7078 } \
7079 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7080 rA(ctx->opcode)); \
7081 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7082 rA(ctx->opcode)); \
7083}
7084#endif
7085GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7086GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7087
7088/* SPE comparison */
7089#if defined(TARGET_PPC64)
7090#define GEN_SPEOP_COMP(name, tcg_cond) \
7091static inline void gen_##name(DisasContext *ctx) \
7092{ \
7093 if (unlikely(!ctx->spe_enabled)) { \
7094 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7095 return; \
7096 } \
7097 int l1 = gen_new_label(); \
7098 int l2 = gen_new_label(); \
7099 int l3 = gen_new_label(); \
7100 int l4 = gen_new_label(); \
7101 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7102 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7103 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7104 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7105 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7106 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7107 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7108 tcg_gen_br(l2); \
7109 gen_set_label(l1); \
7110 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7111 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7112 gen_set_label(l2); \
7113 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7114 tcg_gen_trunc_i64_i32(t0, t2); \
7115 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7116 tcg_gen_trunc_i64_i32(t1, t2); \
7117 tcg_temp_free_i64(t2); \
7118 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7119 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7120 ~(CRF_CH | CRF_CH_AND_CL)); \
7121 tcg_gen_br(l4); \
7122 gen_set_label(l3); \
7123 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7124 CRF_CH | CRF_CH_OR_CL); \
7125 gen_set_label(l4); \
7126 tcg_temp_free_i32(t0); \
7127 tcg_temp_free_i32(t1); \
7128}
7129#else
7130#define GEN_SPEOP_COMP(name, tcg_cond) \
7131static inline void gen_##name(DisasContext *ctx) \
7132{ \
7133 if (unlikely(!ctx->spe_enabled)) { \
7134 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7135 return; \
7136 } \
7137 int l1 = gen_new_label(); \
7138 int l2 = gen_new_label(); \
7139 int l3 = gen_new_label(); \
7140 int l4 = gen_new_label(); \
7141 \
7142 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7143 cpu_gpr[rB(ctx->opcode)], l1); \
7144 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7145 tcg_gen_br(l2); \
7146 gen_set_label(l1); \
7147 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7148 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7149 gen_set_label(l2); \
7150 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7151 cpu_gprh[rB(ctx->opcode)], l3); \
7152 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7153 ~(CRF_CH | CRF_CH_AND_CL)); \
7154 tcg_gen_br(l4); \
7155 gen_set_label(l3); \
7156 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7157 CRF_CH | CRF_CH_OR_CL); \
7158 gen_set_label(l4); \
7159}
7160#endif
7161GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7162GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7163GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7164GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7165GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7166
7167/* SPE misc */
7168static inline void gen_brinc(DisasContext *ctx)
7169{
7170 /* Note: brinc is usable even if SPE is disabled */
7171 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7172 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7173}
7174static inline void gen_evmergelo(DisasContext *ctx)
7175{
7176 if (unlikely(!ctx->spe_enabled)) {
7177 gen_exception(ctx, POWERPC_EXCP_SPEU);
7178 return;
7179 }
7180#if defined(TARGET_PPC64)
7181 TCGv t0 = tcg_temp_new();
7182 TCGv t1 = tcg_temp_new();
7183 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7184 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7185 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7186 tcg_temp_free(t0);
7187 tcg_temp_free(t1);
7188#else
7189 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7190 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7191#endif
7192}
7193static inline void gen_evmergehilo(DisasContext *ctx)
7194{
7195 if (unlikely(!ctx->spe_enabled)) {
7196 gen_exception(ctx, POWERPC_EXCP_SPEU);
7197 return;
7198 }
7199#if defined(TARGET_PPC64)
7200 TCGv t0 = tcg_temp_new();
7201 TCGv t1 = tcg_temp_new();
7202 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7203 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7204 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7205 tcg_temp_free(t0);
7206 tcg_temp_free(t1);
7207#else
7208 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7209 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7210#endif
7211}
7212static inline void gen_evmergelohi(DisasContext *ctx)
7213{
7214 if (unlikely(!ctx->spe_enabled)) {
7215 gen_exception(ctx, POWERPC_EXCP_SPEU);
7216 return;
7217 }
7218#if defined(TARGET_PPC64)
7219 TCGv t0 = tcg_temp_new();
7220 TCGv t1 = tcg_temp_new();
7221 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7222 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7223 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7224 tcg_temp_free(t0);
7225 tcg_temp_free(t1);
7226#else
7227 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7228 TCGv_i32 tmp = tcg_temp_new_i32();
7229 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7230 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7231 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7232 tcg_temp_free_i32(tmp);
7233 } else {
7234 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7235 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7236 }
7237#endif
7238}
7239static inline void gen_evsplati(DisasContext *ctx)
7240{
7241 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7242
7243#if defined(TARGET_PPC64)
7244 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7245#else
7246 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7247 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7248#endif
7249}
7250static inline void gen_evsplatfi(DisasContext *ctx)
7251{
7252 uint64_t imm = rA(ctx->opcode) << 27;
7253
7254#if defined(TARGET_PPC64)
7255 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7256#else
7257 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7258 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7259#endif
7260}
7261
7262static inline void gen_evsel(DisasContext *ctx)
7263{
7264 int l1 = gen_new_label();
7265 int l2 = gen_new_label();
7266 int l3 = gen_new_label();
7267 int l4 = gen_new_label();
7268 TCGv_i32 t0 = tcg_temp_local_new_i32();
7269#if defined(TARGET_PPC64)
7270 TCGv t1 = tcg_temp_local_new();
7271 TCGv t2 = tcg_temp_local_new();
7272#endif
7273 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7274 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7275#if defined(TARGET_PPC64)
7276 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7277#else
7278 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7279#endif
7280 tcg_gen_br(l2);
7281 gen_set_label(l1);
7282#if defined(TARGET_PPC64)
7283 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7284#else
7285 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7286#endif
7287 gen_set_label(l2);
7288 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7289 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7290#if defined(TARGET_PPC64)
7291 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7292#else
7293 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7294#endif
7295 tcg_gen_br(l4);
7296 gen_set_label(l3);
7297#if defined(TARGET_PPC64)
7298 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7299#else
7300 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7301#endif
7302 gen_set_label(l4);
7303 tcg_temp_free_i32(t0);
7304#if defined(TARGET_PPC64)
7305 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7306 tcg_temp_free(t1);
7307 tcg_temp_free(t2);
7308#endif
7309}
7310
7311static void gen_evsel0(DisasContext *ctx)
7312{
7313 gen_evsel(ctx);
7314}
7315
7316static void gen_evsel1(DisasContext *ctx)
7317{
7318 gen_evsel(ctx);
7319}
7320
7321static void gen_evsel2(DisasContext *ctx)
7322{
7323 gen_evsel(ctx);
7324}
7325
7326static void gen_evsel3(DisasContext *ctx)
7327{
7328 gen_evsel(ctx);
7329}
7330
7331/* Multiply */
7332
7333static inline void gen_evmwumi(DisasContext *ctx)
7334{
7335 TCGv_i64 t0, t1;
7336
7337 if (unlikely(!ctx->spe_enabled)) {
7338 gen_exception(ctx, POWERPC_EXCP_SPEU);
7339 return;
7340 }
7341
7342 t0 = tcg_temp_new_i64();
7343 t1 = tcg_temp_new_i64();
7344
7345 /* t0 := rA; t1 := rB */
7346#if defined(TARGET_PPC64)
7347 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7348 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7349#else
7350 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7351 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7352#endif
7353
7354 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7355
7356 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7357
7358 tcg_temp_free_i64(t0);
7359 tcg_temp_free_i64(t1);
7360}
7361
7362static inline void gen_evmwumia(DisasContext *ctx)
7363{
7364 TCGv_i64 tmp;
7365
7366 if (unlikely(!ctx->spe_enabled)) {
7367 gen_exception(ctx, POWERPC_EXCP_SPEU);
7368 return;
7369 }
7370
7371 gen_evmwumi(ctx); /* rD := rA * rB */
7372
7373 tmp = tcg_temp_new_i64();
7374
7375 /* acc := rD */
7376 gen_load_gpr64(tmp, rD(ctx->opcode));
7377 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc));
7378 tcg_temp_free_i64(tmp);
7379}
7380
7381static inline void gen_evmwumiaa(DisasContext *ctx)
7382{
7383 TCGv_i64 acc;
7384 TCGv_i64 tmp;
7385
7386 if (unlikely(!ctx->spe_enabled)) {
7387 gen_exception(ctx, POWERPC_EXCP_SPEU);
7388 return;
7389 }
7390
7391 gen_evmwumi(ctx); /* rD := rA * rB */
7392
7393 acc = tcg_temp_new_i64();
7394 tmp = tcg_temp_new_i64();
7395
7396 /* tmp := rD */
7397 gen_load_gpr64(tmp, rD(ctx->opcode));
7398
7399 /* Load acc */
7400 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
7401
7402 /* acc := tmp + acc */
7403 tcg_gen_add_i64(acc, acc, tmp);
7404
7405 /* Store acc */
7406 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
7407
7408 /* rD := acc */
7409 gen_store_gpr64(rD(ctx->opcode), acc);
7410
7411 tcg_temp_free_i64(acc);
7412 tcg_temp_free_i64(tmp);
7413}
7414
7415static inline void gen_evmwsmi(DisasContext *ctx)
7416{
7417 TCGv_i64 t0, t1;
7418
7419 if (unlikely(!ctx->spe_enabled)) {
7420 gen_exception(ctx, POWERPC_EXCP_SPEU);
7421 return;
7422 }
7423
7424 t0 = tcg_temp_new_i64();
7425 t1 = tcg_temp_new_i64();
7426
7427 /* t0 := rA; t1 := rB */
7428#if defined(TARGET_PPC64)
7429 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7430 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7431#else
7432 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7433 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7434#endif
7435
7436 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7437
7438 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7439
7440 tcg_temp_free_i64(t0);
7441 tcg_temp_free_i64(t1);
7442}
7443
7444static inline void gen_evmwsmia(DisasContext *ctx)
7445{
7446 TCGv_i64 tmp;
7447
7448 gen_evmwsmi(ctx); /* rD := rA * rB */
7449
7450 tmp = tcg_temp_new_i64();
7451
7452 /* acc := rD */
7453 gen_load_gpr64(tmp, rD(ctx->opcode));
7454 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc));
7455
7456 tcg_temp_free_i64(tmp);
7457}
7458
7459static inline void gen_evmwsmiaa(DisasContext *ctx)
7460{
7461 TCGv_i64 acc = tcg_temp_new_i64();
7462 TCGv_i64 tmp = tcg_temp_new_i64();
7463
7464 gen_evmwsmi(ctx); /* rD := rA * rB */
7465
7466 acc = tcg_temp_new_i64();
7467 tmp = tcg_temp_new_i64();
7468
7469 /* tmp := rD */
7470 gen_load_gpr64(tmp, rD(ctx->opcode));
7471
7472 /* Load acc */
7473 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
7474
7475 /* acc := tmp + acc */
7476 tcg_gen_add_i64(acc, acc, tmp);
7477
7478 /* Store acc */
7479 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
7480
7481 /* rD := acc */
7482 gen_store_gpr64(rD(ctx->opcode), acc);
7483
7484 tcg_temp_free_i64(acc);
7485 tcg_temp_free_i64(tmp);
7486}
7487
7488GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7489GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7490GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7491GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7492GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7493GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7494GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7495GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7496GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7497GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7498GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7499GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7500GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7501GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7502GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7503GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7504GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7505GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7506GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7507GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7508GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7509GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7510GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7511GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7512GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7513GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7514GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7515GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7516GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7517
7518/* SPE load and stores */
7519static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7520{
7521 target_ulong uimm = rB(ctx->opcode);
7522
7523 if (rA(ctx->opcode) == 0) {
7524 tcg_gen_movi_tl(EA, uimm << sh);
7525 } else {
7526 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7527#if defined(TARGET_PPC64)
7528 if (!ctx->sf_mode) {
7529 tcg_gen_ext32u_tl(EA, EA);
7530 }
7531#endif
7532 }
7533}
7534
7535static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7536{
7537#if defined(TARGET_PPC64)
7538 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7539#else
7540 TCGv_i64 t0 = tcg_temp_new_i64();
7541 gen_qemu_ld64(ctx, t0, addr);
7542 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7543 tcg_gen_shri_i64(t0, t0, 32);
7544 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7545 tcg_temp_free_i64(t0);
7546#endif
7547}
7548
7549static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7550{
7551#if defined(TARGET_PPC64)
7552 TCGv t0 = tcg_temp_new();
7553 gen_qemu_ld32u(ctx, t0, addr);
7554 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7555 gen_addr_add(ctx, addr, addr, 4);
7556 gen_qemu_ld32u(ctx, t0, addr);
7557 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7558 tcg_temp_free(t0);
7559#else
7560 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7561 gen_addr_add(ctx, addr, addr, 4);
7562 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7563#endif
7564}
7565
7566static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7567{
7568 TCGv t0 = tcg_temp_new();
7569#if defined(TARGET_PPC64)
7570 gen_qemu_ld16u(ctx, t0, addr);
7571 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7572 gen_addr_add(ctx, addr, addr, 2);
7573 gen_qemu_ld16u(ctx, t0, addr);
7574 tcg_gen_shli_tl(t0, t0, 32);
7575 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7576 gen_addr_add(ctx, addr, addr, 2);
7577 gen_qemu_ld16u(ctx, t0, addr);
7578 tcg_gen_shli_tl(t0, t0, 16);
7579 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7580 gen_addr_add(ctx, addr, addr, 2);
7581 gen_qemu_ld16u(ctx, t0, addr);
7582 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7583#else
7584 gen_qemu_ld16u(ctx, t0, addr);
7585 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7586 gen_addr_add(ctx, addr, addr, 2);
7587 gen_qemu_ld16u(ctx, t0, addr);
7588 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7589 gen_addr_add(ctx, addr, addr, 2);
7590 gen_qemu_ld16u(ctx, t0, addr);
7591 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7592 gen_addr_add(ctx, addr, addr, 2);
7593 gen_qemu_ld16u(ctx, t0, addr);
7594 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7595#endif
7596 tcg_temp_free(t0);
7597}
7598
7599static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7600{
7601 TCGv t0 = tcg_temp_new();
7602 gen_qemu_ld16u(ctx, t0, addr);
7603#if defined(TARGET_PPC64)
7604 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7605 tcg_gen_shli_tl(t0, t0, 16);
7606 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7607#else
7608 tcg_gen_shli_tl(t0, t0, 16);
7609 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7610 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7611#endif
7612 tcg_temp_free(t0);
7613}
7614
7615static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7616{
7617 TCGv t0 = tcg_temp_new();
7618 gen_qemu_ld16u(ctx, t0, addr);
7619#if defined(TARGET_PPC64)
7620 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7621 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7622#else
7623 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7624 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7625#endif
7626 tcg_temp_free(t0);
7627}
7628
7629static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7630{
7631 TCGv t0 = tcg_temp_new();
7632 gen_qemu_ld16s(ctx, t0, addr);
7633#if defined(TARGET_PPC64)
7634 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7635 tcg_gen_ext32u_tl(t0, t0);
7636 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7637#else
7638 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7639 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7640#endif
7641 tcg_temp_free(t0);
7642}
7643
7644static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7645{
7646 TCGv t0 = tcg_temp_new();
7647#if defined(TARGET_PPC64)
7648 gen_qemu_ld16u(ctx, t0, addr);
7649 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7650 gen_addr_add(ctx, addr, addr, 2);
7651 gen_qemu_ld16u(ctx, t0, addr);
7652 tcg_gen_shli_tl(t0, t0, 16);
7653 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7654#else
7655 gen_qemu_ld16u(ctx, t0, addr);
7656 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7657 gen_addr_add(ctx, addr, addr, 2);
7658 gen_qemu_ld16u(ctx, t0, addr);
7659 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7660#endif
7661 tcg_temp_free(t0);
7662}
7663
7664static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7665{
7666#if defined(TARGET_PPC64)
7667 TCGv t0 = tcg_temp_new();
7668 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7669 gen_addr_add(ctx, addr, addr, 2);
7670 gen_qemu_ld16u(ctx, t0, addr);
7671 tcg_gen_shli_tl(t0, t0, 32);
7672 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7673 tcg_temp_free(t0);
7674#else
7675 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7676 gen_addr_add(ctx, addr, addr, 2);
7677 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7678#endif
7679}
7680
7681static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7682{
7683#if defined(TARGET_PPC64)
7684 TCGv t0 = tcg_temp_new();
7685 gen_qemu_ld16s(ctx, t0, addr);
7686 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7687 gen_addr_add(ctx, addr, addr, 2);
7688 gen_qemu_ld16s(ctx, t0, addr);
7689 tcg_gen_shli_tl(t0, t0, 32);
7690 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7691 tcg_temp_free(t0);
7692#else
7693 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7694 gen_addr_add(ctx, addr, addr, 2);
7695 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7696#endif
7697}
7698
7699static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7700{
7701 TCGv t0 = tcg_temp_new();
7702 gen_qemu_ld32u(ctx, t0, addr);
7703#if defined(TARGET_PPC64)
7704 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7705 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7706#else
7707 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7708 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7709#endif
7710 tcg_temp_free(t0);
7711}
7712
7713static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7714{
7715 TCGv t0 = tcg_temp_new();
7716#if defined(TARGET_PPC64)
7717 gen_qemu_ld16u(ctx, t0, addr);
7718 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7719 tcg_gen_shli_tl(t0, t0, 32);
7720 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7721 gen_addr_add(ctx, addr, addr, 2);
7722 gen_qemu_ld16u(ctx, t0, addr);
7723 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7724 tcg_gen_shli_tl(t0, t0, 16);
7725 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7726#else
7727 gen_qemu_ld16u(ctx, t0, addr);
7728 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7729 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7730 gen_addr_add(ctx, addr, addr, 2);
7731 gen_qemu_ld16u(ctx, t0, addr);
7732 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7733 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7734#endif
7735 tcg_temp_free(t0);
7736}
7737
7738static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7739{
7740#if defined(TARGET_PPC64)
7741 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7742#else
7743 TCGv_i64 t0 = tcg_temp_new_i64();
7744 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7745 gen_qemu_st64(ctx, t0, addr);
7746 tcg_temp_free_i64(t0);
7747#endif
7748}
7749
7750static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7751{
7752#if defined(TARGET_PPC64)
7753 TCGv t0 = tcg_temp_new();
7754 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7755 gen_qemu_st32(ctx, t0, addr);
7756 tcg_temp_free(t0);
7757#else
7758 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7759#endif
7760 gen_addr_add(ctx, addr, addr, 4);
7761 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7762}
7763
7764static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7765{
7766 TCGv t0 = tcg_temp_new();
7767#if defined(TARGET_PPC64)
7768 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7769#else
7770 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7771#endif
7772 gen_qemu_st16(ctx, t0, addr);
7773 gen_addr_add(ctx, addr, addr, 2);
7774#if defined(TARGET_PPC64)
7775 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7776 gen_qemu_st16(ctx, t0, addr);
7777#else
7778 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7779#endif
7780 gen_addr_add(ctx, addr, addr, 2);
7781 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7782 gen_qemu_st16(ctx, t0, addr);
7783 tcg_temp_free(t0);
7784 gen_addr_add(ctx, addr, addr, 2);
7785 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7786}
7787
7788static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7789{
7790 TCGv t0 = tcg_temp_new();
7791#if defined(TARGET_PPC64)
7792 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7793#else
7794 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7795#endif
7796 gen_qemu_st16(ctx, t0, addr);
7797 gen_addr_add(ctx, addr, addr, 2);
7798 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7799 gen_qemu_st16(ctx, t0, addr);
7800 tcg_temp_free(t0);
7801}
7802
7803static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7804{
7805#if defined(TARGET_PPC64)
7806 TCGv t0 = tcg_temp_new();
7807 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7808 gen_qemu_st16(ctx, t0, addr);
7809 tcg_temp_free(t0);
7810#else
7811 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7812#endif
7813 gen_addr_add(ctx, addr, addr, 2);
7814 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7815}
7816
7817static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7818{
7819#if defined(TARGET_PPC64)
7820 TCGv t0 = tcg_temp_new();
7821 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7822 gen_qemu_st32(ctx, t0, addr);
7823 tcg_temp_free(t0);
7824#else
7825 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7826#endif
7827}
7828
7829static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7830{
7831 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7832}
7833
7834#define GEN_SPEOP_LDST(name, opc2, sh) \
7835static void glue(gen_, name)(DisasContext *ctx) \
7836{ \
7837 TCGv t0; \
7838 if (unlikely(!ctx->spe_enabled)) { \
7839 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7840 return; \
7841 } \
7842 gen_set_access_type(ctx, ACCESS_INT); \
7843 t0 = tcg_temp_new(); \
7844 if (Rc(ctx->opcode)) { \
7845 gen_addr_spe_imm_index(ctx, t0, sh); \
7846 } else { \
7847 gen_addr_reg_index(ctx, t0); \
7848 } \
7849 gen_op_##name(ctx, t0); \
7850 tcg_temp_free(t0); \
7851}
7852
7853GEN_SPEOP_LDST(evldd, 0x00, 3);
7854GEN_SPEOP_LDST(evldw, 0x01, 3);
7855GEN_SPEOP_LDST(evldh, 0x02, 3);
7856GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7857GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7858GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7859GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7860GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7861GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7862GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7863GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7864
7865GEN_SPEOP_LDST(evstdd, 0x10, 3);
7866GEN_SPEOP_LDST(evstdw, 0x11, 3);
7867GEN_SPEOP_LDST(evstdh, 0x12, 3);
7868GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7869GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7870GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7871GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7872
7873/* Multiply and add - TODO */
7874#if 0
7875GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
7876GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7877GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7878GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7879GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7880GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7881GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7882GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7883GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7884GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7885GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7886GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7887
7888GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7889GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7890GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7891GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7892GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7893GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7894GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7895GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7896GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7897GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7898GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7899GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7900
7901GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7902GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7903GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7904GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7905GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
7906
7907GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7908GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7909GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7910GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7911GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7912GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7913GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7914GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7915GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7916GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7917GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7918GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7919
7920GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7921GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7922GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7923GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7924
7925GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7926GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7927GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7928GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7929GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7930GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7931GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7932GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7933GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7934GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7935GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7936GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7937
7938GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7939GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7940GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7941GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7942GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7943#endif
7944
7945/*** SPE floating-point extension ***/
7946#if defined(TARGET_PPC64)
7947#define GEN_SPEFPUOP_CONV_32_32(name) \
7948static inline void gen_##name(DisasContext *ctx) \
7949{ \
7950 TCGv_i32 t0; \
7951 TCGv t1; \
7952 t0 = tcg_temp_new_i32(); \
7953 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7954 gen_helper_##name(t0, t0); \
7955 t1 = tcg_temp_new(); \
7956 tcg_gen_extu_i32_tl(t1, t0); \
7957 tcg_temp_free_i32(t0); \
7958 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7959 0xFFFFFFFF00000000ULL); \
7960 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7961 tcg_temp_free(t1); \
7962}
7963#define GEN_SPEFPUOP_CONV_32_64(name) \
7964static inline void gen_##name(DisasContext *ctx) \
7965{ \
7966 TCGv_i32 t0; \
7967 TCGv t1; \
7968 t0 = tcg_temp_new_i32(); \
7969 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7970 t1 = tcg_temp_new(); \
7971 tcg_gen_extu_i32_tl(t1, t0); \
7972 tcg_temp_free_i32(t0); \
7973 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7974 0xFFFFFFFF00000000ULL); \
7975 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7976 tcg_temp_free(t1); \
7977}
7978#define GEN_SPEFPUOP_CONV_64_32(name) \
7979static inline void gen_##name(DisasContext *ctx) \
7980{ \
7981 TCGv_i32 t0 = tcg_temp_new_i32(); \
7982 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7983 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7984 tcg_temp_free_i32(t0); \
7985}
7986#define GEN_SPEFPUOP_CONV_64_64(name) \
7987static inline void gen_##name(DisasContext *ctx) \
7988{ \
7989 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7990}
7991#define GEN_SPEFPUOP_ARITH2_32_32(name) \
7992static inline void gen_##name(DisasContext *ctx) \
7993{ \
7994 TCGv_i32 t0, t1; \
7995 TCGv_i64 t2; \
7996 if (unlikely(!ctx->spe_enabled)) { \
7997 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7998 return; \
7999 } \
8000 t0 = tcg_temp_new_i32(); \
8001 t1 = tcg_temp_new_i32(); \
8002 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8003 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8004 gen_helper_##name(t0, t0, t1); \
8005 tcg_temp_free_i32(t1); \
8006 t2 = tcg_temp_new(); \
8007 tcg_gen_extu_i32_tl(t2, t0); \
8008 tcg_temp_free_i32(t0); \
8009 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8010 0xFFFFFFFF00000000ULL); \
8011 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8012 tcg_temp_free(t2); \
8013}
8014#define GEN_SPEFPUOP_ARITH2_64_64(name) \
8015static inline void gen_##name(DisasContext *ctx) \
8016{ \
8017 if (unlikely(!ctx->spe_enabled)) { \
8018 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8019 return; \
8020 } \
8021 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8022 cpu_gpr[rB(ctx->opcode)]); \
8023}
8024#define GEN_SPEFPUOP_COMP_32(name) \
8025static inline void gen_##name(DisasContext *ctx) \
8026{ \
8027 TCGv_i32 t0, t1; \
8028 if (unlikely(!ctx->spe_enabled)) { \
8029 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8030 return; \
8031 } \
8032 t0 = tcg_temp_new_i32(); \
8033 t1 = tcg_temp_new_i32(); \
8034 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8035 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8036 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
8037 tcg_temp_free_i32(t0); \
8038 tcg_temp_free_i32(t1); \
8039}
8040#define GEN_SPEFPUOP_COMP_64(name) \
8041static inline void gen_##name(DisasContext *ctx) \
8042{ \
8043 if (unlikely(!ctx->spe_enabled)) { \
8044 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8045 return; \
8046 } \
8047 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8048 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8049}
8050#else
8051#define GEN_SPEFPUOP_CONV_32_32(name) \
8052static inline void gen_##name(DisasContext *ctx) \
8053{ \
8054 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8055}
8056#define GEN_SPEFPUOP_CONV_32_64(name) \
8057static inline void gen_##name(DisasContext *ctx) \
8058{ \
8059 TCGv_i64 t0 = tcg_temp_new_i64(); \
8060 gen_load_gpr64(t0, rB(ctx->opcode)); \
8061 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
8062 tcg_temp_free_i64(t0); \
8063}
8064#define GEN_SPEFPUOP_CONV_64_32(name) \
8065static inline void gen_##name(DisasContext *ctx) \
8066{ \
8067 TCGv_i64 t0 = tcg_temp_new_i64(); \
8068 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
8069 gen_store_gpr64(rD(ctx->opcode), t0); \
8070 tcg_temp_free_i64(t0); \
8071}
8072#define GEN_SPEFPUOP_CONV_64_64(name) \
8073static inline void gen_##name(DisasContext *ctx) \
8074{ \
8075 TCGv_i64 t0 = tcg_temp_new_i64(); \
8076 gen_load_gpr64(t0, rB(ctx->opcode)); \
8077 gen_helper_##name(t0, t0); \
8078 gen_store_gpr64(rD(ctx->opcode), t0); \
8079 tcg_temp_free_i64(t0); \
8080}
8081#define GEN_SPEFPUOP_ARITH2_32_32(name) \
8082static inline void gen_##name(DisasContext *ctx) \
8083{ \
8084 if (unlikely(!ctx->spe_enabled)) { \
8085 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8086 return; \
8087 } \
8088 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
8089 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8090}
8091#define GEN_SPEFPUOP_ARITH2_64_64(name) \
8092static inline void gen_##name(DisasContext *ctx) \
8093{ \
8094 TCGv_i64 t0, t1; \
8095 if (unlikely(!ctx->spe_enabled)) { \
8096 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8097 return; \
8098 } \
8099 t0 = tcg_temp_new_i64(); \
8100 t1 = tcg_temp_new_i64(); \
8101 gen_load_gpr64(t0, rA(ctx->opcode)); \
8102 gen_load_gpr64(t1, rB(ctx->opcode)); \
8103 gen_helper_##name(t0, t0, t1); \
8104 gen_store_gpr64(rD(ctx->opcode), t0); \
8105 tcg_temp_free_i64(t0); \
8106 tcg_temp_free_i64(t1); \
8107}
8108#define GEN_SPEFPUOP_COMP_32(name) \
8109static inline void gen_##name(DisasContext *ctx) \
8110{ \
8111 if (unlikely(!ctx->spe_enabled)) { \
8112 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8113 return; \
8114 } \
8115 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8116 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8117}
8118#define GEN_SPEFPUOP_COMP_64(name) \
8119static inline void gen_##name(DisasContext *ctx) \
8120{ \
8121 TCGv_i64 t0, t1; \
8122 if (unlikely(!ctx->spe_enabled)) { \
8123 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8124 return; \
8125 } \
8126 t0 = tcg_temp_new_i64(); \
8127 t1 = tcg_temp_new_i64(); \
8128 gen_load_gpr64(t0, rA(ctx->opcode)); \
8129 gen_load_gpr64(t1, rB(ctx->opcode)); \
8130 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
8131 tcg_temp_free_i64(t0); \
8132 tcg_temp_free_i64(t1); \
8133}
8134#endif
8135
8136/* Single precision floating-point vectors operations */
8137/* Arithmetic */
8138GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8139GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8140GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8141GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8142static inline void gen_evfsabs(DisasContext *ctx)
8143{
8144 if (unlikely(!ctx->spe_enabled)) {
8145 gen_exception(ctx, POWERPC_EXCP_SPEU);
8146 return;
8147 }
8148#if defined(TARGET_PPC64)
8149 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8150#else
8151 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8152 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8153#endif
8154}
8155static inline void gen_evfsnabs(DisasContext *ctx)
8156{
8157 if (unlikely(!ctx->spe_enabled)) {
8158 gen_exception(ctx, POWERPC_EXCP_SPEU);
8159 return;
8160 }
8161#if defined(TARGET_PPC64)
8162 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8163#else
8164 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8165 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8166#endif
8167}
8168static inline void gen_evfsneg(DisasContext *ctx)
8169{
8170 if (unlikely(!ctx->spe_enabled)) {
8171 gen_exception(ctx, POWERPC_EXCP_SPEU);
8172 return;
8173 }
8174#if defined(TARGET_PPC64)
8175 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8176#else
8177 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8178 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8179#endif
8180}
8181
8182/* Conversion */
8183GEN_SPEFPUOP_CONV_64_64(evfscfui);
8184GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8185GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8186GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8187GEN_SPEFPUOP_CONV_64_64(evfsctui);
8188GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8189GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8190GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8191GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8192GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8193
8194/* Comparison */
8195GEN_SPEFPUOP_COMP_64(evfscmpgt);
8196GEN_SPEFPUOP_COMP_64(evfscmplt);
8197GEN_SPEFPUOP_COMP_64(evfscmpeq);
8198GEN_SPEFPUOP_COMP_64(evfststgt);
8199GEN_SPEFPUOP_COMP_64(evfststlt);
8200GEN_SPEFPUOP_COMP_64(evfststeq);
8201
8202/* Opcodes definitions */
8203GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8204GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8205GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8206GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8207GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8208GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8209GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8210GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8211GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8212GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8213GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8214GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8215GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8216GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8217
8218/* Single precision floating-point operations */
8219/* Arithmetic */
8220GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8221GEN_SPEFPUOP_ARITH2_32_32(efssub);
8222GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8223GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8224static inline void gen_efsabs(DisasContext *ctx)
8225{
8226 if (unlikely(!ctx->spe_enabled)) {
8227 gen_exception(ctx, POWERPC_EXCP_SPEU);
8228 return;
8229 }
8230 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8231}
8232static inline void gen_efsnabs(DisasContext *ctx)
8233{
8234 if (unlikely(!ctx->spe_enabled)) {
8235 gen_exception(ctx, POWERPC_EXCP_SPEU);
8236 return;
8237 }
8238 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8239}
8240static inline void gen_efsneg(DisasContext *ctx)
8241{
8242 if (unlikely(!ctx->spe_enabled)) {
8243 gen_exception(ctx, POWERPC_EXCP_SPEU);
8244 return;
8245 }
8246 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8247}
8248
8249/* Conversion */
8250GEN_SPEFPUOP_CONV_32_32(efscfui);
8251GEN_SPEFPUOP_CONV_32_32(efscfsi);
8252GEN_SPEFPUOP_CONV_32_32(efscfuf);
8253GEN_SPEFPUOP_CONV_32_32(efscfsf);
8254GEN_SPEFPUOP_CONV_32_32(efsctui);
8255GEN_SPEFPUOP_CONV_32_32(efsctsi);
8256GEN_SPEFPUOP_CONV_32_32(efsctuf);
8257GEN_SPEFPUOP_CONV_32_32(efsctsf);
8258GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8259GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8260GEN_SPEFPUOP_CONV_32_64(efscfd);
8261
8262/* Comparison */
8263GEN_SPEFPUOP_COMP_32(efscmpgt);
8264GEN_SPEFPUOP_COMP_32(efscmplt);
8265GEN_SPEFPUOP_COMP_32(efscmpeq);
8266GEN_SPEFPUOP_COMP_32(efststgt);
8267GEN_SPEFPUOP_COMP_32(efststlt);
8268GEN_SPEFPUOP_COMP_32(efststeq);
8269
8270/* Opcodes definitions */
8271GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8272GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8273GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8274GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8275GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8276GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8277GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8278GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8279GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8280GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8281GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8282GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8283GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8284GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8285
8286/* Double precision floating-point operations */
8287/* Arithmetic */
8288GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8289GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8290GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8291GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8292static inline void gen_efdabs(DisasContext *ctx)
8293{
8294 if (unlikely(!ctx->spe_enabled)) {
8295 gen_exception(ctx, POWERPC_EXCP_SPEU);
8296 return;
8297 }
8298#if defined(TARGET_PPC64)
8299 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8300#else
8301 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8302 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8303#endif
8304}
8305static inline void gen_efdnabs(DisasContext *ctx)
8306{
8307 if (unlikely(!ctx->spe_enabled)) {
8308 gen_exception(ctx, POWERPC_EXCP_SPEU);
8309 return;
8310 }
8311#if defined(TARGET_PPC64)
8312 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8313#else
8314 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8315 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8316#endif
8317}
8318static inline void gen_efdneg(DisasContext *ctx)
8319{
8320 if (unlikely(!ctx->spe_enabled)) {
8321 gen_exception(ctx, POWERPC_EXCP_SPEU);
8322 return;
8323 }
8324#if defined(TARGET_PPC64)
8325 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8326#else
8327 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8328 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8329#endif
8330}
8331
8332/* Conversion */
8333GEN_SPEFPUOP_CONV_64_32(efdcfui);
8334GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8335GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8336GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8337GEN_SPEFPUOP_CONV_32_64(efdctui);
8338GEN_SPEFPUOP_CONV_32_64(efdctsi);
8339GEN_SPEFPUOP_CONV_32_64(efdctuf);
8340GEN_SPEFPUOP_CONV_32_64(efdctsf);
8341GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8342GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8343GEN_SPEFPUOP_CONV_64_32(efdcfs);
8344GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8345GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8346GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8347GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8348
8349/* Comparison */
8350GEN_SPEFPUOP_COMP_64(efdcmpgt);
8351GEN_SPEFPUOP_COMP_64(efdcmplt);
8352GEN_SPEFPUOP_COMP_64(efdcmpeq);
8353GEN_SPEFPUOP_COMP_64(efdtstgt);
8354GEN_SPEFPUOP_COMP_64(efdtstlt);
8355GEN_SPEFPUOP_COMP_64(efdtsteq);
8356
8357/* Opcodes definitions */
8358GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8359GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8360GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8361GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8362GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8363GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8364GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8365GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8366GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8367GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8368GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8369GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8370GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8371GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8372GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8373GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8374
8375static opcode_t opcodes[] = {
8376GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8377GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8378GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8379GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8380GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8381GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8382GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8383GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8384GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8385GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8386GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8387GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8388GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8389GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8390GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8391#if defined(TARGET_PPC64)
8392GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8393#endif
8394GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8395GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8396GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8397GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8398GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8399GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8400GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8401GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8402GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8403GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8404GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8405GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8406GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8407GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8408#if defined(TARGET_PPC64)
8409GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8410GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8411#endif
8412GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8413GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8414GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8415GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8416GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8417GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8418GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8419#if defined(TARGET_PPC64)
8420GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8421GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8422GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8423GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8424GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8425#endif
8426GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8427GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8428GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8429GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8430GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8431GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8432GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8433GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8434GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8435GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8436GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8437GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8438#if defined(TARGET_PPC64)
8439GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8440GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8441GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8442#endif
8443GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8444GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8445GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8446GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8447GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8448GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8449GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8450GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8451GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8452GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8453#if defined(TARGET_PPC64)
8454GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8455GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8456#endif
8457GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8458GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8459GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8460GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8461GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8462GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8463GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8464GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8465#if defined(TARGET_PPC64)
8466GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8467GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8468#endif
8469GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8470GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8471GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8472#if defined(TARGET_PPC64)
8473GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8474GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8475#endif
8476GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8477GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8478GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8479GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8480GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8481GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8482#if defined(TARGET_PPC64)
8483GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8484#endif
8485GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8486GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8487GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8488GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8489GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8490GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8491GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8492GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ),
8493GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT),
8494GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8495GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8496GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8497GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8498GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8499GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8500GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8501GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8502GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8503#if defined(TARGET_PPC64)
8504GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8505GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8506 PPC_SEGMENT_64B),
8507GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8508GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8509 PPC_SEGMENT_64B),
8510GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8511GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8512GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8513#endif
8514GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8515GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8516GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8517GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8518#if defined(TARGET_PPC64)
8519GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8520GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8521#endif
8522GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8523GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8524GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8525GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8526GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8527GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8528GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8529GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8530GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8531GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8532GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8533GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8534GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8535GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8536GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8537GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8538GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8539GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8540GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8541GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8542GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8543GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8544GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8545GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8546GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8547GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8548GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8549GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8550GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8551GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8552GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8553GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8554GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8555GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8556GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8557GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8558GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8559GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8560GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8561GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8562GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8563GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8564GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8565GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8566GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8567GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8568GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8569GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8570GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8571GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8572GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8573GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8574GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8575GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8576GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8577GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8578GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8579GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8580GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8581GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8582GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8583GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8584GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8585GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8586GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8587GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8588GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8589GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8590GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8591GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8592GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8593GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8594GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8595GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8596GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8597GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8598GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8599GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8600GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8601GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8602GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8603 PPC_NONE, PPC2_BOOKE206),
8604GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8605 PPC_NONE, PPC2_BOOKE206),
8606GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8607 PPC_NONE, PPC2_BOOKE206),
8608GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8609 PPC_NONE, PPC2_BOOKE206),
8610GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8611 PPC_NONE, PPC2_BOOKE206),
8612GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8613GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8614GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8615GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8616 PPC_BOOKE, PPC2_BOOKE206),
8617GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8618GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8619 PPC_BOOKE, PPC2_BOOKE206),
8620GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8621GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8622GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8623GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8624GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8625GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8626GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8627GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8628GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8629GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8630
8631#undef GEN_INT_ARITH_ADD
8632#undef GEN_INT_ARITH_ADD_CONST
8633#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8634GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8635#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8636 add_ca, compute_ca, compute_ov) \
8637GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8638GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8639GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8640GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8641GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8642GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8643GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8644GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8645GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8646GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8647GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8648
8649#undef GEN_INT_ARITH_DIVW
8650#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8651GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8652GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8653GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8654GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8655GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8656
8657#if defined(TARGET_PPC64)
8658#undef GEN_INT_ARITH_DIVD
8659#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8660GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8661GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8662GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8663GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8664GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8665
8666#undef GEN_INT_ARITH_MUL_HELPER
8667#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8668GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8669GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8670GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8671GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8672#endif
8673
8674#undef GEN_INT_ARITH_SUBF
8675#undef GEN_INT_ARITH_SUBF_CONST
8676#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8677GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8678#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8679 add_ca, compute_ca, compute_ov) \
8680GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8681GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8682GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8683GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8684GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8685GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8686GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8687GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8688GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8689GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8690GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8691
8692#undef GEN_LOGICAL1
8693#undef GEN_LOGICAL2
8694#define GEN_LOGICAL2(name, tcg_op, opc, type) \
8695GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8696#define GEN_LOGICAL1(name, tcg_op, opc, type) \
8697GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8698GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8699GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8700GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8701GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8702GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8703GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8704GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8705GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8706#if defined(TARGET_PPC64)
8707GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8708#endif
8709
8710#if defined(TARGET_PPC64)
8711#undef GEN_PPC64_R2
8712#undef GEN_PPC64_R4
8713#define GEN_PPC64_R2(name, opc1, opc2) \
8714GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8715GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8716 PPC_64B)
8717#define GEN_PPC64_R4(name, opc1, opc2) \
8718GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8719GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8720 PPC_64B), \
8721GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8722 PPC_64B), \
8723GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8724 PPC_64B)
8725GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8726GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8727GEN_PPC64_R4(rldic, 0x1E, 0x04),
8728GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8729GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8730GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8731#endif
8732
8733#undef _GEN_FLOAT_ACB
8734#undef GEN_FLOAT_ACB
8735#undef _GEN_FLOAT_AB
8736#undef GEN_FLOAT_AB
8737#undef _GEN_FLOAT_AC
8738#undef GEN_FLOAT_AC
8739#undef GEN_FLOAT_B
8740#undef GEN_FLOAT_BS
8741#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8742GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8743#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8744_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8745_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8746#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8747GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8748#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8749_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8750_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8751#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8752GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8753#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8754_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8755_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8756#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8757GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8758#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8759GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8760
8761GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8762GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8763GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8764GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8765GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8766GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8767_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8768GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8769GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8770GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8771GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8772GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8773GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8774GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8775GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8776#if defined(TARGET_PPC64)
8777GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8778GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8779GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8780#endif
8781GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8782GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8783GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8784GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8785GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8786GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8787GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8788
8789#undef GEN_LD
8790#undef GEN_LDU
8791#undef GEN_LDUX
8792#undef GEN_LDX
8793#undef GEN_LDS
8794#define GEN_LD(name, ldop, opc, type) \
8795GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8796#define GEN_LDU(name, ldop, opc, type) \
8797GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8798#define GEN_LDUX(name, ldop, opc2, opc3, type) \
8799GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8800#define GEN_LDX(name, ldop, opc2, opc3, type) \
8801GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8802#define GEN_LDS(name, ldop, op, type) \
8803GEN_LD(name, ldop, op | 0x20, type) \
8804GEN_LDU(name, ldop, op | 0x21, type) \
8805GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8806GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8807
8808GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8809GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8810GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8811GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8812#if defined(TARGET_PPC64)
8813GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8814GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8815GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8816GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8817#endif
8818GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8819GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8820
8821#undef GEN_ST
8822#undef GEN_STU
8823#undef GEN_STUX
8824#undef GEN_STX
8825#undef GEN_STS
8826#define GEN_ST(name, stop, opc, type) \
8827GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8828#define GEN_STU(name, stop, opc, type) \
8829GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8830#define GEN_STUX(name, stop, opc2, opc3, type) \
8831GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8832#define GEN_STX(name, stop, opc2, opc3, type) \
8833GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8834#define GEN_STS(name, stop, op, type) \
8835GEN_ST(name, stop, op | 0x20, type) \
8836GEN_STU(name, stop, op | 0x21, type) \
8837GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8838GEN_STX(name, stop, 0x17, op | 0x00, type)
8839
8840GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8841GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8842GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8843#if defined(TARGET_PPC64)
8844GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8845GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8846#endif
8847GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8848GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8849
8850#undef GEN_LDF
8851#undef GEN_LDUF
8852#undef GEN_LDUXF
8853#undef GEN_LDXF
8854#undef GEN_LDFS
8855#define GEN_LDF(name, ldop, opc, type) \
8856GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8857#define GEN_LDUF(name, ldop, opc, type) \
8858GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8859#define GEN_LDUXF(name, ldop, opc, type) \
8860GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8861#define GEN_LDXF(name, ldop, opc2, opc3, type) \
8862GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8863#define GEN_LDFS(name, ldop, op, type) \
8864GEN_LDF(name, ldop, op | 0x20, type) \
8865GEN_LDUF(name, ldop, op | 0x21, type) \
8866GEN_LDUXF(name, ldop, op | 0x01, type) \
8867GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8868
8869GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8870GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8871
8872#undef GEN_STF
8873#undef GEN_STUF
8874#undef GEN_STUXF
8875#undef GEN_STXF
8876#undef GEN_STFS
8877#define GEN_STF(name, stop, opc, type) \
8878GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8879#define GEN_STUF(name, stop, opc, type) \
8880GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8881#define GEN_STUXF(name, stop, opc, type) \
8882GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8883#define GEN_STXF(name, stop, opc2, opc3, type) \
8884GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8885#define GEN_STFS(name, stop, op, type) \
8886GEN_STF(name, stop, op | 0x20, type) \
8887GEN_STUF(name, stop, op | 0x21, type) \
8888GEN_STUXF(name, stop, op | 0x01, type) \
8889GEN_STXF(name, stop, 0x17, op | 0x00, type)
8890
8891GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8892GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8893GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8894
8895#undef GEN_CRLOGIC
8896#define GEN_CRLOGIC(name, tcg_op, opc) \
8897GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8898GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8899GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8900GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8901GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8902GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8903GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8904GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8905GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8906
8907#undef GEN_MAC_HANDLER
8908#define GEN_MAC_HANDLER(name, opc2, opc3) \
8909GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8910GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8911GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8912GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8913GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8914GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8915GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8916GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8917GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8918GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8919GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8920GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8921GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8922GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8923GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8924GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8925GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8926GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8927GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8928GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8929GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8930GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
8931GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
8932GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
8933GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
8934GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
8935GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
8936GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
8937GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
8938GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
8939GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
8940GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
8941GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
8942GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
8943GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
8944GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
8945GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
8946GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
8947GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
8948GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
8949GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
8950GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
8951GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
8952
8953#undef GEN_VR_LDX
8954#undef GEN_VR_STX
8955#undef GEN_VR_LVE
8956#undef GEN_VR_STVE
8957#define GEN_VR_LDX(name, opc2, opc3) \
8958GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8959#define GEN_VR_STX(name, opc2, opc3) \
8960GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8961#define GEN_VR_LVE(name, opc2, opc3) \
8962 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8963#define GEN_VR_STVE(name, opc2, opc3) \
8964 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8965GEN_VR_LDX(lvx, 0x07, 0x03),
8966GEN_VR_LDX(lvxl, 0x07, 0x0B),
8967GEN_VR_LVE(bx, 0x07, 0x00),
8968GEN_VR_LVE(hx, 0x07, 0x01),
8969GEN_VR_LVE(wx, 0x07, 0x02),
8970GEN_VR_STX(svx, 0x07, 0x07),
8971GEN_VR_STX(svxl, 0x07, 0x0F),
8972GEN_VR_STVE(bx, 0x07, 0x04),
8973GEN_VR_STVE(hx, 0x07, 0x05),
8974GEN_VR_STVE(wx, 0x07, 0x06),
8975
8976#undef GEN_VX_LOGICAL
8977#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
8978GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
8979GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
8980GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
8981GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
8982GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
8983GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
8984
8985#undef GEN_VXFORM
8986#define GEN_VXFORM(name, opc2, opc3) \
8987GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
8988GEN_VXFORM(vaddubm, 0, 0),
8989GEN_VXFORM(vadduhm, 0, 1),
8990GEN_VXFORM(vadduwm, 0, 2),
8991GEN_VXFORM(vsububm, 0, 16),
8992GEN_VXFORM(vsubuhm, 0, 17),
8993GEN_VXFORM(vsubuwm, 0, 18),
8994GEN_VXFORM(vmaxub, 1, 0),
8995GEN_VXFORM(vmaxuh, 1, 1),
8996GEN_VXFORM(vmaxuw, 1, 2),
8997GEN_VXFORM(vmaxsb, 1, 4),
8998GEN_VXFORM(vmaxsh, 1, 5),
8999GEN_VXFORM(vmaxsw, 1, 6),
9000GEN_VXFORM(vminub, 1, 8),
9001GEN_VXFORM(vminuh, 1, 9),
9002GEN_VXFORM(vminuw, 1, 10),
9003GEN_VXFORM(vminsb, 1, 12),
9004GEN_VXFORM(vminsh, 1, 13),
9005GEN_VXFORM(vminsw, 1, 14),
9006GEN_VXFORM(vavgub, 1, 16),
9007GEN_VXFORM(vavguh, 1, 17),
9008GEN_VXFORM(vavguw, 1, 18),
9009GEN_VXFORM(vavgsb, 1, 20),
9010GEN_VXFORM(vavgsh, 1, 21),
9011GEN_VXFORM(vavgsw, 1, 22),
9012GEN_VXFORM(vmrghb, 6, 0),
9013GEN_VXFORM(vmrghh, 6, 1),
9014GEN_VXFORM(vmrghw, 6, 2),
9015GEN_VXFORM(vmrglb, 6, 4),
9016GEN_VXFORM(vmrglh, 6, 5),
9017GEN_VXFORM(vmrglw, 6, 6),
9018GEN_VXFORM(vmuloub, 4, 0),
9019GEN_VXFORM(vmulouh, 4, 1),
9020GEN_VXFORM(vmulosb, 4, 4),
9021GEN_VXFORM(vmulosh, 4, 5),
9022GEN_VXFORM(vmuleub, 4, 8),
9023GEN_VXFORM(vmuleuh, 4, 9),
9024GEN_VXFORM(vmulesb, 4, 12),
9025GEN_VXFORM(vmulesh, 4, 13),
9026GEN_VXFORM(vslb, 2, 4),
9027GEN_VXFORM(vslh, 2, 5),
9028GEN_VXFORM(vslw, 2, 6),
9029GEN_VXFORM(vsrb, 2, 8),
9030GEN_VXFORM(vsrh, 2, 9),
9031GEN_VXFORM(vsrw, 2, 10),
9032GEN_VXFORM(vsrab, 2, 12),
9033GEN_VXFORM(vsrah, 2, 13),
9034GEN_VXFORM(vsraw, 2, 14),
9035GEN_VXFORM(vslo, 6, 16),
9036GEN_VXFORM(vsro, 6, 17),
9037GEN_VXFORM(vaddcuw, 0, 6),
9038GEN_VXFORM(vsubcuw, 0, 22),
9039GEN_VXFORM(vaddubs, 0, 8),
9040GEN_VXFORM(vadduhs, 0, 9),
9041GEN_VXFORM(vadduws, 0, 10),
9042GEN_VXFORM(vaddsbs, 0, 12),
9043GEN_VXFORM(vaddshs, 0, 13),
9044GEN_VXFORM(vaddsws, 0, 14),
9045GEN_VXFORM(vsububs, 0, 24),
9046GEN_VXFORM(vsubuhs, 0, 25),
9047GEN_VXFORM(vsubuws, 0, 26),
9048GEN_VXFORM(vsubsbs, 0, 28),
9049GEN_VXFORM(vsubshs, 0, 29),
9050GEN_VXFORM(vsubsws, 0, 30),
9051GEN_VXFORM(vrlb, 2, 0),
9052GEN_VXFORM(vrlh, 2, 1),
9053GEN_VXFORM(vrlw, 2, 2),
9054GEN_VXFORM(vsl, 2, 7),
9055GEN_VXFORM(vsr, 2, 11),
9056GEN_VXFORM(vpkuhum, 7, 0),
9057GEN_VXFORM(vpkuwum, 7, 1),
9058GEN_VXFORM(vpkuhus, 7, 2),
9059GEN_VXFORM(vpkuwus, 7, 3),
9060GEN_VXFORM(vpkshus, 7, 4),
9061GEN_VXFORM(vpkswus, 7, 5),
9062GEN_VXFORM(vpkshss, 7, 6),
9063GEN_VXFORM(vpkswss, 7, 7),
9064GEN_VXFORM(vpkpx, 7, 12),
9065GEN_VXFORM(vsum4ubs, 4, 24),
9066GEN_VXFORM(vsum4sbs, 4, 28),
9067GEN_VXFORM(vsum4shs, 4, 25),
9068GEN_VXFORM(vsum2sws, 4, 26),
9069GEN_VXFORM(vsumsws, 4, 30),
9070GEN_VXFORM(vaddfp, 5, 0),
9071GEN_VXFORM(vsubfp, 5, 1),
9072GEN_VXFORM(vmaxfp, 5, 16),
9073GEN_VXFORM(vminfp, 5, 17),
9074
9075#undef GEN_VXRFORM1
9076#undef GEN_VXRFORM
9077#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9078 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9079#define GEN_VXRFORM(name, opc2, opc3) \
9080 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9081 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9082GEN_VXRFORM(vcmpequb, 3, 0)
9083GEN_VXRFORM(vcmpequh, 3, 1)
9084GEN_VXRFORM(vcmpequw, 3, 2)
9085GEN_VXRFORM(vcmpgtsb, 3, 12)
9086GEN_VXRFORM(vcmpgtsh, 3, 13)
9087GEN_VXRFORM(vcmpgtsw, 3, 14)
9088GEN_VXRFORM(vcmpgtub, 3, 8)
9089GEN_VXRFORM(vcmpgtuh, 3, 9)
9090GEN_VXRFORM(vcmpgtuw, 3, 10)
9091GEN_VXRFORM(vcmpeqfp, 3, 3)
9092GEN_VXRFORM(vcmpgefp, 3, 7)
9093GEN_VXRFORM(vcmpgtfp, 3, 11)
9094GEN_VXRFORM(vcmpbfp, 3, 15)
9095
9096#undef GEN_VXFORM_SIMM
9097#define GEN_VXFORM_SIMM(name, opc2, opc3) \
9098 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9099GEN_VXFORM_SIMM(vspltisb, 6, 12),
9100GEN_VXFORM_SIMM(vspltish, 6, 13),
9101GEN_VXFORM_SIMM(vspltisw, 6, 14),
9102
9103#undef GEN_VXFORM_NOA
9104#define GEN_VXFORM_NOA(name, opc2, opc3) \
9105 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9106GEN_VXFORM_NOA(vupkhsb, 7, 8),
9107GEN_VXFORM_NOA(vupkhsh, 7, 9),
9108GEN_VXFORM_NOA(vupklsb, 7, 10),
9109GEN_VXFORM_NOA(vupklsh, 7, 11),
9110GEN_VXFORM_NOA(vupkhpx, 7, 13),
9111GEN_VXFORM_NOA(vupklpx, 7, 15),
9112GEN_VXFORM_NOA(vrefp, 5, 4),
9113GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9114GEN_VXFORM_NOA(vexptefp, 5, 6),
9115GEN_VXFORM_NOA(vlogefp, 5, 7),
9116GEN_VXFORM_NOA(vrfim, 5, 8),
9117GEN_VXFORM_NOA(vrfin, 5, 9),
9118GEN_VXFORM_NOA(vrfip, 5, 10),
9119GEN_VXFORM_NOA(vrfiz, 5, 11),
9120
9121#undef GEN_VXFORM_UIMM
9122#define GEN_VXFORM_UIMM(name, opc2, opc3) \
9123 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9124GEN_VXFORM_UIMM(vspltb, 6, 8),
9125GEN_VXFORM_UIMM(vsplth, 6, 9),
9126GEN_VXFORM_UIMM(vspltw, 6, 10),
9127GEN_VXFORM_UIMM(vcfux, 5, 12),
9128GEN_VXFORM_UIMM(vcfsx, 5, 13),
9129GEN_VXFORM_UIMM(vctuxs, 5, 14),
9130GEN_VXFORM_UIMM(vctsxs, 5, 15),
9131
9132#undef GEN_VAFORM_PAIRED
9133#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9134 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9135GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9136GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9137GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9138GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9139GEN_VAFORM_PAIRED(vsel, vperm, 21),
9140GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9141
9142#undef GEN_SPE
9143#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9144 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9145GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9146GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9147GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9148GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9149GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9150GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9151GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9152GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9153GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9154GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9155GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9156GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9157GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9158GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9159GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9160GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9161GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9162GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9163GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9164GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9165GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9166GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9167GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9168GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9169GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9170GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9171GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9172GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9173GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9174
9175GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9176GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9177GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9178GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9179GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9180GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9181GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9182GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9183GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9184GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9185GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9186GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9187GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9188GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9189
9190GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9191GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9192GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9193GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9194GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9195GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9196GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9197GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9198GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9199GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9200GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9201GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9202GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9203GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9204
9205GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9206GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9207GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9208GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9209GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9210GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9211GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9212GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9213GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9214GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9215GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9216GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9217GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9218GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9219GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9220GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9221
9222#undef GEN_SPEOP_LDST
9223#define GEN_SPEOP_LDST(name, opc2, sh) \
9224GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9225GEN_SPEOP_LDST(evldd, 0x00, 3),
9226GEN_SPEOP_LDST(evldw, 0x01, 3),
9227GEN_SPEOP_LDST(evldh, 0x02, 3),
9228GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9229GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9230GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9231GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9232GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9233GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9234GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9235GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9236
9237GEN_SPEOP_LDST(evstdd, 0x10, 3),
9238GEN_SPEOP_LDST(evstdw, 0x11, 3),
9239GEN_SPEOP_LDST(evstdh, 0x12, 3),
9240GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9241GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9242GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9243GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9244};
9245
9246#include "translate_init.c"
9247#include "helper_regs.h"
9248
9249/*****************************************************************************/
9250/* Misc PowerPC helpers */
9251void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
9252 int flags)
9253{
9254#define RGPL 4
9255#define RFPL 4
9256
9257 int i;
9258
9259 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9260 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9261 env->nip, env->lr, env->ctr, env->xer);
9262 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9263 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9264 env->hflags, env->mmu_idx);
9265#if !defined(NO_TIMER_DUMP)
9266 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9267#if !defined(CONFIG_USER_ONLY)
9268 " DECR %08" PRIu32
9269#endif
9270 "\n",
9271 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9272#if !defined(CONFIG_USER_ONLY)
9273 , cpu_ppc_load_decr(env)
9274#endif
9275 );
9276#endif
9277 for (i = 0; i < 32; i++) {
9278 if ((i & (RGPL - 1)) == 0)
9279 cpu_fprintf(f, "GPR%02d", i);
9280 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9281 if ((i & (RGPL - 1)) == (RGPL - 1))
9282 cpu_fprintf(f, "\n");
9283 }
9284 cpu_fprintf(f, "CR ");
9285 for (i = 0; i < 8; i++)
9286 cpu_fprintf(f, "%01x", env->crf[i]);
9287 cpu_fprintf(f, " [");
9288 for (i = 0; i < 8; i++) {
9289 char a = '-';
9290 if (env->crf[i] & 0x08)
9291 a = 'L';
9292 else if (env->crf[i] & 0x04)
9293 a = 'G';
9294 else if (env->crf[i] & 0x02)
9295 a = 'E';
9296 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9297 }
9298 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9299 env->reserve_addr);
9300 for (i = 0; i < 32; i++) {
9301 if ((i & (RFPL - 1)) == 0)
9302 cpu_fprintf(f, "FPR%02d", i);
9303 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9304 if ((i & (RFPL - 1)) == (RFPL - 1))
9305 cpu_fprintf(f, "\n");
9306 }
9307 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
9308#if !defined(CONFIG_USER_ONLY)
9309 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9310 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9311 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9312 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9313
9314 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9315 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9316 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9317 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9318
9319 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9320 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9321 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9322 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9323
9324 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9325 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9326 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9327 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9328 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9329
9330 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9331 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9332 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9333 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9334
9335 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9336 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9337 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9338 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9339
9340 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9341 " EPR " TARGET_FMT_lx "\n",
9342 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9343 env->spr[SPR_BOOKE_EPR]);
9344
9345 /* FSL-specific */
9346 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9347 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9348 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9349 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9350
9351 /*
9352 * IVORs are left out as they are large and do not change often --
9353 * they can be read with "p $ivor0", "p $ivor1", etc.
9354 */
9355 }
9356
9357#if defined(TARGET_PPC64)
9358 if (env->flags & POWERPC_FLAG_CFAR) {
9359 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9360 }
9361#endif
9362
9363 switch (env->mmu_model) {
9364 case POWERPC_MMU_32B:
9365 case POWERPC_MMU_601:
9366 case POWERPC_MMU_SOFT_6xx:
9367 case POWERPC_MMU_SOFT_74xx:
9368#if defined(TARGET_PPC64)
9369 case POWERPC_MMU_620:
9370 case POWERPC_MMU_64B:
9371#endif
9372 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9373 break;
9374 case POWERPC_MMU_BOOKE206:
9375 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9376 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9377 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9378 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9379
9380 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9381 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9382 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9383 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9384
9385 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9386 " TLB1CFG " TARGET_FMT_lx "\n",
9387 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9388 env->spr[SPR_BOOKE_TLB1CFG]);
9389 break;
9390 default:
9391 break;
9392 }
9393#endif
9394
9395#undef RGPL
9396#undef RFPL
9397}
9398
9399void cpu_dump_statistics (CPUState *env, FILE*f, fprintf_function cpu_fprintf,
9400 int flags)
9401{
9402#if defined(DO_PPC_STATISTICS)
9403 opc_handler_t **t1, **t2, **t3, *handler;
9404 int op1, op2, op3;
9405
9406 t1 = env->opcodes;
9407 for (op1 = 0; op1 < 64; op1++) {
9408 handler = t1[op1];
9409 if (is_indirect_opcode(handler)) {
9410 t2 = ind_table(handler);
9411 for (op2 = 0; op2 < 32; op2++) {
9412 handler = t2[op2];
9413 if (is_indirect_opcode(handler)) {
9414 t3 = ind_table(handler);
9415 for (op3 = 0; op3 < 32; op3++) {
9416 handler = t3[op3];
9417 if (handler->count == 0)
9418 continue;
9419 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9420 "%016" PRIx64 " %" PRId64 "\n",
9421 op1, op2, op3, op1, (op3 << 5) | op2,
9422 handler->oname,
9423 handler->count, handler->count);
9424 }
9425 } else {
9426 if (handler->count == 0)
9427 continue;
9428 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9429 "%016" PRIx64 " %" PRId64 "\n",
9430 op1, op2, op1, op2, handler->oname,
9431 handler->count, handler->count);
9432 }
9433 }
9434 } else {
9435 if (handler->count == 0)
9436 continue;
9437 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9438 " %" PRId64 "\n",
9439 op1, op1, handler->oname,
9440 handler->count, handler->count);
9441 }
9442 }
9443#endif
9444}
9445
9446/*****************************************************************************/
9447static inline void gen_intermediate_code_internal(CPUState *env,
9448 TranslationBlock *tb,
9449 int search_pc)
9450{
9451 DisasContext ctx, *ctxp = &ctx;
9452 opc_handler_t **table, *handler;
9453 target_ulong pc_start;
9454 uint16_t *gen_opc_end;
9455 CPUBreakpoint *bp;
9456 int j, lj = -1;
9457 int num_insns;
9458 int max_insns;
9459
9460 pc_start = tb->pc;
9461 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
9462 ctx.nip = pc_start;
9463 ctx.tb = tb;
9464 ctx.exception = POWERPC_EXCP_NONE;
9465 ctx.spr_cb = env->spr_cb;
9466 ctx.mem_idx = env->mmu_idx;
9467 ctx.access_type = -1;
9468 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9469#if defined(TARGET_PPC64)
9470 ctx.sf_mode = msr_sf;
9471 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9472#endif
9473 ctx.fpu_enabled = msr_fp;
9474 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9475 ctx.spe_enabled = msr_spe;
9476 else
9477 ctx.spe_enabled = 0;
9478 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9479 ctx.altivec_enabled = msr_vr;
9480 else
9481 ctx.altivec_enabled = 0;
9482 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9483 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9484 else
9485 ctx.singlestep_enabled = 0;
9486 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9487 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9488 if (unlikely(env->singlestep_enabled))
9489 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9490#if defined (DO_SINGLE_STEP) && 0
9491 /* Single step trace mode */
9492 msr_se = 1;
9493#endif
9494 num_insns = 0;
9495 max_insns = tb->cflags & CF_COUNT_MASK;
9496 if (max_insns == 0)
9497 max_insns = CF_COUNT_MASK;
9498
9499 gen_icount_start();
9500 /* Set env in case of segfault during code fetch */
9501 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
9502 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9503 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9504 if (bp->pc == ctx.nip) {
9505 gen_debug_exception(ctxp);
9506 break;
9507 }
9508 }
9509 }
9510 if (unlikely(search_pc)) {
9511 j = gen_opc_ptr - gen_opc_buf;
9512 if (lj < j) {
9513 lj++;
9514 while (lj < j)
9515 gen_opc_instr_start[lj++] = 0;
9516 }
9517 gen_opc_pc[lj] = ctx.nip;
9518 gen_opc_instr_start[lj] = 1;
9519 gen_opc_icount[lj] = num_insns;
9520 }
9521 LOG_DISAS("----------------\n");
9522 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9523 ctx.nip, ctx.mem_idx, (int)msr_ir);
9524 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9525 gen_io_start();
9526 if (unlikely(ctx.le_mode)) {
9527 ctx.opcode = bswap32(ldl_code(ctx.nip));
9528 } else {
9529 ctx.opcode = ldl_code(ctx.nip);
9530 }
9531 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9532 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9533 opc3(ctx.opcode), little_endian ? "little" : "big");
9534 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
9535 tcg_gen_debug_insn_start(ctx.nip);
9536 ctx.nip += 4;
9537 table = env->opcodes;
9538 num_insns++;
9539 handler = table[opc1(ctx.opcode)];
9540 if (is_indirect_opcode(handler)) {
9541 table = ind_table(handler);
9542 handler = table[opc2(ctx.opcode)];
9543 if (is_indirect_opcode(handler)) {
9544 table = ind_table(handler);
9545 handler = table[opc3(ctx.opcode)];
9546 }
9547 }
9548 /* Is opcode *REALLY* valid ? */
9549 if (unlikely(handler->handler == &gen_invalid)) {
9550 if (qemu_log_enabled()) {
9551 qemu_log("invalid/unsupported opcode: "
9552 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9553 opc1(ctx.opcode), opc2(ctx.opcode),
9554 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9555 }
9556 } else {
9557 uint32_t inval;
9558
9559 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9560 inval = handler->inval2;
9561 } else {
9562 inval = handler->inval1;
9563 }
9564
9565 if (unlikely((ctx.opcode & inval) != 0)) {
9566 if (qemu_log_enabled()) {
9567 qemu_log("invalid bits: %08x for opcode: "
9568 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9569 ctx.opcode & inval, opc1(ctx.opcode),
9570 opc2(ctx.opcode), opc3(ctx.opcode),
9571 ctx.opcode, ctx.nip - 4);
9572 }
9573 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9574 break;
9575 }
9576 }
9577 (*(handler->handler))(&ctx);
9578#if defined(DO_PPC_STATISTICS)
9579 handler->count++;
9580#endif
9581 /* Check trace mode exceptions */
9582 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9583 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9584 ctx.exception != POWERPC_SYSCALL &&
9585 ctx.exception != POWERPC_EXCP_TRAP &&
9586 ctx.exception != POWERPC_EXCP_BRANCH)) {
9587 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9588 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9589 (env->singlestep_enabled) ||
9590 singlestep ||
9591 num_insns >= max_insns)) {
9592 /* if we reach a page boundary or are single stepping, stop
9593 * generation
9594 */
9595 break;
9596 }
9597 }
9598 if (tb->cflags & CF_LAST_IO)
9599 gen_io_end();
9600 if (ctx.exception == POWERPC_EXCP_NONE) {
9601 gen_goto_tb(&ctx, 0, ctx.nip);
9602 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9603 if (unlikely(env->singlestep_enabled)) {
9604 gen_debug_exception(ctxp);
9605 }
9606 /* Generate the return instruction */
9607 tcg_gen_exit_tb(0);
9608 }
9609 gen_icount_end(tb, num_insns);
9610 *gen_opc_ptr = INDEX_op_end;
9611 if (unlikely(search_pc)) {
9612 j = gen_opc_ptr - gen_opc_buf;
9613 lj++;
9614 while (lj <= j)
9615 gen_opc_instr_start[lj++] = 0;
9616 } else {
9617 tb->size = ctx.nip - pc_start;
9618 tb->icount = num_insns;
9619 }
9620#if defined(DEBUG_DISAS)
9621 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9622 int flags;
9623 flags = env->bfd_mach;
9624 flags |= ctx.le_mode << 16;
9625 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9626 log_target_disas(pc_start, ctx.nip - pc_start, flags);
9627 qemu_log("\n");
9628 }
9629#endif
9630}
9631
9632void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
9633{
9634 gen_intermediate_code_internal(env, tb, 0);
9635}
9636
9637void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
9638{
9639 gen_intermediate_code_internal(env, tb, 1);
9640}
9641
9642void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
9643{
9644 env->nip = gen_opc_pc[pc_pos];
9645}
Qemu copy for testing