[qemu.git] / target-sparc / cpu.h

#ifndef CPU_SPARC_H
#define CPU_SPARC_H

#include "config.h"

#if !defined(TARGET_SPARC64)
#define TARGET_LONG_BITS 32
#define TARGET_FPREGS 32
#define TARGET_PAGE_BITS 12 /* 4k */
#else
#define TARGET_LONG_BITS 64
#define TARGET_FPREGS 64
#define TARGET_PAGE_BITS 12 /* XXX */
#endif

#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_HAS_ICE 1

#if !defined(TARGET_SPARC64)
#define ELF_MACHINE	EM_SPARC
#else
#define ELF_MACHINE	EM_SPARCV9
#endif

/*#define EXCP_INTERRUPT 0x100*/

/* trap definitions */
#ifndef TARGET_SPARC64
#define TT_TFAULT   0x01
#define TT_ILL_INSN 0x02
#define TT_PRIV_INSN 0x03
#define TT_NFPU_INSN 0x04
#define TT_WIN_OVF  0x05
#define TT_WIN_UNF  0x06 
#define TT_FP_EXCP  0x08
#define TT_DFAULT   0x09
#define TT_TOVF     0x0a
#define TT_EXTINT   0x10
#define TT_DIV_ZERO 0x2a
#define TT_NCP_INSN 0x24
#define TT_TRAP     0x80
#else
#define TT_TFAULT   0x08
#define TT_TMISS    0x09
#define TT_ILL_INSN 0x10
#define TT_PRIV_INSN 0x11
#define TT_NFPU_INSN 0x20
#define TT_FP_EXCP  0x21
#define TT_TOVF     0x23
#define TT_CLRWIN   0x24
#define TT_DIV_ZERO 0x28
#define TT_DFAULT   0x30
#define TT_DMISS    0x31
#define TT_DPROT    0x32
#define TT_PRIV_ACT 0x37
#define TT_EXTINT   0x40
#define TT_SPILL    0x80
#define TT_FILL     0xc0
#define TT_WOTHER   0x10
#define TT_TRAP     0x100
#endif

#define PSR_NEG   (1<<23)
#define PSR_ZERO  (1<<22)
#define PSR_OVF   (1<<21)
#define PSR_CARRY (1<<20)
#define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
#define PSR_EF    (1<<12)
#define PSR_PIL   0xf00
#define PSR_S     (1<<7)
#define PSR_PS    (1<<6)
#define PSR_ET    (1<<5)
#define PSR_CWP   0x1f

/* Trap base register */
#define TBR_BASE_MASK 0xfffff000

#if defined(TARGET_SPARC64)
#define PS_IG    (1<<11)
#define PS_MG    (1<<10)
#define PS_RED   (1<<5)
#define PS_PEF   (1<<4)
#define PS_AM    (1<<3)
#define PS_PRIV  (1<<2)
#define PS_IE    (1<<1)
#define PS_AG    (1<<0)

#define FPRS_FEF (1<<2)
#endif

/* Fcc */
#define FSR_RD1        (1<<31)
#define FSR_RD0        (1<<30)
#define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
#define FSR_RD_NEAREST 0
#define FSR_RD_ZERO    FSR_RD0
#define FSR_RD_POS     FSR_RD1
#define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)

#define FSR_NVM   (1<<27)
#define FSR_OFM   (1<<26)
#define FSR_UFM   (1<<25)
#define FSR_DZM   (1<<24)
#define FSR_NXM   (1<<23)
#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)

#define FSR_NVA   (1<<9)
#define FSR_OFA   (1<<8)
#define FSR_UFA   (1<<7)
#define FSR_DZA   (1<<6)
#define FSR_NXA   (1<<5)
#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)

#define FSR_NVC   (1<<4)
#define FSR_OFC   (1<<3)
#define FSR_UFC   (1<<2)
#define FSR_DZC   (1<<1)
#define FSR_NXC   (1<<0)
#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)

#define FSR_FTT2   (1<<16)
#define FSR_FTT1   (1<<15)
#define FSR_FTT0   (1<<14)
#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
#define FSR_FTT_IEEE_EXCP (1 << 14)
#define FSR_FTT_UNIMPFPOP (3 << 14)
#define FSR_FTT_INVAL_FPR (6 << 14)

#define FSR_FCC1  (1<<11)
#define FSR_FCC0  (1<<10)

/* MMU */
#define MMU_E	  (1<<0)
#define MMU_NF	  (1<<1)

#define PTE_ENTRYTYPE_MASK 3
#define PTE_ACCESS_MASK    0x1c
#define PTE_ACCESS_SHIFT   2
#define PTE_PPN_SHIFT      7
#define PTE_ADDR_MASK      0xffffff00

#define PG_ACCESSED_BIT	5
#define PG_MODIFIED_BIT	6
#define PG_CACHE_BIT    7

#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
#define PG_CACHE_MASK    (1 << PG_CACHE_BIT)

/* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
#define NWINDOWS  8

typedef struct sparc_def_t sparc_def_t;

typedef struct CPUSPARCState {
    target_ulong gregs[8]; /* general registers */
    target_ulong *regwptr; /* pointer to current register window */
    float32 fpr[TARGET_FPREGS];  /* floating point registers */
    target_ulong pc;       /* program counter */
    target_ulong npc;      /* next program counter */
    target_ulong y;        /* multiply/divide register */
    uint32_t psr;      /* processor state register */
    target_ulong fsr;      /* FPU state register */
    uint32_t cwp;      /* index of current register window (extracted
                          from PSR) */
    uint32_t wim;      /* window invalid mask */
    target_ulong tbr;  /* trap base register */
    int      psrs;     /* supervisor mode (extracted from PSR) */
    int      psrps;    /* previous supervisor mode */
    int      psret;    /* enable traps */
    uint32_t psrpil;   /* interrupt level */
    int      psref;    /* enable fpu */
    target_ulong version;
    jmp_buf  jmp_env;
    int user_mode_only;
    int exception_index;
    int interrupt_index;
    int interrupt_request;
    int halted;
    /* NOTE: we allow 8 more registers to handle wrapping */
    target_ulong regbase[NWINDOWS * 16 + 8];

    CPU_COMMON

    /* MMU regs */
#if defined(TARGET_SPARC64)
    uint64_t lsu;
#define DMMU_E 0x8
#define IMMU_E 0x4
    uint64_t immuregs[16];
    uint64_t dmmuregs[16];
    uint64_t itlb_tag[64];
    uint64_t itlb_tte[64];
    uint64_t dtlb_tag[64];
    uint64_t dtlb_tte[64];
#else
    uint32_t mmuregs[16];
#endif
    /* temporary float registers */
    float32 ft0, ft1;
    float64 dt0, dt1;
    float_status fp_status;
#if defined(TARGET_SPARC64)
#define MAXTL 4
    uint64_t t0, t1, t2;
    uint64_t tpc[MAXTL];
    uint64_t tnpc[MAXTL];
    uint64_t tstate[MAXTL];
    uint32_t tt[MAXTL];
    uint32_t xcc;		/* Extended integer condition codes */
    uint32_t asi;
    uint32_t pstate;
    uint32_t tl;
    uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
    uint64_t agregs[8]; /* alternate general registers */
    uint64_t bgregs[8]; /* backup for normal global registers */
    uint64_t igregs[8]; /* interrupt general registers */
    uint64_t mgregs[8]; /* mmu general registers */
    uint64_t fprs;
    uint64_t tick_cmpr, stick_cmpr;
    uint64_t gsr;
#endif
#if !defined(TARGET_SPARC64) && !defined(reg_T2)
    target_ulong t2;
#endif
} CPUSPARCState;
#if defined(TARGET_SPARC64)
#define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
#define PUT_FSR32(env, val) do { uint32_t _tmp = val;			\
	env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL);	\
    } while (0)
#define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
#define PUT_FSR64(env, val) do { uint64_t _tmp = val;	\
	env->fsr = _tmp & 0x3fcfc1c3ffULL;		\
    } while (0)
#else
#define GET_FSR32(env) (env->fsr)
#define PUT_FSR32(env, val) do { uint32_t _tmp = val;                   \
        env->fsr = (_tmp & 0xcfc1ffff) | (env->fsr & 0x000e0000);       \
    } while (0)
#endif

CPUSPARCState *cpu_sparc_init(void);
int cpu_sparc_exec(CPUSPARCState *s);
int cpu_sparc_close(CPUSPARCState *s);
int sparc_find_by_name (const unsigned char *name, const sparc_def_t **def);
void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
                                                 ...));
int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def);

#define GET_PSR(env) (env->version | (env->psr & PSR_ICC) |             \
		      (env->psref? PSR_EF : 0) |			\
		      (env->psrpil << 8) |				\
		      (env->psrs? PSR_S : 0) |				\
		      (env->psrps? PSR_PS : 0) |			\
		      (env->psret? PSR_ET : 0) | env->cwp)

#ifndef NO_CPU_IO_DEFS
void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
#endif

#define PUT_PSR(env, val) do { int _tmp = val;				\
	env->psr = _tmp & PSR_ICC;					\
	env->psref = (_tmp & PSR_EF)? 1 : 0;				\
	env->psrpil = (_tmp & PSR_PIL) >> 8;				\
	env->psrs = (_tmp & PSR_S)? 1 : 0;				\
	env->psrps = (_tmp & PSR_PS)? 1 : 0;				\
	env->psret = (_tmp & PSR_ET)? 1 : 0;				\
        cpu_set_cwp(env, _tmp & PSR_CWP);                               \
    } while (0)

#ifdef TARGET_SPARC64
#define GET_CCR(env) ((env->xcc << 4) | (env->psr & PSR_ICC))
#define PUT_CCR(env, val) do { int _tmp = val;				\
	env->xcc = _tmp >> 4;						\
	env->psr = (_tmp & 0xf) << 20;					\
    } while (0)
#endif

int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);

#include "cpu-all.h"

#endif
Commit	Line	Data
	1	#ifndef CPU_SPARC_H
	2	#define CPU_SPARC_H
	3
	4	#include "config.h"
	5
	6	#if !defined(TARGET_SPARC64)
	7	#define TARGET_LONG_BITS 32
	8	#define TARGET_FPREGS 32
	9	#define TARGET_PAGE_BITS 12 /* 4k */
	10	#else
	11	#define TARGET_LONG_BITS 64
	12	#define TARGET_FPREGS 64
	13	#define TARGET_PAGE_BITS 12 /* XXX */
	14	#endif
	15
	16	#include "cpu-defs.h"
	17
	18	#include "softfloat.h"
	19
	20	#define TARGET_HAS_ICE 1
	21
	22	#if !defined(TARGET_SPARC64)
	23	#define ELF_MACHINE EM_SPARC
	24	#else
	25	#define ELF_MACHINE EM_SPARCV9
	26	#endif
	27
	28	/#define EXCP_INTERRUPT 0x100/
	29
	30	/* trap definitions */
	31	#ifndef TARGET_SPARC64
	32	#define TT_TFAULT 0x01
	33	#define TT_ILL_INSN 0x02
	34	#define TT_PRIV_INSN 0x03
	35	#define TT_NFPU_INSN 0x04
	36	#define TT_WIN_OVF 0x05
	37	#define TT_WIN_UNF 0x06
	38	#define TT_FP_EXCP 0x08
	39	#define TT_DFAULT 0x09
	40	#define TT_TOVF 0x0a
	41	#define TT_EXTINT 0x10
	42	#define TT_DIV_ZERO 0x2a
	43	#define TT_NCP_INSN 0x24
	44	#define TT_TRAP 0x80
	45	#else
	46	#define TT_TFAULT 0x08
	47	#define TT_TMISS 0x09
	48	#define TT_ILL_INSN 0x10
	49	#define TT_PRIV_INSN 0x11
	50	#define TT_NFPU_INSN 0x20
	51	#define TT_FP_EXCP 0x21
	52	#define TT_TOVF 0x23
	53	#define TT_CLRWIN 0x24
	54	#define TT_DIV_ZERO 0x28
	55	#define TT_DFAULT 0x30
	56	#define TT_DMISS 0x31
	57	#define TT_DPROT 0x32
	58	#define TT_PRIV_ACT 0x37
	59	#define TT_EXTINT 0x40
	60	#define TT_SPILL 0x80
	61	#define TT_FILL 0xc0
	62	#define TT_WOTHER 0x10
	63	#define TT_TRAP 0x100
	64	#endif
	65
	66	#define PSR_NEG (1<<23)
	67	#define PSR_ZERO (1<<22)
	68	#define PSR_OVF (1<<21)
	69	#define PSR_CARRY (1<<20)
	70	#define PSR_ICC (PSR_NEG\|PSR_ZERO\|PSR_OVF\|PSR_CARRY)
	71	#define PSR_EF (1<<12)
	72	#define PSR_PIL 0xf00
	73	#define PSR_S (1<<7)
	74	#define PSR_PS (1<<6)
	75	#define PSR_ET (1<<5)
	76	#define PSR_CWP 0x1f
	77
	78	/* Trap base register */
	79	#define TBR_BASE_MASK 0xfffff000
	80
	81	#if defined(TARGET_SPARC64)
	82	#define PS_IG (1<<11)
	83	#define PS_MG (1<<10)
	84	#define PS_RED (1<<5)
	85	#define PS_PEF (1<<4)
	86	#define PS_AM (1<<3)
	87	#define PS_PRIV (1<<2)
	88	#define PS_IE (1<<1)
	89	#define PS_AG (1<<0)
	90
	91	#define FPRS_FEF (1<<2)
	92	#endif
	93
	94	/* Fcc */
	95	#define FSR_RD1 (1<<31)
	96	#define FSR_RD0 (1<<30)
	97	#define FSR_RD_MASK (FSR_RD1 \| FSR_RD0)
	98	#define FSR_RD_NEAREST 0
	99	#define FSR_RD_ZERO FSR_RD0
	100	#define FSR_RD_POS FSR_RD1
	101	#define FSR_RD_NEG (FSR_RD1 \| FSR_RD0)
	102
	103	#define FSR_NVM (1<<27)
	104	#define FSR_OFM (1<<26)
	105	#define FSR_UFM (1<<25)
	106	#define FSR_DZM (1<<24)
	107	#define FSR_NXM (1<<23)
	108	#define FSR_TEM_MASK (FSR_NVM \| FSR_OFM \| FSR_UFM \| FSR_DZM \| FSR_NXM)
	109
	110	#define FSR_NVA (1<<9)
	111	#define FSR_OFA (1<<8)
	112	#define FSR_UFA (1<<7)
	113	#define FSR_DZA (1<<6)
	114	#define FSR_NXA (1<<5)
	115	#define FSR_AEXC_MASK (FSR_NVA \| FSR_OFA \| FSR_UFA \| FSR_DZA \| FSR_NXA)
	116
	117	#define FSR_NVC (1<<4)
	118	#define FSR_OFC (1<<3)
	119	#define FSR_UFC (1<<2)
	120	#define FSR_DZC (1<<1)
	121	#define FSR_NXC (1<<0)
	122	#define FSR_CEXC_MASK (FSR_NVC \| FSR_OFC \| FSR_UFC \| FSR_DZC \| FSR_NXC)
	123
	124	#define FSR_FTT2 (1<<16)
	125	#define FSR_FTT1 (1<<15)
	126	#define FSR_FTT0 (1<<14)
	127	#define FSR_FTT_MASK (FSR_FTT2 \| FSR_FTT1 \| FSR_FTT0)
	128	#define FSR_FTT_IEEE_EXCP (1 << 14)
	129	#define FSR_FTT_UNIMPFPOP (3 << 14)
	130	#define FSR_FTT_INVAL_FPR (6 << 14)
	131
	132	#define FSR_FCC1 (1<<11)
	133	#define FSR_FCC0 (1<<10)
	134
	135	/* MMU */
	136	#define MMU_E (1<<0)
	137	#define MMU_NF (1<<1)
	138
	139	#define PTE_ENTRYTYPE_MASK 3
	140	#define PTE_ACCESS_MASK 0x1c
	141	#define PTE_ACCESS_SHIFT 2
	142	#define PTE_PPN_SHIFT 7
	143	#define PTE_ADDR_MASK 0xffffff00
	144
	145	#define PG_ACCESSED_BIT 5
	146	#define PG_MODIFIED_BIT 6
	147	#define PG_CACHE_BIT 7
	148
	149	#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
	150	#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
	151	#define PG_CACHE_MASK (1 << PG_CACHE_BIT)
	152
	153	/* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
	154	#define NWINDOWS 8
	155
	156	typedef struct sparc_def_t sparc_def_t;
	157
	158	typedef struct CPUSPARCState {
	159	target_ulong gregs[8]; /* general registers */
	160	target_ulong regwptr; / pointer to current register window */
	161	float32 fpr[TARGET_FPREGS]; /* floating point registers */
	162	target_ulong pc; /* program counter */
	163	target_ulong npc; /* next program counter */
	164	target_ulong y; /* multiply/divide register */
	165	uint32_t psr; /* processor state register */
	166	target_ulong fsr; /* FPU state register */
	167	uint32_t cwp; /* index of current register window (extracted
	168	from PSR) */
	169	uint32_t wim; /* window invalid mask */
	170	target_ulong tbr; /* trap base register */
	171	int psrs; /* supervisor mode (extracted from PSR) */
	172	int psrps; /* previous supervisor mode */
	173	int psret; /* enable traps */
	174	uint32_t psrpil; /* interrupt level */
	175	int psref; /* enable fpu */
	176	target_ulong version;
	177	jmp_buf jmp_env;
	178	int user_mode_only;
	179	int exception_index;
	180	int interrupt_index;
	181	int interrupt_request;
	182	int halted;
	183	/* NOTE: we allow 8 more registers to handle wrapping */
	184	target_ulong regbase[NWINDOWS * 16 + 8];
	185
	186	CPU_COMMON
	187
	188	/* MMU regs */
	189	#if defined(TARGET_SPARC64)
	190	uint64_t lsu;
	191	#define DMMU_E 0x8
	192	#define IMMU_E 0x4
	193	uint64_t immuregs[16];
	194	uint64_t dmmuregs[16];
	195	uint64_t itlb_tag[64];
	196	uint64_t itlb_tte[64];
	197	uint64_t dtlb_tag[64];
	198	uint64_t dtlb_tte[64];
	199	#else
	200	uint32_t mmuregs[16];
	201	#endif
	202	/* temporary float registers */
	203	float32 ft0, ft1;
	204	float64 dt0, dt1;
	205	float_status fp_status;
	206	#if defined(TARGET_SPARC64)
	207	#define MAXTL 4
	208	uint64_t t0, t1, t2;
	209	uint64_t tpc[MAXTL];
	210	uint64_t tnpc[MAXTL];
	211	uint64_t tstate[MAXTL];
	212	uint32_t tt[MAXTL];
	213	uint32_t xcc; /* Extended integer condition codes */
	214	uint32_t asi;
	215	uint32_t pstate;
	216	uint32_t tl;
	217	uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
	218	uint64_t agregs[8]; /* alternate general registers */
	219	uint64_t bgregs[8]; /* backup for normal global registers */
	220	uint64_t igregs[8]; /* interrupt general registers */
	221	uint64_t mgregs[8]; /* mmu general registers */
	222	uint64_t fprs;
	223	uint64_t tick_cmpr, stick_cmpr;
	224	uint64_t gsr;
	225	#endif
	226	#if !defined(TARGET_SPARC64) && !defined(reg_T2)
	227	target_ulong t2;
	228	#endif
	229	} CPUSPARCState;
	230	#if defined(TARGET_SPARC64)
	231	#define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
	232	#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
	233	env->fsr = (_tmp & 0xcfc1c3ff) \| (env->fsr & 0x3f00000000ULL); \
	234	} while (0)
	235	#define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
	236	#define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
	237	env->fsr = _tmp & 0x3fcfc1c3ffULL; \
	238	} while (0)
	239	#else
	240	#define GET_FSR32(env) (env->fsr)
	241	#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
	242	env->fsr = (_tmp & 0xcfc1ffff) \| (env->fsr & 0x000e0000); \
	243	} while (0)
	244	#endif
	245
	246	CPUSPARCState *cpu_sparc_init(void);
	247	int cpu_sparc_exec(CPUSPARCState *s);
	248	int cpu_sparc_close(CPUSPARCState *s);
	249	int sparc_find_by_name (const unsigned char name, const sparc_def_t *def);
	250	void sparc_cpu_list (FILE f, int (cpu_fprintf)(FILE f, const char fmt,
	251	...));
	252	int cpu_sparc_register (CPUSPARCState env, const sparc_def_t def);
	253
	254	#define GET_PSR(env) (env->version \| (env->psr & PSR_ICC) \| \
	255	(env->psref? PSR_EF : 0) \| \
	256	(env->psrpil << 8) \| \
	257	(env->psrs? PSR_S : 0) \| \
	258	(env->psrps? PSR_PS : 0) \| \
	259	(env->psret? PSR_ET : 0) \| env->cwp)
	260
	261	#ifndef NO_CPU_IO_DEFS
	262	void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
	263	#endif
	264
	265	#define PUT_PSR(env, val) do { int _tmp = val; \
	266	env->psr = _tmp & PSR_ICC; \
	267	env->psref = (_tmp & PSR_EF)? 1 : 0; \
	268	env->psrpil = (_tmp & PSR_PIL) >> 8; \
	269	env->psrs = (_tmp & PSR_S)? 1 : 0; \
	270	env->psrps = (_tmp & PSR_PS)? 1 : 0; \
	271	env->psret = (_tmp & PSR_ET)? 1 : 0; \
	272	cpu_set_cwp(env, _tmp & PSR_CWP); \
	273	} while (0)
	274
	275	#ifdef TARGET_SPARC64
	276	#define GET_CCR(env) ((env->xcc << 4) \| (env->psr & PSR_ICC))
	277	#define PUT_CCR(env, val) do { int _tmp = val; \
	278	env->xcc = _tmp >> 4; \
	279	env->psr = (_tmp & 0xf) << 20; \
	280	} while (0)
	281	#endif
	282
	283	int cpu_sparc_signal_handler(int host_signum, void pinfo, void puc);
	284
	285	#include "cpu-all.h"
	286
	287	#endif