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1#ifndef CPU_SPARC_H
2#define CPU_SPARC_H
3
4#include "config.h"
5#include "qemu-common.h"
6#include "bswap.h"
7
8#if !defined(TARGET_SPARC64)
9#define TARGET_LONG_BITS 32
10#define TARGET_DPREGS 16
11#define TARGET_PAGE_BITS 12 /* 4k */
12#define TARGET_PHYS_ADDR_SPACE_BITS 36
13#define TARGET_VIRT_ADDR_SPACE_BITS 32
14#else
15#define TARGET_LONG_BITS 64
16#define TARGET_DPREGS 32
17#define TARGET_PAGE_BITS 13 /* 8k */
18#define TARGET_PHYS_ADDR_SPACE_BITS 41
19# ifdef TARGET_ABI32
20# define TARGET_VIRT_ADDR_SPACE_BITS 32
21# else
22# define TARGET_VIRT_ADDR_SPACE_BITS 44
23# endif
24#endif
25
26#define CPUArchState struct CPUSPARCState
27
28#include "cpu-defs.h"
29
30#include "softfloat.h"
31
32#define TARGET_HAS_ICE 1
33
34#if !defined(TARGET_SPARC64)
35#define ELF_MACHINE EM_SPARC
36#else
37#define ELF_MACHINE EM_SPARCV9
38#endif
39
40/*#define EXCP_INTERRUPT 0x100*/
41
42/* trap definitions */
43#ifndef TARGET_SPARC64
44#define TT_TFAULT 0x01
45#define TT_ILL_INSN 0x02
46#define TT_PRIV_INSN 0x03
47#define TT_NFPU_INSN 0x04
48#define TT_WIN_OVF 0x05
49#define TT_WIN_UNF 0x06
50#define TT_UNALIGNED 0x07
51#define TT_FP_EXCP 0x08
52#define TT_DFAULT 0x09
53#define TT_TOVF 0x0a
54#define TT_EXTINT 0x10
55#define TT_CODE_ACCESS 0x21
56#define TT_UNIMP_FLUSH 0x25
57#define TT_DATA_ACCESS 0x29
58#define TT_DIV_ZERO 0x2a
59#define TT_NCP_INSN 0x24
60#define TT_TRAP 0x80
61#else
62#define TT_POWER_ON_RESET 0x01
63#define TT_TFAULT 0x08
64#define TT_CODE_ACCESS 0x0a
65#define TT_ILL_INSN 0x10
66#define TT_UNIMP_FLUSH TT_ILL_INSN
67#define TT_PRIV_INSN 0x11
68#define TT_NFPU_INSN 0x20
69#define TT_FP_EXCP 0x21
70#define TT_TOVF 0x23
71#define TT_CLRWIN 0x24
72#define TT_DIV_ZERO 0x28
73#define TT_DFAULT 0x30
74#define TT_DATA_ACCESS 0x32
75#define TT_UNALIGNED 0x34
76#define TT_PRIV_ACT 0x37
77#define TT_EXTINT 0x40
78#define TT_IVEC 0x60
79#define TT_TMISS 0x64
80#define TT_DMISS 0x68
81#define TT_DPROT 0x6c
82#define TT_SPILL 0x80
83#define TT_FILL 0xc0
84#define TT_WOTHER (1 << 5)
85#define TT_TRAP 0x100
86#endif
87
88#define PSR_NEG_SHIFT 23
89#define PSR_NEG (1 << PSR_NEG_SHIFT)
90#define PSR_ZERO_SHIFT 22
91#define PSR_ZERO (1 << PSR_ZERO_SHIFT)
92#define PSR_OVF_SHIFT 21
93#define PSR_OVF (1 << PSR_OVF_SHIFT)
94#define PSR_CARRY_SHIFT 20
95#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
96#define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
97#if !defined(TARGET_SPARC64)
98#define PSR_EF (1<<12)
99#define PSR_PIL 0xf00
100#define PSR_S (1<<7)
101#define PSR_PS (1<<6)
102#define PSR_ET (1<<5)
103#define PSR_CWP 0x1f
104#endif
105
106#define CC_SRC (env->cc_src)
107#define CC_SRC2 (env->cc_src2)
108#define CC_DST (env->cc_dst)
109#define CC_OP (env->cc_op)
110
111enum {
112 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
113 CC_OP_FLAGS, /* all cc are back in status register */
114 CC_OP_DIV, /* modify N, Z and V, C = 0*/
115 CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
116 CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
117 CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
118 CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
119 CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
120 CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
121 CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
122 CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
123 CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */
124 CC_OP_NB,
125};
126
127/* Trap base register */
128#define TBR_BASE_MASK 0xfffff000
129
130#if defined(TARGET_SPARC64)
131#define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */
132#define PS_IG (1<<11) /* v9, zero on UA2007 */
133#define PS_MG (1<<10) /* v9, zero on UA2007 */
134#define PS_CLE (1<<9) /* UA2007 */
135#define PS_TLE (1<<8) /* UA2007 */
136#define PS_RMO (1<<7)
137#define PS_RED (1<<5) /* v9, zero on UA2007 */
138#define PS_PEF (1<<4) /* enable fpu */
139#define PS_AM (1<<3) /* address mask */
140#define PS_PRIV (1<<2)
141#define PS_IE (1<<1)
142#define PS_AG (1<<0) /* v9, zero on UA2007 */
143
144#define FPRS_FEF (1<<2)
145
146#define HS_PRIV (1<<2)
147#endif
148
149/* Fcc */
150#define FSR_RD1 (1ULL << 31)
151#define FSR_RD0 (1ULL << 30)
152#define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
153#define FSR_RD_NEAREST 0
154#define FSR_RD_ZERO FSR_RD0
155#define FSR_RD_POS FSR_RD1
156#define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
157
158#define FSR_NVM (1ULL << 27)
159#define FSR_OFM (1ULL << 26)
160#define FSR_UFM (1ULL << 25)
161#define FSR_DZM (1ULL << 24)
162#define FSR_NXM (1ULL << 23)
163#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
164
165#define FSR_NVA (1ULL << 9)
166#define FSR_OFA (1ULL << 8)
167#define FSR_UFA (1ULL << 7)
168#define FSR_DZA (1ULL << 6)
169#define FSR_NXA (1ULL << 5)
170#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
171
172#define FSR_NVC (1ULL << 4)
173#define FSR_OFC (1ULL << 3)
174#define FSR_UFC (1ULL << 2)
175#define FSR_DZC (1ULL << 1)
176#define FSR_NXC (1ULL << 0)
177#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
178
179#define FSR_FTT2 (1ULL << 16)
180#define FSR_FTT1 (1ULL << 15)
181#define FSR_FTT0 (1ULL << 14)
182//gcc warns about constant overflow for ~FSR_FTT_MASK
183//#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
184#ifdef TARGET_SPARC64
185#define FSR_FTT_NMASK 0xfffffffffffe3fffULL
186#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
187#define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL
188#define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL
189#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
190#else
191#define FSR_FTT_NMASK 0xfffe3fffULL
192#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
193#define FSR_LDFSR_OLDMASK 0x000fc000ULL
194#endif
195#define FSR_LDFSR_MASK 0xcfc00fffULL
196#define FSR_FTT_IEEE_EXCP (1ULL << 14)
197#define FSR_FTT_UNIMPFPOP (3ULL << 14)
198#define FSR_FTT_SEQ_ERROR (4ULL << 14)
199#define FSR_FTT_INVAL_FPR (6ULL << 14)
200
201#define FSR_FCC1_SHIFT 11
202#define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT)
203#define FSR_FCC0_SHIFT 10
204#define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT)
205
206/* MMU */
207#define MMU_E (1<<0)
208#define MMU_NF (1<<1)
209
210#define PTE_ENTRYTYPE_MASK 3
211#define PTE_ACCESS_MASK 0x1c
212#define PTE_ACCESS_SHIFT 2
213#define PTE_PPN_SHIFT 7
214#define PTE_ADDR_MASK 0xffffff00
215
216#define PG_ACCESSED_BIT 5
217#define PG_MODIFIED_BIT 6
218#define PG_CACHE_BIT 7
219
220#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
221#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
222#define PG_CACHE_MASK (1 << PG_CACHE_BIT)
223
224/* 3 <= NWINDOWS <= 32. */
225#define MIN_NWINDOWS 3
226#define MAX_NWINDOWS 32
227
228#if !defined(TARGET_SPARC64)
229#define NB_MMU_MODES 2
230#else
231#define NB_MMU_MODES 6
232typedef struct trap_state {
233 uint64_t tpc;
234 uint64_t tnpc;
235 uint64_t tstate;
236 uint32_t tt;
237} trap_state;
238#endif
239
240typedef struct sparc_def_t {
241 const char *name;
242 target_ulong iu_version;
243 uint32_t fpu_version;
244 uint32_t mmu_version;
245 uint32_t mmu_bm;
246 uint32_t mmu_ctpr_mask;
247 uint32_t mmu_cxr_mask;
248 uint32_t mmu_sfsr_mask;
249 uint32_t mmu_trcr_mask;
250 uint32_t mxcc_version;
251 uint32_t features;
252 uint32_t nwindows;
253 uint32_t maxtl;
254} sparc_def_t;
255
256#define CPU_FEATURE_FLOAT (1 << 0)
257#define CPU_FEATURE_FLOAT128 (1 << 1)
258#define CPU_FEATURE_SWAP (1 << 2)
259#define CPU_FEATURE_MUL (1 << 3)
260#define CPU_FEATURE_DIV (1 << 4)
261#define CPU_FEATURE_FLUSH (1 << 5)
262#define CPU_FEATURE_FSQRT (1 << 6)
263#define CPU_FEATURE_FMUL (1 << 7)
264#define CPU_FEATURE_VIS1 (1 << 8)
265#define CPU_FEATURE_VIS2 (1 << 9)
266#define CPU_FEATURE_FSMULD (1 << 10)
267#define CPU_FEATURE_HYPV (1 << 11)
268#define CPU_FEATURE_CMT (1 << 12)
269#define CPU_FEATURE_GL (1 << 13)
270#define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */
271#define CPU_FEATURE_ASR17 (1 << 15)
272#define CPU_FEATURE_CACHE_CTRL (1 << 16)
273
274#ifndef TARGET_SPARC64
275#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
276 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
277 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
278 CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
279#else
280#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
281 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
282 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
283 CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
284 CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
285enum {
286 mmu_us_12, // Ultrasparc < III (64 entry TLB)
287 mmu_us_3, // Ultrasparc III (512 entry TLB)
288 mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages)
289 mmu_sun4v, // T1, T2
290};
291#endif
292
293#define TTE_VALID_BIT (1ULL << 63)
294#define TTE_NFO_BIT (1ULL << 60)
295#define TTE_USED_BIT (1ULL << 41)
296#define TTE_LOCKED_BIT (1ULL << 6)
297#define TTE_SIDEEFFECT_BIT (1ULL << 3)
298#define TTE_PRIV_BIT (1ULL << 2)
299#define TTE_W_OK_BIT (1ULL << 1)
300#define TTE_GLOBAL_BIT (1ULL << 0)
301
302#define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
303#define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT)
304#define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
305#define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
306#define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
307#define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT)
308#define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT)
309#define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)
310
311#define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT)
312#define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
313
314#define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL)
315#define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL)
316
317#define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */
318#define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */
319#define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */
320#define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */
321#define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */
322#define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */
323#define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */
324#define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */
325#define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */
326#define SFSR_PR_BIT (1ULL << 3) /* privilege mode */
327#define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */
328#define SFSR_OW_BIT (1ULL << 1) /* status overwritten */
329#define SFSR_VALID_BIT (1ULL << 0) /* status valid */
330
331#define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */
332#define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT)
333#define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */
334#define SFSR_CT_SECONDARY (1ULL << 4)
335#define SFSR_CT_NUCLEUS (2ULL << 4)
336#define SFSR_CT_NOTRANS (3ULL << 4)
337#define SFSR_CT_MASK (3ULL << 4)
338
339/* Leon3 cache control */
340
341/* Cache control: emulate the behavior of cache control registers but without
342 any effect on the emulated */
343
344#define CACHE_STATE_MASK 0x3
345#define CACHE_DISABLED 0x0
346#define CACHE_FROZEN 0x1
347#define CACHE_ENABLED 0x3
348
349/* Cache Control register fields */
350
351#define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */
352#define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */
353#define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */
354#define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */
355#define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */
356#define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */
357#define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */
358#define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */
359
360typedef struct SparcTLBEntry {
361 uint64_t tag;
362 uint64_t tte;
363} SparcTLBEntry;
364
365struct CPUTimer
366{
367 const char *name;
368 uint32_t frequency;
369 uint32_t disabled;
370 uint64_t disabled_mask;
371 int64_t clock_offset;
372 struct QEMUTimer *qtimer;
373};
374
375typedef struct CPUTimer CPUTimer;
376
377struct QEMUFile;
378void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
379void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
380
381typedef struct CPUSPARCState CPUSPARCState;
382
383struct CPUSPARCState {
384 target_ulong gregs[8]; /* general registers */
385 target_ulong *regwptr; /* pointer to current register window */
386 target_ulong pc; /* program counter */
387 target_ulong npc; /* next program counter */
388 target_ulong y; /* multiply/divide register */
389
390 /* emulator internal flags handling */
391 target_ulong cc_src, cc_src2;
392 target_ulong cc_dst;
393 uint32_t cc_op;
394
395 target_ulong cond; /* conditional branch result (XXX: save it in a
396 temporary register when possible) */
397
398 uint32_t psr; /* processor state register */
399 target_ulong fsr; /* FPU state register */
400 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */
401 uint32_t cwp; /* index of current register window (extracted
402 from PSR) */
403#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
404 uint32_t wim; /* window invalid mask */
405#endif
406 target_ulong tbr; /* trap base register */
407#if !defined(TARGET_SPARC64)
408 int psrs; /* supervisor mode (extracted from PSR) */
409 int psrps; /* previous supervisor mode */
410 int psret; /* enable traps */
411#endif
412 uint32_t psrpil; /* interrupt blocking level */
413 uint32_t pil_in; /* incoming interrupt level bitmap */
414#if !defined(TARGET_SPARC64)
415 int psref; /* enable fpu */
416#endif
417 int interrupt_index;
418 /* NOTE: we allow 8 more registers to handle wrapping */
419 target_ulong regbase[MAX_NWINDOWS * 16 + 8];
420
421 CPU_COMMON
422
423 target_ulong version;
424 uint32_t nwindows;
425
426 /* MMU regs */
427#if defined(TARGET_SPARC64)
428 uint64_t lsu;
429#define DMMU_E 0x8
430#define IMMU_E 0x4
431 //typedef struct SparcMMU
432 union {
433 uint64_t immuregs[16];
434 struct {
435 uint64_t tsb_tag_target;
436 uint64_t unused_mmu_primary_context; // use DMMU
437 uint64_t unused_mmu_secondary_context; // use DMMU
438 uint64_t sfsr;
439 uint64_t sfar;
440 uint64_t tsb;
441 uint64_t tag_access;
442 } immu;
443 };
444 union {
445 uint64_t dmmuregs[16];
446 struct {
447 uint64_t tsb_tag_target;
448 uint64_t mmu_primary_context;
449 uint64_t mmu_secondary_context;
450 uint64_t sfsr;
451 uint64_t sfar;
452 uint64_t tsb;
453 uint64_t tag_access;
454 } dmmu;
455 };
456 SparcTLBEntry itlb[64];
457 SparcTLBEntry dtlb[64];
458 uint32_t mmu_version;
459#else
460 uint32_t mmuregs[32];
461 uint64_t mxccdata[4];
462 uint64_t mxccregs[8];
463 uint32_t mmubpctrv, mmubpctrc, mmubpctrs;
464 uint64_t mmubpaction;
465 uint64_t mmubpregs[4];
466 uint64_t prom_addr;
467#endif
468 /* temporary float registers */
469 float128 qt0, qt1;
470 float_status fp_status;
471#if defined(TARGET_SPARC64)
472#define MAXTL_MAX 8
473#define MAXTL_MASK (MAXTL_MAX - 1)
474 trap_state ts[MAXTL_MAX];
475 uint32_t xcc; /* Extended integer condition codes */
476 uint32_t asi;
477 uint32_t pstate;
478 uint32_t tl;
479 uint32_t maxtl;
480 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
481 uint64_t agregs[8]; /* alternate general registers */
482 uint64_t bgregs[8]; /* backup for normal global registers */
483 uint64_t igregs[8]; /* interrupt general registers */
484 uint64_t mgregs[8]; /* mmu general registers */
485 uint64_t fprs;
486 uint64_t tick_cmpr, stick_cmpr;
487 CPUTimer *tick, *stick;
488#define TICK_NPT_MASK 0x8000000000000000ULL
489#define TICK_INT_DIS 0x8000000000000000ULL
490 uint64_t gsr;
491 uint32_t gl; // UA2005
492 /* UA 2005 hyperprivileged registers */
493 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
494 CPUTimer *hstick; // UA 2005
495 /* Interrupt vector registers */
496 uint64_t ivec_status;
497 uint64_t ivec_data[3];
498 uint32_t softint;
499#define SOFTINT_TIMER 1
500#define SOFTINT_STIMER (1 << 16)
501#define SOFTINT_INTRMASK (0xFFFE)
502#define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
503#endif
504 sparc_def_t *def;
505
506 void *irq_manager;
507 void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno);
508
509 /* Leon3 cache control */
510 uint32_t cache_control;
511};
512
513#include "cpu-qom.h"
514
515#ifndef NO_CPU_IO_DEFS
516/* cpu_init.c */
517SPARCCPU *cpu_sparc_init(const char *cpu_model);
518void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
519void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
520/* mmu_helper.c */
521int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
522 int mmu_idx);
523#define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault
524target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
525void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env);
526
527#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
528int target_memory_rw_debug(CPUSPARCState *env, target_ulong addr,
529 uint8_t *buf, int len, int is_write);
530#define TARGET_CPU_MEMORY_RW_DEBUG
531#endif
532
533
534/* translate.c */
535void gen_intermediate_code_init(CPUSPARCState *env);
536
537/* cpu-exec.c */
538int cpu_sparc_exec(CPUSPARCState *s);
539
540/* win_helper.c */
541target_ulong cpu_get_psr(CPUSPARCState *env1);
542void cpu_put_psr(CPUSPARCState *env1, target_ulong val);
543#ifdef TARGET_SPARC64
544target_ulong cpu_get_ccr(CPUSPARCState *env1);
545void cpu_put_ccr(CPUSPARCState *env1, target_ulong val);
546target_ulong cpu_get_cwp64(CPUSPARCState *env1);
547void cpu_put_cwp64(CPUSPARCState *env1, int cwp);
548void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate);
549#endif
550int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
551int cpu_cwp_dec(CPUSPARCState *env1, int cwp);
552void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
553
554/* int_helper.c */
555void do_interrupt(CPUSPARCState *env);
556void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno);
557
558/* sun4m.c, sun4u.c */
559void cpu_check_irqs(CPUSPARCState *env);
560
561/* leon3.c */
562void leon3_irq_ack(void *irq_manager, int intno);
563
564#if defined (TARGET_SPARC64)
565
566static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
567{
568 return (x & mask) == (y & mask);
569}
570
571#define MMU_CONTEXT_BITS 13
572#define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
573
574static inline int tlb_compare_context(const SparcTLBEntry *tlb,
575 uint64_t context)
576{
577 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
578}
579
580#endif
581#endif
582
583/* cpu-exec.c */
584#if !defined(CONFIG_USER_ONLY)
585void cpu_unassigned_access(CPUSPARCState *env1, hwaddr addr,
586 int is_write, int is_exec, int is_asi, int size);
587#if defined(TARGET_SPARC64)
588hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
589 int mmu_idx);
590#endif
591#endif
592int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
593
594#ifndef NO_CPU_IO_DEFS
595static inline CPUSPARCState *cpu_init(const char *cpu_model)
596{
597 SPARCCPU *cpu = cpu_sparc_init(cpu_model);
598 if (cpu == NULL) {
599 return NULL;
600 }
601 return &cpu->env;
602}
603#endif
604
605#define cpu_exec cpu_sparc_exec
606#define cpu_gen_code cpu_sparc_gen_code
607#define cpu_signal_handler cpu_sparc_signal_handler
608#define cpu_list sparc_cpu_list
609
610#define CPU_SAVE_VERSION 7
611
612/* MMU modes definitions */
613#if defined (TARGET_SPARC64)
614#define MMU_USER_IDX 0
615#define MMU_MODE0_SUFFIX _user
616#define MMU_USER_SECONDARY_IDX 1
617#define MMU_MODE1_SUFFIX _user_secondary
618#define MMU_KERNEL_IDX 2
619#define MMU_MODE2_SUFFIX _kernel
620#define MMU_KERNEL_SECONDARY_IDX 3
621#define MMU_MODE3_SUFFIX _kernel_secondary
622#define MMU_NUCLEUS_IDX 4
623#define MMU_MODE4_SUFFIX _nucleus
624#define MMU_HYPV_IDX 5
625#define MMU_MODE5_SUFFIX _hypv
626#else
627#define MMU_USER_IDX 0
628#define MMU_MODE0_SUFFIX _user
629#define MMU_KERNEL_IDX 1
630#define MMU_MODE1_SUFFIX _kernel
631#endif
632
633#if defined (TARGET_SPARC64)
634static inline int cpu_has_hypervisor(CPUSPARCState *env1)
635{
636 return env1->def->features & CPU_FEATURE_HYPV;
637}
638
639static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
640{
641 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
642}
643
644static inline int cpu_supervisor_mode(CPUSPARCState *env1)
645{
646 return env1->pstate & PS_PRIV;
647}
648#endif
649
650static inline int cpu_mmu_index(CPUSPARCState *env1)
651{
652#if defined(CONFIG_USER_ONLY)
653 return MMU_USER_IDX;
654#elif !defined(TARGET_SPARC64)
655 return env1->psrs;
656#else
657 if (env1->tl > 0) {
658 return MMU_NUCLEUS_IDX;
659 } else if (cpu_hypervisor_mode(env1)) {
660 return MMU_HYPV_IDX;
661 } else if (cpu_supervisor_mode(env1)) {
662 return MMU_KERNEL_IDX;
663 } else {
664 return MMU_USER_IDX;
665 }
666#endif
667}
668
669static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
670{
671#if !defined (TARGET_SPARC64)
672 if (env1->psret != 0)
673 return 1;
674#else
675 if (env1->pstate & PS_IE)
676 return 1;
677#endif
678
679 return 0;
680}
681
682static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
683{
684#if !defined(TARGET_SPARC64)
685 /* level 15 is non-maskable on sparc v8 */
686 return pil == 15 || pil > env1->psrpil;
687#else
688 return pil > env1->psrpil;
689#endif
690}
691
692#if defined(CONFIG_USER_ONLY)
693static inline void cpu_clone_regs(CPUSPARCState *env, target_ulong newsp)
694{
695 if (newsp)
696 env->regwptr[22] = newsp;
697 env->regwptr[0] = 0;
698 /* FIXME: Do we also need to clear CF? */
699 /* XXXXX */
700 printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
701}
702#endif
703
704#include "cpu-all.h"
705
706#ifdef TARGET_SPARC64
707/* sun4u.c */
708void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
709uint64_t cpu_tick_get_count(CPUTimer *timer);
710void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
711trap_state* cpu_tsptr(CPUSPARCState* env);
712#endif
713
714#define TB_FLAG_FPU_ENABLED (1 << 4)
715#define TB_FLAG_AM_ENABLED (1 << 5)
716
717static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
718 target_ulong *cs_base, int *flags)
719{
720 *pc = env->pc;
721 *cs_base = env->npc;
722#ifdef TARGET_SPARC64
723 // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
724 *flags = (env->pstate & PS_PRIV) /* 2 */
725 | ((env->lsu & (DMMU_E | IMMU_E)) >> 2) /* 1, 0 */
726 | ((env->tl & 0xff) << 8)
727 | (env->dmmu.mmu_primary_context << 16); /* 16... */
728 if (env->pstate & PS_AM) {
729 *flags |= TB_FLAG_AM_ENABLED;
730 }
731 if ((env->def->features & CPU_FEATURE_FLOAT) && (env->pstate & PS_PEF)
732 && (env->fprs & FPRS_FEF)) {
733 *flags |= TB_FLAG_FPU_ENABLED;
734 }
735#else
736 // FPU enable . Supervisor
737 *flags = env->psrs;
738 if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
739 *flags |= TB_FLAG_FPU_ENABLED;
740 }
741#endif
742}
743
744static inline bool tb_fpu_enabled(int tb_flags)
745{
746#if defined(CONFIG_USER_ONLY)
747 return true;
748#else
749 return tb_flags & TB_FLAG_FPU_ENABLED;
750#endif
751}
752
753static inline bool tb_am_enabled(int tb_flags)
754{
755#ifndef TARGET_SPARC64
756 return false;
757#else
758 return tb_flags & TB_FLAG_AM_ENABLED;
759#endif
760}
761
762static inline bool cpu_has_work(CPUState *cpu)
763{
764 CPUSPARCState *env1 = &SPARC_CPU(cpu)->env;
765
766 return (env1->interrupt_request & CPU_INTERRUPT_HARD) &&
767 cpu_interrupts_enabled(env1);
768}
769
770#include "exec-all.h"
771
772static inline void cpu_pc_from_tb(CPUSPARCState *env, TranslationBlock *tb)
773{
774 env->pc = tb->pc;
775 env->npc = tb->cs_base;
776}
777
778#endif
Qemu copy for testing