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1 | /* | |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net> | |
5 | * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
26 | #include "tcg-be-null.h" | |
27 | ||
28 | /* | |
29 | * Register definitions | |
30 | */ | |
31 | ||
32 | #ifndef NDEBUG | |
33 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { | |
34 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
35 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
36 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
37 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
38 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", | |
39 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
40 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
41 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
42 | }; | |
43 | #endif | |
44 | ||
45 | #ifdef CONFIG_USE_GUEST_BASE | |
46 | #define TCG_GUEST_BASE_REG TCG_REG_R55 | |
47 | #else | |
48 | #define TCG_GUEST_BASE_REG TCG_REG_R0 | |
49 | #endif | |
50 | #ifndef GUEST_BASE | |
51 | #define GUEST_BASE 0 | |
52 | #endif | |
53 | ||
54 | /* Branch registers */ | |
55 | enum { | |
56 | TCG_REG_B0 = 0, | |
57 | TCG_REG_B1, | |
58 | TCG_REG_B2, | |
59 | TCG_REG_B3, | |
60 | TCG_REG_B4, | |
61 | TCG_REG_B5, | |
62 | TCG_REG_B6, | |
63 | TCG_REG_B7, | |
64 | }; | |
65 | ||
66 | /* Floating point registers */ | |
67 | enum { | |
68 | TCG_REG_F0 = 0, | |
69 | TCG_REG_F1, | |
70 | TCG_REG_F2, | |
71 | TCG_REG_F3, | |
72 | TCG_REG_F4, | |
73 | TCG_REG_F5, | |
74 | TCG_REG_F6, | |
75 | TCG_REG_F7, | |
76 | TCG_REG_F8, | |
77 | TCG_REG_F9, | |
78 | TCG_REG_F10, | |
79 | TCG_REG_F11, | |
80 | TCG_REG_F12, | |
81 | TCG_REG_F13, | |
82 | TCG_REG_F14, | |
83 | TCG_REG_F15, | |
84 | }; | |
85 | ||
86 | /* Predicate registers */ | |
87 | enum { | |
88 | TCG_REG_P0 = 0, | |
89 | TCG_REG_P1, | |
90 | TCG_REG_P2, | |
91 | TCG_REG_P3, | |
92 | TCG_REG_P4, | |
93 | TCG_REG_P5, | |
94 | TCG_REG_P6, | |
95 | TCG_REG_P7, | |
96 | TCG_REG_P8, | |
97 | TCG_REG_P9, | |
98 | TCG_REG_P10, | |
99 | TCG_REG_P11, | |
100 | TCG_REG_P12, | |
101 | TCG_REG_P13, | |
102 | TCG_REG_P14, | |
103 | TCG_REG_P15, | |
104 | }; | |
105 | ||
106 | /* Application registers */ | |
107 | enum { | |
108 | TCG_REG_PFS = 64, | |
109 | }; | |
110 | ||
111 | static const int tcg_target_reg_alloc_order[] = { | |
112 | TCG_REG_R33, | |
113 | TCG_REG_R35, | |
114 | TCG_REG_R36, | |
115 | TCG_REG_R37, | |
116 | TCG_REG_R38, | |
117 | TCG_REG_R39, | |
118 | TCG_REG_R40, | |
119 | TCG_REG_R41, | |
120 | TCG_REG_R42, | |
121 | TCG_REG_R43, | |
122 | TCG_REG_R44, | |
123 | TCG_REG_R45, | |
124 | TCG_REG_R46, | |
125 | TCG_REG_R47, | |
126 | TCG_REG_R48, | |
127 | TCG_REG_R49, | |
128 | TCG_REG_R50, | |
129 | TCG_REG_R51, | |
130 | TCG_REG_R52, | |
131 | TCG_REG_R53, | |
132 | TCG_REG_R54, | |
133 | TCG_REG_R55, | |
134 | TCG_REG_R14, | |
135 | TCG_REG_R15, | |
136 | TCG_REG_R16, | |
137 | TCG_REG_R17, | |
138 | TCG_REG_R18, | |
139 | TCG_REG_R19, | |
140 | TCG_REG_R20, | |
141 | TCG_REG_R21, | |
142 | TCG_REG_R22, | |
143 | TCG_REG_R23, | |
144 | TCG_REG_R24, | |
145 | TCG_REG_R25, | |
146 | TCG_REG_R26, | |
147 | TCG_REG_R27, | |
148 | TCG_REG_R28, | |
149 | TCG_REG_R29, | |
150 | TCG_REG_R30, | |
151 | TCG_REG_R31, | |
152 | TCG_REG_R56, | |
153 | TCG_REG_R57, | |
154 | TCG_REG_R58, | |
155 | TCG_REG_R59, | |
156 | TCG_REG_R60, | |
157 | TCG_REG_R61, | |
158 | TCG_REG_R62, | |
159 | TCG_REG_R63, | |
160 | TCG_REG_R8, | |
161 | TCG_REG_R9, | |
162 | TCG_REG_R10, | |
163 | TCG_REG_R11 | |
164 | }; | |
165 | ||
166 | static const int tcg_target_call_iarg_regs[8] = { | |
167 | TCG_REG_R56, | |
168 | TCG_REG_R57, | |
169 | TCG_REG_R58, | |
170 | TCG_REG_R59, | |
171 | TCG_REG_R60, | |
172 | TCG_REG_R61, | |
173 | TCG_REG_R62, | |
174 | TCG_REG_R63, | |
175 | }; | |
176 | ||
177 | static const int tcg_target_call_oarg_regs[] = { | |
178 | TCG_REG_R8 | |
179 | }; | |
180 | ||
181 | /* | |
182 | * opcode formation | |
183 | */ | |
184 | ||
185 | /* bundle templates: stops (double bar in the IA64 manual) are marked with | |
186 | an uppercase letter. */ | |
187 | enum { | |
188 | mii = 0x00, | |
189 | miI = 0x01, | |
190 | mIi = 0x02, | |
191 | mII = 0x03, | |
192 | mlx = 0x04, | |
193 | mLX = 0x05, | |
194 | mmi = 0x08, | |
195 | mmI = 0x09, | |
196 | Mmi = 0x0a, | |
197 | MmI = 0x0b, | |
198 | mfi = 0x0c, | |
199 | mfI = 0x0d, | |
200 | mmf = 0x0e, | |
201 | mmF = 0x0f, | |
202 | mib = 0x10, | |
203 | miB = 0x11, | |
204 | mbb = 0x12, | |
205 | mbB = 0x13, | |
206 | bbb = 0x16, | |
207 | bbB = 0x17, | |
208 | mmb = 0x18, | |
209 | mmB = 0x19, | |
210 | mfb = 0x1c, | |
211 | mfB = 0x1d, | |
212 | }; | |
213 | ||
214 | enum { | |
215 | OPC_ADD_A1 = 0x10000000000ull, | |
216 | OPC_AND_A1 = 0x10060000000ull, | |
217 | OPC_AND_A3 = 0x10160000000ull, | |
218 | OPC_ANDCM_A1 = 0x10068000000ull, | |
219 | OPC_ANDCM_A3 = 0x10168000000ull, | |
220 | OPC_ADDS_A4 = 0x10800000000ull, | |
221 | OPC_ADDL_A5 = 0x12000000000ull, | |
222 | OPC_ALLOC_M34 = 0x02c00000000ull, | |
223 | OPC_BR_DPTK_FEW_B1 = 0x08400000000ull, | |
224 | OPC_BR_SPTK_MANY_B1 = 0x08000001000ull, | |
225 | OPC_BR_SPTK_MANY_B4 = 0x00100001000ull, | |
226 | OPC_BR_CALL_SPTK_MANY_B5 = 0x02100001000ull, | |
227 | OPC_BR_RET_SPTK_MANY_B4 = 0x00108001100ull, | |
228 | OPC_BRL_SPTK_MANY_X3 = 0x18000001000ull, | |
229 | OPC_BRL_CALL_SPTK_MANY_X4 = 0x1a000001000ull, | |
230 | OPC_CMP_LT_A6 = 0x18000000000ull, | |
231 | OPC_CMP_LTU_A6 = 0x1a000000000ull, | |
232 | OPC_CMP_EQ_A6 = 0x1c000000000ull, | |
233 | OPC_CMP4_LT_A6 = 0x18400000000ull, | |
234 | OPC_CMP4_LTU_A6 = 0x1a400000000ull, | |
235 | OPC_CMP4_EQ_A6 = 0x1c400000000ull, | |
236 | OPC_DEP_I14 = 0x0ae00000000ull, | |
237 | OPC_DEP_I15 = 0x08000000000ull, | |
238 | OPC_DEP_Z_I12 = 0x0a600000000ull, | |
239 | OPC_EXTR_I11 = 0x0a400002000ull, | |
240 | OPC_EXTR_U_I11 = 0x0a400000000ull, | |
241 | OPC_FCVT_FX_TRUNC_S1_F10 = 0x004d0000000ull, | |
242 | OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull, | |
243 | OPC_FCVT_XF_F11 = 0x000e0000000ull, | |
244 | OPC_FMA_S1_F1 = 0x10400000000ull, | |
245 | OPC_FNMA_S1_F1 = 0x18400000000ull, | |
246 | OPC_FRCPA_S1_F6 = 0x00600000000ull, | |
247 | OPC_GETF_SIG_M19 = 0x08708000000ull, | |
248 | OPC_LD1_M1 = 0x08000000000ull, | |
249 | OPC_LD1_M3 = 0x0a000000000ull, | |
250 | OPC_LD2_M1 = 0x08040000000ull, | |
251 | OPC_LD2_M3 = 0x0a040000000ull, | |
252 | OPC_LD4_M1 = 0x08080000000ull, | |
253 | OPC_LD4_M3 = 0x0a080000000ull, | |
254 | OPC_LD8_M1 = 0x080c0000000ull, | |
255 | OPC_LD8_M3 = 0x0a0c0000000ull, | |
256 | OPC_MUX1_I3 = 0x0eca0000000ull, | |
257 | OPC_NOP_B9 = 0x04008000000ull, | |
258 | OPC_NOP_F16 = 0x00008000000ull, | |
259 | OPC_NOP_I18 = 0x00008000000ull, | |
260 | OPC_NOP_M48 = 0x00008000000ull, | |
261 | OPC_MOV_I21 = 0x00e00100000ull, | |
262 | OPC_MOV_RET_I21 = 0x00e00500000ull, | |
263 | OPC_MOV_I22 = 0x00188000000ull, | |
264 | OPC_MOV_I_I26 = 0x00150000000ull, | |
265 | OPC_MOVL_X2 = 0x0c000000000ull, | |
266 | OPC_OR_A1 = 0x10070000000ull, | |
267 | OPC_SETF_EXP_M18 = 0x0c748000000ull, | |
268 | OPC_SETF_SIG_M18 = 0x0c708000000ull, | |
269 | OPC_SHL_I7 = 0x0f240000000ull, | |
270 | OPC_SHR_I5 = 0x0f220000000ull, | |
271 | OPC_SHR_U_I5 = 0x0f200000000ull, | |
272 | OPC_SHRP_I10 = 0x0ac00000000ull, | |
273 | OPC_SXT1_I29 = 0x000a0000000ull, | |
274 | OPC_SXT2_I29 = 0x000a8000000ull, | |
275 | OPC_SXT4_I29 = 0x000b0000000ull, | |
276 | OPC_ST1_M4 = 0x08c00000000ull, | |
277 | OPC_ST2_M4 = 0x08c40000000ull, | |
278 | OPC_ST4_M4 = 0x08c80000000ull, | |
279 | OPC_ST8_M4 = 0x08cc0000000ull, | |
280 | OPC_SUB_A1 = 0x10028000000ull, | |
281 | OPC_SUB_A3 = 0x10128000000ull, | |
282 | OPC_UNPACK4_L_I2 = 0x0f860000000ull, | |
283 | OPC_XMA_L_F2 = 0x1d000000000ull, | |
284 | OPC_XOR_A1 = 0x10078000000ull, | |
285 | OPC_ZXT1_I29 = 0x00080000000ull, | |
286 | OPC_ZXT2_I29 = 0x00088000000ull, | |
287 | OPC_ZXT4_I29 = 0x00090000000ull, | |
288 | ||
289 | INSN_NOP_M = OPC_NOP_M48, /* nop.m 0 */ | |
290 | INSN_NOP_I = OPC_NOP_I18, /* nop.i 0 */ | |
291 | }; | |
292 | ||
293 | static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1, | |
294 | int r2, int r3) | |
295 | { | |
296 | return opc | |
297 | | ((r3 & 0x7f) << 20) | |
298 | | ((r2 & 0x7f) << 13) | |
299 | | ((r1 & 0x7f) << 6) | |
300 | | (qp & 0x3f); | |
301 | } | |
302 | ||
303 | static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1, | |
304 | uint64_t imm, int r3) | |
305 | { | |
306 | return opc | |
307 | | ((imm & 0x80) << 29) /* s */ | |
308 | | ((imm & 0x7f) << 13) /* imm7b */ | |
309 | | ((r3 & 0x7f) << 20) | |
310 | | ((r1 & 0x7f) << 6) | |
311 | | (qp & 0x3f); | |
312 | } | |
313 | ||
314 | static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1, | |
315 | uint64_t imm, int r3) | |
316 | { | |
317 | return opc | |
318 | | ((imm & 0x2000) << 23) /* s */ | |
319 | | ((imm & 0x1f80) << 20) /* imm6d */ | |
320 | | ((imm & 0x007f) << 13) /* imm7b */ | |
321 | | ((r3 & 0x7f) << 20) | |
322 | | ((r1 & 0x7f) << 6) | |
323 | | (qp & 0x3f); | |
324 | } | |
325 | ||
326 | static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1, | |
327 | uint64_t imm, int r3) | |
328 | { | |
329 | return opc | |
330 | | ((imm & 0x200000) << 15) /* s */ | |
331 | | ((imm & 0x1f0000) << 6) /* imm5c */ | |
332 | | ((imm & 0x00ff80) << 20) /* imm9d */ | |
333 | | ((imm & 0x00007f) << 13) /* imm7b */ | |
334 | | ((r3 & 0x03) << 20) | |
335 | | ((r1 & 0x7f) << 6) | |
336 | | (qp & 0x3f); | |
337 | } | |
338 | ||
339 | static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1, | |
340 | int p2, int r2, int r3) | |
341 | { | |
342 | return opc | |
343 | | ((p2 & 0x3f) << 27) | |
344 | | ((r3 & 0x7f) << 20) | |
345 | | ((r2 & 0x7f) << 13) | |
346 | | ((p1 & 0x3f) << 6) | |
347 | | (qp & 0x3f); | |
348 | } | |
349 | ||
350 | static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm) | |
351 | { | |
352 | return opc | |
353 | | ((imm & 0x100000) << 16) /* s */ | |
354 | | ((imm & 0x0fffff) << 13) /* imm20b */ | |
355 | | (qp & 0x3f); | |
356 | } | |
357 | ||
358 | static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2) | |
359 | { | |
360 | return opc | |
361 | | ((b2 & 0x7) << 13) | |
362 | | (qp & 0x3f); | |
363 | } | |
364 | ||
365 | static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2) | |
366 | { | |
367 | return opc | |
368 | | ((b2 & 0x7) << 13) | |
369 | | ((b1 & 0x7) << 6) | |
370 | | (qp & 0x3f); | |
371 | } | |
372 | ||
373 | ||
374 | static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm) | |
375 | { | |
376 | return opc | |
377 | | ((imm & 0x100000) << 16) /* i */ | |
378 | | ((imm & 0x0fffff) << 6) /* imm20a */ | |
379 | | (qp & 0x3f); | |
380 | } | |
381 | ||
382 | static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1, | |
383 | int f3, int f4, int f2) | |
384 | { | |
385 | return opc | |
386 | | ((f4 & 0x7f) << 27) | |
387 | | ((f3 & 0x7f) << 20) | |
388 | | ((f2 & 0x7f) << 13) | |
389 | | ((f1 & 0x7f) << 6) | |
390 | | (qp & 0x3f); | |
391 | } | |
392 | ||
393 | static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1, | |
394 | int f3, int f4, int f2) | |
395 | { | |
396 | return opc | |
397 | | ((f4 & 0x7f) << 27) | |
398 | | ((f3 & 0x7f) << 20) | |
399 | | ((f2 & 0x7f) << 13) | |
400 | | ((f1 & 0x7f) << 6) | |
401 | | (qp & 0x3f); | |
402 | } | |
403 | ||
404 | static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1, | |
405 | int p2, int f2, int f3) | |
406 | { | |
407 | return opc | |
408 | | ((p2 & 0x3f) << 27) | |
409 | | ((f3 & 0x7f) << 20) | |
410 | | ((f2 & 0x7f) << 13) | |
411 | | ((f1 & 0x7f) << 6) | |
412 | | (qp & 0x3f); | |
413 | } | |
414 | ||
415 | static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2) | |
416 | { | |
417 | return opc | |
418 | | ((f2 & 0x7f) << 13) | |
419 | | ((f1 & 0x7f) << 6) | |
420 | | (qp & 0x3f); | |
421 | } | |
422 | ||
423 | static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2) | |
424 | { | |
425 | return opc | |
426 | | ((f2 & 0x7f) << 13) | |
427 | | ((f1 & 0x7f) << 6) | |
428 | | (qp & 0x3f); | |
429 | } | |
430 | ||
431 | static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm) | |
432 | { | |
433 | return opc | |
434 | | ((imm & 0x100000) << 16) /* i */ | |
435 | | ((imm & 0x0fffff) << 6) /* imm20a */ | |
436 | | (qp & 0x3f); | |
437 | } | |
438 | ||
439 | static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1, | |
440 | int r2, int r3) | |
441 | { | |
442 | return opc | |
443 | | ((r3 & 0x7f) << 20) | |
444 | | ((r2 & 0x7f) << 13) | |
445 | | ((r1 & 0x7f) << 6) | |
446 | | (qp & 0x3f); | |
447 | } | |
448 | ||
449 | static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1, | |
450 | int r2, int mbtype) | |
451 | { | |
452 | return opc | |
453 | | ((mbtype & 0x0f) << 20) | |
454 | | ((r2 & 0x7f) << 13) | |
455 | | ((r1 & 0x7f) << 6) | |
456 | | (qp & 0x3f); | |
457 | } | |
458 | ||
459 | static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1, | |
460 | int r3, int r2) | |
461 | { | |
462 | return opc | |
463 | | ((r3 & 0x7f) << 20) | |
464 | | ((r2 & 0x7f) << 13) | |
465 | | ((r1 & 0x7f) << 6) | |
466 | | (qp & 0x3f); | |
467 | } | |
468 | ||
469 | static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1, | |
470 | int r2, int r3) | |
471 | { | |
472 | return opc | |
473 | | ((r3 & 0x7f) << 20) | |
474 | | ((r2 & 0x7f) << 13) | |
475 | | ((r1 & 0x7f) << 6) | |
476 | | (qp & 0x3f); | |
477 | } | |
478 | ||
479 | static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1, | |
480 | int r2, int r3, uint64_t count) | |
481 | { | |
482 | return opc | |
483 | | ((count & 0x3f) << 27) | |
484 | | ((r3 & 0x7f) << 20) | |
485 | | ((r2 & 0x7f) << 13) | |
486 | | ((r1 & 0x7f) << 6) | |
487 | | (qp & 0x3f); | |
488 | } | |
489 | ||
490 | static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1, | |
491 | int r3, uint64_t pos, uint64_t len) | |
492 | { | |
493 | return opc | |
494 | | ((len & 0x3f) << 27) | |
495 | | ((r3 & 0x7f) << 20) | |
496 | | ((pos & 0x3f) << 14) | |
497 | | ((r1 & 0x7f) << 6) | |
498 | | (qp & 0x3f); | |
499 | } | |
500 | ||
501 | static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1, | |
502 | int r2, uint64_t pos, uint64_t len) | |
503 | { | |
504 | return opc | |
505 | | ((len & 0x3f) << 27) | |
506 | | ((pos & 0x3f) << 20) | |
507 | | ((r2 & 0x7f) << 13) | |
508 | | ((r1 & 0x7f) << 6) | |
509 | | (qp & 0x3f); | |
510 | } | |
511 | ||
512 | static inline uint64_t tcg_opc_i14(int qp, uint64_t opc, int r1, uint64_t imm, | |
513 | int r3, uint64_t pos, uint64_t len) | |
514 | { | |
515 | return opc | |
516 | | ((imm & 0x01) << 36) | |
517 | | ((len & 0x3f) << 27) | |
518 | | ((r3 & 0x7f) << 20) | |
519 | | ((pos & 0x3f) << 14) | |
520 | | ((r1 & 0x7f) << 6) | |
521 | | (qp & 0x3f); | |
522 | } | |
523 | ||
524 | static inline uint64_t tcg_opc_i15(int qp, uint64_t opc, int r1, int r2, | |
525 | int r3, uint64_t pos, uint64_t len) | |
526 | { | |
527 | return opc | |
528 | | ((pos & 0x3f) << 31) | |
529 | | ((len & 0x0f) << 27) | |
530 | | ((r3 & 0x7f) << 20) | |
531 | | ((r2 & 0x7f) << 13) | |
532 | | ((r1 & 0x7f) << 6) | |
533 | | (qp & 0x3f); | |
534 | } | |
535 | ||
536 | static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm) | |
537 | { | |
538 | return opc | |
539 | | ((imm & 0x100000) << 16) /* i */ | |
540 | | ((imm & 0x0fffff) << 6) /* imm20a */ | |
541 | | (qp & 0x3f); | |
542 | } | |
543 | ||
544 | static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1, | |
545 | int r2, uint64_t imm) | |
546 | { | |
547 | return opc | |
548 | | ((imm & 0x1ff) << 24) | |
549 | | ((r2 & 0x7f) << 13) | |
550 | | ((b1 & 0x7) << 6) | |
551 | | (qp & 0x3f); | |
552 | } | |
553 | ||
554 | static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2) | |
555 | { | |
556 | return opc | |
557 | | ((b2 & 0x7) << 13) | |
558 | | ((r1 & 0x7f) << 6) | |
559 | | (qp & 0x3f); | |
560 | } | |
561 | ||
562 | static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2) | |
563 | { | |
564 | return opc | |
565 | | ((ar3 & 0x7f) << 20) | |
566 | | ((r2 & 0x7f) << 13) | |
567 | | (qp & 0x3f); | |
568 | } | |
569 | ||
570 | static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3) | |
571 | { | |
572 | return opc | |
573 | | ((r3 & 0x7f) << 20) | |
574 | | ((r1 & 0x7f) << 6) | |
575 | | (qp & 0x3f); | |
576 | } | |
577 | ||
578 | static inline uint64_t tcg_opc_l2(uint64_t imm) | |
579 | { | |
580 | return (imm & 0x7fffffffffc00000ull) >> 22; | |
581 | } | |
582 | ||
583 | static inline uint64_t tcg_opc_l3(uint64_t imm) | |
584 | { | |
585 | return (imm & 0x07fffffffff00000ull) >> 18; | |
586 | } | |
587 | ||
588 | #define tcg_opc_l4 tcg_opc_l3 | |
589 | ||
590 | static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3) | |
591 | { | |
592 | return opc | |
593 | | ((r3 & 0x7f) << 20) | |
594 | | ((r1 & 0x7f) << 6) | |
595 | | (qp & 0x3f); | |
596 | } | |
597 | ||
598 | static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1, | |
599 | int r3, uint64_t imm) | |
600 | { | |
601 | return opc | |
602 | | ((imm & 0x100) << 28) /* s */ | |
603 | | ((imm & 0x080) << 20) /* i */ | |
604 | | ((imm & 0x07f) << 13) /* imm7b */ | |
605 | | ((r3 & 0x7f) << 20) | |
606 | | ((r1 & 0x7f) << 6) | |
607 | | (qp & 0x3f); | |
608 | } | |
609 | ||
610 | static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3) | |
611 | { | |
612 | return opc | |
613 | | ((r3 & 0x7f) << 20) | |
614 | | ((r2 & 0x7f) << 13) | |
615 | | (qp & 0x3f); | |
616 | } | |
617 | ||
618 | static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2) | |
619 | { | |
620 | return opc | |
621 | | ((r2 & 0x7f) << 13) | |
622 | | ((f1 & 0x7f) << 6) | |
623 | | (qp & 0x3f); | |
624 | } | |
625 | ||
626 | static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2) | |
627 | { | |
628 | return opc | |
629 | | ((f2 & 0x7f) << 13) | |
630 | | ((r1 & 0x7f) << 6) | |
631 | | (qp & 0x3f); | |
632 | } | |
633 | ||
634 | static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1, | |
635 | int sof, int sol, int sor) | |
636 | { | |
637 | return opc | |
638 | | ((sor & 0x0f) << 27) | |
639 | | ((sol & 0x7f) << 20) | |
640 | | ((sof & 0x7f) << 13) | |
641 | | ((r1 & 0x7f) << 6) | |
642 | | (qp & 0x3f); | |
643 | } | |
644 | ||
645 | static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm) | |
646 | { | |
647 | return opc | |
648 | | ((imm & 0x100000) << 16) /* i */ | |
649 | | ((imm & 0x0fffff) << 6) /* imm20a */ | |
650 | | (qp & 0x3f); | |
651 | } | |
652 | ||
653 | static inline uint64_t tcg_opc_x2(int qp, uint64_t opc, | |
654 | int r1, uint64_t imm) | |
655 | { | |
656 | return opc | |
657 | | ((imm & 0x8000000000000000ull) >> 27) /* i */ | |
658 | | (imm & 0x0000000000200000ull) /* ic */ | |
659 | | ((imm & 0x00000000001f0000ull) << 6) /* imm5c */ | |
660 | | ((imm & 0x000000000000ff80ull) << 20) /* imm9d */ | |
661 | | ((imm & 0x000000000000007full) << 13) /* imm7b */ | |
662 | | ((r1 & 0x7f) << 6) | |
663 | | (qp & 0x3f); | |
664 | } | |
665 | ||
666 | static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm) | |
667 | { | |
668 | return opc | |
669 | | ((imm & 0x0800000000000000ull) >> 23) /* i */ | |
670 | | ((imm & 0x00000000000fffffull) << 13) /* imm20b */ | |
671 | | (qp & 0x3f); | |
672 | } | |
673 | ||
674 | static inline uint64_t tcg_opc_x4(int qp, uint64_t opc, int b1, uint64_t imm) | |
675 | { | |
676 | return opc | |
677 | | ((imm & 0x0800000000000000ull) >> 23) /* i */ | |
678 | | ((imm & 0x00000000000fffffull) << 13) /* imm20b */ | |
679 | | ((b1 & 0x7) << 6) | |
680 | | (qp & 0x3f); | |
681 | } | |
682 | ||
683 | ||
684 | /* | |
685 | * Relocations | |
686 | */ | |
687 | ||
688 | static inline void reloc_pcrel21b(void *pc, intptr_t target) | |
689 | { | |
690 | uint64_t imm; | |
691 | int64_t disp; | |
692 | int slot; | |
693 | ||
694 | slot = (intptr_t)pc & 3; | |
695 | pc = (void *)((intptr_t)pc & ~3); | |
696 | ||
697 | disp = target - (intptr_t)pc; | |
698 | imm = (uint64_t) disp >> 4; | |
699 | ||
700 | switch(slot) { | |
701 | case 0: | |
702 | *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull) | |
703 | | ((imm & 0x100000) << 21) /* s */ | |
704 | | ((imm & 0x0fffff) << 18); /* imm20b */ | |
705 | break; | |
706 | case 1: | |
707 | *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull) | |
708 | | ((imm & 0x100000) >> 2) /* s */ | |
709 | | ((imm & 0x0fffe0) >> 5); /* imm20b */ | |
710 | *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull) | |
711 | | ((imm & 0x00001f) << 59); /* imm20b */ | |
712 | break; | |
713 | case 2: | |
714 | *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull) | |
715 | | ((imm & 0x100000) << 39) /* s */ | |
716 | | ((imm & 0x0fffff) << 36); /* imm20b */ | |
717 | break; | |
718 | } | |
719 | } | |
720 | ||
721 | static inline uint64_t get_reloc_pcrel21b (void *pc) | |
722 | { | |
723 | int64_t low, high; | |
724 | int slot; | |
725 | ||
726 | slot = (tcg_target_long) pc & 3; | |
727 | pc = (void *)((tcg_target_long) pc & ~3); | |
728 | ||
729 | low = (*(uint64_t *)(pc + 0)); | |
730 | high = (*(uint64_t *)(pc + 8)); | |
731 | ||
732 | switch(slot) { | |
733 | case 0: | |
734 | return ((low >> 21) & 0x100000) + /* s */ | |
735 | ((low >> 18) & 0x0fffff); /* imm20b */ | |
736 | case 1: | |
737 | return ((high << 2) & 0x100000) + /* s */ | |
738 | ((high << 5) & 0x0fffe0) + /* imm20b */ | |
739 | ((low >> 59) & 0x00001f); /* imm20b */ | |
740 | case 2: | |
741 | return ((high >> 39) & 0x100000) + /* s */ | |
742 | ((high >> 36) & 0x0fffff); /* imm20b */ | |
743 | default: | |
744 | tcg_abort(); | |
745 | } | |
746 | } | |
747 | ||
748 | static inline void reloc_pcrel60b(void *pc, intptr_t target) | |
749 | { | |
750 | int64_t disp; | |
751 | uint64_t imm; | |
752 | ||
753 | disp = target - (intptr_t)pc; | |
754 | imm = (uint64_t) disp >> 4; | |
755 | ||
756 | *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull) | |
757 | | (imm & 0x0800000000000000ull) /* s */ | |
758 | | ((imm & 0x07fffff000000000ull) >> 36) /* imm39 */ | |
759 | | ((imm & 0x00000000000fffffull) << 36); /* imm20b */ | |
760 | *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull) | |
761 | | ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */ | |
762 | } | |
763 | ||
764 | static inline uint64_t get_reloc_pcrel60b (void *pc) | |
765 | { | |
766 | int64_t low, high; | |
767 | ||
768 | low = (*(uint64_t *)(pc + 0)); | |
769 | high = (*(uint64_t *)(pc + 8)); | |
770 | ||
771 | return ((high) & 0x0800000000000000ull) + /* s */ | |
772 | ((high >> 36) & 0x00000000000fffffull) + /* imm20b */ | |
773 | ((high << 36) & 0x07fffff000000000ull) + /* imm39 */ | |
774 | ((low >> 28) & 0x0000000ffff00000ull); /* imm39 */ | |
775 | } | |
776 | ||
777 | ||
778 | static void patch_reloc(uint8_t *code_ptr, int type, | |
779 | intptr_t value, intptr_t addend) | |
780 | { | |
781 | value += addend; | |
782 | switch (type) { | |
783 | case R_IA64_PCREL21B: | |
784 | reloc_pcrel21b(code_ptr, value); | |
785 | break; | |
786 | case R_IA64_PCREL60B: | |
787 | reloc_pcrel60b(code_ptr, value); | |
788 | default: | |
789 | tcg_abort(); | |
790 | } | |
791 | } | |
792 | ||
793 | /* | |
794 | * Constraints | |
795 | */ | |
796 | ||
797 | /* parse target specific constraints */ | |
798 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) | |
799 | { | |
800 | const char *ct_str; | |
801 | ||
802 | ct_str = *pct_str; | |
803 | switch(ct_str[0]) { | |
804 | case 'r': | |
805 | ct->ct |= TCG_CT_REG; | |
806 | tcg_regset_set(ct->u.regs, 0xffffffffffffffffull); | |
807 | break; | |
808 | case 'I': | |
809 | ct->ct |= TCG_CT_CONST_S22; | |
810 | break; | |
811 | case 'S': | |
812 | ct->ct |= TCG_CT_REG; | |
813 | tcg_regset_set(ct->u.regs, 0xffffffffffffffffull); | |
814 | #if defined(CONFIG_SOFTMMU) | |
815 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56); | |
816 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57); | |
817 | #endif | |
818 | break; | |
819 | case 'Z': | |
820 | /* We are cheating a bit here, using the fact that the register | |
821 | r0 is also the register number 0. Hence there is no need | |
822 | to check for const_args in each instruction. */ | |
823 | ct->ct |= TCG_CT_CONST_ZERO; | |
824 | break; | |
825 | default: | |
826 | return -1; | |
827 | } | |
828 | ct_str++; | |
829 | *pct_str = ct_str; | |
830 | return 0; | |
831 | } | |
832 | ||
833 | /* test if a constant matches the constraint */ | |
834 | static inline int tcg_target_const_match(tcg_target_long val, | |
835 | const TCGArgConstraint *arg_ct) | |
836 | { | |
837 | int ct; | |
838 | ct = arg_ct->ct; | |
839 | if (ct & TCG_CT_CONST) | |
840 | return 1; | |
841 | else if ((ct & TCG_CT_CONST_ZERO) && val == 0) | |
842 | return 1; | |
843 | else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10) | |
844 | return 1; | |
845 | else | |
846 | return 0; | |
847 | } | |
848 | ||
849 | /* | |
850 | * Code generation | |
851 | */ | |
852 | ||
853 | static uint8_t *tb_ret_addr; | |
854 | ||
855 | static inline void tcg_out_bundle(TCGContext *s, int template, | |
856 | uint64_t slot0, uint64_t slot1, | |
857 | uint64_t slot2) | |
858 | { | |
859 | template &= 0x1f; /* 5 bits */ | |
860 | slot0 &= 0x1ffffffffffull; /* 41 bits */ | |
861 | slot1 &= 0x1ffffffffffull; /* 41 bits */ | |
862 | slot2 &= 0x1ffffffffffull; /* 41 bits */ | |
863 | ||
864 | *(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template; | |
865 | *(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18); | |
866 | s->code_ptr += 16; | |
867 | } | |
868 | ||
869 | static inline void tcg_out_mov(TCGContext *s, TCGType type, | |
870 | TCGReg ret, TCGReg arg) | |
871 | { | |
872 | tcg_out_bundle(s, mmI, | |
873 | INSN_NOP_M, | |
874 | INSN_NOP_M, | |
875 | tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, 0, arg)); | |
876 | } | |
877 | ||
878 | static inline void tcg_out_movi(TCGContext *s, TCGType type, | |
879 | TCGReg reg, tcg_target_long arg) | |
880 | { | |
881 | tcg_out_bundle(s, mLX, | |
882 | INSN_NOP_M, | |
883 | tcg_opc_l2 (arg), | |
884 | tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg)); | |
885 | } | |
886 | ||
887 | static void tcg_out_br(TCGContext *s, int label_index) | |
888 | { | |
889 | TCGLabel *l = &s->labels[label_index]; | |
890 | ||
891 | /* We pay attention here to not modify the branch target by reading | |
892 | the existing value and using it again. This ensure that caches and | |
893 | memory are kept coherent during retranslation. */ | |
894 | tcg_out_bundle(s, mmB, | |
895 | INSN_NOP_M, | |
896 | INSN_NOP_M, | |
897 | tcg_opc_b1 (TCG_REG_P0, OPC_BR_SPTK_MANY_B1, | |
898 | get_reloc_pcrel21b(s->code_ptr + 2))); | |
899 | ||
900 | if (l->has_value) { | |
901 | reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value); | |
902 | } else { | |
903 | tcg_out_reloc(s, (s->code_ptr - 16) + 2, | |
904 | R_IA64_PCREL21B, label_index, 0); | |
905 | } | |
906 | } | |
907 | ||
908 | static inline void tcg_out_calli(TCGContext *s, uintptr_t addr) | |
909 | { | |
910 | /* Look through the function descriptor. */ | |
911 | uintptr_t disp, *desc = (uintptr_t *)addr; | |
912 | tcg_out_bundle(s, mlx, | |
913 | INSN_NOP_M, | |
914 | tcg_opc_l2 (desc[1]), | |
915 | tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, TCG_REG_R1, desc[1])); | |
916 | disp = (desc[0] - (uintptr_t)s->code_ptr) >> 4; | |
917 | tcg_out_bundle(s, mLX, | |
918 | INSN_NOP_M, | |
919 | tcg_opc_l4 (disp), | |
920 | tcg_opc_x4 (TCG_REG_P0, OPC_BRL_CALL_SPTK_MANY_X4, | |
921 | TCG_REG_B0, disp)); | |
922 | } | |
923 | ||
924 | static inline void tcg_out_callr(TCGContext *s, TCGReg addr) | |
925 | { | |
926 | tcg_out_bundle(s, MmI, | |
927 | tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr), | |
928 | tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr), | |
929 | tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, | |
930 | TCG_REG_B6, TCG_REG_R2, 0)); | |
931 | tcg_out_bundle(s, mmB, | |
932 | tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3), | |
933 | INSN_NOP_M, | |
934 | tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5, | |
935 | TCG_REG_B0, TCG_REG_B6)); | |
936 | } | |
937 | ||
938 | static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg) | |
939 | { | |
940 | int64_t disp; | |
941 | uint64_t imm; | |
942 | ||
943 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg); | |
944 | ||
945 | disp = tb_ret_addr - s->code_ptr; | |
946 | imm = (uint64_t)disp >> 4; | |
947 | ||
948 | tcg_out_bundle(s, mLX, | |
949 | INSN_NOP_M, | |
950 | tcg_opc_l3 (imm), | |
951 | tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm)); | |
952 | } | |
953 | ||
954 | static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg) | |
955 | { | |
956 | if (s->tb_jmp_offset) { | |
957 | /* direct jump method */ | |
958 | tcg_abort(); | |
959 | } else { | |
960 | /* indirect jump method */ | |
961 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, | |
962 | (tcg_target_long)(s->tb_next + arg)); | |
963 | tcg_out_bundle(s, MmI, | |
964 | tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, | |
965 | TCG_REG_R2, TCG_REG_R2), | |
966 | INSN_NOP_M, | |
967 | tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, | |
968 | TCG_REG_R2, 0)); | |
969 | tcg_out_bundle(s, mmB, | |
970 | INSN_NOP_M, | |
971 | INSN_NOP_M, | |
972 | tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, | |
973 | TCG_REG_B6)); | |
974 | } | |
975 | s->tb_next_offset[arg] = s->code_ptr - s->code_buf; | |
976 | } | |
977 | ||
978 | static inline void tcg_out_jmp(TCGContext *s, TCGArg addr) | |
979 | { | |
980 | tcg_out_bundle(s, mmI, | |
981 | INSN_NOP_M, | |
982 | INSN_NOP_M, | |
983 | tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0)); | |
984 | tcg_out_bundle(s, mmB, | |
985 | INSN_NOP_M, | |
986 | INSN_NOP_M, | |
987 | tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6)); | |
988 | } | |
989 | ||
990 | static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg, | |
991 | TCGArg arg1, tcg_target_long arg2) | |
992 | { | |
993 | if (arg2 == ((int16_t)arg2 >> 2) << 2) { | |
994 | tcg_out_bundle(s, MmI, | |
995 | tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, | |
996 | TCG_REG_R2, arg2, arg1), | |
997 | tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), | |
998 | INSN_NOP_I); | |
999 | } else { | |
1000 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2); | |
1001 | tcg_out_bundle(s, MmI, | |
1002 | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, | |
1003 | TCG_REG_R2, TCG_REG_R2, arg1), | |
1004 | tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), | |
1005 | INSN_NOP_I); | |
1006 | } | |
1007 | } | |
1008 | ||
1009 | static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg, | |
1010 | TCGArg arg1, tcg_target_long arg2) | |
1011 | { | |
1012 | if (arg2 == ((int16_t)arg2 >> 2) << 2) { | |
1013 | tcg_out_bundle(s, MmI, | |
1014 | tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, | |
1015 | TCG_REG_R2, arg2, arg1), | |
1016 | tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), | |
1017 | INSN_NOP_I); | |
1018 | } else { | |
1019 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2); | |
1020 | tcg_out_bundle(s, MmI, | |
1021 | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, | |
1022 | TCG_REG_R2, TCG_REG_R2, arg1), | |
1023 | tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), | |
1024 | INSN_NOP_I); | |
1025 | } | |
1026 | } | |
1027 | ||
1028 | static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, | |
1029 | TCGReg arg1, intptr_t arg2) | |
1030 | { | |
1031 | if (type == TCG_TYPE_I32) { | |
1032 | tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2); | |
1033 | } else { | |
1034 | tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2); | |
1035 | } | |
1036 | } | |
1037 | ||
1038 | static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, | |
1039 | TCGReg arg1, intptr_t arg2) | |
1040 | { | |
1041 | if (type == TCG_TYPE_I32) { | |
1042 | tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2); | |
1043 | } else { | |
1044 | tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2); | |
1045 | } | |
1046 | } | |
1047 | ||
1048 | static inline void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGArg ret, | |
1049 | TCGArg arg1, int const_arg1, | |
1050 | TCGArg arg2, int const_arg2) | |
1051 | { | |
1052 | uint64_t opc1, opc2; | |
1053 | ||
1054 | if (const_arg1 && arg1 != 0) { | |
1055 | opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, | |
1056 | TCG_REG_R2, arg1, TCG_REG_R0); | |
1057 | arg1 = TCG_REG_R2; | |
1058 | } else { | |
1059 | opc1 = INSN_NOP_M; | |
1060 | } | |
1061 | ||
1062 | if (const_arg2 && arg2 != 0) { | |
1063 | opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, | |
1064 | TCG_REG_R3, arg2, TCG_REG_R0); | |
1065 | arg2 = TCG_REG_R3; | |
1066 | } else { | |
1067 | opc2 = INSN_NOP_I; | |
1068 | } | |
1069 | ||
1070 | tcg_out_bundle(s, mII, | |
1071 | opc1, | |
1072 | opc2, | |
1073 | tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2)); | |
1074 | } | |
1075 | ||
1076 | static inline void tcg_out_eqv(TCGContext *s, TCGArg ret, | |
1077 | TCGArg arg1, int const_arg1, | |
1078 | TCGArg arg2, int const_arg2) | |
1079 | { | |
1080 | tcg_out_bundle(s, mII, | |
1081 | INSN_NOP_M, | |
1082 | tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2), | |
1083 | tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret)); | |
1084 | } | |
1085 | ||
1086 | static inline void tcg_out_nand(TCGContext *s, TCGArg ret, | |
1087 | TCGArg arg1, int const_arg1, | |
1088 | TCGArg arg2, int const_arg2) | |
1089 | { | |
1090 | tcg_out_bundle(s, mII, | |
1091 | INSN_NOP_M, | |
1092 | tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2), | |
1093 | tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret)); | |
1094 | } | |
1095 | ||
1096 | static inline void tcg_out_nor(TCGContext *s, TCGArg ret, | |
1097 | TCGArg arg1, int const_arg1, | |
1098 | TCGArg arg2, int const_arg2) | |
1099 | { | |
1100 | tcg_out_bundle(s, mII, | |
1101 | INSN_NOP_M, | |
1102 | tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2), | |
1103 | tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret)); | |
1104 | } | |
1105 | ||
1106 | static inline void tcg_out_orc(TCGContext *s, TCGArg ret, | |
1107 | TCGArg arg1, int const_arg1, | |
1108 | TCGArg arg2, int const_arg2) | |
1109 | { | |
1110 | tcg_out_bundle(s, mII, | |
1111 | INSN_NOP_M, | |
1112 | tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2), | |
1113 | tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2)); | |
1114 | } | |
1115 | ||
1116 | static inline void tcg_out_mul(TCGContext *s, TCGArg ret, | |
1117 | TCGArg arg1, TCGArg arg2) | |
1118 | { | |
1119 | tcg_out_bundle(s, mmI, | |
1120 | tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1), | |
1121 | tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2), | |
1122 | INSN_NOP_I); | |
1123 | tcg_out_bundle(s, mmF, | |
1124 | INSN_NOP_M, | |
1125 | INSN_NOP_M, | |
1126 | tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6, | |
1127 | TCG_REG_F7, TCG_REG_F0)); | |
1128 | tcg_out_bundle(s, miI, | |
1129 | tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6), | |
1130 | INSN_NOP_I, | |
1131 | INSN_NOP_I); | |
1132 | } | |
1133 | ||
1134 | static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1135 | TCGArg arg2, int const_arg2) | |
1136 | { | |
1137 | if (const_arg2) { | |
1138 | tcg_out_bundle(s, miI, | |
1139 | INSN_NOP_M, | |
1140 | INSN_NOP_I, | |
1141 | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11, | |
1142 | ret, arg1, arg2, 31 - arg2)); | |
1143 | } else { | |
1144 | tcg_out_bundle(s, mII, | |
1145 | tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, | |
1146 | TCG_REG_R3, 0x1f, arg2), | |
1147 | tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1), | |
1148 | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, | |
1149 | TCG_REG_R2, TCG_REG_R3)); | |
1150 | } | |
1151 | } | |
1152 | ||
1153 | static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1154 | TCGArg arg2, int const_arg2) | |
1155 | { | |
1156 | if (const_arg2) { | |
1157 | tcg_out_bundle(s, miI, | |
1158 | INSN_NOP_M, | |
1159 | INSN_NOP_I, | |
1160 | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11, | |
1161 | ret, arg1, arg2, 63 - arg2)); | |
1162 | } else { | |
1163 | tcg_out_bundle(s, miI, | |
1164 | INSN_NOP_M, | |
1165 | INSN_NOP_I, | |
1166 | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2)); | |
1167 | } | |
1168 | } | |
1169 | ||
1170 | static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1171 | TCGArg arg2, int const_arg2) | |
1172 | { | |
1173 | if (const_arg2) { | |
1174 | tcg_out_bundle(s, miI, | |
1175 | INSN_NOP_M, | |
1176 | INSN_NOP_I, | |
1177 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, | |
1178 | arg1, 63 - arg2, 31 - arg2)); | |
1179 | } else { | |
1180 | tcg_out_bundle(s, mII, | |
1181 | INSN_NOP_M, | |
1182 | tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2, | |
1183 | 0x1f, arg2), | |
1184 | tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret, | |
1185 | arg1, TCG_REG_R2)); | |
1186 | } | |
1187 | } | |
1188 | ||
1189 | static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1190 | TCGArg arg2, int const_arg2) | |
1191 | { | |
1192 | if (const_arg2) { | |
1193 | tcg_out_bundle(s, miI, | |
1194 | INSN_NOP_M, | |
1195 | INSN_NOP_I, | |
1196 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, | |
1197 | arg1, 63 - arg2, 63 - arg2)); | |
1198 | } else { | |
1199 | tcg_out_bundle(s, miI, | |
1200 | INSN_NOP_M, | |
1201 | INSN_NOP_I, | |
1202 | tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret, | |
1203 | arg1, arg2)); | |
1204 | } | |
1205 | } | |
1206 | ||
1207 | static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1208 | TCGArg arg2, int const_arg2) | |
1209 | { | |
1210 | if (const_arg2) { | |
1211 | tcg_out_bundle(s, miI, | |
1212 | INSN_NOP_M, | |
1213 | INSN_NOP_I, | |
1214 | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, | |
1215 | arg1, arg2, 31 - arg2)); | |
1216 | } else { | |
1217 | tcg_out_bundle(s, mII, | |
1218 | tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, | |
1219 | 0x1f, arg2), | |
1220 | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1), | |
1221 | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, | |
1222 | TCG_REG_R2, TCG_REG_R3)); | |
1223 | } | |
1224 | } | |
1225 | ||
1226 | static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1227 | TCGArg arg2, int const_arg2) | |
1228 | { | |
1229 | if (const_arg2) { | |
1230 | tcg_out_bundle(s, miI, | |
1231 | INSN_NOP_M, | |
1232 | INSN_NOP_I, | |
1233 | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, | |
1234 | arg1, arg2, 63 - arg2)); | |
1235 | } else { | |
1236 | tcg_out_bundle(s, miI, | |
1237 | INSN_NOP_M, | |
1238 | INSN_NOP_I, | |
1239 | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, | |
1240 | arg1, arg2)); | |
1241 | } | |
1242 | } | |
1243 | ||
1244 | static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1245 | TCGArg arg2, int const_arg2) | |
1246 | { | |
1247 | if (const_arg2) { | |
1248 | tcg_out_bundle(s, mII, | |
1249 | INSN_NOP_M, | |
1250 | tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, | |
1251 | TCG_REG_R2, arg1, arg1), | |
1252 | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, | |
1253 | TCG_REG_R2, 32 - arg2, 31)); | |
1254 | } else { | |
1255 | tcg_out_bundle(s, miI, | |
1256 | INSN_NOP_M, | |
1257 | tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, | |
1258 | TCG_REG_R2, arg1, arg1), | |
1259 | tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, | |
1260 | 0x1f, arg2)); | |
1261 | tcg_out_bundle(s, mII, | |
1262 | INSN_NOP_M, | |
1263 | tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3, | |
1264 | 0x20, TCG_REG_R3), | |
1265 | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, | |
1266 | TCG_REG_R2, TCG_REG_R3)); | |
1267 | } | |
1268 | } | |
1269 | ||
1270 | static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1271 | TCGArg arg2, int const_arg2) | |
1272 | { | |
1273 | if (const_arg2) { | |
1274 | tcg_out_bundle(s, miI, | |
1275 | INSN_NOP_M, | |
1276 | INSN_NOP_I, | |
1277 | tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1, | |
1278 | arg1, 0x40 - arg2)); | |
1279 | } else { | |
1280 | tcg_out_bundle(s, mII, | |
1281 | tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2, | |
1282 | 0x40, arg2), | |
1283 | tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3, | |
1284 | arg1, arg2), | |
1285 | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2, | |
1286 | arg1, TCG_REG_R2)); | |
1287 | tcg_out_bundle(s, miI, | |
1288 | INSN_NOP_M, | |
1289 | INSN_NOP_I, | |
1290 | tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, | |
1291 | TCG_REG_R2, TCG_REG_R3)); | |
1292 | } | |
1293 | } | |
1294 | ||
1295 | static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1296 | TCGArg arg2, int const_arg2) | |
1297 | { | |
1298 | if (const_arg2) { | |
1299 | tcg_out_bundle(s, mII, | |
1300 | INSN_NOP_M, | |
1301 | tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, | |
1302 | TCG_REG_R2, arg1, arg1), | |
1303 | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, | |
1304 | TCG_REG_R2, arg2, 31)); | |
1305 | } else { | |
1306 | tcg_out_bundle(s, mII, | |
1307 | tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, | |
1308 | 0x1f, arg2), | |
1309 | tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, | |
1310 | TCG_REG_R2, arg1, arg1), | |
1311 | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, | |
1312 | TCG_REG_R2, TCG_REG_R3)); | |
1313 | } | |
1314 | } | |
1315 | ||
1316 | static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1, | |
1317 | TCGArg arg2, int const_arg2) | |
1318 | { | |
1319 | if (const_arg2) { | |
1320 | tcg_out_bundle(s, miI, | |
1321 | INSN_NOP_M, | |
1322 | INSN_NOP_I, | |
1323 | tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1, | |
1324 | arg1, arg2)); | |
1325 | } else { | |
1326 | tcg_out_bundle(s, mII, | |
1327 | tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2, | |
1328 | 0x40, arg2), | |
1329 | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3, | |
1330 | arg1, arg2), | |
1331 | tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2, | |
1332 | arg1, TCG_REG_R2)); | |
1333 | tcg_out_bundle(s, miI, | |
1334 | INSN_NOP_M, | |
1335 | INSN_NOP_I, | |
1336 | tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, | |
1337 | TCG_REG_R2, TCG_REG_R3)); | |
1338 | } | |
1339 | } | |
1340 | ||
1341 | static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29, | |
1342 | TCGArg ret, TCGArg arg) | |
1343 | { | |
1344 | tcg_out_bundle(s, miI, | |
1345 | INSN_NOP_M, | |
1346 | INSN_NOP_I, | |
1347 | tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg)); | |
1348 | } | |
1349 | ||
1350 | static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg) | |
1351 | { | |
1352 | tcg_out_bundle(s, mII, | |
1353 | INSN_NOP_M, | |
1354 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15), | |
1355 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb)); | |
1356 | } | |
1357 | ||
1358 | static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg) | |
1359 | { | |
1360 | tcg_out_bundle(s, mII, | |
1361 | INSN_NOP_M, | |
1362 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31), | |
1363 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb)); | |
1364 | } | |
1365 | ||
1366 | static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg) | |
1367 | { | |
1368 | tcg_out_bundle(s, miI, | |
1369 | INSN_NOP_M, | |
1370 | INSN_NOP_I, | |
1371 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb)); | |
1372 | } | |
1373 | ||
1374 | static inline void tcg_out_deposit(TCGContext *s, TCGArg ret, TCGArg a1, | |
1375 | TCGArg a2, int const_a2, int pos, int len) | |
1376 | { | |
1377 | uint64_t i1 = 0, i2 = 0; | |
1378 | int cpos = 63 - pos, lm1 = len - 1; | |
1379 | ||
1380 | if (const_a2) { | |
1381 | /* Truncate the value of a constant a2 to the width of the field. */ | |
1382 | int mask = (1u << len) - 1; | |
1383 | a2 &= mask; | |
1384 | ||
1385 | if (a2 == 0 || a2 == mask) { | |
1386 | /* 1-bit signed constant inserted into register. */ | |
1387 | i2 = tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, ret, a2, a1, cpos, lm1); | |
1388 | } else { | |
1389 | /* Otherwise, load any constant into a temporary. Do this into | |
1390 | the first I slot to help out with cross-unit delays. */ | |
1391 | i1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, | |
1392 | TCG_REG_R2, a2, TCG_REG_R0); | |
1393 | a2 = TCG_REG_R2; | |
1394 | } | |
1395 | } | |
1396 | if (i2 == 0) { | |
1397 | i2 = tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, ret, a2, a1, cpos, lm1); | |
1398 | } | |
1399 | tcg_out_bundle(s, (i1 ? mII : miI), | |
1400 | INSN_NOP_M, | |
1401 | i1 ? i1 : INSN_NOP_I, | |
1402 | i2); | |
1403 | } | |
1404 | ||
1405 | static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1, | |
1406 | TCGArg arg2, int cmp4) | |
1407 | { | |
1408 | uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6; | |
1409 | ||
1410 | if (cmp4) { | |
1411 | opc_eq_a6 = OPC_CMP4_EQ_A6; | |
1412 | opc_lt_a6 = OPC_CMP4_LT_A6; | |
1413 | opc_ltu_a6 = OPC_CMP4_LTU_A6; | |
1414 | } else { | |
1415 | opc_eq_a6 = OPC_CMP_EQ_A6; | |
1416 | opc_lt_a6 = OPC_CMP_LT_A6; | |
1417 | opc_ltu_a6 = OPC_CMP_LTU_A6; | |
1418 | } | |
1419 | ||
1420 | switch (cond) { | |
1421 | case TCG_COND_EQ: | |
1422 | return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2); | |
1423 | case TCG_COND_NE: | |
1424 | return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2); | |
1425 | case TCG_COND_LT: | |
1426 | return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2); | |
1427 | case TCG_COND_LTU: | |
1428 | return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2); | |
1429 | case TCG_COND_GE: | |
1430 | return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2); | |
1431 | case TCG_COND_GEU: | |
1432 | return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2); | |
1433 | case TCG_COND_LE: | |
1434 | return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1); | |
1435 | case TCG_COND_LEU: | |
1436 | return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1); | |
1437 | case TCG_COND_GT: | |
1438 | return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1); | |
1439 | case TCG_COND_GTU: | |
1440 | return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1); | |
1441 | default: | |
1442 | tcg_abort(); | |
1443 | break; | |
1444 | } | |
1445 | } | |
1446 | ||
1447 | static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGArg arg1, | |
1448 | int const_arg1, TCGArg arg2, int const_arg2, | |
1449 | int label_index, int cmp4) | |
1450 | { | |
1451 | TCGLabel *l = &s->labels[label_index]; | |
1452 | uint64_t opc1, opc2; | |
1453 | ||
1454 | if (const_arg1 && arg1 != 0) { | |
1455 | opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2, | |
1456 | arg1, TCG_REG_R0); | |
1457 | arg1 = TCG_REG_R2; | |
1458 | } else { | |
1459 | opc1 = INSN_NOP_M; | |
1460 | } | |
1461 | ||
1462 | if (const_arg2 && arg2 != 0) { | |
1463 | opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3, | |
1464 | arg2, TCG_REG_R0); | |
1465 | arg2 = TCG_REG_R3; | |
1466 | } else { | |
1467 | opc2 = INSN_NOP_I; | |
1468 | } | |
1469 | ||
1470 | tcg_out_bundle(s, mII, | |
1471 | opc1, | |
1472 | opc2, | |
1473 | tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4)); | |
1474 | tcg_out_bundle(s, mmB, | |
1475 | INSN_NOP_M, | |
1476 | INSN_NOP_M, | |
1477 | tcg_opc_b1 (TCG_REG_P6, OPC_BR_DPTK_FEW_B1, | |
1478 | get_reloc_pcrel21b(s->code_ptr + 2))); | |
1479 | ||
1480 | if (l->has_value) { | |
1481 | reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value); | |
1482 | } else { | |
1483 | tcg_out_reloc(s, (s->code_ptr - 16) + 2, | |
1484 | R_IA64_PCREL21B, label_index, 0); | |
1485 | } | |
1486 | } | |
1487 | ||
1488 | static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret, | |
1489 | TCGArg arg1, TCGArg arg2, int cmp4) | |
1490 | { | |
1491 | tcg_out_bundle(s, MmI, | |
1492 | tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4), | |
1493 | tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, 1, TCG_REG_R0), | |
1494 | tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0)); | |
1495 | } | |
1496 | ||
1497 | static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret, | |
1498 | TCGArg c1, TCGArg c2, | |
1499 | TCGArg v1, int const_v1, | |
1500 | TCGArg v2, int const_v2, int cmp4) | |
1501 | { | |
1502 | uint64_t opc1, opc2; | |
1503 | ||
1504 | if (const_v1) { | |
1505 | opc1 = tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, v1, TCG_REG_R0); | |
1506 | } else if (ret == v1) { | |
1507 | opc1 = INSN_NOP_M; | |
1508 | } else { | |
1509 | opc1 = tcg_opc_a4(TCG_REG_P6, OPC_ADDS_A4, ret, 0, v1); | |
1510 | } | |
1511 | if (const_v2) { | |
1512 | opc2 = tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, v2, TCG_REG_R0); | |
1513 | } else if (ret == v2) { | |
1514 | opc2 = INSN_NOP_I; | |
1515 | } else { | |
1516 | opc2 = tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, ret, 0, v2); | |
1517 | } | |
1518 | ||
1519 | tcg_out_bundle(s, MmI, | |
1520 | tcg_opc_cmp_a(TCG_REG_P0, cond, c1, c2, cmp4), | |
1521 | opc1, | |
1522 | opc2); | |
1523 | } | |
1524 | ||
1525 | #if defined(CONFIG_SOFTMMU) | |
1526 | /* Load and compare a TLB entry, and return the result in (p6, p7). | |
1527 | R2 is loaded with the address of the addend TLB entry. | |
1528 | R57 is loaded with the address, zero extented on 32-bit targets. */ | |
1529 | static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg, | |
1530 | TCGMemOp s_bits, uint64_t offset_rw, | |
1531 | uint64_t offset_addend) | |
1532 | { | |
1533 | tcg_out_bundle(s, mII, | |
1534 | INSN_NOP_M, | |
1535 | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2, | |
1536 | addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1), | |
1537 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R2, | |
1538 | TCG_REG_R2, 63 - CPU_TLB_ENTRY_BITS, | |
1539 | 63 - CPU_TLB_ENTRY_BITS)); | |
1540 | tcg_out_bundle(s, mII, | |
1541 | tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2, | |
1542 | offset_rw, TCG_REG_R2), | |
1543 | #if TARGET_LONG_BITS == 32 | |
1544 | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R57, addr_reg), | |
1545 | #else | |
1546 | tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R57, | |
1547 | 0, addr_reg), | |
1548 | #endif | |
1549 | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, | |
1550 | TCG_REG_R2, TCG_AREG0)); | |
1551 | tcg_out_bundle(s, mII, | |
1552 | tcg_opc_m3 (TCG_REG_P0, | |
1553 | (TARGET_LONG_BITS == 32 | |
1554 | ? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R56, | |
1555 | TCG_REG_R2, offset_addend - offset_rw), | |
1556 | tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, TCG_REG_R3, 0, | |
1557 | TCG_REG_R57, 63 - s_bits, | |
1558 | TARGET_PAGE_BITS - s_bits - 1), | |
1559 | tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6, | |
1560 | TCG_REG_P7, TCG_REG_R3, TCG_REG_R56)); | |
1561 | } | |
1562 | ||
1563 | /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, | |
1564 | int mmu_idx) */ | |
1565 | static const void * const qemu_ld_helpers[4] = { | |
1566 | helper_ldb_mmu, | |
1567 | helper_ldw_mmu, | |
1568 | helper_ldl_mmu, | |
1569 | helper_ldq_mmu, | |
1570 | }; | |
1571 | ||
1572 | static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, | |
1573 | TCGMemOp opc) | |
1574 | { | |
1575 | static const uint64_t opc_ld_m1[4] = { | |
1576 | OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 | |
1577 | }; | |
1578 | static const uint64_t opc_ext_i29[8] = { | |
1579 | OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0, | |
1580 | OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 | |
1581 | }; | |
1582 | int addr_reg, data_reg, mem_index; | |
1583 | TCGMemOp s_bits, bswap; | |
1584 | ||
1585 | data_reg = *args++; | |
1586 | addr_reg = *args++; | |
1587 | mem_index = *args; | |
1588 | s_bits = opc & MO_SIZE; | |
1589 | bswap = opc & MO_BSWAP; | |
1590 | ||
1591 | /* Read the TLB entry */ | |
1592 | tcg_out_qemu_tlb(s, addr_reg, s_bits, | |
1593 | offsetof(CPUArchState, tlb_table[mem_index][0].addr_read), | |
1594 | offsetof(CPUArchState, tlb_table[mem_index][0].addend)); | |
1595 | ||
1596 | /* P6 is the fast path, and P7 the slow path */ | |
1597 | tcg_out_bundle(s, mLX, | |
1598 | tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, | |
1599 | TCG_REG_R56, 0, TCG_AREG0), | |
1600 | tcg_opc_l2 ((tcg_target_long) qemu_ld_helpers[s_bits]), | |
1601 | tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2, | |
1602 | (tcg_target_long) qemu_ld_helpers[s_bits])); | |
1603 | tcg_out_bundle(s, MmI, | |
1604 | tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3, | |
1605 | TCG_REG_R2, 8), | |
1606 | tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3, | |
1607 | TCG_REG_R3, TCG_REG_R57), | |
1608 | tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6, | |
1609 | TCG_REG_R3, 0)); | |
1610 | if (bswap && s_bits == MO_16) { | |
1611 | tcg_out_bundle(s, MmI, | |
1612 | tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], | |
1613 | TCG_REG_R8, TCG_REG_R3), | |
1614 | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), | |
1615 | tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, | |
1616 | TCG_REG_R8, TCG_REG_R8, 15, 15)); | |
1617 | } else if (bswap && s_bits == MO_32) { | |
1618 | tcg_out_bundle(s, MmI, | |
1619 | tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], | |
1620 | TCG_REG_R8, TCG_REG_R3), | |
1621 | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), | |
1622 | tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, | |
1623 | TCG_REG_R8, TCG_REG_R8, 31, 31)); | |
1624 | } else { | |
1625 | tcg_out_bundle(s, mmI, | |
1626 | tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], | |
1627 | TCG_REG_R8, TCG_REG_R3), | |
1628 | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), | |
1629 | INSN_NOP_I); | |
1630 | } | |
1631 | if (!bswap) { | |
1632 | tcg_out_bundle(s, miB, | |
1633 | tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58, | |
1634 | mem_index, TCG_REG_R0), | |
1635 | INSN_NOP_I, | |
1636 | tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5, | |
1637 | TCG_REG_B0, TCG_REG_B6)); | |
1638 | } else { | |
1639 | tcg_out_bundle(s, miB, | |
1640 | tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58, | |
1641 | mem_index, TCG_REG_R0), | |
1642 | tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, | |
1643 | TCG_REG_R8, TCG_REG_R8, 0xb), | |
1644 | tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5, | |
1645 | TCG_REG_B0, TCG_REG_B6)); | |
1646 | } | |
1647 | ||
1648 | if (s_bits == MO_64) { | |
1649 | tcg_out_bundle(s, miI, | |
1650 | INSN_NOP_M, | |
1651 | INSN_NOP_I, | |
1652 | tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, | |
1653 | data_reg, 0, TCG_REG_R8)); | |
1654 | } else { | |
1655 | tcg_out_bundle(s, miI, | |
1656 | INSN_NOP_M, | |
1657 | INSN_NOP_I, | |
1658 | tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc & MO_SSIZE], | |
1659 | data_reg, TCG_REG_R8)); | |
1660 | } | |
1661 | } | |
1662 | ||
1663 | /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, | |
1664 | uintxx_t val, int mmu_idx) */ | |
1665 | static const void * const qemu_st_helpers[4] = { | |
1666 | helper_stb_mmu, | |
1667 | helper_stw_mmu, | |
1668 | helper_stl_mmu, | |
1669 | helper_stq_mmu, | |
1670 | }; | |
1671 | ||
1672 | static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, | |
1673 | TCGMemOp opc) | |
1674 | { | |
1675 | static const uint64_t opc_st_m4[4] = { | |
1676 | OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 | |
1677 | }; | |
1678 | int addr_reg, data_reg, mem_index; | |
1679 | TCGMemOp s_bits; | |
1680 | ||
1681 | data_reg = *args++; | |
1682 | addr_reg = *args++; | |
1683 | mem_index = *args; | |
1684 | s_bits = opc & MO_SIZE; | |
1685 | ||
1686 | tcg_out_qemu_tlb(s, addr_reg, s_bits, | |
1687 | offsetof(CPUArchState, tlb_table[mem_index][0].addr_write), | |
1688 | offsetof(CPUArchState, tlb_table[mem_index][0].addend)); | |
1689 | ||
1690 | /* P6 is the fast path, and P7 the slow path */ | |
1691 | tcg_out_bundle(s, mLX, | |
1692 | tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, | |
1693 | TCG_REG_R56, 0, TCG_AREG0), | |
1694 | tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[s_bits]), | |
1695 | tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2, | |
1696 | (tcg_target_long) qemu_st_helpers[s_bits])); | |
1697 | tcg_out_bundle(s, MmI, | |
1698 | tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3, | |
1699 | TCG_REG_R2, 8), | |
1700 | tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3, | |
1701 | TCG_REG_R3, TCG_REG_R57), | |
1702 | tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6, | |
1703 | TCG_REG_R3, 0)); | |
1704 | ||
1705 | switch (opc) { | |
1706 | case MO_8: | |
1707 | case MO_16: | |
1708 | case MO_32: | |
1709 | case MO_64: | |
1710 | tcg_out_bundle(s, mii, | |
1711 | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, | |
1712 | TCG_REG_R1, TCG_REG_R2), | |
1713 | tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58, | |
1714 | 0, data_reg), | |
1715 | INSN_NOP_I); | |
1716 | break; | |
1717 | ||
1718 | case MO_16 | MO_BSWAP: | |
1719 | tcg_out_bundle(s, miI, | |
1720 | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, | |
1721 | TCG_REG_R1, TCG_REG_R2), | |
1722 | INSN_NOP_I, | |
1723 | tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, | |
1724 | TCG_REG_R2, data_reg, 15, 15)); | |
1725 | tcg_out_bundle(s, miI, | |
1726 | tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58, | |
1727 | 0, data_reg), | |
1728 | INSN_NOP_I, | |
1729 | tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, | |
1730 | TCG_REG_R2, TCG_REG_R2, 0xb)); | |
1731 | data_reg = TCG_REG_R2; | |
1732 | break; | |
1733 | ||
1734 | case MO_32 | MO_BSWAP: | |
1735 | tcg_out_bundle(s, miI, | |
1736 | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, | |
1737 | TCG_REG_R1, TCG_REG_R2), | |
1738 | INSN_NOP_I, | |
1739 | tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, | |
1740 | TCG_REG_R2, data_reg, 31, 31)); | |
1741 | tcg_out_bundle(s, miI, | |
1742 | tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58, | |
1743 | 0, data_reg), | |
1744 | INSN_NOP_I, | |
1745 | tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, | |
1746 | TCG_REG_R2, TCG_REG_R2, 0xb)); | |
1747 | data_reg = TCG_REG_R2; | |
1748 | break; | |
1749 | ||
1750 | case MO_64 | MO_BSWAP: | |
1751 | tcg_out_bundle(s, miI, | |
1752 | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, | |
1753 | TCG_REG_R1, TCG_REG_R2), | |
1754 | tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58, | |
1755 | 0, data_reg), | |
1756 | tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, | |
1757 | TCG_REG_R2, data_reg, 0xb)); | |
1758 | data_reg = TCG_REG_R2; | |
1759 | break; | |
1760 | ||
1761 | default: | |
1762 | tcg_abort(); | |
1763 | } | |
1764 | ||
1765 | tcg_out_bundle(s, miB, | |
1766 | tcg_opc_m4 (TCG_REG_P6, opc_st_m4[s_bits], | |
1767 | data_reg, TCG_REG_R3), | |
1768 | tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59, | |
1769 | mem_index, TCG_REG_R0), | |
1770 | tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5, | |
1771 | TCG_REG_B0, TCG_REG_B6)); | |
1772 | } | |
1773 | ||
1774 | #else /* !CONFIG_SOFTMMU */ | |
1775 | ||
1776 | static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, | |
1777 | TCGMemOp opc) | |
1778 | { | |
1779 | static uint64_t const opc_ld_m1[4] = { | |
1780 | OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 | |
1781 | }; | |
1782 | static uint64_t const opc_sxt_i29[4] = { | |
1783 | OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 | |
1784 | }; | |
1785 | int addr_reg, data_reg; | |
1786 | TCGMemOp s_bits, bswap; | |
1787 | ||
1788 | data_reg = *args++; | |
1789 | addr_reg = *args++; | |
1790 | s_bits = opc & MO_SIZE; | |
1791 | bswap = opc & MO_BSWAP; | |
1792 | ||
1793 | #if TARGET_LONG_BITS == 32 | |
1794 | if (GUEST_BASE != 0) { | |
1795 | tcg_out_bundle(s, mII, | |
1796 | INSN_NOP_M, | |
1797 | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, | |
1798 | TCG_REG_R3, addr_reg), | |
1799 | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, | |
1800 | TCG_GUEST_BASE_REG, TCG_REG_R3)); | |
1801 | } else { | |
1802 | tcg_out_bundle(s, miI, | |
1803 | INSN_NOP_M, | |
1804 | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, | |
1805 | TCG_REG_R2, addr_reg), | |
1806 | INSN_NOP_I); | |
1807 | } | |
1808 | ||
1809 | if (!bswap) { | |
1810 | if (!(opc & MO_SIGN)) { | |
1811 | tcg_out_bundle(s, miI, | |
1812 | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], | |
1813 | data_reg, TCG_REG_R2), | |
1814 | INSN_NOP_I, | |
1815 | INSN_NOP_I); | |
1816 | } else { | |
1817 | tcg_out_bundle(s, mII, | |
1818 | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], | |
1819 | data_reg, TCG_REG_R2), | |
1820 | INSN_NOP_I, | |
1821 | tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits], | |
1822 | data_reg, data_reg)); | |
1823 | } | |
1824 | } else if (s_bits == MO_64) { | |
1825 | tcg_out_bundle(s, mII, | |
1826 | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], | |
1827 | data_reg, TCG_REG_R2), | |
1828 | INSN_NOP_I, | |
1829 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
1830 | data_reg, data_reg, 0xb)); | |
1831 | } else { | |
1832 | if (s_bits == MO_16) { | |
1833 | tcg_out_bundle(s, mII, | |
1834 | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], | |
1835 | data_reg, TCG_REG_R2), | |
1836 | INSN_NOP_I, | |
1837 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, | |
1838 | data_reg, data_reg, 15, 15)); | |
1839 | } else { | |
1840 | tcg_out_bundle(s, mII, | |
1841 | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], | |
1842 | data_reg, TCG_REG_R2), | |
1843 | INSN_NOP_I, | |
1844 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, | |
1845 | data_reg, data_reg, 31, 31)); | |
1846 | } | |
1847 | if (!(opc & MO_SIGN)) { | |
1848 | tcg_out_bundle(s, miI, | |
1849 | INSN_NOP_M, | |
1850 | INSN_NOP_I, | |
1851 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
1852 | data_reg, data_reg, 0xb)); | |
1853 | } else { | |
1854 | tcg_out_bundle(s, mII, | |
1855 | INSN_NOP_M, | |
1856 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
1857 | data_reg, data_reg, 0xb), | |
1858 | tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits], | |
1859 | data_reg, data_reg)); | |
1860 | } | |
1861 | } | |
1862 | #else | |
1863 | if (GUEST_BASE != 0) { | |
1864 | tcg_out_bundle(s, MmI, | |
1865 | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, | |
1866 | TCG_GUEST_BASE_REG, addr_reg), | |
1867 | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], | |
1868 | data_reg, TCG_REG_R2), | |
1869 | INSN_NOP_I); | |
1870 | } else { | |
1871 | tcg_out_bundle(s, mmI, | |
1872 | INSN_NOP_M, | |
1873 | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], | |
1874 | data_reg, addr_reg), | |
1875 | INSN_NOP_I); | |
1876 | } | |
1877 | ||
1878 | if (bswap && s_bits == MO_16) { | |
1879 | tcg_out_bundle(s, mII, | |
1880 | INSN_NOP_M, | |
1881 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, | |
1882 | data_reg, data_reg, 15, 15), | |
1883 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
1884 | data_reg, data_reg, 0xb)); | |
1885 | } else if (bswap && s_bits == MO_32) { | |
1886 | tcg_out_bundle(s, mII, | |
1887 | INSN_NOP_M, | |
1888 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, | |
1889 | data_reg, data_reg, 31, 31), | |
1890 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
1891 | data_reg, data_reg, 0xb)); | |
1892 | } else if (bswap && s_bits == MO_64) { | |
1893 | tcg_out_bundle(s, miI, | |
1894 | INSN_NOP_M, | |
1895 | INSN_NOP_I, | |
1896 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
1897 | data_reg, data_reg, 0xb)); | |
1898 | } | |
1899 | if (opc & MO_SIGN) { | |
1900 | tcg_out_bundle(s, miI, | |
1901 | INSN_NOP_M, | |
1902 | INSN_NOP_I, | |
1903 | tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits], | |
1904 | data_reg, data_reg)); | |
1905 | } | |
1906 | #endif | |
1907 | } | |
1908 | ||
1909 | static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, | |
1910 | TCGMemOp opc) | |
1911 | { | |
1912 | static uint64_t const opc_st_m4[4] = { | |
1913 | OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 | |
1914 | }; | |
1915 | int addr_reg, data_reg; | |
1916 | #if TARGET_LONG_BITS == 64 | |
1917 | uint64_t add_guest_base; | |
1918 | #endif | |
1919 | TCGMemOp s_bits, bswap; | |
1920 | ||
1921 | data_reg = *args++; | |
1922 | addr_reg = *args++; | |
1923 | s_bits = opc & MO_SIZE; | |
1924 | bswap = opc & MO_BSWAP; | |
1925 | ||
1926 | #if TARGET_LONG_BITS == 32 | |
1927 | if (GUEST_BASE != 0) { | |
1928 | tcg_out_bundle(s, mII, | |
1929 | INSN_NOP_M, | |
1930 | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, | |
1931 | TCG_REG_R3, addr_reg), | |
1932 | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, | |
1933 | TCG_GUEST_BASE_REG, TCG_REG_R3)); | |
1934 | } else { | |
1935 | tcg_out_bundle(s, miI, | |
1936 | INSN_NOP_M, | |
1937 | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, | |
1938 | TCG_REG_R2, addr_reg), | |
1939 | INSN_NOP_I); | |
1940 | } | |
1941 | ||
1942 | if (bswap) { | |
1943 | if (s_bits == MO_16) { | |
1944 | tcg_out_bundle(s, mII, | |
1945 | INSN_NOP_M, | |
1946 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, | |
1947 | TCG_REG_R3, data_reg, 15, 15), | |
1948 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
1949 | TCG_REG_R3, TCG_REG_R3, 0xb)); | |
1950 | data_reg = TCG_REG_R3; | |
1951 | } else if (s_bits == MO_32) { | |
1952 | tcg_out_bundle(s, mII, | |
1953 | INSN_NOP_M, | |
1954 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, | |
1955 | TCG_REG_R3, data_reg, 31, 31), | |
1956 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
1957 | TCG_REG_R3, TCG_REG_R3, 0xb)); | |
1958 | data_reg = TCG_REG_R3; | |
1959 | } else if (s_bits == MO_64) { | |
1960 | tcg_out_bundle(s, miI, | |
1961 | INSN_NOP_M, | |
1962 | INSN_NOP_I, | |
1963 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
1964 | TCG_REG_R3, data_reg, 0xb)); | |
1965 | data_reg = TCG_REG_R3; | |
1966 | } | |
1967 | } | |
1968 | tcg_out_bundle(s, mmI, | |
1969 | tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits], | |
1970 | data_reg, TCG_REG_R2), | |
1971 | INSN_NOP_M, | |
1972 | INSN_NOP_I); | |
1973 | #else | |
1974 | if (GUEST_BASE != 0) { | |
1975 | add_guest_base = tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, | |
1976 | TCG_GUEST_BASE_REG, addr_reg); | |
1977 | addr_reg = TCG_REG_R2; | |
1978 | } else { | |
1979 | add_guest_base = INSN_NOP_M; | |
1980 | } | |
1981 | ||
1982 | if (!bswap) { | |
1983 | tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI), | |
1984 | add_guest_base, | |
1985 | tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits], | |
1986 | data_reg, addr_reg), | |
1987 | INSN_NOP_I); | |
1988 | } else { | |
1989 | if (s_bits == MO_16) { | |
1990 | tcg_out_bundle(s, mII, | |
1991 | add_guest_base, | |
1992 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, | |
1993 | TCG_REG_R3, data_reg, 15, 15), | |
1994 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
1995 | TCG_REG_R3, TCG_REG_R3, 0xb)); | |
1996 | data_reg = TCG_REG_R3; | |
1997 | } else if (s_bits == MO_32) { | |
1998 | tcg_out_bundle(s, mII, | |
1999 | add_guest_base, | |
2000 | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, | |
2001 | TCG_REG_R3, data_reg, 31, 31), | |
2002 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
2003 | TCG_REG_R3, TCG_REG_R3, 0xb)); | |
2004 | data_reg = TCG_REG_R3; | |
2005 | } else if (s_bits == MO_64) { | |
2006 | tcg_out_bundle(s, miI, | |
2007 | add_guest_base, | |
2008 | INSN_NOP_I, | |
2009 | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, | |
2010 | TCG_REG_R3, data_reg, 0xb)); | |
2011 | data_reg = TCG_REG_R3; | |
2012 | } | |
2013 | tcg_out_bundle(s, miI, | |
2014 | tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits], | |
2015 | data_reg, addr_reg), | |
2016 | INSN_NOP_I, | |
2017 | INSN_NOP_I); | |
2018 | } | |
2019 | #endif | |
2020 | } | |
2021 | ||
2022 | #endif | |
2023 | ||
2024 | static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, | |
2025 | const TCGArg *args, const int *const_args) | |
2026 | { | |
2027 | switch(opc) { | |
2028 | case INDEX_op_exit_tb: | |
2029 | tcg_out_exit_tb(s, args[0]); | |
2030 | break; | |
2031 | case INDEX_op_br: | |
2032 | tcg_out_br(s, args[0]); | |
2033 | break; | |
2034 | case INDEX_op_call: | |
2035 | if (likely(const_args[0])) { | |
2036 | tcg_out_calli(s, args[0]); | |
2037 | } else { | |
2038 | tcg_out_callr(s, args[0]); | |
2039 | } | |
2040 | break; | |
2041 | case INDEX_op_goto_tb: | |
2042 | tcg_out_goto_tb(s, args[0]); | |
2043 | break; | |
2044 | ||
2045 | case INDEX_op_movi_i32: | |
2046 | tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]); | |
2047 | break; | |
2048 | case INDEX_op_movi_i64: | |
2049 | tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); | |
2050 | break; | |
2051 | ||
2052 | case INDEX_op_ld8u_i32: | |
2053 | case INDEX_op_ld8u_i64: | |
2054 | tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]); | |
2055 | break; | |
2056 | case INDEX_op_ld8s_i32: | |
2057 | case INDEX_op_ld8s_i64: | |
2058 | tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]); | |
2059 | tcg_out_ext(s, OPC_SXT1_I29, args[0], args[0]); | |
2060 | break; | |
2061 | case INDEX_op_ld16u_i32: | |
2062 | case INDEX_op_ld16u_i64: | |
2063 | tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]); | |
2064 | break; | |
2065 | case INDEX_op_ld16s_i32: | |
2066 | case INDEX_op_ld16s_i64: | |
2067 | tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]); | |
2068 | tcg_out_ext(s, OPC_SXT2_I29, args[0], args[0]); | |
2069 | break; | |
2070 | case INDEX_op_ld_i32: | |
2071 | case INDEX_op_ld32u_i64: | |
2072 | tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]); | |
2073 | break; | |
2074 | case INDEX_op_ld32s_i64: | |
2075 | tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]); | |
2076 | tcg_out_ext(s, OPC_SXT4_I29, args[0], args[0]); | |
2077 | break; | |
2078 | case INDEX_op_ld_i64: | |
2079 | tcg_out_ld_rel(s, OPC_LD8_M1, args[0], args[1], args[2]); | |
2080 | break; | |
2081 | case INDEX_op_st8_i32: | |
2082 | case INDEX_op_st8_i64: | |
2083 | tcg_out_st_rel(s, OPC_ST1_M4, args[0], args[1], args[2]); | |
2084 | break; | |
2085 | case INDEX_op_st16_i32: | |
2086 | case INDEX_op_st16_i64: | |
2087 | tcg_out_st_rel(s, OPC_ST2_M4, args[0], args[1], args[2]); | |
2088 | break; | |
2089 | case INDEX_op_st_i32: | |
2090 | case INDEX_op_st32_i64: | |
2091 | tcg_out_st_rel(s, OPC_ST4_M4, args[0], args[1], args[2]); | |
2092 | break; | |
2093 | case INDEX_op_st_i64: | |
2094 | tcg_out_st_rel(s, OPC_ST8_M4, args[0], args[1], args[2]); | |
2095 | break; | |
2096 | ||
2097 | case INDEX_op_add_i32: | |
2098 | case INDEX_op_add_i64: | |
2099 | tcg_out_alu(s, OPC_ADD_A1, args[0], args[1], const_args[1], | |
2100 | args[2], const_args[2]); | |
2101 | break; | |
2102 | case INDEX_op_sub_i32: | |
2103 | case INDEX_op_sub_i64: | |
2104 | tcg_out_alu(s, OPC_SUB_A1, args[0], args[1], const_args[1], | |
2105 | args[2], const_args[2]); | |
2106 | break; | |
2107 | ||
2108 | case INDEX_op_and_i32: | |
2109 | case INDEX_op_and_i64: | |
2110 | tcg_out_alu(s, OPC_AND_A1, args[0], args[1], const_args[1], | |
2111 | args[2], const_args[2]); | |
2112 | break; | |
2113 | case INDEX_op_andc_i32: | |
2114 | case INDEX_op_andc_i64: | |
2115 | tcg_out_alu(s, OPC_ANDCM_A1, args[0], args[1], const_args[1], | |
2116 | args[2], const_args[2]); | |
2117 | break; | |
2118 | case INDEX_op_eqv_i32: | |
2119 | case INDEX_op_eqv_i64: | |
2120 | tcg_out_eqv(s, args[0], args[1], const_args[1], | |
2121 | args[2], const_args[2]); | |
2122 | break; | |
2123 | case INDEX_op_nand_i32: | |
2124 | case INDEX_op_nand_i64: | |
2125 | tcg_out_nand(s, args[0], args[1], const_args[1], | |
2126 | args[2], const_args[2]); | |
2127 | break; | |
2128 | case INDEX_op_nor_i32: | |
2129 | case INDEX_op_nor_i64: | |
2130 | tcg_out_nor(s, args[0], args[1], const_args[1], | |
2131 | args[2], const_args[2]); | |
2132 | break; | |
2133 | case INDEX_op_or_i32: | |
2134 | case INDEX_op_or_i64: | |
2135 | tcg_out_alu(s, OPC_OR_A1, args[0], args[1], const_args[1], | |
2136 | args[2], const_args[2]); | |
2137 | break; | |
2138 | case INDEX_op_orc_i32: | |
2139 | case INDEX_op_orc_i64: | |
2140 | tcg_out_orc(s, args[0], args[1], const_args[1], | |
2141 | args[2], const_args[2]); | |
2142 | break; | |
2143 | case INDEX_op_xor_i32: | |
2144 | case INDEX_op_xor_i64: | |
2145 | tcg_out_alu(s, OPC_XOR_A1, args[0], args[1], const_args[1], | |
2146 | args[2], const_args[2]); | |
2147 | break; | |
2148 | ||
2149 | case INDEX_op_mul_i32: | |
2150 | case INDEX_op_mul_i64: | |
2151 | tcg_out_mul(s, args[0], args[1], args[2]); | |
2152 | break; | |
2153 | ||
2154 | case INDEX_op_sar_i32: | |
2155 | tcg_out_sar_i32(s, args[0], args[1], args[2], const_args[2]); | |
2156 | break; | |
2157 | case INDEX_op_sar_i64: | |
2158 | tcg_out_sar_i64(s, args[0], args[1], args[2], const_args[2]); | |
2159 | break; | |
2160 | case INDEX_op_shl_i32: | |
2161 | tcg_out_shl_i32(s, args[0], args[1], args[2], const_args[2]); | |
2162 | break; | |
2163 | case INDEX_op_shl_i64: | |
2164 | tcg_out_shl_i64(s, args[0], args[1], args[2], const_args[2]); | |
2165 | break; | |
2166 | case INDEX_op_shr_i32: | |
2167 | tcg_out_shr_i32(s, args[0], args[1], args[2], const_args[2]); | |
2168 | break; | |
2169 | case INDEX_op_shr_i64: | |
2170 | tcg_out_shr_i64(s, args[0], args[1], args[2], const_args[2]); | |
2171 | break; | |
2172 | case INDEX_op_rotl_i32: | |
2173 | tcg_out_rotl_i32(s, args[0], args[1], args[2], const_args[2]); | |
2174 | break; | |
2175 | case INDEX_op_rotl_i64: | |
2176 | tcg_out_rotl_i64(s, args[0], args[1], args[2], const_args[2]); | |
2177 | break; | |
2178 | case INDEX_op_rotr_i32: | |
2179 | tcg_out_rotr_i32(s, args[0], args[1], args[2], const_args[2]); | |
2180 | break; | |
2181 | case INDEX_op_rotr_i64: | |
2182 | tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]); | |
2183 | break; | |
2184 | ||
2185 | case INDEX_op_ext8s_i32: | |
2186 | case INDEX_op_ext8s_i64: | |
2187 | tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]); | |
2188 | break; | |
2189 | case INDEX_op_ext8u_i32: | |
2190 | case INDEX_op_ext8u_i64: | |
2191 | tcg_out_ext(s, OPC_ZXT1_I29, args[0], args[1]); | |
2192 | break; | |
2193 | case INDEX_op_ext16s_i32: | |
2194 | case INDEX_op_ext16s_i64: | |
2195 | tcg_out_ext(s, OPC_SXT2_I29, args[0], args[1]); | |
2196 | break; | |
2197 | case INDEX_op_ext16u_i32: | |
2198 | case INDEX_op_ext16u_i64: | |
2199 | tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]); | |
2200 | break; | |
2201 | case INDEX_op_ext32s_i64: | |
2202 | tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]); | |
2203 | break; | |
2204 | case INDEX_op_ext32u_i64: | |
2205 | tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]); | |
2206 | break; | |
2207 | ||
2208 | case INDEX_op_bswap16_i32: | |
2209 | case INDEX_op_bswap16_i64: | |
2210 | tcg_out_bswap16(s, args[0], args[1]); | |
2211 | break; | |
2212 | case INDEX_op_bswap32_i32: | |
2213 | case INDEX_op_bswap32_i64: | |
2214 | tcg_out_bswap32(s, args[0], args[1]); | |
2215 | break; | |
2216 | case INDEX_op_bswap64_i64: | |
2217 | tcg_out_bswap64(s, args[0], args[1]); | |
2218 | break; | |
2219 | ||
2220 | case INDEX_op_deposit_i32: | |
2221 | case INDEX_op_deposit_i64: | |
2222 | tcg_out_deposit(s, args[0], args[1], args[2], const_args[2], | |
2223 | args[3], args[4]); | |
2224 | break; | |
2225 | ||
2226 | case INDEX_op_brcond_i32: | |
2227 | tcg_out_brcond(s, args[2], args[0], const_args[0], | |
2228 | args[1], const_args[1], args[3], 1); | |
2229 | break; | |
2230 | case INDEX_op_brcond_i64: | |
2231 | tcg_out_brcond(s, args[2], args[0], const_args[0], | |
2232 | args[1], const_args[1], args[3], 0); | |
2233 | break; | |
2234 | case INDEX_op_setcond_i32: | |
2235 | tcg_out_setcond(s, args[3], args[0], args[1], args[2], 1); | |
2236 | break; | |
2237 | case INDEX_op_setcond_i64: | |
2238 | tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0); | |
2239 | break; | |
2240 | case INDEX_op_movcond_i32: | |
2241 | tcg_out_movcond(s, args[5], args[0], args[1], args[2], | |
2242 | args[3], const_args[3], args[4], const_args[4], 1); | |
2243 | break; | |
2244 | case INDEX_op_movcond_i64: | |
2245 | tcg_out_movcond(s, args[5], args[0], args[1], args[2], | |
2246 | args[3], const_args[3], args[4], const_args[4], 0); | |
2247 | break; | |
2248 | ||
2249 | case INDEX_op_qemu_ld8u: | |
2250 | tcg_out_qemu_ld(s, args, MO_UB); | |
2251 | break; | |
2252 | case INDEX_op_qemu_ld8s: | |
2253 | tcg_out_qemu_ld(s, args, MO_SB); | |
2254 | break; | |
2255 | case INDEX_op_qemu_ld16u: | |
2256 | tcg_out_qemu_ld(s, args, MO_TEUW); | |
2257 | break; | |
2258 | case INDEX_op_qemu_ld16s: | |
2259 | tcg_out_qemu_ld(s, args, MO_TESW); | |
2260 | break; | |
2261 | case INDEX_op_qemu_ld32: | |
2262 | case INDEX_op_qemu_ld32u: | |
2263 | tcg_out_qemu_ld(s, args, MO_TEUL); | |
2264 | break; | |
2265 | case INDEX_op_qemu_ld32s: | |
2266 | tcg_out_qemu_ld(s, args, MO_TESL); | |
2267 | break; | |
2268 | case INDEX_op_qemu_ld64: | |
2269 | tcg_out_qemu_ld(s, args, MO_TEQ); | |
2270 | break; | |
2271 | ||
2272 | case INDEX_op_qemu_st8: | |
2273 | tcg_out_qemu_st(s, args, MO_UB); | |
2274 | break; | |
2275 | case INDEX_op_qemu_st16: | |
2276 | tcg_out_qemu_st(s, args, MO_TEUW); | |
2277 | break; | |
2278 | case INDEX_op_qemu_st32: | |
2279 | tcg_out_qemu_st(s, args, MO_TEUL); | |
2280 | break; | |
2281 | case INDEX_op_qemu_st64: | |
2282 | tcg_out_qemu_st(s, args, MO_TEQ); | |
2283 | break; | |
2284 | ||
2285 | default: | |
2286 | tcg_abort(); | |
2287 | } | |
2288 | } | |
2289 | ||
2290 | static const TCGTargetOpDef ia64_op_defs[] = { | |
2291 | { INDEX_op_br, { } }, | |
2292 | { INDEX_op_call, { "ri" } }, | |
2293 | { INDEX_op_exit_tb, { } }, | |
2294 | { INDEX_op_goto_tb, { } }, | |
2295 | ||
2296 | { INDEX_op_mov_i32, { "r", "r" } }, | |
2297 | { INDEX_op_movi_i32, { "r" } }, | |
2298 | ||
2299 | { INDEX_op_ld8u_i32, { "r", "r" } }, | |
2300 | { INDEX_op_ld8s_i32, { "r", "r" } }, | |
2301 | { INDEX_op_ld16u_i32, { "r", "r" } }, | |
2302 | { INDEX_op_ld16s_i32, { "r", "r" } }, | |
2303 | { INDEX_op_ld_i32, { "r", "r" } }, | |
2304 | { INDEX_op_st8_i32, { "rZ", "r" } }, | |
2305 | { INDEX_op_st16_i32, { "rZ", "r" } }, | |
2306 | { INDEX_op_st_i32, { "rZ", "r" } }, | |
2307 | ||
2308 | { INDEX_op_add_i32, { "r", "rI", "rI" } }, | |
2309 | { INDEX_op_sub_i32, { "r", "rI", "rI" } }, | |
2310 | ||
2311 | { INDEX_op_and_i32, { "r", "rI", "rI" } }, | |
2312 | { INDEX_op_andc_i32, { "r", "rI", "rI" } }, | |
2313 | { INDEX_op_eqv_i32, { "r", "rZ", "rZ" } }, | |
2314 | { INDEX_op_nand_i32, { "r", "rZ", "rZ" } }, | |
2315 | { INDEX_op_nor_i32, { "r", "rZ", "rZ" } }, | |
2316 | { INDEX_op_or_i32, { "r", "rI", "rI" } }, | |
2317 | { INDEX_op_orc_i32, { "r", "rZ", "rZ" } }, | |
2318 | { INDEX_op_xor_i32, { "r", "rI", "rI" } }, | |
2319 | ||
2320 | { INDEX_op_mul_i32, { "r", "rZ", "rZ" } }, | |
2321 | ||
2322 | { INDEX_op_sar_i32, { "r", "rZ", "ri" } }, | |
2323 | { INDEX_op_shl_i32, { "r", "rZ", "ri" } }, | |
2324 | { INDEX_op_shr_i32, { "r", "rZ", "ri" } }, | |
2325 | { INDEX_op_rotl_i32, { "r", "rZ", "ri" } }, | |
2326 | { INDEX_op_rotr_i32, { "r", "rZ", "ri" } }, | |
2327 | ||
2328 | { INDEX_op_ext8s_i32, { "r", "rZ"} }, | |
2329 | { INDEX_op_ext8u_i32, { "r", "rZ"} }, | |
2330 | { INDEX_op_ext16s_i32, { "r", "rZ"} }, | |
2331 | { INDEX_op_ext16u_i32, { "r", "rZ"} }, | |
2332 | ||
2333 | { INDEX_op_bswap16_i32, { "r", "rZ" } }, | |
2334 | { INDEX_op_bswap32_i32, { "r", "rZ" } }, | |
2335 | ||
2336 | { INDEX_op_brcond_i32, { "rI", "rI" } }, | |
2337 | { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } }, | |
2338 | { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rI", "rI" } }, | |
2339 | ||
2340 | { INDEX_op_mov_i64, { "r", "r" } }, | |
2341 | { INDEX_op_movi_i64, { "r" } }, | |
2342 | ||
2343 | { INDEX_op_ld8u_i64, { "r", "r" } }, | |
2344 | { INDEX_op_ld8s_i64, { "r", "r" } }, | |
2345 | { INDEX_op_ld16u_i64, { "r", "r" } }, | |
2346 | { INDEX_op_ld16s_i64, { "r", "r" } }, | |
2347 | { INDEX_op_ld32u_i64, { "r", "r" } }, | |
2348 | { INDEX_op_ld32s_i64, { "r", "r" } }, | |
2349 | { INDEX_op_ld_i64, { "r", "r" } }, | |
2350 | { INDEX_op_st8_i64, { "rZ", "r" } }, | |
2351 | { INDEX_op_st16_i64, { "rZ", "r" } }, | |
2352 | { INDEX_op_st32_i64, { "rZ", "r" } }, | |
2353 | { INDEX_op_st_i64, { "rZ", "r" } }, | |
2354 | ||
2355 | { INDEX_op_add_i64, { "r", "rI", "rI" } }, | |
2356 | { INDEX_op_sub_i64, { "r", "rI", "rI" } }, | |
2357 | ||
2358 | { INDEX_op_and_i64, { "r", "rI", "rI" } }, | |
2359 | { INDEX_op_andc_i64, { "r", "rI", "rI" } }, | |
2360 | { INDEX_op_eqv_i64, { "r", "rZ", "rZ" } }, | |
2361 | { INDEX_op_nand_i64, { "r", "rZ", "rZ" } }, | |
2362 | { INDEX_op_nor_i64, { "r", "rZ", "rZ" } }, | |
2363 | { INDEX_op_or_i64, { "r", "rI", "rI" } }, | |
2364 | { INDEX_op_orc_i64, { "r", "rZ", "rZ" } }, | |
2365 | { INDEX_op_xor_i64, { "r", "rI", "rI" } }, | |
2366 | ||
2367 | { INDEX_op_mul_i64, { "r", "rZ", "rZ" } }, | |
2368 | ||
2369 | { INDEX_op_sar_i64, { "r", "rZ", "ri" } }, | |
2370 | { INDEX_op_shl_i64, { "r", "rZ", "ri" } }, | |
2371 | { INDEX_op_shr_i64, { "r", "rZ", "ri" } }, | |
2372 | { INDEX_op_rotl_i64, { "r", "rZ", "ri" } }, | |
2373 | { INDEX_op_rotr_i64, { "r", "rZ", "ri" } }, | |
2374 | ||
2375 | { INDEX_op_ext8s_i64, { "r", "rZ"} }, | |
2376 | { INDEX_op_ext8u_i64, { "r", "rZ"} }, | |
2377 | { INDEX_op_ext16s_i64, { "r", "rZ"} }, | |
2378 | { INDEX_op_ext16u_i64, { "r", "rZ"} }, | |
2379 | { INDEX_op_ext32s_i64, { "r", "rZ"} }, | |
2380 | { INDEX_op_ext32u_i64, { "r", "rZ"} }, | |
2381 | ||
2382 | { INDEX_op_bswap16_i64, { "r", "rZ" } }, | |
2383 | { INDEX_op_bswap32_i64, { "r", "rZ" } }, | |
2384 | { INDEX_op_bswap64_i64, { "r", "rZ" } }, | |
2385 | ||
2386 | { INDEX_op_brcond_i64, { "rI", "rI" } }, | |
2387 | { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } }, | |
2388 | { INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rI", "rI" } }, | |
2389 | ||
2390 | { INDEX_op_deposit_i32, { "r", "rZ", "ri" } }, | |
2391 | { INDEX_op_deposit_i64, { "r", "rZ", "ri" } }, | |
2392 | ||
2393 | { INDEX_op_qemu_ld8u, { "r", "r" } }, | |
2394 | { INDEX_op_qemu_ld8s, { "r", "r" } }, | |
2395 | { INDEX_op_qemu_ld16u, { "r", "r" } }, | |
2396 | { INDEX_op_qemu_ld16s, { "r", "r" } }, | |
2397 | { INDEX_op_qemu_ld32, { "r", "r" } }, | |
2398 | { INDEX_op_qemu_ld32u, { "r", "r" } }, | |
2399 | { INDEX_op_qemu_ld32s, { "r", "r" } }, | |
2400 | { INDEX_op_qemu_ld64, { "r", "r" } }, | |
2401 | ||
2402 | { INDEX_op_qemu_st8, { "SZ", "r" } }, | |
2403 | { INDEX_op_qemu_st16, { "SZ", "r" } }, | |
2404 | { INDEX_op_qemu_st32, { "SZ", "r" } }, | |
2405 | { INDEX_op_qemu_st64, { "SZ", "r" } }, | |
2406 | ||
2407 | { -1 }, | |
2408 | }; | |
2409 | ||
2410 | /* Generate global QEMU prologue and epilogue code */ | |
2411 | static void tcg_target_qemu_prologue(TCGContext *s) | |
2412 | { | |
2413 | int frame_size; | |
2414 | ||
2415 | /* reserve some stack space */ | |
2416 | frame_size = TCG_STATIC_CALL_ARGS_SIZE + | |
2417 | CPU_TEMP_BUF_NLONGS * sizeof(long); | |
2418 | frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) & | |
2419 | ~(TCG_TARGET_STACK_ALIGN - 1); | |
2420 | tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, | |
2421 | CPU_TEMP_BUF_NLONGS * sizeof(long)); | |
2422 | ||
2423 | /* First emit adhoc function descriptor */ | |
2424 | *(uint64_t *)(s->code_ptr) = (uint64_t)s->code_ptr + 16; /* entry point */ | |
2425 | s->code_ptr += 16; /* skip GP */ | |
2426 | ||
2427 | /* prologue */ | |
2428 | tcg_out_bundle(s, miI, | |
2429 | tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34, | |
2430 | TCG_REG_R34, 32, 24, 0), | |
2431 | tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, | |
2432 | TCG_AREG0, 0, TCG_REG_R32), | |
2433 | tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, | |
2434 | TCG_REG_B6, TCG_REG_R33, 0)); | |
2435 | ||
2436 | /* ??? If GUEST_BASE < 0x200000, we could load the register via | |
2437 | an ADDL in the M slot of the next bundle. */ | |
2438 | if (GUEST_BASE != 0) { | |
2439 | tcg_out_bundle(s, mlx, | |
2440 | INSN_NOP_M, | |
2441 | tcg_opc_l2 (GUEST_BASE), | |
2442 | tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, | |
2443 | TCG_GUEST_BASE_REG, GUEST_BASE)); | |
2444 | tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); | |
2445 | } | |
2446 | ||
2447 | tcg_out_bundle(s, miB, | |
2448 | tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, | |
2449 | TCG_REG_R12, -frame_size, TCG_REG_R12), | |
2450 | tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22, | |
2451 | TCG_REG_R32, TCG_REG_B0), | |
2452 | tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6)); | |
2453 | ||
2454 | /* epilogue */ | |
2455 | tb_ret_addr = s->code_ptr; | |
2456 | tcg_out_bundle(s, miI, | |
2457 | INSN_NOP_M, | |
2458 | tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, | |
2459 | TCG_REG_B0, TCG_REG_R32, 0), | |
2460 | tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, | |
2461 | TCG_REG_R12, frame_size, TCG_REG_R12)); | |
2462 | tcg_out_bundle(s, miB, | |
2463 | INSN_NOP_M, | |
2464 | tcg_opc_i26(TCG_REG_P0, OPC_MOV_I_I26, | |
2465 | TCG_REG_PFS, TCG_REG_R34), | |
2466 | tcg_opc_b4 (TCG_REG_P0, OPC_BR_RET_SPTK_MANY_B4, | |
2467 | TCG_REG_B0)); | |
2468 | } | |
2469 | ||
2470 | static void tcg_target_init(TCGContext *s) | |
2471 | { | |
2472 | tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32], | |
2473 | 0xffffffffffffffffull); | |
2474 | tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64], | |
2475 | 0xffffffffffffffffull); | |
2476 | ||
2477 | tcg_regset_clear(tcg_target_call_clobber_regs); | |
2478 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); | |
2479 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); | |
2480 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); | |
2481 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); | |
2482 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); | |
2483 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R15); | |
2484 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R16); | |
2485 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R17); | |
2486 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R18); | |
2487 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R19); | |
2488 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R20); | |
2489 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R21); | |
2490 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R22); | |
2491 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R23); | |
2492 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R24); | |
2493 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R25); | |
2494 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R26); | |
2495 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R27); | |
2496 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R28); | |
2497 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R29); | |
2498 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R30); | |
2499 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R31); | |
2500 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R56); | |
2501 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R57); | |
2502 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R58); | |
2503 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R59); | |
2504 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R60); | |
2505 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R61); | |
2506 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R62); | |
2507 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R63); | |
2508 | ||
2509 | tcg_regset_clear(s->reserved_regs); | |
2510 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* zero register */ | |
2511 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* global pointer */ | |
2512 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* internal use */ | |
2513 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* internal use */ | |
2514 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12); /* stack pointer */ | |
2515 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ | |
2516 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R32); /* return address */ | |
2517 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R34); /* PFS */ | |
2518 | ||
2519 | /* The following 3 are not in use, are call-saved, but *not* saved | |
2520 | by the prologue. Therefore we cannot use them without modifying | |
2521 | the prologue. There doesn't seem to be any good reason to use | |
2522 | these as opposed to the windowed registers. */ | |
2523 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R4); | |
2524 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R5); | |
2525 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6); | |
2526 | ||
2527 | tcg_add_target_add_op_defs(ia64_op_defs); | |
2528 | } |