3 Copyright (c) 2011, ARM Limited. All rights reserved.
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include <Library/ArmLib.h>
17 #include <Library/ArmCpuLib.h>
18 #include <Library/ArmGicLib.h>
19 #include <Library/ArmV7ArchTimerLib.h>
20 #include <Library/DebugLib.h>
21 #include <Library/IoLib.h>
22 #include <Library/PcdLib.h>
24 #include <Chipset/ArmV7.h>
27 ArmCpuSynchronizeSignal (
28 IN ARM_CPU_SYNCHRONIZE_EVENT Event
31 if (Event
== ARM_CPU_EVENT_BOOT_MEM_INIT
) {
32 // Do nothing, Cortex A15 secondary cores are waiting for the GIC Distributor
33 // to be enabled (done by the Sec module itself) as a way to know when the Init Boot
34 // Mem as been initialized
36 // Send SGI to all Secondary core to wake them up from WFI state.
37 ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase
), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE
, 0x0E);
42 CArmCpuSynchronizeWait (
43 IN ARM_CPU_SYNCHRONIZE_EVENT Event
46 // Waiting for the SGI from the primary core
49 // Acknowledge the interrupt and send End of Interrupt signal.
50 ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase
), PRIMARY_CORE_ID
);
58 // Check if Architectural Timer frequency is valid number (should not be 0)
59 ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz
));
60 ASSERT(ArmIsArchTimerImplemented () != 0);
62 // Enable SWP instructions
63 ArmEnableSWPInstruction ();
65 // Enable program flow prediction, if supported.
66 ArmEnableBranchPrediction ();
68 // Note: System Counter frequency can only be set in Secure privileged mode,
69 // if security extensions are implemented.
70 ArmArchTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz
));
72 /*// If MPCore then Enable the SCU
80 ArmCpuSetupSmpNonSecure (
84 //ArmSetAuxCrBit (A15_FEATURE_SMP);
86 /*// Make the SCU accessible in Non Secure world
87 if (IS_PRIMARY_CORE(MpId)) {
88 ScuBase = ArmGetScuBaseAddress();
90 // Allow NS access to SCU register
91 MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
92 // Allow NS access to Private Peripherals
93 MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);