ArmPkg/Drivers/ArmGic/ArmGicLib.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Base.h>
  16 #include <Library/ArmGicLib.h>
  17 #include <Library/DebugLib.h>
  18 #include <Library/IoLib.h>
  19
  20 #include "GicV2/ArmGicV2Lib.h"
  21
  22 UINTN
  23 EFIAPI
  24 ArmGicGetInterfaceIdentification (
  25   IN  INTN          GicInterruptInterfaceBase
  26   )
  27 {
  28   // Read the GIC Identification Register
  29   return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIIDR);
  30 }
  31
  32 UINTN
  33 EFIAPI
  34 ArmGicGetMaxNumInterrupts (
  35   IN  INTN          GicDistributorBase
  36   )
  37 {
  38   return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);
  39 }
  40
  41 VOID
  42 EFIAPI
  43 ArmGicSendSgiTo (
  44   IN  INTN          GicDistributorBase,
  45   IN  INTN          TargetListFilter,
  46   IN  INTN          CPUTargetList,
  47   IN  INTN          SgiId
  48   )
  49 {
  50   MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);
  51 }
  52
  53 /*
  54  * Acknowledge and return the value of the Interrupt Acknowledge Register
  55  *
  56  * InterruptId is returned separately from the register value because in
  57  * the GICv2 the register value contains the CpuId and InterruptId while
  58  * in the GICv3 the register value is only the InterruptId.
  59  *
  60  * @param GicInterruptInterfaceBase   Base Address of the GIC CPU Interface
  61  * @param InterruptId                 InterruptId read from the Interrupt Acknowledge Register
  62  *
  63  * @retval value returned by the Interrupt Acknowledge Register
  64  *
  65  */
  66 UINTN
  67 EFIAPI
  68 ArmGicAcknowledgeInterrupt (
  69   IN  UINTN          GicInterruptInterfaceBase,
  70   OUT UINTN          *InterruptId
  71   )
  72 {
  73   UINTN Value;
  74
  75   Value = ArmGicV2AcknowledgeInterrupt (GicInterruptInterfaceBase);
  76
  77   // InterruptId is required for the caller to know if a valid or spurious
  78   // interrupt has been read
  79   ASSERT (InterruptId != NULL);
  80
  81   if (InterruptId != NULL) {
  82     *InterruptId = Value & ARM_GIC_ICCIAR_ACKINTID;
  83   }
  84
  85   return Value;
  86 }
  87
  88 VOID
  89 EFIAPI
  90 ArmGicEndOfInterrupt (
  91   IN  UINTN                 GicInterruptInterfaceBase,
  92   IN UINTN                  Source
  93   )
  94 {
  95   ArmGicV2EndOfInterrupt (GicInterruptInterfaceBase, Source);
  96 }
  97
  98 VOID
  99 EFIAPI
 100 ArmGicEnableInterrupt (
 101   IN UINTN                  GicDistributorBase,
 102   IN UINTN                  Source
 103   )
 104 {
 105   UINT32    RegOffset;
 106   UINTN     RegShift;
 107
 108   // Calculate enable register offset and bit position
 109   RegOffset = Source / 32;
 110   RegShift = Source % 32;
 111
 112   // Write set-enable register
 113   MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);
 114 }
 115
 116 VOID
 117 EFIAPI
 118 ArmGicDisableInterrupt (
 119   IN UINTN                  GicDistributorBase,
 120   IN UINTN                  Source
 121   )
 122 {
 123   UINT32    RegOffset;
 124   UINTN     RegShift;
 125
 126   // Calculate enable register offset and bit position
 127   RegOffset = Source / 32;
 128   RegShift = Source % 32;
 129
 130   // Write clear-enable register
 131   MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);
 132 }
 133
 134 BOOLEAN
 135 EFIAPI
 136 ArmGicIsInterruptEnabled (
 137   IN UINTN                  GicDistributorBase,
 138   IN UINTN                  Source
 139   )
 140 {
 141   UINT32    RegOffset;
 142   UINTN     RegShift;
 143
 144   // Calculate enable register offset and bit position
 145   RegOffset = Source / 32;
 146   RegShift = Source % 32;
 147
 148   return ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);
 149 }
 150
 151 VOID
 152 EFIAPI
 153 ArmGicDisableDistributor (
 154   IN  INTN          GicDistributorBase
 155   )
 156 {
 157   // Disable Gic Distributor
 158   MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x0);
 159 }
 160
 161 VOID
 162 EFIAPI
 163 ArmGicEnableInterruptInterface (
 164   IN  INTN          GicInterruptInterfaceBase
 165   )
 166 {
 167   return ArmGicV2EnableInterruptInterface (GicInterruptInterfaceBase);
 168 }
 169
 170 VOID
 171 EFIAPI
 172 ArmGicDisableInterruptInterface (
 173   IN  INTN          GicInterruptInterfaceBase
 174   )
 175 {
 176   return ArmGicV2DisableInterruptInterface (GicInterruptInterfaceBase);
 177 }