ArmPkg/Drivers/ArmGic/ArmGicLib.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Base.h>
  16 #include <Library/ArmGicLib.h>
  17 #include <Library/IoLib.h>
  18
  19 UINTN
  20 EFIAPI
  21 ArmGicGetInterfaceIdentification (
  22   IN  INTN          GicInterruptInterfaceBase
  23   )
  24 {
  25   // Read the GIC Identification Register
  26   return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIIDR);
  27 }
  28
  29 UINTN
  30 EFIAPI
  31 ArmGicGetMaxNumInterrupts (
  32   IN  INTN          GicDistributorBase
  33   )
  34 {
  35   return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);
  36 }
  37
  38 VOID
  39 EFIAPI
  40 ArmGicSendSgiTo (
  41   IN  INTN          GicDistributorBase,
  42   IN  INTN          TargetListFilter,
  43   IN  INTN          CPUTargetList,
  44   IN  INTN          SgiId
  45   )
  46 {
  47   MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);
  48 }
  49
  50 UINTN
  51 EFIAPI
  52 ArmGicAcknowledgeInterrupt (
  53   IN  UINTN          GicInterruptInterfaceBase
  54   )
  55 {
  56   // Read the Interrupt Acknowledge Register
  57   return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
  58 }
  59
  60 VOID
  61 EFIAPI
  62 ArmGicEndOfInterrupt (
  63   IN  UINTN                 GicInterruptInterfaceBase,
  64   IN UINTN                  Source
  65   )
  66 {
  67   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source);
  68 }
  69
  70 VOID
  71 EFIAPI
  72 ArmGicEnableInterrupt (
  73   IN UINTN                  GicDistributorBase,
  74   IN UINTN                  Source
  75   )
  76 {
  77   UINT32    RegOffset;
  78   UINTN     RegShift;
  79
  80   // Calculate enable register offset and bit position
  81   RegOffset = Source / 32;
  82   RegShift = Source % 32;
  83
  84   // Write set-enable register
  85   MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);
  86 }
  87
  88 VOID
  89 EFIAPI
  90 ArmGicDisableInterrupt (
  91   IN UINTN                  GicDistributorBase,
  92   IN UINTN                  Source
  93   )
  94 {
  95   UINT32    RegOffset;
  96   UINTN     RegShift;
  97
  98   // Calculate enable register offset and bit position
  99   RegOffset = Source / 32;
 100   RegShift = Source % 32;
 101
 102   // Write clear-enable register
 103   MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);
 104 }
 105
 106 BOOLEAN
 107 EFIAPI
 108 ArmGicIsInterruptEnabled (
 109   IN UINTN                  GicDistributorBase,
 110   IN UINTN                  Source
 111   )
 112 {
 113   UINT32    RegOffset;
 114   UINTN     RegShift;
 115
 116   // Calculate enable register offset and bit position
 117   RegOffset = Source / 32;
 118   RegShift = Source % 32;
 119
 120   return ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);
 121 }
 122
 123 VOID
 124 EFIAPI
 125 ArmGicDisableDistributor (
 126   IN  INTN          GicDistributorBase
 127   )
 128 {
 129   // Disable Gic Distributor
 130   MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x0);
 131 }