3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 Copyright (c) 2011, ARM Limited. All rights reserved.
6 SPDX-License-Identifier: BSD-2-Clause-Patent
12 #include <Guid/IdleLoopEvent.h>
14 BOOLEAN mIsFlushingGCD
;
17 This function flushes the range of addresses from Start to Start+Length
18 from the processor's data cache. If Start is not aligned to a cache line
19 boundary, then the bytes before Start to the preceding cache line boundary
20 are also flushed. If Start+Length is not aligned to a cache line boundary,
21 then the bytes past Start+Length to the end of the next cache line boundary
22 are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
23 supported. If the data cache is fully coherent with all DMA operations, then
24 this function can just return EFI_SUCCESS. If the processor does not support
25 flushing a range of the data cache, then the entire data cache can be flushed.
27 @param This The EFI_CPU_ARCH_PROTOCOL instance.
28 @param Start The beginning physical address to flush from the processor's data
30 @param Length The number of bytes to flush from the processor's data cache. This
31 function may flush more bytes than Length specifies depending upon
32 the granularity of the flush operation that the processor supports.
33 @param FlushType Specifies the type of flush operation to perform.
35 @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from
36 the processor's data cache.
37 @retval EFI_UNSUPPORTED The processor does not support the cache flush type specified
39 @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed
40 from the processor's data cache.
45 CpuFlushCpuDataCache (
46 IN EFI_CPU_ARCH_PROTOCOL
*This
,
47 IN EFI_PHYSICAL_ADDRESS Start
,
49 IN EFI_CPU_FLUSH_TYPE FlushType
54 case EfiCpuFlushTypeWriteBack
:
55 WriteBackDataCacheRange ((VOID
*)(UINTN
)Start
, (UINTN
)Length
);
57 case EfiCpuFlushTypeInvalidate
:
58 InvalidateDataCacheRange ((VOID
*)(UINTN
)Start
, (UINTN
)Length
);
60 case EfiCpuFlushTypeWriteBackInvalidate
:
61 WriteBackInvalidateDataCacheRange ((VOID
*)(UINTN
)Start
, (UINTN
)Length
);
64 return EFI_INVALID_PARAMETER
;
72 This function enables interrupt processing by the processor.
74 @param This The EFI_CPU_ARCH_PROTOCOL instance.
76 @retval EFI_SUCCESS Interrupts are enabled on the processor.
77 @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.
83 IN EFI_CPU_ARCH_PROTOCOL
*This
86 ArmEnableInterrupts ();
93 This function disables interrupt processing by the processor.
95 @param This The EFI_CPU_ARCH_PROTOCOL instance.
97 @retval EFI_SUCCESS Interrupts are disabled on the processor.
98 @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.
103 CpuDisableInterrupt (
104 IN EFI_CPU_ARCH_PROTOCOL
*This
107 ArmDisableInterrupts ();
114 This function retrieves the processor's current interrupt state a returns it in
115 State. If interrupts are currently enabled, then TRUE is returned. If interrupts
116 are currently disabled, then FALSE is returned.
118 @param This The EFI_CPU_ARCH_PROTOCOL instance.
119 @param State A pointer to the processor's current interrupt state. Set to TRUE if
120 interrupts are enabled and FALSE if interrupts are disabled.
122 @retval EFI_SUCCESS The processor's current interrupt state was returned in State.
123 @retval EFI_INVALID_PARAMETER State is NULL.
128 CpuGetInterruptState (
129 IN EFI_CPU_ARCH_PROTOCOL
*This
,
134 return EFI_INVALID_PARAMETER
;
137 *State
= ArmGetInterruptState();
143 This function generates an INIT on the processor. If this function succeeds, then the
144 processor will be reset, and control will not be returned to the caller. If InitType is
145 not supported by this processor, or the processor cannot programmatically generate an
146 INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error
147 occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.
149 @param This The EFI_CPU_ARCH_PROTOCOL instance.
150 @param InitType The type of processor INIT to perform.
152 @retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.
153 @retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported
155 @retval EFI_DEVICE_ERROR The processor INIT failed.
161 IN EFI_CPU_ARCH_PROTOCOL
*This
,
162 IN EFI_CPU_INIT_TYPE InitType
165 return EFI_UNSUPPORTED
;
170 CpuRegisterInterruptHandler (
171 IN EFI_CPU_ARCH_PROTOCOL
*This
,
172 IN EFI_EXCEPTION_TYPE InterruptType
,
173 IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
176 return RegisterInterruptHandler (InterruptType
, InterruptHandler
);
182 IN EFI_CPU_ARCH_PROTOCOL
*This
,
183 IN UINT32 TimerIndex
,
184 OUT UINT64
*TimerValue
,
185 OUT UINT64
*TimerPeriod OPTIONAL
188 return EFI_UNSUPPORTED
;
192 Callback function for idle events.
194 @param Event Event whose notification function is being invoked.
195 @param Context The pointer to the notification function's context,
196 which is implementation-dependent.
201 IdleLoopEventCallback (
210 // Globals used to initialize the protocol
212 EFI_HANDLE mCpuHandle
= NULL
;
213 EFI_CPU_ARCH_PROTOCOL mCpu
= {
214 CpuFlushCpuDataCache
,
217 CpuGetInterruptState
,
219 CpuRegisterInterruptHandler
,
221 CpuSetMemoryAttributes
,
223 2048, // DmaBufferAlignment
229 IN OUT EFI_CPU_ARCH_PROTOCOL
*CpuArchProtocol
232 CpuArchProtocol
->DmaBufferAlignment
= ArmCacheWritebackGranule ();
237 IN EFI_HANDLE ImageHandle
,
238 IN EFI_SYSTEM_TABLE
*SystemTable
242 EFI_EVENT IdleLoopEvent
;
244 InitializeExceptions (&mCpu
);
246 InitializeDma (&mCpu
);
248 Status
= gBS
->InstallMultipleProtocolInterfaces (
250 &gEfiCpuArchProtocolGuid
, &mCpu
,
255 // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()
256 // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go
257 // after the protocol is installed
259 mIsFlushingGCD
= TRUE
;
260 SyncCacheConfig (&mCpu
);
261 mIsFlushingGCD
= FALSE
;
263 // If the platform is a MPCore system then install the Configuration Table describing the
264 // secondary core states
266 PublishArmProcessorTable();
270 // Setup a callback for idle events
272 Status
= gBS
->CreateEventEx (
275 IdleLoopEventCallback
,
280 ASSERT_EFI_ERROR (Status
);