3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 Copyright (c) 2011, ARM Limited. All rights reserved.
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Guid/IdleLoopEvent.h>
22 This function flushes the range of addresses from Start to Start+Length
23 from the processor's data cache. If Start is not aligned to a cache line
24 boundary, then the bytes before Start to the preceding cache line boundary
25 are also flushed. If Start+Length is not aligned to a cache line boundary,
26 then the bytes past Start+Length to the end of the next cache line boundary
27 are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
28 supported. If the data cache is fully coherent with all DMA operations, then
29 this function can just return EFI_SUCCESS. If the processor does not support
30 flushing a range of the data cache, then the entire data cache can be flushed.
32 @param This The EFI_CPU_ARCH_PROTOCOL instance.
33 @param Start The beginning physical address to flush from the processor's data
35 @param Length The number of bytes to flush from the processor's data cache. This
36 function may flush more bytes than Length specifies depending upon
37 the granularity of the flush operation that the processor supports.
38 @param FlushType Specifies the type of flush operation to perform.
40 @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from
41 the processor's data cache.
42 @retval EFI_UNSUPPORTED The processor does not support the cache flush type specified
44 @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed
45 from the processor's data cache.
50 CpuFlushCpuDataCache (
51 IN EFI_CPU_ARCH_PROTOCOL
*This
,
52 IN EFI_PHYSICAL_ADDRESS Start
,
54 IN EFI_CPU_FLUSH_TYPE FlushType
59 case EfiCpuFlushTypeWriteBack
:
60 WriteBackDataCacheRange ((VOID
*)(UINTN
)Start
, (UINTN
)Length
);
62 case EfiCpuFlushTypeInvalidate
:
63 InvalidateDataCacheRange ((VOID
*)(UINTN
)Start
, (UINTN
)Length
);
65 case EfiCpuFlushTypeWriteBackInvalidate
:
66 WriteBackInvalidateDataCacheRange ((VOID
*)(UINTN
)Start
, (UINTN
)Length
);
69 return EFI_INVALID_PARAMETER
;
77 This function enables interrupt processing by the processor.
79 @param This The EFI_CPU_ARCH_PROTOCOL instance.
81 @retval EFI_SUCCESS Interrupts are enabled on the processor.
82 @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.
88 IN EFI_CPU_ARCH_PROTOCOL
*This
91 ArmEnableInterrupts ();
98 This function disables interrupt processing by the processor.
100 @param This The EFI_CPU_ARCH_PROTOCOL instance.
102 @retval EFI_SUCCESS Interrupts are disabled on the processor.
103 @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.
108 CpuDisableInterrupt (
109 IN EFI_CPU_ARCH_PROTOCOL
*This
112 ArmDisableInterrupts ();
119 This function retrieves the processor's current interrupt state a returns it in
120 State. If interrupts are currently enabled, then TRUE is returned. If interrupts
121 are currently disabled, then FALSE is returned.
123 @param This The EFI_CPU_ARCH_PROTOCOL instance.
124 @param State A pointer to the processor's current interrupt state. Set to TRUE if
125 interrupts are enabled and FALSE if interrupts are disabled.
127 @retval EFI_SUCCESS The processor's current interrupt state was returned in State.
128 @retval EFI_INVALID_PARAMETER State is NULL.
133 CpuGetInterruptState (
134 IN EFI_CPU_ARCH_PROTOCOL
*This
,
139 return EFI_INVALID_PARAMETER
;
142 *State
= ArmGetInterruptState();
148 This function generates an INIT on the processor. If this function succeeds, then the
149 processor will be reset, and control will not be returned to the caller. If InitType is
150 not supported by this processor, or the processor cannot programmatically generate an
151 INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error
152 occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.
154 @param This The EFI_CPU_ARCH_PROTOCOL instance.
155 @param InitType The type of processor INIT to perform.
157 @retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.
158 @retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported
160 @retval EFI_DEVICE_ERROR The processor INIT failed.
166 IN EFI_CPU_ARCH_PROTOCOL
*This
,
167 IN EFI_CPU_INIT_TYPE InitType
170 return EFI_UNSUPPORTED
;
175 CpuRegisterInterruptHandler (
176 IN EFI_CPU_ARCH_PROTOCOL
*This
,
177 IN EFI_EXCEPTION_TYPE InterruptType
,
178 IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
181 return RegisterInterruptHandler (InterruptType
, InterruptHandler
);
187 IN EFI_CPU_ARCH_PROTOCOL
*This
,
188 IN UINT32 TimerIndex
,
189 OUT UINT64
*TimerValue
,
190 OUT UINT64
*TimerPeriod OPTIONAL
193 return EFI_UNSUPPORTED
;
197 Callback function for idle events.
199 @param Event Event whose notification function is being invoked.
200 @param Context The pointer to the notification function's context,
201 which is implementation-dependent.
206 IdleLoopEventCallback (
215 // Globals used to initialize the protocol
217 EFI_HANDLE mCpuHandle
= NULL
;
218 EFI_CPU_ARCH_PROTOCOL mCpu
= {
219 CpuFlushCpuDataCache
,
222 CpuGetInterruptState
,
224 CpuRegisterInterruptHandler
,
226 CpuSetMemoryAttributes
,
228 2048, // DmaBufferAlignment
234 IN OUT EFI_CPU_ARCH_PROTOCOL
*CpuArchProtocol
237 CpuArchProtocol
->DmaBufferAlignment
= ArmCacheWritebackGranule ();
242 IN EFI_HANDLE ImageHandle
,
243 IN EFI_SYSTEM_TABLE
*SystemTable
247 EFI_EVENT IdleLoopEvent
;
249 InitializeExceptions (&mCpu
);
251 InitializeDma (&mCpu
);
253 Status
= gBS
->InstallMultipleProtocolInterfaces (
255 &gEfiCpuArchProtocolGuid
, &mCpu
,
260 // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()
261 // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go
262 // after the protocol is installed
264 SyncCacheConfig (&mCpu
);
266 // If the platform is a MPCore system then install the Configuration Table describing the
267 // secondary core states
269 PublishArmProcessorTable();
273 // Setup a callback for idle events
275 Status
= gBS
->CreateEventEx (
278 IdleLoopEventCallback
,
283 ASSERT_EFI_ERROR (Status
);