1 #------------------------------------------------------------------------------
3 # Use ARMv6 instruction to operate on a single stack
5 # Copyright (c) 2008-2010 Apple Inc. All rights reserved.
7 # All rights reserved. This program and the accompanying materials
8 # are licensed and made available under the terms and conditions of the BSD License
9 # which accompanies this distribution. The full text of the license may be found at
10 # http://opensource.org/licenses/bsd-license.php
12 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #------------------------------------------------------------------------------
19 This is the stack constructed by the exception handler (low address to high address)
20 # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
23 R0 0x00 # stmfd SP!,{R0-R12}
36 SP 0x34 # reserved via adding 0x20 (32) to the SP
45 LR 0x54 # SVC Link register (we need to restore it)
47 LR 0x58 # pushed by srsfd
53 .globl ASM_PFX(ExceptionHandlersStart)
54 .globl ASM_PFX(ExceptionHandlersEnd)
55 .globl ASM_PFX(CommonExceptionEntry)
56 .globl ASM_PFX(AsmCommonExceptionEntry)
57 .globl ASM_PFX(CommonCExceptionHandler)
64 // This code gets copied to the ARM vector table
65 // ExceptionHandlersStart - ExceptionHandlersEnd gets copied
67 ASM_PFX(ExceptionHandlersStart):
72 ASM_PFX(UndefinedInstruction):
73 b ASM_PFX(UndefinedInstructionEntry)
75 ASM_PFX(SoftwareInterrupt):
76 b ASM_PFX(SoftwareInterruptEntry)
78 ASM_PFX(PrefetchAbort):
79 b ASM_PFX(PrefetchAbortEntry)
82 b ASM_PFX(DataAbortEntry)
84 ASM_PFX(ReservedException):
85 b ASM_PFX(ReservedExceptionEntry)
94 srsdb #0x13! @ Store return state on SVC stack
95 @ We are already in SVC mode
97 stmfd SP!,{LR} @ Store the link register for the current mode
98 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
99 stmfd SP!,{R0-R12} @ Store the register state
101 mov R0,#0 @ ExceptionType
102 ldr R1,ASM_PFX(CommonExceptionEntry)
105 ASM_PFX(UndefinedInstructionEntry):
106 sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
107 srsdb #0x13! @ Store return state on SVC stack
108 cps #0x13 @ Switch to SVC for common stack
109 stmfd SP!,{LR} @ Store the link register for the current mode
110 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
111 stmfd SP!,{R0-R12} @ Store the register state
113 mov R0,#1 @ ExceptionType
114 ldr R1,ASM_PFX(CommonExceptionEntry)
117 ASM_PFX(SoftwareInterruptEntry):
118 sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
119 srsdb #0x13! @ Store return state on SVC stack
120 @ We are already in SVC mode
121 stmfd SP!,{LR} @ Store the link register for the current mode
122 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
123 stmfd SP!,{R0-R12} @ Store the register state
125 mov R0,#2 @ ExceptionType
126 ldr R1,ASM_PFX(CommonExceptionEntry)
129 ASM_PFX(PrefetchAbortEntry):
131 srsdb #0x13! @ Store return state on SVC stack
132 cps #0x13 @ Switch to SVC for common stack
133 stmfd SP!,{LR} @ Store the link register for the current mode
134 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
135 stmfd SP!,{R0-R12} @ Store the register state
137 mov R0,#3 @ ExceptionType
138 ldr R1,ASM_PFX(CommonExceptionEntry)
141 ASM_PFX(DataAbortEntry):
143 srsdb #0x13! @ Store return state on SVC stack
144 cps #0x13 @ Switch to SVC for common stack
145 stmfd SP!,{LR} @ Store the link register for the current mode
146 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
147 stmfd SP!,{R0-R12} @ Store the register state
150 ldr R1,ASM_PFX(CommonExceptionEntry)
153 ASM_PFX(ReservedExceptionEntry):
154 srsdb #0x13! @ Store return state on SVC stack
155 cps #0x13 @ Switch to SVC for common stack
156 stmfd SP!,{LR} @ Store the link register for the current mode
157 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
158 stmfd SP!,{R0-R12} @ Store the register state
161 ldr R1,ASM_PFX(CommonExceptionEntry)
166 srsdb #0x13! @ Store return state on SVC stack
167 cps #0x13 @ Switch to SVC for common stack
168 stmfd SP!,{LR} @ Store the link register for the current mode
169 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
170 stmfd SP!,{R0-R12} @ Store the register state
172 mov R0,#6 @ ExceptionType
173 ldr R1,ASM_PFX(CommonExceptionEntry)
178 srsdb #0x13! @ Store return state on SVC stack
179 cps #0x13 @ Switch to SVC for common stack
180 stmfd SP!,{LR} @ Store the link register for the current mode
181 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
182 stmfd SP!,{R0-R12} @ Store the register state
183 @ Since we have already switch to SVC R8_fiq - R12_fiq
184 @ never get used or saved
185 mov R0,#7 @ ExceptionType
186 ldr R1,ASM_PFX(CommonExceptionEntry)
190 // This gets patched by the C code that patches in the vector table
192 ASM_PFX(CommonExceptionEntry):
198 ASM_PFX(ExceptionHandlersEnd):
201 // This code runs from CpuDxe driver loaded address. It is patched into
202 // CommonExceptionEntry.
204 ASM_PFX(AsmCommonExceptionEntry):
205 mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
206 str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
208 mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
209 str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
211 mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
212 str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
214 mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
215 str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
217 ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack
218 str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
220 add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
221 and R3, R1, #0x1f @ Check CPSR to see if User or System Mode
222 cmp R3, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1df))
224 stmeqed R2, {lr}^ @ save unbanked lr
226 stmneed R2, {lr} @ save SVC lr
229 ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd
230 @ Check to see if we have to adjust for Thumb entry
231 sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType ==2)) {
232 cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb
235 tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry
236 addne R5, R5, #2 @ PC += 2@
237 str R5,[SP,#0x58] @ Update LR value pused by srsfd
241 str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
243 sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack
244 str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
246 @ R0 is ExceptionType
247 mov R1,SP @ R1 is SystemContext
252 CommonCExceptionHandler (
253 IN EFI_EXCEPTION_TYPE ExceptionType, R0
254 IN OUT EFI_SYSTEM_CONTEXT SystemContext R1
258 blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler
260 ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
261 str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored
263 ldr R1,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR
264 str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored
266 add R3, SP, #0x54 @ Make R3 point to SVC LR saved on entry
267 add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
268 and R1, R1, #0x1f @ Check to see if User or System Mode
269 cmp R1, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f))
271 ldmeqed R2, {lr}^ @ restore unbanked lr
273 ldmneed R3, {lr} @ restore SVC lr, via ldmfd SP!, {LR}
275 ldmfd SP!,{R0-R12} @ Restore general purpose registers
276 @ Exception handler can not change SP
278 add SP,SP,#0x20 @ Clear out the remaining stack space
279 ldmfd SP!,{LR} @ restore the link register for this context
280 rfefd SP! @ return from exception via srsfd stack slot